DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT163
Presettable synchronous 4-bit
binary counter; synchronous reset
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
FEATURES
•Synchronous counting and loading
•Two count enable inputs for n-bit cascading
•Positive-edge triggered clock
•Synchronous reset
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT163 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT163 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q0 to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements forPE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
For the “163” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level after the
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
fmax 1
tP max()
(CPtoTC) t
SU(CEP to CP)+
-------------------------------------------------------------------------------------------------
=
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f=6ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay
CP to Qn
CP to TC
CET to TC
CL=15pF;
V
CC =5V 17
21
11
20
25
14
ns
ns
ns
fmax maximum clock frequency 51 50 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation
capacitance per package notes 1 and 2 33 35 pF
Notes
1. CPD is used to determine the
dynamic power dissipation
(PD in µW):
PD=C
PD ×VCC2×fi+
∑(CL×VCC2×fo)
where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of
outputs
CL= output load capacitance in
pF
VCC = supply voltage in V
2. For HC the condition is
VI= GND to VCC
For HCT the condition is
VI= GND to VCC −1.5 V
December 1990 3
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1MR synchronous master reset (active LOW)
2 CP clock input (LOW-to-HIGH, edge-triggered)
3, 4, 5, 6 D0 to D3data inputs
7 CEP count enable input
8 GND ground (0 V)
9PE parallel enable input (active LOW)
10 CET count enable carry input
14, 13, 12, 11 Q0 to Q3flip-flop outputs
15 TC terminal count output
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
FUNCTION TABLE
Notes
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑= LOW-to-HIGH CP transition
OPERATING MODE INPUTS OUTPUTS
MR CP CEP CET PE DnQnTC
reset (clear) I ↑XXXXL L
parallel load h
h↑
↑X
XX
XI
II
hL
HL
(1)
count h ↑h h h X count (1)
hold
(do nothing) h
hX
XI
XX
Ih
hX
Xqn
qn
(1)
L
Fig.4 Functional diagram.
December 1990 5
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
Fig.5 State diagram.
Fig.6 Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen,
zero, one and two; inhibit.
December 1990 6
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
Fig.7 Logic diagram.
December 1990 7
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
55
20
16
185
37
31
230
46
39
280
56
48 ns 2.0
4.5
6.0
Fig.8
tPHL/ tPLH propagation delay
CP to TC 69
25
20
215
43
37
270
54
46
320
65
55 ns 2.0
4.5
6.0
Fig.8
tPHL/ tPLH propagation delay
CET to TC 36
13
10
120
24
20
150
30
26
180
36
31 ns 2.0
4.5
6.0
Fig.9
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19 ns 2.0
4.5
6.0
Figs 8 and 9
tWclock pulse width
HIGH or LOW 80
16
14
17
6
5
100
20
17
120
24
20 ns 2.0
4.5
6.0
Fig.8
tsu set-up time
MR, Dn to CP 80
16
14
17
6
5
100
20
17
120
24
20 ns 2.0
4.5
6.0
Figs 10 and 11
tsu set-up time
PE to CP 80
16
14
22
8
6
100
20
17
120
24
20 ns 2.0
4.5
6.0
Fig.10
tsu set-up time
CEP, CET to CP 175
35
30
58
21
17
220
44
37
265
53
45 ns 2.0
4.5
6.0
Fig.12
thhold time
Dn, PE, CEP,
CET, MR to CP
0
0
0
−14
−5
−4
0
0
0
0
0
0ns 2.0
4.5
6.0
Figs 10, 11 and 12
fmax maximum clock pulse
frequency 5
27
32
15
46
55
4
22
26
4
18
21 MHz 2.0
4.5
6.0
Fig.8
December 1990 8
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
MR 0.95
CP 1.10
CEP 0.25
Dn0.25
CET 0.75
PE 0.30
December 1990 9
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
23 39 49 59 ns 4.5 Fig.8
tPHL/ tPLH propagation delay
CP to TC 29 49 61 74 ns 4.5 Fig.8
tPHL/ tPLH propagation delay
CET to TC 17 32 44 48 ns 4.5 Fig.9
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 8 and 9
tWclock pulse width
HIGH or LOW 20 6 25 30 ns 4.5 Fig.8
tsu set-up time
MR, Dn to CP 20 9 25 30 ns 4.5 Figs 10 and 11
tsu set-up time
PE to CP 20 11 25 30 ns 4.5 Fig.10
tsu set-up time
CEP, CET to CP 40 24 50 60 ns 4.5 Fig.12
thhold time
Dn, PE, CEP,
CET, MR to CP
0−5 0 0 ns 4.5 Figs 10, 11 and 12
fmax maximum clock pulse
frequency 26 45 21 17 MHz 4.5 Fig.8
December 1990 10
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
AC WAVEFORMS
Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
December 1990 11
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; synchronous reset 74HC/HCT163
Fig.11 Waveforms showing the MR set-up and hold times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
APPLICATION INFORMATION
The HC/HCT163 facilitate designing counters of any
modulus with minimal external logic.
The output is glitch-free due to the synchronous reset.
Fig.13 Modulo-5 counter. PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.14 Modulo-11 counter.
