S-5725 Series
www.sii-ic.com HIGH-SPEED BIPOLAR HALL EFFECT LATCH
© Seiko Instruments Inc., 2011-2013 Rev.2.4_00
Seiko Instruments Inc. 1
The S-5725 Series, developed by CMOS technology, is a high-accuracy Hall IC that operates with a high-sensitivity, a high-
speed detection and low current consumption.
The output voltage changes when the S-5725 Series detects the intensity level of magnetic flux density and a polarity
change. Using the S-5725 Series with a magnet makes it possible to detect the rotation status in various devices.
High-density mounting is possible by using the small SOT-23-3 or the super-small SNT-4A packages.
Due to its high-accuracy magnetic characteristics, the S-5725 Series can make operation's dispersion in the system
combined with magnet smaller.
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to SII is
indispensable.
Features
• Pole detection: Bipolar latch
• Detection logic for magnetism*1: VOUT = "L" at S pole detection
V
OUT = "H" at S pole detection
• Output form*1: Nch open-drain output, CMOS output
• Magnetic sensitivity*1: BOP = 0.8 mT typ.
B
OP = 1.8 mT typ.
B
OP = 3.0 mT typ.
• Operating cycle (current consumption)*1: tCYCLE = 50 μs (IDD = 1400.0 μA) typ.
t
CYCLE = 1.25 ms (IDD = 60.0 μA) typ.
t
CYCLE = 6.05 ms (IDD = 13.0 μA) typ.
• Power supply voltage range: VDD = 2.7 V to 5.5 V
• Operation temperature range: Ta = −40°C to +85°C
• Built-in power-down circuit: Extends battery life (only SNT-4A)
• Lead-free (Sn 100%), halogen-free
*1. The option can be selected.
Applications
• Plaything, portable game
• Home appliance
• Housing equipment
• Industrial equipment
Packages
• SOT-23-3
• SNT-4A
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
2
Block Diagrams
1. Nch open-drain output product
1. 1 Product without power-down function
OUT
VDD
VSS
*1 *1
Sleep / Awake logic
Chopping
stabilized am plifi er
*1. Parasitic diode
Figure 1
1. 2 Product with power-down function (SNT-4A)
OUT
*1
Sleep / Awake logic
*1
Power-down circuit
*1
VSS
CE
*1
VDD
Chopping
stabilized am plifi er
*1. Parasitic diode
Figure 2
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 3
2. CMOS output product
2. 1 Product without power-down function
OUT
VDD
VSS
*1
Sleep / Awake logic
*1
Chopping
stabilized am plifi er
*1
*1. Parasitic diode
Figure 3
2. 2 Product with power-down function (SNT-4A)
OUT
*1
Sleep / Awake logic
*1
*1
Power-down circuit
*1
VSS
CE
*1
VDD
Chopping
stabilized am plifi er
*1. Parasitic diode
Figure 4
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
4
Product Name Structure
1. Product name
S-5725 x x B x x - xxxx U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and packing specifications*1
M3T1: SOT-23-3, Tape
I4T1: SNT-4A, Tape
Magnetic sensitivity
9: BOP = 0.8 mT typ.
0: BOP = 1.8 mT typ.
1: BOP = 3.0 mT typ.
Detection logic for magnetism
L: VOUT = "L" at S pole detection
H: VOUT = "H" at S pole detection
Pole detection
B: Bipolar latch
Output form
N: Nch open-drain output
C: CMOS output
Operating cycle
C: tCYCLE = 6.05 ms typ. (Without power-down function)
D: tCYCLE = 1.25 ms typ. (Without power-down function)
E: tCYCLE = 50 μs typ. (Without power-down function)
H: tCYCLE = 6.05 ms typ. (With power-down function, SNT-4A
)
I: tCYCLE = 1.25 ms typ. (With power-down function, SNT-4A
)
J: tCYCLE = 50 μs typ. (With power-down function, SNT-4A
)
*1. Refer to the tape drawing.
2. Packages
Table 1 Package Drawing Codes
Package Name Dimension Tape Reel Land
SOT-23-3 MP003-C-P-SD MP003-C-C-SD MP003-Z-R-SD −
SNT-4A PF004-A-P-SD PF004-A-C-SD PF004-A-R-SD PF004-A-L-SD
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 5
3. Product name list
3. 1 SOT-23-3
3. 1. 1 Nch open-drain output product
Table 2
Product Name Operating Cycle
(tCYCLE)
Power-down
Function Output Form Pole
Detection
Detection Logic
for Magnetism
Magnetic
Sensitivity
(BOP)
S-5725CNBL9-M3T1U 6.05 ms typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "L" at S pole
detection 0.8 mT typ.
S-5725CNBL0-M3T1U 6.05 ms typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "L" at S pole
detection 1.8 mT typ.
S-5725CNBL1-M3T1U 6.05 ms typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "L" at S pole
detection 3.0 mT typ.
S-5725DNBL1-M3T1U 1.25 ms typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "L" at S pole
detection 3.0 mT typ.
S-5725ENBL9-M3T1U 50 μs typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "L" at S pole
detection 0.8 mT typ.
S-5725ENBL0-M3T1U 50 μs typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "L" at S pole
detection 1.8 mT typ.
S-5725ENBL1-M3T1U 50 μs typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "L" at S pole
detection 3.0 mT typ.
S-5725ENBH1-M3T1U 50 μs typ. Unavailable Nch open-drain
output Bipolar
latch VOUT = "H" at S pole
detection 3.0 mT typ.
Remark Please contact our sales office for products other than the above.
3. 1. 2 CMOS output product
Table 3
Product Name Operating Cycle
(tCYCLE)
Power-down
Function Output Form Pole
Detection Detection Logic
for Magnetism
Magnetic
Sensitivity
(BOP)
S-5725CCBL9-M3T1U 6.05 ms typ. Unavailable CMOS output Bipolar
latch VOUT = "L" at S pole
detection 0.8 mT typ.
S-5725CCBL0-M3T1U 6.05 ms typ. Unavailable CMOS output Bipolar
latch VOUT = "L" at S pole
detection 1.8 mT typ.
S-5725CCBL1-M3T1U 6.05 ms typ. Unavailable CMOS output Bipolar
latch VOUT = "L" at S pole
detection 3.0 mT typ.
S-5725DCBL1-M3T1U 1.25 ms typ. Unavailable CMOS output Bipolar
latch VOUT = "L" at S pole
detection 3.0 mT typ.
S-5725ECBL9-M3T1U 50 μs typ. Unavailable CMOS output
Bipolar
latch VOUT = "L" at S pole
detection 0.8 mT typ.
S-5725ECBL0-M3T1U 50 μs typ. Unavailable CMOS output
Bipolar
latch VOUT = "L" at S pole
detection 1.8 mT typ.
S-5725ECBL1-M3T1U 50 μs typ. Unavailable CMOS output
Bipolar
latch VOUT = "L" at S pole
detection 3.0 mT typ.
S-5725ECBH1-M3T1U 50 μs typ. Unavailable CMOS output
Bipolar
latch VOUT = "H" at S pole
detection 3.0 mT typ.
Remark Please contact our sales office for products other than the above.
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
6
3. 2 SNT-4A
3. 2. 1 Nch open-drain output product
Table 4
Product Name Operating Cycle
(tCYCLE)
Power-down
Function Output Form Pole
Detection Detection Logic
for Magnetism
Magnetic
Sensitivity
(BOP)
S-5725HNBH0-I4T1U 6.05 ms typ. Available Nch open-drain
output Bipolar
latch VOUT = "H" at S pole
detection 1.8 mT typ.
S-5725INBH0-I4T1U 1.25 ms typ. Available Nch open-drain
output Bipolar
latch VOUT = "H" at S pole
detection 1.8 mT typ.
S-5725JNBH0-I4T1U 50 μs typ. Available Nch open-drain
output Bipolar
latch VOUT = "H" at S pole
detection 1.8 mT typ.
Remark Please contact our sales office for products other than the above.
3. 2. 2 CMOS output product
Table 5
Product Name Operating Cycle
(tCYCLE)
Power-down
Function Output Form Pole
Detection Detection Logic
for Magnetism
Magnetic
Sensitivity
(BOP)
S-5725HCBH0-I4T1U 6.05 ms typ. Available CMOS output Bipolar
latch VOUT = "H" at S pole
detection 1.8 mT typ.
S-5725HCBH1-I4T1U 6.05 ms typ. Available CMOS output Bipolar
latch VOUT = "H" at S pole
detection 3.0 mT typ.
S-5725ICBH0-I4T1U 1.25 ms typ. Available CMOS output Bipolar
latch VOUT = "H" at S pole
detection 1.8 mT typ.
S-5725ICBH1-I4T1U 1.25 ms typ. Available CMOS output Bipolar
latch VOUT = "H" at S pole
detection 3.0 mT typ.
S-5725JCBH0-I4T1U 50 μs typ. Available CMOS output
Bipolar
latch VOUT = "H" at S pole
detection 1.8 mT typ.
S-5725JCBH1-I4T1U 50 μs typ. Available CMOS output
Bipolar
latch VOUT = "H" at S pole
detection 3.0 mT typ.
Remark Please contact our sales office for products other than the above.
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 7
Pin Configurations
1. SOT-23-3
Table 6
Pin No. Symbol Pin Description
1 VSS GND pin
2 VDD Power supply pin
3 OUT Output pin
23
1
Top view
Figure 5
2. SNT-4A
Table 7
Pin No. Symbol Description
1 VDD Power supply pin
2 VSS GND pin
3 CE
Enabling pin
"H": Enables operation
"L": Power-down
4 OUT Output pin
4
32
1
Top view
Figure 6
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
8
Absolute Maximum Ratings
Table 8
(Ta = +25°C unless otherwise specified)
Item Symbol Absolute Maximum Rating Unit
Power supply voltage VDD VSS − 0.3 to VSS + 7.0 V
Input voltage VCE VSS − 0.3 to VDD + 0.3 V
Output current IOUT ±2.0 mA
Nch open-drain output product VSS − 0.3 to VSS + 7.0 V
Output voltage CMOS output product VOUT VSS − 0.3 to VDD + 0.3 V
SOT-23-3 430*1 mW
Power dissipation SNT-4A PD 300*1 mW
Operation ambient temperature Topr −40 to +85 °C
Storage temperature Tstg −40 to +125 °C
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm × 76.2 mm × t1.6 mm
(2) Name: JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Power Dissipation (P
D
) [mW]
Ambient Temperature (Ta) [°C]
050 100 150
0
400
600
200
SNT-4A
SOT-23-3
Figure 7 Power Dissipation of Package (When Mounted on Board)
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 9
Electrical Characteristics
1. Product without power-down function
1. 1 S-5725CxBxx
Table 9
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Power supply voltage VDD − 2.7 5.0 5.5 V −
Current consumption IDD Average value − 13.0 20.0 μA 1
Nch open-drain output
product Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output voltage VOUT CMOS output product Output transistor Pch,
IOUT = −2 mA VDD −
0.4 − − V 3
Leakage current ILEAK Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V − − 1 μA 4
Awake mode time t AW − − 0.05 − ms −
Sleep mode time tSL − − 6.00 − ms −
Operating cycle tCYCLE tAW + t
SL − 6.05 12.00 ms −
1. 2 S-5725DxBxx
Table 10
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Power supply voltage VDD − 2.7 5.0 5.5 V −
Current consumption IDD Average value − 60.0 90.0 μA 1
Nch open-drain output
product Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output voltage VOUT CMOS output product Output transistor Pch,
IOUT = −2 mA VDD −
0.4 − − V 3
Leakage current ILEAK Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V − − 1 μA 4
Awake mode time t AW − − 0.05 − ms −
Sleep mode time tSL − − 1.20 − ms −
Operating cycle tCYCLE tAW + t
SL − 1.25 2.50 ms −
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
10
1. 3 S-5725ExBxx
Table 11
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Power supply voltage VDD − 2.7 5.0 5.5 V −
Current consumption IDD Average value − 1400.0 2000.0 μA 1
Nch open-drain output
product Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output voltage VOUT CMOS output product Output transistor Pch,
IOUT = −2 mA VDD −
0.4 − − V 3
Leakage current ILEAK Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V − − 1 μA 4
Awake mode time tAW − − 50 − μs −
Sleep mode time tSL − − 0 − μs −
Operating cycle tCYCLE t
AW + t
SL − 50 100 μs −
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 11
2. Product with power-down function (SNT-4A)
2. 1 S-5725HxBxx
Table 12
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test
Circuit
Power supply voltage VDD − 2.7 5.0 5.5 V −
Current consumption IDD Average value − 13.0 20.0 μA 1
Current consumption during
power-down IDD2 V
CE = VSS − − 1 μA 6
Nch open-drain
output product Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output voltage VOUT CMOS output
product Output transistor Pch,
IOUT = −2 mA VDD −
0.4 − − V 3
Leakage current ILEAK Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V − − 1 μA 4
Awake mode time t AW − − 0.05 − ms −
Sleep mode time tSL − − 6.00 − ms −
Operating cycle tCYCLE t
AW + t
SL − 6.05 12.00 ms −
Enabling pin input voltage "L" VCEL − − − VDD ×
0.3 V −
Enabling pin input voltage "H" VCEH − VDD ×
0.7 − − V −
Enabling pin input current "L" ICEL V
DD = 5.0 V, VCE = 0 V −1 − 1 μA 7
Enabling pin input current "H" ICEH V
DD = 5.0 V, VCE = 5.0 V −1 − 1 μA 8
Power-down transition time tOFF − − − 100 μs −
Enable transition time tON − − − 100 μs −
Output logic update time after
inputting "H" to enabling pin tOE − − − 200 μs −
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
12
2. 2 S-5725IxBxx
Table 13
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Power supply voltage VDD − 2.7 5.0 5.5 V −
Current consumption IDD Average value − 60.0 90.0 μA 1
Current consumption during
power-down IDD2 V
CE = VSS − − 1 μA 6
Nch open-drain
output product Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output voltage VOUT CMOS output
product Output transistor Pch,
IOUT = −2 mA VDD −
0.4 − − V 3
Leakage current ILEAK Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V − − 1 μA 4
Awake mode time tAW − − 0.05 − ms −
Sleep mode time tSL − − 1.20 − ms −
Operating cycle tCYCLE t
AW + tSL − 1.25 2.50 ms −
Enabling pin input voltage "L" VCEL − − − VDD ×
0.3 V −
Enabling pin input voltage "H" VCEH − VDD ×
0.7 − − V −
Enabling pin input current "L" ICEL V
DD = 5.0 V, VCE = 0 V −1 − 1 μA 7
Enabling pin input current "H" ICEH V
DD = 5.0 V, VCE = 5.0 V −1 − 1 μA 8
Power-down transition time tOFF − − − 100 μs −
Enable transition time tON − − − 100 μs −
Output logic update time after
inputting "H" to enabling pin tOE − − − 200 μs −
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 13
2. 3 S-5725JxBxx
Table 14
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Power supply voltage VDD − 2.7 5.0 5.5 V −
Current consumption IDD Average value − 1400.0 2000.0 μA 1
Current consumption during
power-down IDD2 V
CE = VSS − − 1 μA 6
Nch open-drain
output product Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output transistor Nch,
IOUT = 2 mA − − 0.4 V 2
Output voltage VOUT CMOS output
product Output transistor Pch,
IOUT = −2 mA VDD −
0.4 − − V 3
Leakage current ILEAK Nch open-drain output product
Output transistor Nch, VOUT = 5.5 V − − 1 μA 4
Awake mode time tAW − − 50 − μs −
Sleep mode time tSL − − 0 − μs −
Operating cycle tCYCLE t
AW + tSL − 50 100 μs −
Enabling pin input voltage "L" VCEL − − − VDD ×
0.3 V −
Enabling pin input voltage "H" VCEH − VDD ×
0.7 − − V −
Enabling pin input current "L" ICEL V
DD = 5.0 V, VCE = 0 V −1 − 1 μA 7
Enabling pin input current "H" ICEH V
DD = 5.0 V, VCE = 5.0 V −1 − 1 μA 8
Power-down transition time tOFF − − − 100 μs −
Enable transition time tON − − − 100 μs −
Output logic update time after
inputting "H" to enabling pin tOE − − − 200 μs −
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
14
Magnetic Characteristics
1. Product with BOP = 0.8 mT typ.
Table 15
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test Circuit
Operation point*1 S pole BOP − 0.1 0.8 1.5 mT 5
Release point*2 N pole BRP − −1.5 −0.8 −0.1 mT 5
Hysteresis width*3 BHYS B
HYS = BOP − BRP − 1.6 − mT 5
2. Product with BOP = 1.8 mT typ.
Table 16
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test Circuit
Operation point*1 S pole BOP − 0.9 1.8 2.7 mT 5
Release point*2 N pole BRP − −2.7 −1.8 −0.9 mT 5
Hysteresis width*3 BHYS B
HYS = BOP − BRP − 3.6 − mT 5
3. Product with BOP = 3.0 mT typ.
Table 17
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit Test Circuit
Operation point*1 S pole BOP − 1.4 3.0 4.0 mT 5
Release point*2 N pole BRP − −4.0 −3.0 −1.4 mT 5
Hysteresis width*3 BHYS B
HYS = BOP − BRP − 6.0 − mT 5
*1. BOP: Operation point
BOP is the value of magnetic flux density when the output voltage (V OUT) changes after the magnetic flux density applied
to the S-5725 Series by the magnet (S pole) is increased (by moving the magnet closer).
VOUT retains the status until a magnetic flux density of the N pole higher than BRP is applied.
*2. BRP: Release point
BRP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied
to the S-5725 Series by the magnet (N pole) is increased (by moving the magnet closer).
VOUT retains the status until a magnetic flux density of the S pole higher than BOP is applied.
*3. BHYS: Hysteresis width
BHYS is the difference between BOP and BRP.
Remark The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss.
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 15
Test Circuits
1. Product without power-down function
S-5725
Series
VDD
VSS
OUT A
V
S-5725
Series
VDD
VSS
OUT A
V
Figure 10 Test Circuit 3 Figure 11 Test Circuit 4
S-5725
Series
VDD
VSS
OUT
V
R
*1
100 kΩ
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 12 Test Circuit 5
S-5725
Series
VDD
VSS
OUT
A R
*1
100 kΩ
S-5725
Series
VDD
VSS
OUT A
V
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 8 Test Circuit 1 Figure 9 Test Circuit 2
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
16
2. Product with power-down function (SNT-4A)
A
V
VSS
S-5725
Series
VDD
OUT
CE
A
V
VSS
S-5725
Series
VDD
OUT
CE
Figure 15 Test Circuit 3 Figure 16 Test Circuit 4
S-5725
Series
VDD
VSS
OUT
A
R*1
100 kΩ
CE
A
V
VSS
S-5725
Series
VDD
OUT
CE
*1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 13 Test Circuit 1 Figure 14 Test Circuit 2
V
R*1
100 kΩ
VSS
S-5725
Series
VDD
OUT
CE
S-5725
Series
VDD
VSS
OUT
A
R*1
100 kΩ
CE
*1. Resistor (R) is unnecessary for the CMOS
output product. *1. Resistor (R) is unnecessary for the CMOS
output product.
Figure 17 Test Circuit 5 Figure 18 Test Circuit 6
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 17
VDD
VSS
OUT
CE
AS-5725
Series
VDD
VSS
OUT
CE
AS-5725
Series
Figure 19 Test Circuit 7 Figure 20 Test Circuit 8
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
18
Standard Circuits
1. Product without power-down function
S-5725 Series
VDD
VSS
OUT
R
*1
100 k
Ω
C
IN
0.1
μ
F
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 21
2. Product with power-down function (SNT-4A)
S-5725 Series
VDD
VSS
OUT
R
*1
100 k
Ω
CE
C
IN
0.1
μ
F
V
DD
or
V
SS
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 22
Caution The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 19
Operation
1. Direction of applied magnetic flux
The S-5725 Series detects t he magnetic flux density which is vertical to the marking surface.
Figure 23 and Figure 24 show the direction in which magnetic flux is being applied.
1. 1 SOT-23-3 1. 2 SNT-4A
Marking surface
S
N
Marking surface
S
N
Figure 23 Figure 24
2. Position of Hall sensor
Figure 25 and Figure 26 show the position of Hall sensor.
The center of this Hall sensor is located in the area indicated by a circle, which is in the center of a package as
described below.
The following also shows the distance (typ. value) between t he marking surface and the chip surface of a package.
2. 1 SOT-23-3 2. 2 SNT-4A
1
Top view
2 3
0.7 mm (typ.)
The center of Hall sens or;
in this φ 0.3 mm
Top view
14
23
0.16 mm (typ.)
The center of Hall sensor;
in this φ 0.3 mm
Figure 25 Figure 26
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
20
3. Basic operation
The S-5725 Series changes the output volt age (VOUT) according to the level of the magnetic f lux density and a polarity
change (N pole or S pole) applied by a magnet.
Definition of the magnetic field is performed every operating cycle indicated in " Electrical Characteristics".
3. 1 Product with VOUT = "L" at S pole detection
When the magnetic flux density of the S pole perpendicular to the marking surface exceeds the operation point
(BOP) after the S pole of a magnet is moved closer to the marking surf ace of the S-5725 Series, V OUT changes from
"H" to "L". When the N pole of a magnet is moved closer to the marking surface of the S-5725 Series and the
magnetic flux density of the N pole is higher than the release point (BRP), VOUT changes from "L" to "H". In case of
BRP < B < BOP, VOUT retains the status.
Figure 27 shows the relationship between the magnetic flux density and VOUT.
S poleN pole
Magnetic flux density (B)
V
OUT
0
B
RP
B
OP
B
HYS
H
L
Figure 27
3. 2 Product with VOUT = "H" at S pole detection
When the magnetic flux density of the S pole perpendicular to the marking surf ace exceeds BOP after the S pole of
a magnet is moved closer to the marking surface of the S-5725 Series, VOUT changes from "L" to "H". When the N
pole of a magnet is moved closer to the marking surface of t he S-5725 Series and the magnetic flux density of the
N pole is higher than BRP, VOUT changes from "H" to "L". In case of BRP < B < BOP, VOUT retains the status.
Figure 28 shows the relationship between the magnetic flux density and VOUT.
S pole
N pole
Magnetic flux density (B)
V
OUT
0
B
RP
B
OP
B
HYS
H
L
Figure 28
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 21
Precautions
• If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feed-
through current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.
• Note that the IC may malfunction if the power supply voltage rapidly changes.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Large stress on this IC may affect on the magnetic characteristics. Avoid large stress which is caused by bend and
distortion during mounting the IC on a board or handle after mounting.
• SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including
this IC of patents owned by a third party.
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
S-5725 Series Rev.2.4_00
Seiko Instruments Inc.
22
Marking Specifications
1. SOT-23-3
(1) to (3):
Product code (Refer to Product name vs. Product code.)
(4): Lot number
23
1
Top view
(1) (2) (3) (4)
Product name vs. Product code
1. 1 Nch open-drain output product
Product Code
Product Name (1) (2) (3)
S-5725CNBL9-M3T1U X 9 R
S-5725CNBL0-M3T1U X 9 S
S-5725CNBL1-M3T1U X 9 J
S-5725DNBL1-M3T1U X 9 K
S-5725ENBL9-M3T1U X 9 V
S-5725ENBL0-M3T1U X 9 A
S-5725ENBL1-M3T1U X 9 B
S-5725ENBH1-M3T1U X 9 L
1. 2 CMOS output product Product Code
Product Name (1) (2) (3)
S-5725CCBL9-M3T1U X 9 P
S-5725CCBL0-M3T1U X 9 Q
S-5725CCBL1-M3T1U X 9 T
S-5725DCBL1-M3T1U X 9 U
S-5725ECBL9-M3T1U X 9 W
S-5725ECBL0-M3T1U X 9 X
S-5725ECBL1-M3T1U X 9 C
S-5725ECBH1-M3T1U X 9 Y
HIGH-SPEED BIPOLAR HALL EFFECT LATCH
Rev.2.4_00 S-5725 Series
Seiko Instruments Inc. 23
2. SNT-4A
(1) to (3): Product code (Refer to Product name vs. Product code.)
1
2
4
3
Top view
(1) (2) (3)
Product name vs. Product code
2. 1 Nch open-drain output product
Product Code
Product Name (1) (2) (3)
S-5725HNBH0-I4T1U X 9 D
S-5725INBH0-I4T1U X 9 F
S-5725JNBH0-I4T1U X 9 H
2. 2 CMOS output product Product Code
Product Name (1) (2) (3)
S-5725HCBH0-I4T1U X 9 E
S-5725HCBH1-I4T1U X 9 M
S-5725ICBH0-I4T1U X 9 G
S-5725ICBH1-I4T1U X 9 N
S-5725JCBH0-I4T1U X 9 I
S-5725JCBH1-I4T1U X 9 O
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
No. MP003-C-P-SD-1.0
MP003-C-P-SD-1.0
SOT233-C-PKG Dimensions
2.9±0.2
0.95±0.1
1.9±0.2
+0.1
-0.06
0.16
0.4±0.1
1
23
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
No. MP003-C-C-SD-2.0
MP003-C-C-SD-2.0
SOT233-C-Carrier Tape
1.4±0.2
0.23±0.1
4.0±0.1
2.0±0.1
4.0±0.1
ø1.5 +0.1
-0
ø1.0
3.2±0.2
Feed direction
1
23
+0.25
-0
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
QTY. 3,000
No. MP003-Z-R-SD-1.0
MP003-Z-R-SD-1.0
SOT233-C-Reel
ø13±0.2
12.5max.
9.2±0.5
Enlarged drawing in the central part
1.2±0.04
0.65
0.2±0.05
0.48±0.02
0.08
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-4A-A-PKG Dimensions
PF004-A-P-SD-4.0
No. PF004-A-P-SD-4.0
+0.05
-0.02
12
3
4
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
PF004-A-C-SD-1.0
SNT-4A-A-Carrier Tape
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5
1.45±0.1 0.65±0.05
0.25±0.05
1
2
34
5°
No. PF004-A-C-SD-1.0
+0.1
-0
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY. 5,000
No. PF004-A-R-SD-1.0
PF004-A-R-SD-1.0
Enlarged drawing in the central part
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-4A-A-Reel
No.
TITLE
SCALE
UNIT mm
SNT-4A-A-Land Recommendation
Seiko Instruments Inc.
PF004-A-L-SD-4.0
No. PF004-A-L-SD-4.0
0.3
0.35
0.52
1.16
0.52
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.10 mm ~ 1.20 mm)
1
2
0.03 mm
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm).
1.
2.
※1. 䇋⊼ᛣ⛞Ⲭᓣⱘᆑᑺ(0.25 mm min. / 0.30 mm typ.)DŽ
※2. 䇋䇋࣓ᇕ㺙Ё䯈ᠽሩ⛞Ⲭᓣ (1.10 mm ~ 1.20 mm)DŽ
⊼ᛣ1. 䇋࣓㛖ൟᇕ㺙ⱘϟ䴶ࠋϱ㔥ǃ⛞䫵DŽ
2. ᇕ㺙ϟǃᏗ㒓Ϟⱘ䰏⛞㝰ᑺ (Ң⛞Ⲭᓣ㸼䴶䍋) 䇋ࠊ0.03 mmҹϟDŽ
3. 㝰ⱘᓔষሎᇌᓔষԡ㕂䇋Ϣ⛞Ⲭᓣᇍ唤DŽ
4. 䆺㒚ݙᆍ䇋খ䯙 "SNTᇕ㺙ⱘᑨ⫼ᣛ"DŽ
www.sii-ic.com
• The information described herein is subject to change without notice.
• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
• When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the approp riate governmental authority.
• Use of the information described herein for other purposes and/or reproduction or copying without the
express permissi on of Seiko Instruments Inc. is strictly prohibited.
• The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, vehicle equipment,
in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment, without prior
written permission of Seiko Instrum ents Inc.
• The products described herein are not de signed to be radiation-proof.
• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or comm unity damage that may ensue.
