Semiconductor, Inc. TC7116 TC7116A 1TC7117 TC7117A 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD FEATURES Low Temperature Drift Internal Reference TO71 G/T C7117 ones ceccnsensesnseenenes 80 ppm/C Typ TO71IGAITO7117A...ccsccssecserneerenee 20 ppm/C Typ Display Hold Function Directly Drives LCD or LED Display Guaranteed Zero Reading With Zero Input Low Noise for Stable Display ......... 2V or 200 mV Full-Scale Range (FSR) Auto-Zero Cycle Eliminates Need for Zero Adjustment Potentiometer True Polarity Indication for Precision Null Applications Convenient 9V Battery Operation (TC7116/TC7116A) High Impedance CMOS Differential Inputs.... 10120 Low Power Operation ...........c:::cesccsssseeeesne 10 mW ORDERING INFORMATION PART CODE 6=LCD 7=LED A or blank* R (reversed pins) or blank (CPL pkg. only) * "A" parts have an improved reference TC TC711X x X XXX Package Code (see below): GENERAL DESCRIPTION The TC7116A/TC7117A are 3-1/2 digit CMOS analog- to-digital converters (ADCs) containing all the active components necessary to construct a 0.05% resolution measurement system. Seven-segment decoders, polarity and digit drivers, voltage reference, and clock circuit are integrated on-chip. The TC7116A drives liquid crystal displays (LCDs) and includes a backplane driver. The TC7117A drives common anode light emitting diode (LED) displays directly with an 8-mA drive current per segment. These devices incorporate a display hold (HLDR) function. The displayed reading remains indefinitely, as long as HLDR is held high. Conversions continue, but output data display latches are not updated. The reference low input (VReEF) is not available as it is with the TC7106/ 7107. Vrer is tied internally to analog common in the TC7116A/7117A devices. The TC7116A/7117A reduces linearity error to less than 1 count. Roll-over error (the difference in readings for equal magnitude but opposite polarity input signals) is below +1 count. High-impedance differential inputs offer 1 pA leakage current and a 10'2Q input impedance. The 15 iVp-p noise performance guarantees a rock solid reading. The auto-zero cycle guarantees a zero display reading with a OV input. The TC7116A and TC7117A feature a precision, low- drift internal reference, and are functionally identical to the TC7116/TC7117. A low-drift external reference is not normally required with the TC7116A/TC7117A. Package Temperature 0.1 UF DISPLAY HOLD LCD DISPLAY (TC7116/7116A) Code Package Range 3a] aa] OR COMMON ANODE LED - 7 on ALOR DISPLAY (1C711777117A} CKW 44-Pin PQFP 0C to +70C ima aif EF CREF CLW 44-Pin PLCC 0C to +70C anacog YN 22-28 7 7 0.01 pF = CPL 40-Pin Plastic DIP 0C to +70C INPUT HF all vig POL GMssey |eackeLane JL 40-Pin CerDIP 25C to +85C ANaLog BR/GNO 121 DRIVE 32 COMMON AVAILABLE PACKAGES wv" = 40-Pin Plastic 40-Pin CerDIP aay. TOTTIBIA DIP BUFF TC7117/A a7 ka =w gq K qe 0.47 UF vi 47 & 4 & sl q E E 0.22 pF 4 EK Ee 7A Vint vw y E g [> 44-Pin Plastic Quad Fiat OSC, O8Cg OSC, TO ANALOG BS 4 ie Package Formed Leads 35) 381 Coscl 40 COMMON (PIN 32) [> o b Rog100pr/ 2 CONVERSIONS/SEC g ER AA 3 Be 100 ka ER E 44-Pin Plastic Chip Carrier PLCC Figure 1. Typical TC7116/A/7/A Operating Circuit % TELCOM SEMICONDUCTOR, INC. TC7VGIAT117/0-7 10/18/96 3-203TC7116 TC7116A TC7117 TC7117A ABSOLUTE MAXIMUM RATINGS* Supply Voltage TC7116/TC7116A: Vt tO Vo oe eeeeereteeerereee TC7117/TC7117A: V* to GND V- to GND Analog Input Voltage (Either Input) (Note 1) ........ Vt to V- Reference Input Voltage (Either Input) ....0...0.00. Vt to V- Clock Input 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD Operating Temperature a Od D)-\\/ (0, > OC to +70C P? Device oo... 7 25C to +85C Storage Temperature 0.0... 65C to +150C Lead Temperature (Soldering, 10 sec)... +300C Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may aiiect device reliability. TO7116/TC7116A nc ccccerecseeetseceneesteeeee TC7117/TC7117A.... Package Power Dissipation, Ta < 70C (Note 2) CerDIP occ cece cee ctectesenesseeeneesersaeecentestaeteas 2.29W Plastic DIP .........ceeeeeeecsneeteetresesssneeeneerereeteeete 1.23W Plastic Chip Carrier (PLCC)... ccceeereerees 1.23W Plastic Quad Flat Package (PQFP) ............. 1.00W ELECTRICAL CHARACTERISTICS (Note 3) Parameter Test Conditions Min Typ Max Unit Zero Input Reading Vin = OV _ +0 ~ Digital Full Scale = 200 mV Reading Ratiometric Reading Vin = VREF 999 | 999/1000) 1000 Digital Veer = 100 mV Reading Roll-Over Error (Difference in Vin = +Vin = 200 mV or = 2V -1 +0.2 +1 Counts Reading for Equal Positive and Negative Readings Near Full Scale) Linearity (Maximum Deviation From Full Scale = 200 mV or 2V -1 +0.2 +1 Counts Best Straight Line Fit) Common-Mode Rejection Ratio (Note 4) Vom = +1V, Vin = OV _ 50 pViVv Full Scale = 200 mV Noise (Peak-to-Peak Value Not Vin = OV _ 15 pV Exceeded 95% of Time) Full Scale = 200 mV Leakage Current at input Vin = OV 1 10 i pA Zero Reading Drift Vin = OV C Device: 0C to +70C 0.2 1 uvieC P Device: -25C to +85C 1 2 pv/?C. Scale Factor Temperature Coefficient Vin = 199 mV C Device: 0C to +70C _ 1 5 ppm/?c (Ext Ref = 0 ppm/C) I Device: -25C to +85C _ _ 20 ppnv/c Input Resistance, Pin 1 Note 6 30 70 kQ Vit, Pin 1 TC7116/A Only _ Test+1.5 V Vit, Pin 1 TC7117/A Only _ _ GND +1.5; V Vin, Pin 1 Both Vt=-15 _ Vv Supply Current (Does Not Include Vin = OV _ 0.8 1.8 mA LED Current for 7117/A) Analog Common Voltage 25 kQ Between Common 2.4 3.05 3.35 Vv (With Respect to Positive Supply) and Positive Supply Temperature Coefficient of Analog Common "C" Device: 0C to +70C (With Respect to Positive Supply) TC7116A/TC7117A _ 20 50 ppm/C TC7116/TC7117 _ 80 ppm/C 3-204 %yY TELCOM SEMICONDUCTOR, INC.3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A ELECTRICAL CHARACTERISTICS (Cont.) Parameter Test Conditions Min Typ Max Unit Temperature Coefficient of Analog Common "I" Device: -25C to +85C _ _ 75 ppm/C (With Respect to Positive Supply) 25 kQ Between Common and Positive Supply (TC7116A/TC7117A) _ i TC7116/TC7116A ONLY Peak-to-Peak Vt ta V7 =9V 4 5 6 Vv Segment Drive Voltage (Note 5) _ TC7116/TC7116A ONLY Peak-to-Peak Vt to VW" =9V 4 5 6 Vv Backplane Drive Voltage (Note 5) ! TC7117/TC7117A ONLY Segment Vt=5V 5 8 mA Sinking Current (Except Pin 19) Segment Voltage = 3V TC7117/TC7117A ONLY Segment Vt = 5V 10 16 _ mA Sinking Current (Pin 19 Only) Segment Voltage = 3V NOTES: 1. Input voltages may exceed supply voltages, provided input current is limited to +100 LA. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Unless otherwise noted, specifications apply at Ta = +25C, fotock = 48 kHz. TC7116/TC7116A and TC7117/TC7117A are tested in the circuit of Figure 1. 4. Reter to "Differential Input" discussion. 5. Backplane drive is in-phase with segment drive for OFF segment, 180 out-of-phase for ON segment. Frequency is 20 times conversion rate. Average DC component is less than 50 mV. 6. The TC7116/TC7116A logic inputs have an internal pull-down resistor connected fram HLDR, pin 1 to TEST, pin 37. The T67117/TC7117A logic inputs have an internal pull-down resistor connected from HLDR, pin 1 to GND, pin 21. yy TELCOM SEMICONDUCTOR, INC. 3-205TC7116 TC7116A TC07117 TC7117A PIN CONFIGURATIONS 3-1/2 DIGIT ANALOG-TO-DIGITAL. CONVERTERS WITH HOLD NOTES: 1. NC =No internal connection. should be made. 2. Pins 9, 25, 40, and 56 are connected to the die substrat HupR [74 Je ~ [40] osc, D, [2] 38] osc2 c, [3] [38] oscg B, [4] 37] TEST ts A,[5] [36] Vier F; [6] 35] Ve o (7 ] [34] Cher | Er [8] 7 [33] Cher oe] te7tier. = [2 mele t eTeAIPL COMMON C2 fo} re7izce. [Si] vin 1C7117ACPL - to's Bg [11 | (PDIP) [30] Vin Ag [12] [28] Caz Fe [13] [28] VeurF E2 [14] [27] Vint Dy [15] 26] v~ Bg [7s Eat | mS Fg Liz a] cg 100's e, [i FS] A, 1000's > ABg [19 | [22] G3 pot [20] 21] BP/GND (MINUS SIGN) (TC7116/7117) (TC7T416ANTC7117A) r no, FE 6 000 8 wu tego zt 2SSskea Cel(si (413) 211 | f44) [43] [42] [41] [20] [@} 39] v* 38] CREF 37] CREF Wy 36] COMMON TC7116CLW S5}IN HI TC7116ACLW 34] NC TCT117CLW TC7117ACLW 33] IN LO (PLCC) 32] az 131] BUFF 30] INT [21] Pea] Tes] Tea] j25] [26} [27] ze) o 3 3 52 g<acos HLDR [14 | [40] oscy D, [2] [39] osce 1 [3] 138] osc B, [4] 37] TEST ts Ay [5] [36] Viner F, [a] 35] V+ @ [7] [34] Cher | Fi [8 WEB crer 9 TC7116NWL 32 o2 [9 TC7116ANL [32] common c,fo} termine Pat) vi, TC7117AWL - 10's B [it {CerDIP) [30] Vin Ap [12] [28] Caz Fo [13] [28] VeuFF E2 [14] [27] Vint Dg [45] 26] v- be [is 3] og ms Fs G7 [2a] cg 100's Eg [18] [23] Ay 1000's > AB, [19] 22] G3 pot [20] 21] BP/GND (MINUS SIGN) (707116/7117) (TCTH1SAITC7117A} z = wis uo uu 9 it we eeSzzsezEL [a4] [43] [22] [41] [40] [sa] [38] (57) [36] [35] [34 f ne [1] ne [2] test [3] osc; [4] yy ne [5| TC7116CKW osc, [6 TC7116ACKW TC7117CKW osc, [7] TC7117ACKW HLoR [6] (FLAT PACKAGE) b, [9] cy lig B, [| [raf [a3] [aa] Tas] [9] [17] [19] [is] leo] {21} [zl ee re we NNN NUK OD <keowoacmdatwa e. The potential at these pins is approximately v* No external connections 3-206 QY TELCOM SEMICONDUCTOR, INC.3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A PIN DESCRIPTION 40-Pin PDIP/ 44-Pin 40-PinCerDIP Plastic Quad Pin Number Flat Package Normal Pin Number Symbol Description 1 8 HLDR Hold pin, Logic 1 holds present display reading. 2 9 Dy Activates the D section of the units display. 3 10 Cy Activates the C section of the units display. 4 11 By Activates the B section of the units display. 5 12 Ai Activates the A section of the units display. 6 13 Fy Activates the F section of the units display. 7 14 Gy Activates the G section of the units display. 8 15 Ey Activates the E section of the units display. 9 16 De Activates the D section of the tens display. _ 10 17 Co Activates the C section of the tens display. 11 18 Bo Activates the B section of the tens display. 12 19 Ao Activates the A section of the tens display. 13 20 Fo Activates the F section of the tens display. 14 21 Eo Activates the E section of the tens display. 15 22 D3 Activates the D section of the hundreds display. 16 23 Bg Activates the B section of the hundreds display. 17 24 Fs Activates the F section of the hundreds display. 18 25 E3 Activates the E section of the hundreds display. 19 26 ABs Activates both halves of the 1 in the thousands display. 20 27 POL Activates the negative polarity display. 21 28 BP LCD backplane drive output (TC7116/TC7116A). GND Digital ground (TC7117/TC7117A). 22 29 G3 Activates the G section of the hundreds display. 23 30 A3 Activates the A section of the hundreds display. 24 31 C3 Activates the C section of the hundreds display. 25 32 Ge Activates the G section of the tens display. 26 34 vw Negative power supply voltage. 27 35 VINT Integrator output. Connection paint for integration capacitor. See Integration Capacitor section for additional details. 28 36 VeuUFF Integration resistor connection. Use a 47 kQ resistor for 200 mV full-scale range and a 470 kQ resistor for 2V full-scale range. 29 37 Caz The size of the auto-zero capacitor influences system noise. Use a 0.47 uF capacitor for 200 mV full scale and a 0.047 uF capacitor for 2V full scale. See Auto-Zero Capacitor paragraph for more details. 30 38 Vin The analog LOW input is connected to this pin. 31 39 "iN The analog HIGH input is connected to this pin. 39 40 COMMON This pin is primarily used to set the analog common- mode COMMON voltage for battery operation or in systems where the input signal is referenced to the power supply. See Analog Common paragraph for more details. It also acts as a reference voltage source. TELCOM SEMICONDUCTOR, INC. 3-2073-1/2 DIGIT ANALOG-TO-DIGITAL TC7116 CONVERTERS WITH HOLD TC7116A TC07117 TC7117A PIN DESCRIPTION (Cont.) 40-Pin CerDIP 44-Pin 40-Pin PDIP Plastic Quad Pin Number Flat Package Normal Pin Number Symbol Description 33 41 Crer See pin 34. 34 42 Cher A 0.1 UWF capacitor is used in most applications. If a large, common-mode voltage exists (e.g., the Vin pin is not at analog common), and a 200 mV scale is used, a 1 pF capacitor is recommended and will hold the roll-over . error to 0.5 count. 35 43 vr Positive power supply voltage. 36 44 "REF The analog input required to generate a full-scale output (1999 counts}. Place 100 mV between pins 32 and 36 for 199.9 mV full scale. Place 1V between pins 32 and 36 for 2V full scale. See paragraph on Reference Voltage. 37 3 TEST Lamp test. When pulled HIGH (to V*), all segments will be turned on and the display should read 1888. It may also be used as a negative supply for externally- generated decimal points. See Test paragraph for more details. 38 4 OSC3 See pin 40. 39 6 OSC, See pin 40. 40 7 Osc, Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings per sec), connect pin 40 to the junction of a 100 kQ resistor and a 100 pF capacitor. The 100 kQ resistor is tied to pin 39 and the 100 pF capacitor is tied to pin 38. 3-208 TELCOM SEMICONDUCTOR, INC.3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A + VIN ANALOG COMMON INTEGRATOR TO DIGITAL SECTION COMPARATOR ww TC7116 TC7116A TC7117 VIN TCTHITA Figure 3. Analog Section of TC7116/TC7116A and TC7117/TC7117A ANALOG SECTION (All Pin designations refers to 40-Pin Dip) Figure 3 shows the block diagram of the analog section for the TC7116/TC7116A and 107117/TC7117A. Each measurement cycle is divided into three phases: (1) auto- zero (A-Z), (2) signal integrate (INT), and (3) reference integrate (REF) or deintegrate (DE). Auto-Zero Phase High and low inputs are disconnected from the pins and internally shorted to analog common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the system to charge the auto-zero capacitor (Caz) to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the com- parator is included in the loop, A-Z accuracy is limited only by system noise. The offset referred to the input is less than 10 LV. Signal-Integrate Phase The auto-zero loop is opened, the internal short is removed, and the internal high and low inputs are con- nected to the external pins. The converter then integrates the differential voltages between Vix and Vin for a fixed time. This differential voltage can be within a wide com- mon-mode range; 1V of either supply. However, if the input signal has no return with respect to the converter power supply, Vin can be tied to analog common to establish the correct common-mode voltage. At the end of this phase, the polarity of the integrated signal is determined. y TELCOM SEMICONDUCTOR, INC. Reference Integrate Phase The final phase is reference integrate, or deintegrate. Input low is internally connected to analog common and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. The digital reading displayed is: Vin 1000 x -N- VREF Reference The positive reference voltage (VRer) is referred to analog common. Differential Input This input can accept differential voltages anywhere within the common-mode range of the input amplifier or, specifically, from 1V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86 dB, typical. However, since the integrator also swings with the common-mode voltage, care must be exercised to ensure that the integrator output does not saturate. A worst- case condition would be a large, positive common- mode voltage with a near full-scale negative differential input voltage. The negative-input signal drives the integra- tor positive when most of its swing has been used up by the positive common-mode voltage. For these critical applica- tions, the integrator swing can be reduced to less than the 3-2093-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A vt yr 6.8 KO TC7116 TC7116A Terii7a | 20Ka Vinee Ye Te94910zM 1.2 } REF COMMON [ we nbee vr ' veiw l 4 wy 1 4049 ! 1 i TC7116 ' ' TC7116A ' ' ' TOLCD BP t DECIMAL 1 ' POINT a= =o GND TESTIS TO LCD L______ BACK- PLANE Figure 4. Using an External Reference recommended 2V full-scale swing with little loss of accu- racy. The integrator output can swing within 0.3V of either supply without loss of linearity. Analog Common This pin is included primarily to set the common-mode voltage for battery operation (TC7116/TCG7116A) or for any system where the input signals are floating with respect to the power supply. The analog common pin sets a voltage approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog common has some attributes ofa reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the analog common voltage will have a low voltage coefficient (0.001%/ %), jow output impedance (=15Q), and a temperature coef- ficient of less than 20 ppm/C, typically, and 50 ppm maxi- mum. The 1C7116/TC7117 temperature coefficients are typically 80 ppm/C. An external reference may be used, if necessary, as shown in Figure 4. Analog common is also used as Vin return during auto- zero and deintegrate. If Vinis different from analog common, a common-mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications, Vin will be set at a fixed, known voltage (power supply common for instance). In this application, analog common should be tied to the same point, thus removing the common-mode voltage from the converter. The same holds true for the reference voltage; if it can be conveniently referenced to analog common, it should be. This removes the common-mode voltage from the reference system. Within the IC, analog common is tied to an N-channel FET that can sink 30 mA or more of current to hold the voltage 3V below the positive supply (when a load is trying 3-210 Figure 5. Simple Inverter for Fixed Decimal Point HS DECIMAL| . DECIMAL POINT 1 107116 SELECT Ty POINTS TC7116A I D+ I Figure 6. Exclusive OR Gate for Decimal Point Drive TC7116/TC7116A TC7117/TC7117A TO, COUNTER, 38 ' TO TEST PIN ON TC7116/TC7116A TO GROUND PIN ON 77117/7C7117A Figure 7. Clock Circuits to pull the analog common line positive). However, there is only 10 WA of source current, so analog common may easily be tied to a more negative voltage, thus overriding the internal reference. TEST The TEST pin serves two functions. On the TC7117/ TC7117A, it is coupled to the internally-generated digital supply through a 5000 resistor. Thus, it can be used as a | TELCOM SEMICONDUCTOR, INC.3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A negative supply for externally-generated segment drivers, such as decimal points or any other presentation the user may want to include on the LCD. (Figures 5 and 6 show such an application.) No more than a 1 mA load should be applied. The second function is a lamp test." When TEST is pulled HIGH (to V*), all segments will be turned ON and the display should read -1888. The TEST pin will sink about 10 mA under these conditions. DIGITAL SECTION Figures 8 and 9 show the digital section for TC7116/ TC7116A and TC7117/TC7117A, respectively. For the TC7116/TC7116A (Figure 8), an internal digital ground is generated from a 6V zener diode and a large P-channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the backplane (BP) voltage is switched. The BP frequency is the clock fre- quency +800. For 3 readings per second, this is a 60-Hz square wave with a nominal amplitude of 5V. The seg- ments are driven at the same frequency and amplitude, and are in-phase with BP when OFF, but out-of-phase when ON. In all cases, negligible DC voltage exists across the segments. Figure 9 is the digital section of the TC7117/TC7117A. It is identical to the TC7116/TC7116A, except that the regulated supply and BP drive have been eliminated, and the segment drive is typically 8 MA. The 1000's output (pin 19) sinks current from two LED segments, and has a 16-mA drive capability. The TC7117/TC7117A are designed to drive common anode LED displays. In both devices, the polarity indication is ON for analog inputs. If Viyand Vin are reversed, this indication can be reversed also, if desired. wv 86 86 8 TC7116A BACKPLANE 21 ' I ' t LCD PHASE DRIVER ' ! TYPICAL SEGMENT OUTPUT, ' Vv 1 ; 7-SEGMENT| |7-SEGMENT| {7-SEGMENT] | . 55 f ! 0.5 mA DECODE DECODE DECODE , a 4 [SEGMENT HH Hi HW OUTPUT 1 4 LATCH a i INTERNAL DIGITAL GROUND ' THOUSANDS HUNDREDS|-@-] TENS /# UNITS [* \ 1 1 TO SWITCH DRIVERS ~ \ FROM COMPARATOR OUTPUT as! oy Vv CLOCK ~70 kQ ' > 62V 37 +4 1 LOGIC CONTROL AAA TEST [ q VtH =1V 5002 F 1 26, _ 40 39 3a | INTERNAL DIGITAL GROUND 1 Vv seme pee eee eseunue (eee eeaese maanmoe ene ane seen een ee ee =m Osc, OSCo OSC3 HLDR Figure 8. TC7116/TC7116A Digital Section wy TELCOM SEMICONDUCTOR, INC. 3-211TC7116 TC7116A TC7117 TC7117A System Timing The clocking method used for the TC7116/TC7116A and TC7117/TC7117A is shown in Figure 9. Three clocking methods may be used: (1) An external oscillator connected to pin 40. (2) Acrystal between pins 39 and 40. (3) An RC network using all three pins. The oscillator frequency is + 4 before it clocks the decade counters. it is then further divided to form the three convert-cycle phases: signal integrate (1000 counts), refer- ence deintegrate (0 to 2000 counts), and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference deintegrate. This makes a complete measure cycle of 4000 (16,000 clock pulses) independent of input voltage. For 3 readings per second, an oscillator frequency of 48 kHz would be used. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD To achieve maximum rejection of 60-Hz pickup, the signal-integrate cycle should be a multiple of 60 Hz. Oscil- lator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz, 48 kHz, 40 kHz, etc. should be selected. For 50 Hz rejection, oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5 readings per second) will reject both 50 Hz and 60 Hz. HOLD Reading Input When HLOR is at a logic HIGH the latch will not be updated. Analog-to-digital conversions will continue but will not be updated until HLDR is returned to LOW. To continu- ously update the display, connectto test (TC7116/TC7116A) or ground (TC7117/TC7117A), or disconnect. This input is CMOS compatible with 70 kQ typical resistance to TEST (TC7116/TC7116A) or ground (TC7117/TC7117A). ror? i 8 @ 8 TC7117A we eee eee ee bl bl ew ld bt eh Lt ee, a TYPICAL SEGMENT OUTPUT, v = 7-SEGMENT| |7-SEGMENT] |7-SEGMENT 1 0.5 mA DECODE DECODE DECODE 1 a . TO ' SEGMENT 1 ' FI mma LATCH \ 4 DIGITAL GROUND ' 1 ! THOUSANDS}-<+4 HUNDREDS| + TENS [+t UNITS | ' ! ! TO SWITCH DRIVERS ~ , a vt FROM COMPARATOR OUTPUT 354 yt Y 37 2 TEST +4 >] CONTROL LOGIC soon . 214 DIGITAL V~WA__ GND ' 1 ~70 kQQ a Le ee ee ad onc eee enneee eaneeeeee HLDR Figure 9. TC7117/TC7117A Digital Section 3-212 % TELCOM SEMICONDUCTOR, INC.3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A C7117 TC7117A COMPONENT VALUE SELECTION Auto-Zero Capacitor The size of the auto-zero capacitor has some influ- ence on system noise. For 200 mV full scale, where noise is very important, a 0.47 uF capacitor is recommended. On the 2V scale, a 0.047 uF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Capacitor A 0.1 uF capacitor is acceptable in most applications. However, where a large common-mode voltage exists (i.e., the Vin pin is not at analog common), and a 200-mV scale is used, a larger value is required to prevent roll-over error. Generally, 1 uF will hold the roll-over error to 0.5 count in this instance. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not saturate the integrator swing (approximately 0.3V from either supply). In the TC7116/TC7116A or the TC7117/ TC7117A, when the analog common is used as a reference, anominal 2V full- scale integrator swing is acceptable. For the TC7117/TC7117A, with 5V supplies and analog com- mon tied to supply ground, a+3.5V to +4V swing is nominal. For 3 readings per second (48 kHz clock), nominal values for Ciwr are 0.22 1 1F and 0.10 uF, respectively. If different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the output swing. The integrating capacitor must have low dielectric ab- sorption to prevent roll-over errors. Polypropylene capaci- tors are recommended for this application. Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100 LA of quiescent current. They can supply 20 LA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470 kQ is near optimum and, similarly, 47 kQ for 200 mV full scale. Oscillator Components For all frequency ranges, a 100-kQ resistor is recom- mended; the capacitor is selected from the equation: 45 fa. RC For a 48 kHz clock (3 readings per second), C = 100 pF. | TELCOM SEMICONDUCTOR, INC. Reference Voltage To generate full-scale output (2000 counts), the analog input requirement is Vij = 2 Vrer. Thus, for the 200 mV and 2V scale, Veer should equal 100 mV and 1V, respectively. In many applications, where the ADC is connected to a transducer, a scale factor exists between the input voltage and the digital reading. For instance, in a measuring system the designer might like to have a full-scale reading when the voltage from the transducer is 700 mV. Instead of dividing the input down to 200 mV, the designer should use the input voltage directly and select Vaer = 350 mV. Suitable values for integrating resistor and capacitor would be 120 kQ and 0.22 uF. This makes the system slightly quieter and also avoids a divider network on the input. The TC7117/TC7117A, with +5V supplies, can accept input signals up to t4V. Another advantage of this system is when a digital reading of zero is desired for Vin + 0. Temperature and weighing systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between V4iy and analog common, and the variable (or fixed) offset voltage between analog com- mon and Vin. TC7117/TC7117A POWER SUPPLIES The TC7117/TC7117A are designed to operate from +5V supplies. However, ifanegative supply is not available, it can be generated with a TC7660 DC-to-DC converter and two capacitors. Figure 10 shows this application. In selected applications, a negative supply is not re- quired. The conditions for using a single +5V supply are: (1) The input signal can be referenced to the center of the common-mode range of the converter. (2) The signal is less than 1.5V. (3) An external reference is used. ASV +] 35 i V" vier 3S wv 9 LED 9 DRIVE wy com|22 { g TC7117 vin wd TC7117A L Vin 8 Vin ne y~ aude HFT 4 Te7e60 |5 (sv) |?6 . = 10pF Figure 10. Negative Power Supply Generation With TC7660 3-2133-1/2 DIGIT ANALOG-TO-DIGITAL TC7116 CONVERTERS WITH HOLD TC7116A TC7117 TC7117A TYPICAL APPLICATIONS SET Vper= 100 mv xo 100 kQ 97 A 100 pF 36 To 350 22 Ke Loaic ~y 2h TC7116 TC7116A 3 L Hb 2 z iO _ OF z < TO DISPLAY TO BACKPLANE GND Ww C7116 TC7116A UUT BC ae UR D4023 |___ { OR 7410 CD4077 O/R = OVERRANGE UR = UNDERRANGE Figure 11. TC7116/TC7116A Using the Internal Reference (200 mV Full Scale, 3 Readings Per Second (RPS) Figure 13. Circuit for Developing Underrange and Overrange Signals from TC7116/TC7116A Outputs SET V, = 100 mV -T REF 100 kQ 7 oH 100 pF TO7117 TC7117A 40 3s 38 37 36 SET Vpgr= 100 mV Ln 10 kQ wr 2 } Fr 31 0.01 pF 1MQ IN Tc7117 30 | Oo rt Te7117a 29 PR OAZHA ai = 28 27 = 0.22 oH 26 25 24 23 22 ) 21 1 TO DISPLAY Figure 12. 1C7117/TC7117A Internal Reference (200 mV Full Scale, 3 RPS, Vin Tied to GND for Single-Ended Inputs.) 3-214 Figure 14. TC7117/TC7117A With a 1.2V External Band-Gap Reference (Vin Tied to Common) % TELCOM SEMICONDUCTOR, INC.3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD TC7116 TC7116A TC7117 TC7117A __ SET Veer = 1V 40 pW AAA 100 kQ. per 39 38 PJ 37p 100 pF 36 24 Bah 2 35 Bah 2 Love 34 PP gi pe] 25 ko 33 D"~ 1MQ + yY 32 pt}? WW te7116 31 -}__ 0.01 pF IN ph Tc7116A 30 v TC7117A 28 27b4 a6 PRs ly 230 240 230 20 ag) 2 21 SET Vagr= 100 mv 10 kQ 10kQ YW 2 te71i7 31 tTc7117A 30 29 28 27 26 25 24 Figure 15. Recommended Component Values for 2V Full Scale (7C7116/TC7116A and TC7117/TC7117A) APPLICATIONS INFORMATION The TC7117/TC7117A sink the LED display current, causing heat to build up in the IC package. If the internal voltage reference is used, the changing chip temperature can cause the display to change reading. By reducing the LED common anode voltage, the T07117/TC7117A pack- age power dissipation is reduced. Figure 17 is a curve-tracer display showing the relation- ship between output current and output voltage for typical TC7117CPL/TC7117ACPL devices. Since a typical LED has 1.8V across it at 8 mA and its common anode is connected to +5V, the TC7117/TC7117A output is at 3.2V (Point A, Figure 17). Maximum power dissipation is 8.1 mA x 3.2V x 24 segments = 622 mW. However, notice that once the TC7117/TC7117A's out- put voltage is above 2V, the LED current is essentially constant as output voltage increases. Reducing the output voltage by 0.7V (Point B Figure 17) results in 7.7 mA of LED current, only a 5% reduction. Maximum power dissipation is now only 7.7 mA x 2.5V x 24 = 462 mW, a reduction of 26%. An output voltage reduction of 1V (Point C) reduces LED current by 10% (7.3 mA), but power dissipation by 38% (7.3 mA x 2.2V x 24 = 385 mW). | TELCOM SEMICONDUCTOR, INC. Figure 16. TC7117/TC7117A Operated from Single +5V Supply (An External Reference Must Be Used in This Application.) Reduced power dissipation is very easy to obtain. Figure 18 shows two ways: Either a5.1Q, 1/4W resistor, or a 1A diode placed in series with the display (but notin series with the TC7117/TC7117A). The resistor reduces the TC7117/TC7117A's output voltage (when all 24 segments are ON) to Point C of Figure 17. When segments turn off, the output voltage will increase. The diode, however, will result in a relatively steady output voltage, around Point B. In addition to limiting maximum power dissipation, the resistor reduces change in power dissipation as the display changes. The effect is caused by the fact that, as fewer segments are ON, each ON output drops more voltage and current. For the best case of six segments (a 111 display) to worst case (a 1888 display), the resistor circuit will change about 230 mW, while a circuit without the resistor will change about 470 mW. Therefore, the resistor will reduce the effect of display dissipation on reference voltage drift by about 50%. The change in LED brightness caused by the resistor is almost unnoticeable as more segments tur off. If display brightness remaining steady is very important to the de- signer, a diode may be used instead of the resistor. 3-2153-1/2 DIGIT ANALOG-TO-DIGITAL TC7116 CONVERTERS WITH HOLD TC7116A TC7117 TC7117A 100 ka 40 Te7117 4 D TC7117A 1 10 20 Prreyr?ttrrrrrrrrri td yo I IV 2V 3V 4V 5V 1.5Q, 1/4W DISPLAY AW - 1 Ls 4n4oo1 - wee -1999 +} Figure 17. 1C7117/TC7117A Output Current vs Output Voltage Figure 18. Diode or Resistor Limits Package Power Dissipation 3-216 % TELCOM SEMICONDUCTOR, INC.