UPD78F0034BGC-8BS-A - Renesas Electronics

PD780024A, 780034A, 780024AY, 780034AY Subseries

8-Bit Single-Chip Microcontrollers

PD780021A

PD780031A

PD780021AY

PD780031AY

PD780022A

PD780032A

PD780022AY

PD780032AY

PD780023A

PD780033A

PD780023AY

PD780033AY

PD780024A

PD780034A

PD780024AY

PD780034AY

PD780021A(A)

PD780031A(A)

PD780021AY(A)

PD780031AY(A)

PD780022A(A)

PD780032A(A)

PD780022AY(A)

PD780032AY(A)

PD780023A(A)

PD780033A(A)

PD780023AY(A)

PD780033AY(A)

PD780024A(A)

PD780034A(A)

PD780024AY(A)

PD780034AY(A)

PD78F0034A

PD78F0034AY

PD78F0034B

PD78F0034BY

PD78F0034B(A)

PD78F0034BY(A)

Document No. U14046EJ3V0UD00 (3rd edition)

Date Published October 2003 N CP(K)

1999, 2003

User’s Manual

Printed in Japan

2User’s Manual U14046EJ3V0UD

[MEMO]

User’s Manual U14046EJ3V0UD

EEPROM, FIP, and IEBus are trademarks of NEC Electronics Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

4User’s Manual U14046EJ3V0UD

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

User’s Manual U14046EJ3V0UD

Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to use these

components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by

Philips.

The information in this document is current as of March, 2003. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or

data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all

products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer’s equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics’ willingness to support a given application.

(Note)

•

M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

"Standard":

"Special":

"Specific":

6User’s Manual U14046EJ3V0UD

Regional Information

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

[GLOBAL SUPPORT]

http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-558-3737

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China

Tel: 021-6841-1138

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 6253-8311

J03.4

EC Electronics (Europe) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 01

• Sucursal en España

Madrid, Spain

Tel: 091-504 27 87

Vélizy-Villacoublay, France

Tel: 01-30-67 58 00

• Succursale Française

• Filiale Italiana

Milano, Italy

Tel: 02-66 75 41

• Branch The Netherlands

Eindhoven, The Netherlands

Tel: 040-244 58 45

• Tyskland Filial

Taeby, Sweden

Tel: 08-63 80 820

• United Kingdom Branch

Milton Keynes, UK

Tel: 01908-691-133

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

User’s Manual U14046EJ3V0UD

Major Revisions in This Edition (1/3)

Page Description

Throughout Addition of the following products

PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A),

PD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A),

PD78F0034B, 78F0034B(A), 78F0034BY, 78F0034BY(A)

Addition of the following packages

• 64-pin plastic LQFP (GC-8BS type)

• 73-pin plastic FBGA (F1-CN3 type)

Addition of expanded-specification products to

PD780024A, 780034A Subseries

p.34 Addition of 1.1 Expanded-Specification Products and Conventional Products

p.54 Addition of 1.10 Correspondence Between Mask ROM Versions and Flash Memory Versions

p.54 Modification of 1.11 Differences Between Standard Grade Products and Special Grade Products

p.55 Addition of 1.12 Correspondence Between Products and Packages

p.74 Addition of 2.9 Correspondence Between Mask ROM Versions and Flash Memory Versions

p.75 Modification of 2.10 Differences Between Standard Grade Products and Special Grade Products

p.75 Addition of 2.11 Correspondence Between Products and Packages

p.84 Addition of description of pin processing in 3.2.18 VPP (flash memory versions only)

p.85 Modification of Table 3-1 Pin I/O Circuit Types

p.96 Addition of description of pin processing in 4.2.18 VPP (flash memory versions only)

p.97 Modification of Table 4-1 Pin I/O Circuit Types

p.108 Addition of description of program area in 5.1.2 Internal data memory space

pp.116, 117 Modification of Figure 5-14 Data to Be Saved to Stack Memory and Figure 5-15 Data to Be Restored from

Stack Memory

p.130 Modification of [Description example] in 5.4.4 Short direct addressing

pp.133 to 135 Addition of [Illustration] in 5.4.7 Based addressing, 5.4.8 Based indexed addressing, and 5.4.9 Stack

addressing

pp.140 to 160 Modification of port block diagram (Figures 6-2 Block Diagram of P00 to P03 to 6-23 Block Diagram of P74

and P75)

p.163 Addition of Table 6-6 Port Mode Registers and Output Latch Settings When Alternate Function Is Used

pp.171, 174 Addition of description of internal feedback resistor and oscillation stabilization time select register (OSTS) in

7.3 Clock Generator Control Registers

p.185 Modification of Figure 8-1 Block Diagram of 16-Bit Timer/Event Counter 0

pp.186, 187 Modification of Tables 8-2 TI00/TO0/P70 Pin Valid Edge and CR00, CR01 Capture Trigger and 8-3 TI01/

P71 Pin Valid Edge and CR00 Capture Trigger in 2nd edition to Table 8-2 CR00 Capture Trigger and Valid

Edges of TI00 and TI01 Pins and Table 8-3 CR01 Capture Trigger and Valid Edge of TI00 Pin (CRC02

= 1)

p.194 Modification of description procedure of each function in 8.4 Operation of 16-Bit Timer/Event Counter 0

p.208 Addition of Figure 8-26 PPG Output Configuration Diagram and Figure 8-27 PPG Output Operation Timing

p.209 Addition of 8.5 Program List

pp.216, 218 Modification of 8.6 (3) Capture register data retention timing and addition of (11) STOP mode or main

system clock stop mode setting

8User’s Manual U14046EJ3V0UD

Major Revisions in This Edition (2/3)

Page Description

p.220 Modification of Figures 9-1 Block Diagram of 8-Bit Timer/Event Counter 50 and 9-2 Block Diagram of 8-

Bit Timer/Event Counter 51

pp.224, 225 Deletion of Caution in Figures 9-5 Format of 8-Bit Timer Mode Control Register 50 (TMC50) and 9-6 Format

of 8-Bit Timer Mode Control Register 51 (TMC51)

p.231 Addition of [Setting] in 9.4.2 External event counter operation

p.232 Addition of description of frequency to [Setting] in 9.4.3 Square-wave output (8-bit resolution) operation

p.233 Addition of description of cycle and duty ratio to [Setting] in 9.4.4 8-bit PWM output operation

p.238 Addition of 9.5 Program List

p.200 in 2nd Deletion of 9.5 (2) Operation after compare register change during timer count operation in 2nd edition

edition

p.208 in 2nd Deletion of oscillation stabilization time select register (OSTS) from 11.3 Registers to Control Watchdog

edition Timer in 2nd edition

p.252 Modification of Figure 12-1 Block Diagram of Clock Output/Buzzer Output Controller

pp.259, 260 Modification of description in 13.2 (3) Sample & hold circuit, (4) Voltage comparator, and addition of (10)

ADTRG pin

p.266 Addition of Table 13-2 Sampling Time and A/D Conversion Start Delay Time of A/D Converter

pp.277, 278 Deletion of 13.6 (4) Noise countermeasures (contents of deletion are added to Figure 13-18 Example of

Connecting Capacitor to AVREF Pin and Figure 13-20 Example of Connection If Signal Source Impedance

Is High), and addition of (14) Input impedance of ANI0 to ANI7 pins

p.278 Modification of Table 13-3 Resistances and Capacitances of Equivalent Circuit (Reference Values)

p.281 Addition of Figure 14-2 Format of A/D Conversion Result Register 0 (ADCR0)

pp.281, 282 Modification of description in 14.2 (3) Sample & hold circuit, (4) Voltage comparator, and addition of (10)

ADTRG pin

p.288 Addition of Table 14-2 Sampling Time and A/D Conversion Start Delay Time of A/D Converter

pp.298, 299 Deletion of 14.6 (4) Noise countermeasures (contents of deletion are added to Figure 14-19 Example of

Connecting Capacitor to AVREF Pin and Figure 14-21 Example of Connection If Signal Source Impedance

Is High), and addition of (14) Input impedance of ANI0 to ANI7 pins

p.299 Modification of Table 14-3 Resistances and Capacitances of Equivalent Circuit (Reference Values)

p.302 Modification of Figure 16-1 Block Diagram of Serial Interface UART0

p.304 Move of description of asynchronous serial interface status register 0 (ASIS0) in 16.3 Registers to Control

Serial Interface UART0 to 16.2 Configuration of Serial Interface UART0

p.315 Addition of Caution in Figure 16-7 Error Tolerance (When k = 0 ), Including Sampling Errors

p.319 Modification of Caution in Figure 16-10 Timing of Asynchronous Serial Interface Receive Completion

Interrupt Request

pp.321, 326 Addition of (1) Registers to be used and (3) Relationship between main system clock and baud rate in

16.4.3 Infrared data transfer mode

p.328 Addition of Table 16-6 Register Settings

p.329 Modification of Figure 17-1 Block Diagram of Serial Interface SIO3n

pp.332, 333 Addition of Note 3 and Caution in Figures 17-2 Format of Serial Operation Mode Register 30 (CSIM30)

and 17-3 Format of Serial Operation Mode Register 31 (CSIM31)

p.339 Addition of Table 17-2 Register Settings

p.341 Modification of Figure 18-1 Block Diagram of Serial Interface IIC0

User’s Manual U14046EJ3V0UD

Major Revisions in This Edition (3/3)

Page Description

p.343 Unification of 18.2 (1) IIC shift register 0 (IIC0) and (4) IIC shift register 0 (IIC0) in 2nd edition, and (2) Slave

address register 0 (SVA0) and (3) Slave address register 0 (SVA0) in 2nd edition

p.360 Addition of description to “Transfer lines” in Figure 18-16 Wait Signal

p.362 Addition of description to Notes 1 and 2 in Table 18-2 INTIIC0 Timing and Wait Control

p.369 Modification of Figure 18-21 Master Operation Flowchart

p.374 Modification of 18.5.15 (2) Slave operation

p.396 Modification of (1) Start condition ~ address and (2) Data in Figure 18-23 Example of Master to Slave

Communication (When 9-Clock Wait Is Selected for Both Master and Slave)

p.399 Modification of Figure 18-24 Example of Slave to Master Communication (When 9-Clock Wait Is Selected

for Both Master and Slave)

p.405 Modification of (E) Software interrupt in Figure 19-1 Basic Configuration of Interrupt Function

p.407 Addition of Caution 5 in Figure 19-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)

p.410 Addition of Caution in Figure 19-5 Format of External Interrupt Rising Edge Enable Register (EGP),

External Interrupt Falling Edge Enable Register (EGN)

p.412 Addition of description and Remark in 19.4.1 Non-maskable interrupt request acknowledgment operation

p.415 Addition of description in 19.4.2 Maskable interrupt request acknowledgment operation

p.418 Addition of an item in Table 19-4 Interrupt Requests Enabled for Nesting During Interrupt Servicing

p.422 Addition of description of using expanded-specification products in CHAPTER 20 EXTERNAL DEVICE

EXPANSION FUNCTION

p.435 Addition of clock output and buzzer output in Table 21-1 HALT Mode Operating Statuses

p.438 Modification of clock output in Table 21-3 STOP Mode Operating Statuses

p.445 Revision of CHAPTER 23

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY

p.487 Addition of CHAPTER 25 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS: fX

= 1.0 TO 12 MHz)

p.518 Addition of CHAPTER 26 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS: fX = 1.0 TO 8.38

MHz)

p.550 Addition of CHAPTER 27 PACKAGE DRAWINGS

p.556 Addition of CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS

p.561 Revision of APPENDIX A DIFFERENCES BETWEEN

PD78018F, 780024A, 780034A, AND 780078

SUBSERIES

p.564 Revision of APPENDIX B DEVELOPMENT TOOLS

p.581 Addition of APPENDIX C NOTES ON TARGET SYSTEM DESIGN

The mark shows major revised points.

10 User’s Manual U14046EJ3V0UD

INTRODUCTION

Readers This manual has been prepared for user engineers who understand the functions of the

PD780024A, 780034A, 780024AY, and 780034AY Subseries and wish to design and

develop application systems and programs for these devices.

•

PD780024A Subseries

PD780021A, 780022A, 780023A, 780024A

PD780021A(A), 780022A(A), 780023A(A), 780024A(A)

•

PD780034A Subseries

PD780031A, 780032A, 780033A, 780034A, 78F0034A, 78F0034B

PD780031A(A), 780032A(A), 780033A(A), 780034A(A), 78F0034B(A)

•

PD780024AY Subseries

PD780021AY, 780022AY, 780023AY, 780024AY

PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)

•

PD780034AY Subseries

PD780031AY, 780032AY, 780033AY, 780034AY, 78F0034AY, 78F0034BY

PD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A), 78F0034BY(A)

Purpose This manual is intended to provide users an understanding of the functions described in

the organization below.

Organization The

PD780024A, 780034A, 780024AY, and 780034AY Subseries manual is separated

into two parts: this manual and the instructions edition (common to the 78K/0 Series).

PD780024A, 780034A, 780024AY, 780034AY 78K/0 Series

Subseries User’s Manual User’s Manual

(This Manual) Instructions

• Pin functions • CPU functions

• Internal block functions • Instruction set

• Interrupt • Explanation of each instruction

• Other on-chip peripheral functions

• Electrical specifications

User’s Manual U14046EJ3V0UD

How To Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of

electrical engineering, logic circuits, and microcontrollers.

•For readers who use this as an (A) product:

→Standard products differ from (A) products in their quality grade only. Re-read the

product name as indicated below if your product is an (A) product.

PD780021A →

PD780021A(A)

PD780021AY →

PD780021AY(A)

PD780022A →

PD780022A(A)

PD780022AY →

PD780022AY(A)

PD780023A →

PD780023A(A)

PD780023AY →

PD780023AY(A)

PD780024A →

PD780024A(A)

PD780024AY →

PD780024AY(A)

PD780031A →

PD780031A(A)

PD780031AY →

PD780031AY(A)

PD780032A →

PD780032A(A)

PD780032AY →

PD780032AY(A)

PD780033A →

PD780033A(A)

PD780033AY →

PD780033AY(A)

PD780034A →

PD780034A(A)

PD780034AY →

PD780034AY(A)

PD78F0034B →

PD78F0034B(A)

PD78F0034BY →

PD78F0034BY(A)

•To gain a general understanding of functions:

→Read this manual in the order of the contents.

•How to interpret the register format:

→For the bit number enclosed in brackets, the bit name is defined as a reserved word

in RA78K0, and in CC78K0, already defined in the header file named sfrbit.h.

•To check the details of a register when you know the register name:

→See APPENDIX D REGISTER INDEX.

•To know the details of the 78K/0 Series instruction functions:

→Refer to the 78K/0 Series Instructions User’s Manual (U12326E).

•To know the electrical specifications of the

PD780024A, 780034A, 780024AY,

780034AY Subseries:

→See CHAPTER 25 ELECTRICAL SPECIFICATIONS (EXPANDED-SPECIFICATION

PRODUCTS: fX = 1.0 TO 12 MHz) and CHAPTER 26 ELECTRICAL

SPECIFICATIONS (CONVENTIONAL PRODUCTS: fX = 1.0 TO 8.38 MHz).

Caution Examples in this manual employ the “standard” quality grade for general

electronics. When using examples in this manual for the “special” quality

grade, review the quality grade of each part and/or circuit actually used.

Differences between

PD780024A, 780034A, 780024AY, and 780034AY Subseries

The configuration of the serial interface and the resolution of the A/D converter differ on

PD780024A, 780034A,

780024AY, and 780034AY Subseries products.

Subseries

PD780024A

PD780034A

PD780024AY

PD780034AY

Item

Configuration of 3-wire serial I/O mode 2ch (SIO30, SIO31) 1ch (SIO30 only)

serial interface UART mode 1ch 1ch

I2C mode None 1ch

A/D converter 8-bit resolution 10-bit resolution 8-bit resolution 10-bit resolution

12 User’s Manual U14046EJ3V0UD

Chapter Organization This manual divides the descriptions for the subseries into different chapters as shown

below. Read only the chapters related to the device you use.

Chapter

PD780024A

PD780034A

PD780024AY

PD780034AY

Subseries Subseries Subseries Subseries

Chapter 1 Outline (

PD780024A, 780034A Subseries) √√−−

Chapter 2 Outline (

PD780024AY, 780034AY Subseries) −−√√

Chapter 3 Pin Function (

PD780024A, 780034A Subseries) √√−−

Chapter 4 Pin Function (

PD780024AY, 780034AY Subseries) −−√√

Chapter 5 CPU Architecture √√√√

Chapter 6 Port Functions √√√√

Chapter 7 Clock Generator √√√√

Chapter 8 16-Bit Timer/Event Counter 0 √√√√

Chapter 9 8-Bit Timer/Event Counters 50, 51 √√√√

Chapter 10 Watch Timer √√√√

Chapter 11 Watchdog Timer √√√√

Chapter 12 Clock Output/Buzzer Output Controller √√√√

Chapter 13 8-Bit A/D Converter √−√−

(

PD780024A, 780024AY Subseries)

Chapter 14 10-Bit A/D Converter −√−√

(

PD780034A, 780034AY Subseries)

Chapter 15 Serial Interface Outline √√√√

Chapter 16 Serial Interface UART0 √√√√

Chapter 17 Serial Interface SIO3 √√√√

Chapter 18 Serial Interface IIC0 −−√√

(

PD780024AY, 780034AY Subseries only)

Chapter 19 Interrupt Functions √√√√

Chapter 20 External Device Expansion Function √√√√

Chapter 21 Standby Function √√√√

Chapter 22 Reset Function √√√√

Chapter 23

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY √√√√

Chapter 24 Instruction Set √√√√

Chapter 25 Electrical Specifications (Expanded-Specification √√√√

Products: fX = 1.0 to 12 MHz)

Chapter 26 Electrical Specifications (Conventional Products: √√√√

fX = 1.0 to 8.38 MHz)

Chapter 27 Package Drawings √√√√

Chapter 28 Recommended Soldering Conditions √√√√

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: ××× (overscore over pin or signal name)

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representation: Binary ··· ×××× or ××××B

Decimal ··· ××××

Hexadecimal ··· ××××H

User’s Manual U14046EJ3V0UD

Other Documents

Document Name Document No.

SEMICONDUCTOR SELECTION GUIDE − Products and Packages −X13769X

Semiconductor Device Mount Manual Note

Quality Grades on NEC Semiconductor Devices C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

User’s Manual U14046EJ3V0UD

CONTENTS

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES) .................................................... 34

1.1 Expanded-Specification Products and Conventional Products ....................................... 34

1.2 Features ................................................................................................................................. 35

1.3 Applications .......................................................................................................................... 36

1.4 Ordering Information ............................................................................................................ 37

1.5 Quality Grade ........................................................................................................................ 41

1.6 Pin Configuration (Top View) ............................................................................................... 45

1.7 78K/0 Series Lineup .............................................................................................................. 49

1.8 Block Diagram ....................................................................................................................... 51

1.9 Outline of Function ............................................................................................................... 52

1.10 Correspondence Between Mask ROM Versions and Flash Memory Versions ............... 54

1.11 Differences Between Standard Grade Products and Special Grade Products ............... 54

1.12 Correspondence Between Products and Packages .......................................................... 55

1.13 Mask Options ........................................................................................................................ 55

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES) .................................................. 56

2.1 Features ................................................................................................................................. 56

2.2 Applications .......................................................................................................................... 57

2.3 Ordering Information ............................................................................................................ 58

2.4 Quality Grade ........................................................................................................................ 62

2.5 Pin Configuration (Top View) ............................................................................................... 66

2.6 78K/0 Series Lineup .............................................................................................................. 70

2.7 Block Diagram ....................................................................................................................... 72

2.8 Outline of Function ............................................................................................................... 73

2.9 Correspondence Between Mask ROM Versions and Flash Memory Versions ............... 74

2.10 Differences Between Standard Grade Products and Special Grade Products ............... 75

2.11 Correspondence Between Products and Packages .......................................................... 75

2.12 Mask Options ........................................................................................................................ 76

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES) .......................................... 77

3.1 Pin Function List ................................................................................................................... 77

3.2 Description of Pin Functions ............................................................................................... 80

3.2.1 P00 to P03 (Port 0) .................................................................................................................... 80

3.2.2 P10 to P17 (Port 1) .................................................................................................................... 80

3.2.3 P20 to P25 (Port 2) .................................................................................................................... 81

3.2.4 P30 to P36 (Port 3) .................................................................................................................... 81

3.2.5 P40 to P47 (Port 4) .................................................................................................................... 82

3.2.6 P50 to P57 (Port 5) .................................................................................................................... 82

3.2.7 P64 to P67 (Port 6) .................................................................................................................... 82

3.2.8 P70 to P75 (Port 7) .................................................................................................................... 83

3.2.9 AVREF .......................................................................................................................................... 83

3.2.10 AVDD ........................................................................................................................................... 83

3.2.11 AVSS ........................................................................................................................................... 83

3.2.12 RESET ....................................................................................................................................... 84

3.2.13 NC .............................................................................................................................................. 84

16 User’s Manual U14046EJ3V0UD

3.2.14 X1 and X2 .................................................................................................................................. 84

3.2.15 XT1 and XT2 .............................................................................................................................. 84

3.2.16 VDD0 and VDD1 ............................................................................................................................. 84

3.2.17 VSS0 and VSS1 ............................................................................................................................. 84

3.2.18 VPP (flash memory versions only) ............................................................................................... 84

3.2.19 IC (mask ROM version only) ...................................................................................................... 84

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................... 85

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES) ....................................... 89

4.1 Pin Function List ................................................................................................................... 89

4.2 Description of Pin Functions ............................................................................................... 92

4.2.1 P00 to P03 (Port 0) .................................................................................................................... 92

4.2.2 P10 to P17 (Port 1) .................................................................................................................... 92

4.2.3 P20 to P25 (Port 2) .................................................................................................................... 93

4.2.4 P30 to P36 (Port 3) .................................................................................................................... 93

4.2.5 P40 to P47 (Port 4) .................................................................................................................... 94

4.2.6 P50 to P57 (Port 5) .................................................................................................................... 94

4.2.7 P64 to P67 (Port 6) .................................................................................................................... 94

4.2.8 P70 to P75 (Port 7) .................................................................................................................... 95

4.2.9 AVREF .......................................................................................................................................... 95

4.2.10 AVDD ........................................................................................................................................... 95

4.2.11 AVSS ........................................................................................................................................... 95

4.2.12 RESET ....................................................................................................................................... 96

4.2.13 NC .............................................................................................................................................. 96

4.2.14 X1 and X2 .................................................................................................................................. 96

4.2.15 XT1 and XT2 .............................................................................................................................. 96

4.2.16 VDD0 and VDD1 ............................................................................................................................. 96

4.2.17 VSS0 and VSS1 ............................................................................................................................. 96

4.2.18 VPP (flash memory versions only) ............................................................................................... 96

4.2.19 IC (mask ROM version only) ...................................................................................................... 96

4.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................... 97

CHAPTER 5 CPU ARCHITECTURE ................................................................................................. 101

5.1 Memory Spaces ..................................................................................................................... 101

5.1.1 Internal program memory space ................................................................................................ 106

5.1.2 Internal data memory space ...................................................................................................... 108

5.1.3 Special function register (SFR) area .......................................................................................... 108

5.1.4 External memory space ............................................................................................................. 108

5.1.5 Data memory addressing ........................................................................................................... 109

5.2 Processor Registers ............................................................................................................. 114

5.2.1 Control registers ......................................................................................................................... 114

5.2.2 General-purpose registers ......................................................................................................... 118

5.2.3 Special function register (SFR) .................................................................................................. 119

5.3 Instruction Address Addressing ......................................................................................... 123

5.3.1 Relative addressing ................................................................................................................... 123

5.3.2 Immediate addressing ................................................................................................................ 124

5.3.3 Table indirect addressing ........................................................................................................... 125

5.3.4 Register addressing ................................................................................................................... 126

User’s Manual U14046EJ3V0UD

5.4 Operand Address Addressing ............................................................................................. 127

5.4.1 Implied addressing ..................................................................................................................... 127

5.4.2 Register addressing ................................................................................................................... 128

5.4.3 Direct addressing ....................................................................................................................... 129

5.4.4 Short direct addressing .............................................................................................................. 130

5.4.5 Special function register (SFR) addressing ............................................................................... 131

5.4.6 Register indirect addressing ...................................................................................................... 132

5.4.7 Based addressing ...................................................................................................................... 133

5.4.8 Based indexed addressing ......................................................................................................... 134

5.4.9 Stack addressing ....................................................................................................................... 135

CHAPTER 6 PORT FUNCTIONS ...................................................................................................... 136

6.1 Port Functions ....................................................................................................................... 136

6.2 Port Configuration ................................................................................................................ 139

6.2.1 Port 0 .......................................................................................................................................... 139

6.2.2 Port 1 .......................................................................................................................................... 141

6.2.3 Port 2 .......................................................................................................................................... 142

6.2.4 Port 3 (

PD780024A, 780034A Subseries) ............................................................................... 145

6.2.5 Port 3 (

PD780024AY, 780034AY Subseries) ........................................................................... 150

6.2.6 Port 4 .......................................................................................................................................... 154

6.2.7 Port 5 .......................................................................................................................................... 155

6.2.8 Port 6 .......................................................................................................................................... 156

6.2.9 Port 7 .......................................................................................................................................... 158

6.3 Port Function Control Registers ......................................................................................... 161

6.4 Port Function Operations..................................................................................................... 167

6.4.1 Writing to I/O port ....................................................................................................................... 167

6.4.2 Reading from I/O port ................................................................................................................ 167

6.4.3 Operations on I/O port ............................................................................................................... 167

6.5 Selection of Mask Option ..................................................................................................... 168

CHAPTER 7 CLOCK GENERATOR ................................................................................................. 169

7.1 Clock Generator Functions .................................................................................................. 169

7.2 Clock Generator Configuration ........................................................................................... 169

7.3 Clock Generator Control Registers ..................................................................................... 171

7.4 System Clock Oscillator ....................................................................................................... 175

7.4.1 Main system clock oscillator ...................................................................................................... 175

7.4.2 Subsystem clock oscillator ......................................................................................................... 176

7.4.3 When subsystem clock is not used ............................................................................................ 179

7.5 Clock Generator Operations ................................................................................................ 180

7.5.1 Main system clock operations .................................................................................................... 181

7.5.2 Subsystem clock operations ...................................................................................................... 182

7.6 Changing System Clock and CPU Clock Settings ............................................................. 182

7.6.1 Time required for switchover between system clock and CPU clock ......................................... 182

7.6.2 System clock and CPU clock switching procedure .................................................................... 183

CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 .......................................................................... 184

8.1 Functions of 16-Bit Timer/Event Counter 0 ........................................................................ 184

8.2 Configuration of 16-Bit Timer/Event Counter 0 .................................................................. 185

18 User’s Manual U14046EJ3V0UD

8.3 Registers to Control 16-Bit Timer/Event Counter 0 ........................................................... 188

8.4 Operation of 16-Bit Timer/Event Counter 0 ........................................................................ 194

8.4.1 Interval timer operation .............................................................................................................. 194

8.4.2 External event counter operation ............................................................................................... 197

8.4.3 Pulse width measurement operations ........................................................................................ 199

8.4.4 Square-wave output operation ................................................................................................... 206

8.4.5 PPG output operation ................................................................................................................ 207

8.5 Program List .......................................................................................................................... 209

8.5.1 Interval timer .............................................................................................................................. 210

8.5.2 Pulse width measurement by free-running counter and one capture register ........................... 211

8.5.3 Two pulse widths measurement by free-running counter .......................................................... 212

8.5.4 Pulse width measurement by restart .......................................................................................... 214

8.5.5 PPG output ................................................................................................................................ 215

8.6 Cautions Related to 16-Bit Timer/Event Counter 0 ............................................................ 216

CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51 ................................................................ 219

9.1 Functions of 8-Bit Timer/Event Counters 50, 51 ................................................................ 219

9.2 Configuration of 8-Bit Timer/Event Counters 50, 51 .......................................................... 221

9.3 Registers to Control 8-Bit Timer/Event Counters 50, 51 ................................................... 222

9.4 Operation of 8-Bit Timer/Event Counters 50, 51 ................................................................ 227

9.4.1 8-bit interval timer operation ...................................................................................................... 227

9.4.2 External event counter operation ............................................................................................... 231

9.4.3 Square-wave output (8-bit resolution) operation ........................................................................ 232

9.4.4 8-bit PWM output operation ....................................................................................................... 233

9.4.5 Interval timer (16-bit) operations ................................................................................................ 237

9.5 Program List .......................................................................................................................... 238

9.5.1 Interval timer (8-bit) .................................................................................................................... 238

9.5.2 External event counter ............................................................................................................... 239

9.5.3 Interval timer (16-bit) .................................................................................................................. 240

9.6 Cautions Related to 8-Bit Timer/Event Counters 50, 51 .................................................... 241

CHAPTER 10 WATCH TIMER .......................................................................................................... 242

10.1 Watch Timer Functions ........................................................................................................ 242

10.2 Watch Timer Configuration .................................................................................................. 243

10.3 Register to Control Watch Timer ......................................................................................... 244

10.4 Watch Timer Operations ...................................................................................................... 245

10.4.1 Watch timer operation ................................................................................................................ 245

10.4.2 Interval timer operation .............................................................................................................. 245

CHAPTER 11 WATCHDOG TIMER .................................................................................................. 247

11.1 Watchdog Timer Functions .................................................................................................. 247

11.2 Watchdog Timer Configuration ........................................................................................... 248

11.3 Registers to Control Watchdog Timer ................................................................................ 248

11.4 Watchdog Timer Operations ................................................................................................ 250

11.4.1 Watchdog timer operation .......................................................................................................... 250

11.4.2 Interval timer operation ............................................................................................................... 251

User’s Manual U14046EJ3V0UD

CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................ 252

12.1 Clock Output/Buzzer Output Controller Functions ........................................................... 252

12.2 Configuration of Clock Output/Buzzer Output Controller ................................................ 253

12.3 Register to Control Clock Output/Buzzer Output Controller ............................................ 253

12.4 Operation of Clock Output/Buzzer Output Controller ....................................................... 256

12.4.1 Operation as clock output .......................................................................................................... 256

12.4.2 Operation as buzzer output ........................................................................................................ 256

CHAPTER 13 8-BIT A/D CONVERTER (

PD780024A, 780024AY SUBSERIES) ....................... 257

13.1 A/D Converter Functions ..................................................................................................... 257

13.2 A/D Converter Configuration ............................................................................................... 259

13.3 Registers to Control A/D Converter .................................................................................... 261

13.4 A/D Converter Operations.................................................................................................... 264

13.4.1 Basic operations of A/D converter .............................................................................................. 264

13.4.2 Input voltage and conversion results .......................................................................................... 267

13.4.3 A/D converter operation mode ................................................................................................... 268

13.5 How to Read A/D Converter Characteristics Table ........................................................... 271

13.6 A/D Converter Cautions ....................................................................................................... 274

CHAPTER 14 10-BIT A/D CONVERTER (

PD780034A, 780034AY SUBSERIES) ...................... 279

14.1 A/D Converter Functions ..................................................................................................... 279

14.2 A/D Converter Configuration ............................................................................................... 281

14.3 Registers to Control A/D Converter .................................................................................... 283

14.4 A/D Converter Operation...................................................................................................... 286

14.4.1 Basic operations of A/D converter .............................................................................................. 286

14.4.2 Input voltage and conversion results .......................................................................................... 289

14.4.3 A/D converter operation mode ................................................................................................... 290

14.5 How to Read A/D Converter Characteristics Table ........................................................... 292

14.6 A/D Converter Cautions ....................................................................................................... 295

CHAPTER 15 SERIAL INTERFACE OUTLINE ............................................................................... 300

CHAPTER 16 SERIAL INTERFACE UART0 ................................................................................... 301

16.1 Functions of Serial Interface UART0 ................................................................................... 301

16.2 Configuration of Serial Interface UART0 ............................................................................ 303

16.3 Registers to Control Serial Interface UART0 ...................................................................... 305

16.4 Operation of Serial Interface UART0 ................................................................................... 310

16.4.1 Operation stop mode .................................................................................................................. 310

16.4.2 Asynchronous serial interface (UART) mode ............................................................................. 310

16.4.3 Infrared data transfer mode ........................................................................................................ 321

CHAPTER 17 SERIAL INTERFACES SIO30 AND SIO31 ............................................................ 329

17.1 Functions of Serial Interfaces SIO30 and SIO31 ................................................................ 329

17.2 Configuration of Serial Interfaces SIO30 and SIO31 ......................................................... 330

17.3 Registers to Control Serial Interfaces SIO30 and SIO31 ................................................... 331

17.4 Operations of Serial Interfaces SIO30 and SIO31 .............................................................. 335

17.4.1 Operation stop mode .................................................................................................................. 335

17.4.2 3-wire serial I/O mode ................................................................................................................ 336

20 User’s Manual U14046EJ3V0UD

CHAPTER 18 SERIAL INTERFACE IIC0 (

PD780024AY, 780034AY SUBSERIES ONLY) ..... 340

18.1 Functions of Serial Interface IIC0 ........................................................................................ 340

18.2 Configuration of Serial Interface IIC0 .................................................................................. 343

18.3 Registers to Control Serial Interface IIC0 ........................................................................... 345

18.4 I2C Bus Mode Functions ....................................................................................................... 355

18.4.1 Pin configuration ........................................................................................................................ 355

18.5 I2C Bus Definitions and Control Methods ........................................................................... 356

18.5.1 Start conditions .......................................................................................................................... 356

18.5.2 Addresses .................................................................................................................................. 357

18.5.3 Transfer direction specification .................................................................................................. 357

18.5.4 Acknowledge (ACK) signal ........................................................................................................ 358

18.5.5 Stop condition ............................................................................................................................ 359

18.5.6 Wait signal (WAIT) ..................................................................................................................... 360

18.5.7 Interrupt request (INTIIC0) generation timing and wait control .................................................. 362

18.5.8 Address match detection method .............................................................................................. 363

18.5.9 Error detection ........................................................................................................................... 363

18.5.10 Extension code .......................................................................................................................... 363

18.5.11 Arbitration ................................................................................................................................... 364

18.5.12 Wake-up function ....................................................................................................................... 365

18.5.13 Communication reservation ....................................................................................................... 366

18.5.14 Other cautions ............................................................................................................................ 368

18.5.15 Communication operations ........................................................................................................ 369

18.5.16 Timing of I2C interrupt request (INTIIC0) occurrence ................................................................. 377

18.6 Timing Charts ........................................................................................................................ 395

CHAPTER 19 INTERRUPT FUNCTIONS ......................................................................................... 402

19.1 Interrupt Function Types ...................................................................................................... 402

19.2 Interrupt Sources and Configuration .................................................................................. 402

19.3 Interrupt Function Control Registers .................................................................................. 406

19.4 Interrupt Servicing Operations ............................................................................................ 412

19.4.1 Non-maskable interrupt request acknowledgment operation ..................................................... 412

19.4.2 Maskable interrupt request acknowledgment operation ............................................................ 415

19.4.3 Software interrupt request acknowledgment operation .............................................................. 417

19.4.4 Nesting interrupt servicing ......................................................................................................... 418

19.4.5 Interrupt request hold ................................................................................................................. 421

CHAPTER 20 EXTERNAL DEVICE EXPANSION FUNCTION ...................................................... 422

20.1 External Device Expansion Function .................................................................................. 422

20.2 External Device Expansion Function Control Registers ................................................... 425

20.3 External Device Expansion Function Timing ..................................................................... 427

20.4 Example of Connection with Memory ................................................................................. 432

CHAPTER 21 STANDBY FUNCTION ............................................................................................... 433

21.1 Standby Function and Configuration .................................................................................. 433

21.1.1 Standby function ........................................................................................................................ 433

21.1.2 Standby function control register ............................................................................................... 434

21.2 Standby Function Operations .............................................................................................. 435

21.2.1 HALT mode ................................................................................................................................ 435

21.2.2 STOP mode ............................................................................................................................... 438

User’s Manual U14046EJ3V0UD

CHAPTER 22 RESET FUNCTION .................................................................................................... 441

CHAPTER 23

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY .............................................. 445

23.1 Differences Between

PD78F0034A, 78F0034AY and

PD78F0034B, 78F0034BY ......... 446

23.2 Differences Between

PD78F0034B, 78F0034BY and

PD78F0034B(A), 78F0034BY(A) ......................................................................................... 447

23.3 Differences Between

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY

and Mask ROM Versions ...................................................................................................... 448

23.4 Memory Size Switching Register ......................................................................................... 450

23.5 Flash Memory Characteristics ............................................................................................. 451

23.5.1 Programming environment ......................................................................................................... 451

23.5.2 Communication mode ................................................................................................................ 452

23.5.3 On-board pin processing ............................................................................................................ 457

23.5.4 Connection on adapter for flash memory writing ....................................................................... 460

CHAPTER 24 INSTRUCTION SET ................................................................................................... 472

24.1 Conventions .......................................................................................................................... 473

24.1.1 Operand identifiers and specification methods .......................................................................... 473

24.1.2 Description of “operation” column .............................................................................................. 474

24.1.3 Description of “flag operation” column ....................................................................................... 474

24.2 Operation List ........................................................................................................................ 475

24.3 Instructions Listed by Addressing Type ............................................................................ 483

CHAPTER 25 ELECTRICAL SPECIFICATIONS

(EXPANDED-SPECIFICATION PRODUCTS: fx = 1.0 TO 12 MHz) ..................... 487

CHAPTER 26 ELECTRICAL SPECIFICATIONS

(CONVENTIONAL PRODUCTS: fx = 1.0 TO 8.38 MHz) ...................................... 518

CHAPTER 27 PACKAGE DRAWINGS ............................................................................................. 550

CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS ........................................................ 556

APPENDIX A DIFFERENCES BETWEEN

PD78018F, 780024A, 780034A,

AND 780078 SUBSERIES......................................................................................... 561

APPENDIX B DEVELOPMENT TOOLS ........................................................................................... 564

B.1 Software Package ................................................................................................................. 567

B.2 Language Processing Software .......................................................................................... 567

B.3 Control Software ................................................................................................................... 568

B.4 Flash Memory Writing Tools ................................................................................................ 569

B.5 Debugging Tools (Hardware) ............................................................................................... 569

B.5.1 When using the in-circuit emulator IE-78K0-NS, IE-78K0-NS-A ................................................ 569

B.5.2 When using the in-circuit emulator IE-78001-R-A ...................................................................... 571

B.6 Debugging Tools (Software) ................................................................................................ 572

B.7 Embedded Software ............................................................................................................. 573

B.8 System Upgrade from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A .... 574

B.9 Package Drawings of Conversion Socket and Conversion Adapter ............................... 575

22 User’s Manual U14046EJ3V0UD

APPENDIX C NOTES ON TARGET SYSTEM DESIGN ................................................................ 581

APPENDIX D REGISTER INDEX ...................................................................................................... 591

D.1 Register Name Index ............................................................................................................ 591

D.2 Register Symbol Index ......................................................................................................... 594

APPENDIX E REVISION HISTORY .................................................................................................. 597

User’s Manual U14046EJ3V0UD

LIST OF FIGURES (1/8)

Figure No. Title Page

3-1 Pin I/O Circuit List ................................................................................................................................ 87

4-1 Pin I/O Circuit List ................................................................................................................................ 99

5-1 Memory Map (

PD780021A, 780031A, 780021AY, 780031AY) .......................................................... 101

5-2 Memory Map (

PD780022A, 780032A, 780022AY, 780032AY) .......................................................... 102

5-3 Memory Map (

PD780023A, 780033A, 780023AY, 780033AY) .......................................................... 103

5-4 Memory Map (

PD780024A, 780034A, 780024AY, 780034AY) .......................................................... 104

5-5 Memory Map (

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY) ................................................. 105

5-6 Correspondence Between Data Memory and Addressing

(

PD780021A, 780031A, 780021AY, 780031AY) ................................................................................ 109

5-7 Correspondence Between Data Memory and Addressing

(

PD780022A, 780032A, 780022AY, 780032AY) ................................................................................ 110

5-8 Correspondence Between Data Memory and Addressing

(

PD780023A, 780033A, 780023AY, 780033AY) ................................................................................ 111

5-9 Correspondence Between Data Memory and Addressing

(

PD780024A, 780034A, 780024AY, 780034AY) ................................................................................ 112

5-10 Correspondence Between Data Memory and Addressing

(

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY) ....................................................................... 113

5-11 Program Counter Format ..................................................................................................................... 114

5-12 Program Status Word Format .............................................................................................................. 114

5-13 Stack Pointer Format ........................................................................................................................... 116

5-14 Data to Be Saved to Stack Memory ..................................................................................................... 116

5-15 Data to Be Restored from Stack Memory ............................................................................................ 117

5-16 General-Purpose Register Configuration ............................................................................................. 118

6-1 Port Types ............................................................................................................................................ 136

6-2 Block Diagram of P00 to P03 ............................................................................................................... 140

6-3 Block Diagram of P10 to P17 ............................................................................................................... 141

6-4 Block Diagram of P20, P23, and P25 .................................................................................................. 142

6-5 Block Diagram of P21 and P24 ............................................................................................................ 143

6-6 Block Diagram of P22 .......................................................................................................................... 144

6-7 Block Diagram of P30 and P31 (

PD780024A, 780034A Subseries) .................................................. 145

6-8 Block Diagram of P32 and P33 (

PD780024A, 780034A Subseries) .................................................. 146

6-9 Block Diagram of P34 (

PD780024A, 780034A Subseries) ................................................................ 147

6-10 Block Diagram of P35 (

PD780024A, 780034A Subseries) ................................................................ 148

6-11 Block Diagram of P36 (

PD780024A, 780034A Subseries) ................................................................ 149

6-12 Block Diagram of P30 and P31 (

PD780024AY, 780034AY Subseries) .............................................. 151

6-13 Block Diagram of P32 and P33 (

PD780024AY, 780034AY Subseries) .............................................. 151

6-14 Block Diagram of P34 and P36 (

PD780024AY, 780034AY Subseries) .............................................. 152

24 User’s Manual U14046EJ3V0UD

LIST OF FIGURES (2/8)

Figure No. Title Page

6-15 Block Diagram of P35 (

PD780024AY, 780034AY Subseries) ............................................................ 153

6-16 Block Diagram of P40 to P47 ............................................................................................................... 154

6-17 Block Diagram of Falling Edge Detector .............................................................................................. 155

6-18 Block Diagram of P50 to P57 ............................................................................................................... 155

6-19 Block Diagram of P64, P65, and P67 .................................................................................................. 156

6-20 Block Diagram of P66 .......................................................................................................................... 157

6-21 Block Diagram of P70, P72, and P73 .................................................................................................. 158

6-22 Block Diagram of P71 .......................................................................................................................... 159

6-23 Block Diagram of P74 and P75 ............................................................................................................ 160

6-24 Format of Port Mode Register (PM0, PM2 to PM7) ............................................................................. 162

6-25 Format of Pull-Up Resistor Option Register (PU0, PU2 to PU7) ......................................................... 166

7-1 Block Diagram of Clock Generator ...................................................................................................... 170

7-2 Format of Processor Clock Control Register (PCC) ............................................................................ 172

7-3 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................ 174

7-4 External Circuit of Main System Clock Oscillator ................................................................................. 175

7-5 External Circuit of Subsystem Clock Oscillator .................................................................................... 176

7-6 Examples of Incorrect Oscillator Connection ....................................................................................... 177

7-7 Subsystem Clock Feedback Resistor .................................................................................................. 179

7-8 Main System Clock Stop Function ....................................................................................................... 181

7-9 System Clock and CPU Clock Switching ............................................................................................. 183

8-1 Block Diagram of 16-Bit Timer/Event Counter 0 .................................................................................. 185

8-2 Format of 16-Bit Timer Mode Control Register 0 (TMC0) .................................................................... 189

8-3 Format of Capture/Compare Control Register 0 (CRC0) ..................................................................... 190

8-4 Format of 16-Bit Timer Output Control Register 0 (TOC0) .................................................................. 191

8-5 Format of Prescaler Mode Register 0 (PRM0) .................................................................................... 192

8-6 Format of Port Mode Register 7 (PM7) ................................................................................................ 193

8-7 Control Register Settings for Interval Timer Operation ........................................................................ 194

8-8 Interval Timer Configuration Diagram .................................................................................................. 195

8-9 Timing of Interval Timer Operation ....................................................................................................... 195

8-10 Timing After Change of Compare Register During Timer Count Operation ......................................... 196

8-11 Control Register Settings in External Event Counter Mode ................................................................. 197

8-12 External Event Counter Configuration Diagram ................................................................................... 198

8-13 External Event Counter Operation Timing (with Rising Edge Specified) ............................................. 198

8-14 Control Register Settings for Pulse Width Measurement with Free-Running Counter

and One Capture Register ................................................................................................................... 199

8-15 Configuration Diagram for Pulse Width Measurement with Free-Running Counter ............................ 200

8-16 Timing of Pulse Width Measurement Operation with Free-Running Counter

and One Capture Register (with Both Edges Specified) ...................................................................... 200

8-17 Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ........... 201

User’s Manual U14046EJ3V0UD

LIST OF FIGURES (3/8)

Figure No. Title Page

8-18 Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified) ................................................................................................................. 202

8-19 Control Register Settings for Pulse Width Measurement with Free-Running Counter

and Two Capture Registers ................................................................................................................. 203

8-20 Timing of Pulse Width Measurement Operation with Free-Running Counter

and Two Capture Registers (with Rising Edge Specified) ................................................................... 204

8-21 Control Register Settings for Pulse Width Measurement by Means of Restart ................................... 205

8-22 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) ... 205

8-23 Control Register Settings in Square-Wave Output Mode .................................................................... 206

8-24 Square-Wave Output Operation Timing ............................................................................................... 206

8-25 Control Register Settings for PPG Output Operation .......................................................................... 207

8-26 PPG Output Configuration Diagram .................................................................................................... 208

8-27 PPG Output Operation Timing ............................................................................................................. 208

8-28 Start Timing of 16-Bit Timer Counter 0 (TM0) ...................................................................................... 216

8-29 Capture Register Data Retention Timing ............................................................................................. 216

8-30 Operation Timing of OVF0 Flag ........................................................................................................... 217

8-31 CR01 Capture Operation with Rising Edge Specified ......................................................................... 218

9-1 Block Diagram of 8-Bit Timer/Event Counter 50 .................................................................................. 220

9-2 Block Diagram of 8-Bit Timer/Event Counter 51 .................................................................................. 220

9-3 Format of Timer Clock Select Register 50 (TCL50) ............................................................................. 222

9-4 Format of Timer Clock Select Register 51 (TCL51) ............................................................................. 223

9-5 Format of 8-Bit Timer Mode Control Register 50 (TMC50) .................................................................. 224

9-6 Format of 8-Bit Timer Mode Control Register 51 (TMC51) .................................................................. 225

9-7 Format of Port Mode Register 7 (PM7) ................................................................................................ 226

9-8 Interval Timer Operation Timing ........................................................................................................... 228

9-9 External Event Counter Operation Timing (with Rising Edge Specified) ............................................. 231

9-10 Square-Wave Output Operation Timing ............................................................................................... 233

9-11 PWM Output Operation Timing ............................................................................................................ 235

9-12 Timing of Operation by Change of CR5n ............................................................................................. 236

9-13 16-Bit Resolution Cascade Connection Mode ..................................................................................... 237

9-14 Start Timing of 8-Bit Timer Counter 5n (TM5n) .................................................................................... 241

10-1 Watch Timer Block Diagram ................................................................................................................ 242

10-2 Format of Watch Timer Operation Mode Register (WTM) ................................................................... 244

10-3 Operation Timing of Watch Timer/Interval Timer .................................................................................. 246

11-1 Watchdog Timer Block Diagram .......................................................................................................... 247

11-2 Format of Watchdog Timer Clock Select Register (WDCS) ................................................................. 248

11-3 Format of Watchdog Timer Mode Register (WDTM) ........................................................................... 249

26 User’s Manual U14046EJ3V0UD

LIST OF FIGURES (4/8)

Figure No. Title Page

12-1 Block Diagram of Clock Output/Buzzer Output Controller ................................................................... 252

12-2 Format of Clock Output Select Register (CKS) ................................................................................... 254

12-3 Format of Port Mode Register 7 (PM7) ................................................................................................ 255

12-4 Remote Control Output Application Example ...................................................................................... 256

13-1 8-Bit A/D Converter Block Diagram ..................................................................................................... 258

13-2 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 262

13-3 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 263

13-4 Basic Operation of 8-Bit A/D Converter ............................................................................................... 265

13-5 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 267

13-6 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................ 269

13-7 A/D Conversion by Software Start ....................................................................................................... 270

13-8 Overall Error......................................................................................................................................... 271

13-9 Quantization Error ................................................................................................................................ 271

13-10 Zero Scale Error................................................................................................................................... 272

13-11 Full Scale Error .................................................................................................................................... 272

13-12 Integral Linearity Error ......................................................................................................................... 272

13-13 Differential Linearity Error .................................................................................................................... 272

13-14 Circuit Configuration of Series Resistor String .................................................................................... 274

13-15 A/D Conversion End Interrupt Request Generation Timing ................................................................. 275

13-16 Timing of Reading Conversion Result (When Conversion Result Is Undefined) ................................. 276

13-17 AVDD Pin Connection ........................................................................................................................... 276

13-18 Example of Connecting Capacitor to AVREF Pin ................................................................................... 277

13-19 Internal Equivalent Circuit of Pins ANI0 to ANI7 .................................................................................. 277

13-20 Example of Connection If Signal Source Impedance Is High .............................................................. 278

14-1 10-Bit A/D Converter Block Diagram ................................................................................................... 280

14-2 Format of A/D Conversion Result Register 0 (ADCR0) ....................................................................... 281

14-3 Format of A/D Converter Mode Register 0 (ADM0) ............................................................................. 284

14-4 Format of Analog Input Channel Specification Register 0 (ADS0) ...................................................... 285

14-5 Basic Operation of 10-Bit A/D Converter ............................................................................................. 287

14-6 Relationship Between Analog Input Voltage and A/D Conversion Result ............................................ 289

14-7 A/D Conversion by Hardware Start (When Falling Edge Is Specified) ................................................ 290

14-8 A/D Conversion by Software Start ....................................................................................................... 291

14-9 Overall Error......................................................................................................................................... 292

14-10 Quantization Error ................................................................................................................................ 292

14-11 Zero Scale Error................................................................................................................................... 293

14-12 Full Scale Error .................................................................................................................................... 293

14-13 Integral Linearity Error ......................................................................................................................... 293

14-14 Differential Linearity Error .................................................................................................................... 293

User’s Manual U14046EJ3V0UD

LIST OF FIGURES (5/8)

Figure No. Title Page

14-15 Circuit Configuration of Series Resistor String .................................................................................... 295

14-16 A/D Conversion End Interrupt Request Generation Timing ................................................................. 296

14-17 Timing of Reading Conversion Result (When Conversion Result Is Undefined) ................................. 297

14-18 AVDD Pin Connection ........................................................................................................................... 297

14-19 Example of Connecting Capacitor to AVREF Pin ................................................................................... 298

14-20 Internal Equivalent Circuit of Pins ANI0 to ANI7 .................................................................................. 298

14-21 Example of Connection If Signal Source Impedance Is High .............................................................. 299

16-1 Block Diagram of Serial Interface UART0............................................................................................ 302

16-2 Block Diagram of Baud Rate Generator .............................................................................................. 302

16-3 Format of Asynchronous Serial Interface Status Register 0 (ASIS0) .................................................. 304

16-4 Format of Asynchronous Serial Interface Mode Register 0 (ASIM0) ................................................... 306

16-5 Format of Baud Rate Generator Control Register 0 (BRGC0) ............................................................ 308

16-6 Format of Port Mode Register 2 (PM2) ................................................................................................ 309

16-7 Error Tolerance (When k = 0), Including Sampling Errors ................................................................... 315

16-8 Example of Transmit/Receive Data Format in Asynchronous Serial Interface .................................... 316

16-9 Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request ............................... 318

16-10 Timing of Asynchronous Serial Interface Receive Completion Interrupt Request ............................... 319

16-11 Receive Error Timing ........................................................................................................................... 320

16-12 Data Format Comparison Between Infrared Data Transfer Mode and UART Mode............................ 326

17-1 Block Diagram of Serial Interface SIO3n ............................................................................................. 329

17-2 Format of Serial Operation Mode Register 30 (CSIM30) ..................................................................... 332

17-3 Format of Serial Operation Mode Register 31 (CSIM31) ..................................................................... 333

17-4 Format of Port Mode Register 2 (PM2) ................................................................................................ 334

17-5 Format of Port Mode Register 3 (PM3) ................................................................................................ 334

17-6 Timing of 3-Wire Serial I/O Mode ......................................................................................................... 338

18-1 Block Diagram of Serial Interface IIC0 ................................................................................................. 341

18-2 Serial Bus Configuration Example Using I2C Bus ............................................................................... 342

18-3 Format of IIC Shift Register 0 (IIC0) .................................................................................................... 343

18-4 Format of Slave Address Register 0 (SVA0) ........................................................................................ 343

18-5 Format of IIC Control Register 0 (IICC0) ............................................................................................. 346

18-6 Format of IIC Status Register 0 (IICS0) ............................................................................................... 350

18-7 Format of IIC Transfer Clock Select Register 0 (IICCL0) ..................................................................... 353

18-8 Format of Port Mode Register 3 (PM3) ................................................................................................ 354

18-9 Pin Configuration Diagram ................................................................................................................... 355

18-10 I2C Bus Serial Data Transfer Timing .................................................................................................... 356

18-11 Start Conditions ................................................................................................................................... 356

18-12 Address ................................................................................................................................................ 357

18-13 Transfer Direction Specification ........................................................................................................... 357

28 User’s Manual U14046EJ3V0UD

LIST OF FIGURES (6/8)

Figure No. Title Page

18-14 ACK Signal........................................................................................................................................... 358

18-15 Stop Condition ..................................................................................................................................... 359

18-16 Wait Signal ........................................................................................................................................... 360

18-17 Arbitration Timing Example .................................................................................................................. 364

18-18 Communication Reservation Timing .................................................................................................... 367

18-19 Timing for Accepting Communication Reservations ............................................................................ 367

18-20 Communication Reservation Protocol ................................................................................................. 368

18-21 Master Operation Flowchart ................................................................................................................ 369

18-22 Slave Operation Flowchart .................................................................................................................. 375

18-23 Example of Master to Slave Communication

(When 9-Clock Wait Is Selected for Both Master and Slave) .............................................................. 396

18-24 Example of Slave to Master Communication

(When 9-Clock Wait Is Selected for Both Master and Slave) .............................................................. 399

19-1 Basic Configuration of Interrupt Function ............................................................................................ 404

19-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L) ........................................................... 407

19-3 Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) ......................................................... 408

19-4 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L) ................................................. 409

19-5 Format of External Interrupt Rising Edge Enable Register (EGP),

External Interrupt Falling Edge Enable Register (EGN) ...................................................................... 410

19-6 Program Status Word Format .............................................................................................................. 411

19-7 Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ........................................... 413

19-8 Non-Maskable Interrupt Request Acknowledge Timing ....................................................................... 413

19-9 Non-Maskable Interrupt Request Acknowledge Operation .................................................................. 414

19-10 Interrupt Request Acknowledge Processing Algorithm ........................................................................ 416

19-11 Interrupt Request Acknowledge Timing (Minimum Time) .................................................................... 417

19-12 Interrupt Request Acknowledge Timing (Maximum Time) ................................................................... 417

19-13 Nesting Examples ................................................................................................................................ 419

19-14 Interrupt Request Hold ......................................................................................................................... 421

20-1 Memory Map When Using External Device Expansion Function ........................................................ 423

20-2 Format of Memory Expansion Mode Register (MEM).......................................................................... 425

20-3 Format of Memory Expansion Wait Setting Register (MM) .................................................................. 426

20-4 Instruction Fetch from External Memory .............................................................................................. 428

20-5 External Memory Read Timing ............................................................................................................ 429

20-6 External Memory Write Timing ............................................................................................................. 430

20-7 External Memory Read Modify Write Timing ........................................................................................ 431

20-8 Connection Example of

PD780024A and Memory ............................................................................ 432

21-1 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................ 434

21-2 HALT Mode Release by Interrupt Request Generation ....................................................................... 436

User’s Manual U14046EJ3V0UD

LIST OF FIGURES (7/8)

Figure No. Title Page

21-3 HALT Mode Release by RESET Input ................................................................................................. 437

21-4 STOP Mode Release by Interrupt Request Generation ....................................................................... 439

21-5 STOP Mode Release by RESET Input ................................................................................................ 440

22-1 Reset Function Block Diagram ............................................................................................................ 441

22-2 Timing of Reset by RESET Input ......................................................................................................... 442

22-3 Timing of Reset Due to Watchdog Timer Overflow .............................................................................. 442

22-4 Timing of Reset in STOP Mode by RESET Input ................................................................................. 442

23-1 Format of Memory Size Switching Register (IMS) ............................................................................... 450

23-2 Environment for Writing Program to Flash Memory ............................................................................. 451

23-3 Communication Mode Selection Format .............................................................................................. 453

23-4 Example of Connection with Dedicated Flash Programmer ................................................................ 454

23-5 VPP Pin Connection Example ............................................................................................................... 457

23-6 Signal Conflict (Input Pin of Serial Interface) ....................................................................................... 458

23-7 Abnormal Operation of Other Device ................................................................................................... 458

23-8 Signal Conflict (RESET Pin) ................................................................................................................ 459

23-9 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (SIO30) Mode .................. 460

23-10 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (SIO31) Mode

(

PD78F0034A, 78F0034B only) ......................................................................................................... 462

23-11 Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (SIO30 + HS) Mode

(

PD78F0034B, 78F0034BY only) ...................................................................................................... 464

23-12 Example of Wiring Adapter for Flash Memory Writing in I2C Bus (IIC0) Mode

(

PD78F0034AY, 78F0034BY only)..................................................................................................... 466

23-13 Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode.................................. 468

23-14 Example of Wiring Adapter for Flash Memory Writing in Pseudo 3-Wire Serial I/O Mode ................... 470

B-1 Development Tool Configuration .......................................................................................................... 565

B-2 EV-9200GC-64 Package Drawing (for Reference Only) ...................................................................... 575

B-3 EV-9200GC-64 Recommended Board Mounting Pattern (for Reference Only) .................................. 576

B-4 TGC-064SAP Package Drawing (for Reference Only) ........................................................................ 577

B-5 TGK-064SBW Package Drawing (for Reference Only) ....................................................................... 578

B-6 TGB-064SDP Package Drawing (for Reference Only) ........................................................................ 579

C-1 Distance Between In-Circuit Emulator and Conversion Adapter (When Using 64CW) ....................... 582

C-2 Connection Conditions of Target System (When Using NP-64CW)..................................................... 582

C-3 Connection Conditions of Target System (When Using NP-H64CW) .................................................. 583

C-4 Distance Between In-Circuit Emulator and Conversion Adapter (When Using 64GC) ........................ 584

C-5 Connection Conditions of Target System (When Using NP-64GC-TQ) ............................................... 584

C-6 Connection Conditions of Target System (When Using NP-H64GC-TQ) ............................................ 585

30 User’s Manual U14046EJ3V0UD

LIST OF FIGURES (8/8)

Figure No. Title Page

C-7 Distance Between In-Circuit Emulator and Conversion Adapter (When Using 64GK) ........................ 586

C-8 Connection Conditions of Target System (When Using NP-64GK) ..................................................... 586

C-9 Connection Conditions of Target System (When Using NP-H64GK-TQ) ............................................. 587

C-10 Distance Between In-Circuit Emulator and Conversion Adapter (When Using 64GB) ........................ 588

C-11 Connection Conditions of Target System (When Using NP-64GB-TQ) ............................................... 588

C-12 Connection Conditions of Target System (When Using NP-H64GB-TQ) ............................................. 589

C-13 Distance Between In-Circuit Emulator and Conversion Socket (When Using NP-73F1-CN3) ............ 590

C-14 Connection Conditions of Target System (When Using NP-73F1-CN3) .............................................. 590

User’s Manual U14046EJ3V0UD

LIST OF TABLES (1/3)

Table No. Title Page

1-1 Correspondence Between Mask ROM Versions and Flash Memory Versions .................................... 54

1-2 Differences Between Standard Grade Products and Special Grade Products .................................... 54

1-3 Correspondence Between Products and Packages ............................................................................ 55

1-4 Mask Options of Mask ROM Versions ................................................................................................. 55

2-1 Correspondence Between Mask ROM Versions and Flash Memory Versions .................................... 74

2-2 Differences Between Standard Grade Products and Special Grade Products .................................... 75

2-3 Correspondence Between Products and Packages ............................................................................ 75

2-4 Mask Options of Mask ROM Versions ................................................................................................. 76

3-1 Pin I/O Circuit Types ............................................................................................................................ 85

4-1 Pin I/O Circuit Types ............................................................................................................................ 97

5-1 Internal ROM Capacity ........................................................................................................................ 106

5-2 Vector Table ......................................................................................................................................... 107

5-3 Internal High-Speed RAM Capacity ..................................................................................................... 108

5-4 Internal High-Speed RAM Area ........................................................................................................... 115

5-5 Special Function Register List ............................................................................................................. 120

6-1 Port Functions (

PD780024A, 780034A Subseries) ............................................................................ 137

6-2 Port Functions (

PD780024AY, 780034AY Subseries) ........................................................................ 138

6-3 Port Configuration ................................................................................................................................ 139

6-4 Pull-Up Resistor of Port 3 (

PD780024A, 780034A Subseries) .......................................................... 145

6-5 Pull-Up Resistor of Port 3 (

PD780024AY, 780034AY Subseries) ...................................................... 150

6-6 Port Mode Registers and Output Latch Settings When Alternate Function Is Used ............................ 163

6-7 Comparison Between Mask ROM Version and Flash Memory Version ............................................... 168

7-1 Clock Generator Configuration ............................................................................................................ 169

7-2 Relationship Between CPU Clock and Minimum Instruction Execution Time ...................................... 173

7-3 Maximum Time Required for CPU Clock Switchover .......................................................................... 182

8-1 Configuration of 16-Bit Timer/Event Counter 0 .................................................................................... 185

8-2 CR00 Capture Trigger and Valid Edges of TI00 and TI01 Pins ........................................................... 186

8-3 CR01 Capture Trigger and Valid Edge of TI00 Pin (CRC02 = 1) ......................................................... 187

9-1 Configuration of 8-Bit Timer/Event Counters 50, 51 ............................................................................ 221

10-1 Watch Timer Configuration .................................................................................................................. 243

10-2 Interval Timer Interval Time ................................................................................................................. 245

32 User’s Manual U14046EJ3V0UD

LIST OF TABLES (2/3)

Table No. Title Page

11-1 Watchdog Timer Configuration ............................................................................................................ 248

11-2 Watchdog Timer Loop Detection Time ................................................................................................. 250

11-3 Interval Timer Interval Time ................................................................................................................. 251

12-1 Configuration of Clock Output/Buzzer Output Controller ..................................................................... 253

13-1 A/D Converter Configuration ................................................................................................................ 259

13-2 Sampling Time and A/D Conversion Start Delay Time of A/D Converter ............................................. 266

13-3 Resistances and Capacitances of Equivalent Circuit (Reference Values) ........................................... 278

14-1 A/D Converter Configuration ................................................................................................................ 281

14-2 Sampling Time and A/D Conversion Start Delay Time of A/D Converter ............................................. 288

14-3 Resistances and Capacitances of Equivalent Circuit (Reference Values) ........................................... 299

15-1 Differences Between

PD780024A, 780034A Subseries and

PD780024AY, 780034AY Subseries .................................................................................................. 300

16-1 Configuration of Serial Interface UART0.............................................................................................. 303

16-2 Relationship Between Main System Clock and Baud Rate Error ........................................................ 314

16-3 Causes of Receive Errors .................................................................................................................... 320

16-4 Relationship Between Main System Clock and Baud Rate ................................................................. 326

16-5 Bit Rate and Pulse Width Values ......................................................................................................... 326

16-6 Register Settings ................................................................................................................................. 328

17-1 Configuration of Serial Interface SIO3n ............................................................................................... 330

17-2 Register Settings ................................................................................................................................. 339

18-1 Configuration of Serial Interface IIC0 ................................................................................................... 343

18-2 INTIIC0 Timing and Wait Control ......................................................................................................... 362

18-3 Extension Code Bit Definitions ............................................................................................................ 363

18-4 Status During Arbitration and Interrupt Request Generation Timing .................................................... 365

18-5 Wait Periods ......................................................................................................................................... 366

19-1 Interrupt Source List ............................................................................................................................ 403

19-2 Flags Corresponding to Interrupt Request Sources ............................................................................ 406

19-3 Times from Generation of Maskable Interrupt Until Servicing ............................................................. 415

19-4 Interrupt Requests Enabled for Nesting During Interrupt Servicing ..................................................... 418

20-1 Pin Functions in External Memory Expansion Mode ........................................................................... 422

20-2 State of Port 4 to 6 Pins in External Memory Expansion Mode ........................................................... 422

User’s Manual U14046EJ3V0UD

LIST OF TABLES (3/3)

Table No. Title Page

21-1 HALT Mode Operating Statuses ......................................................................................................... 435

21-2 Operation After HALT Mode Release .................................................................................................. 437

21-3 STOP Mode Operating Statuses ........................................................................................................ 438

21-4 Operation After STOP Mode Release ................................................................................................. 440

22-1 Hardware Statuses After Reset ........................................................................................................... 443

23-1 Correspondence Between

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY,

and Mask ROM Versions ..................................................................................................................... 445

23-2 Differences Between

PD78F0034A and

PD78F0034B .................................................................... 446

23-3 Differences Between

PD78F0034AY and

PD78F0034BY ............................................................... 447

23-4 Differences Between

PD78F0034B, 78F0034BY and

PD78F0034B(A), 78F0034BY(A) ................ 447

23-5 Differences Between

PD78F0034A, 78F0034B and Mask ROM Versions ........................................ 448

23-6 Differences Between

PD78F0034AY, 78F0034BY and Mask ROM Versions .................................... 449

23-7 Memory Size Switching Register Settings ........................................................................................... 450

23-8 Communication Mode List ................................................................................................................... 452

23-9 Pin Connection List .............................................................................................................................. 456

24-1 Operand Identifiers and Specification Methods ................................................................................... 473

28-1 Surface Mounting Type Soldering Conditions ...................................................................................... 556

28-2 Insertion Type Soldering Conditions .................................................................................................... 560

A-1 Major Differences Between

PD78018F, 780024A, 780034A, and 780078 Subseries (Hardware) .... 561

A-2 Major Differences Between

PD78018F, 780024A, 780034A, and 780078 Subseries (Software) ..... 562

B-1 System Upgrade Method from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A ............ 574

C-1 Distance Between IE System and Conversion Adapter ....................................................................... 581

34 User’s Manual U14046EJ3V0UD

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

1.1 Expanded-Specification Products and Conventional Products

The expanded-specification products and conventional products refer to the following products.

Expanded-specification products:

PD780021A, 780022A, 780023A, 780024A, 780031A, 780032A, 780033A,

780034A for which orders were received after December 1, 2001

(Products with a rankNote other than K, E, P, X)

PD78F0034B

Conventional products: Products other than the above expanded-specification products

(Products with rankNote K, E, P, X)

PD78F0034A

Note The rank is indicated by the 5th digit from the left in the lot number marked on the package.

Lot number

Year

code

Rank

Week

code

Expanded-specification products and conventional products differ in the operating frequency ratings.

Power Supply Voltage (VDD) Guaranteed Operating Speed (Operating Frequency)

Conventional Products Expanded-Specification Products

4.5 to 5.5 V 8.38 MHz (0.238

s) 12 MHz (0.166

4.0 to 5.5 V 8.38 MHz (0.238

s) 8.38 MHz (0.238

3.0 to 5.5 V 5 MHz (0.4

s) 8.38 MHz (0.238

2.7 to 5.5 V 5 MHz (0.4

s) 5 MHz (0.4

1.8 to 5.5 V 1.25 MHz (1.6

s) 1.25 MHz (1.6

Remark The parenthesized values indicate the minimum instruction execution time.

Caution Only the conventional products are available in the

PD780024AY and 780034AY Subseries

(

PD780021AY, 780022AY, 780023AY, 780024AY, 780031AY, 780032AY, 780033AY, 780034AY,

78F0034AY, 78F0034BY).

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.2 Features

•Internal memory

Type Program Memory Data Memory

Part Number (ROM/Flash Memory) (High-Speed RAM)

PD780021A, 780031A 8 KB 512 bytes

PD780022A, 780032A 16 KB

PD780023A, 780033A 24 KB 1024 bytes

PD780024A, 780034A 32 KB

PD78F0034A, 78F0034B 32 KBNote 1024 bytesNote

Note The capacities of internal flash memory and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

•External memory expansion space: 64 KB

•Minimum instruction execution time changeable from high speed (expanded-specification product (0.166

s: @12

MHz operation with main system clock), conventional product (0.238

s: @ 8.38 MHz operation with main system

clock)) to ultra-low speed (122

s: @ 32.768 kHz operation with subsystem clock)

•Instruction set suited to system control

•Bit manipulation possible in all address spaces

•Multiply and divide instructions

•Fifty-one I/O ports: (Four N-ch open-drain ports)

•8-bit resolution A/D converter: 8 channels (

PD780024A Subseries only)

•10-bit resolution A/D converter: 8 channels (

PD780034A Subseries only)

•Serial interface: 3 channels

•3-wire serial I/O mode: 2 channels

•UART mode: 1 channel

•Timer: Five channels

•16-bit timer/event counter: 1 channel

•8-bit timer/event counter: 2 channels

•Watch timer: 1 channel

•Watchdog timer: 1 channel

•Vectored interrupt sources: 20

•Two types of on-chip clock oscillators (main system clock and subsystem clock)

•Power supply voltage: VDD = 1.8 to 5.5 V

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.3 Applications

PD780021A, 780022A, 780023A, 780024A

PD780031A, 780032A, 780033A, 780034A, 78F0034A, 78F0034B

Home electric appliances, pagers, AV equipment, car audios, car electric equipment, office automation

equipment, etc.

PD780021A(A), 780022A(A), 780023A(A), 780024A(A)

PD780031A(A), 780032A(A), 780033A(A), 780034A(A), 78F0034B(A)

Control of transportation equipment, gas detection breakers, safety devices, etc.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.4 Ordering Information

(1)

PD780024A Subseries (1/2)

Part Number Package Internal ROM

PD780021ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780021AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780021AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780021AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780021AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780021AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780022ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780022AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780022AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780022AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780022AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780022AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780023ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780023AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780023AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780023AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780023AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780023AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780024ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780024AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780024AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780024AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780024AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780024AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

Remark ××× indicates ROM code suffix.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

(1)

PD780024A Subseries (2/2)

Part Number Package Internal ROM

PD780021ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780021AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780021AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780021AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780021AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780022ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780022AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780022AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780022AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780022AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780023ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780023AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780023AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780023AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780023AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780024ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780024AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780024AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780024AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780024AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

Note Under development

Remark ××× indicates ROM code suffix.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034A Subseries (1/2)

Part Number Package Internal ROM

PD780031ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780031AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780031AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780031AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780031AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780031AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780032ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780032AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780032AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780032AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780032AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780032AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780033ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780033AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780033AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780033AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780033AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780033AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780034ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780034AGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780034AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780034AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780034AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780034AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD78F0034ACW 64-pin plastic SDIP (19.05 mm (750)) Flash memory

PD78F0034AGC-AB8Note 64-pin plastic QFP (14 × 14) Flash memory

PD78F0034AGC-8BS 64-pin plastic LQFP (14 × 14) Flash memory

PD78F0034AGK-9ET 64-pin plastic TQFP (12 × 12) Flash memory

PD78F0034AGB-8EU 64-pin plastic LQFP (10 × 10) Flash memory

PD78F0034BGC-8BS 64-pin plastic LQFP (14 × 14) Flash memory

PD78F0034BGK-9ET 64-pin plastic TQFP (12 × 12) Flash memory

PD78F0034BGB-8EU 64-pin plastic LQFP (10 × 10) Flash memory

PD78F0034BF1-CN3 73-pin plastic FBGA (9 × 9) Flash memory

Note Maintenance product

Remark ××× indicates ROM code suffix.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034A Subseries (2/2)

Part Number Package Internal ROM

PD780031ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780031AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780031AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780031AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780031AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780032ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780032AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780032AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780032AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780032AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780033ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780033AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780033AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780033AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780033AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780034ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780034AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780034AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780034AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780034AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD78F0034BGC(A)-8BS 64-pin plastic LQFP (14 × 14) Flash memory

PD78F0034BGK(A)-9ET 64-pin plastic TQFP (12 × 12) Flash memory

PD78F0034BGB(A)-8EU 64-pin plastic LQFP (10 × 10) Flash memory

Note Under development

Remark ××× indicates ROM code suffix.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.5 Quality Grade

(1)

PD780024A Subseries (1/2)

Part Number Package Quality Grades

PD780021ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780021AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780021AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780021AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780021AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780021AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780022ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780022AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780022AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780022AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780022AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780022AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780023ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780023AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780023AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780023AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780023AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780023AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780024ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780024AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780024AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780024AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780024AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780024AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

(1)

PD780024A Subseries (2/2)

Part Number Package Quality Grades

PD780021ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780021AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780021AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780021AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780021AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780022ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780022AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780022AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780022AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780022AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780023ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780023AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780023AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780023AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780023AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780024ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780024AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780024AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780024AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780024AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

Note Under development

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034A Subseries (1/2)

Part Number Package Quality Grades

PD780031ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780031AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780031AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780031AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780031AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780031AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780032ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780032AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780032AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780032AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780032AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780032AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780033ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780033AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780033AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780033AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780033AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780033AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780034ACW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780034AGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780034AGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780034AGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780034AGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780034AF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD78F0034ACW 64-pin plastic SDIP (19.05 mm (750)) Standard

PD78F0034AGC-AB8Note 64-pin plastic QFP (14 × 14) Standard

PD78F0034AGC-8BS 64-pin plastic LQFP (14 × 14) Standard

PD78F0034AGK-9ET 64-pin plastic TQFP (12 × 12) Standard

PD78F0034AGB-8EU 64-pin plastic LQFP (10 × 10) Standard

PD78F0034BGC-8BS 64-pin plastic LQFP (14 × 14) Standard

PD78F0034BGK-9ET 64-pin plastic TQFP (12 × 12) Standard

PD78F0034BGB-8EU 64-pin plastic LQFP (10 × 10) Standard

PD78F0034BF1-CN3 73-pin plastic FBGA (9 × 9) Standard

Note Maintenance product

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034A Subseries (2/2)

Part Number Package Quality Grades

PD780031ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780031AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780031AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780031AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780031AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780032ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780032AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780032AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780032AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780032AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780033ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780033AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780033AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780033AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780033AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780034ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) Special

PD780034AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780034AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) Special

PD780034AGK(A)-×××-9ET 64-pin plastic TQFP (12 × 12) Special

PD780034AGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD78F0034BGC(A)-8BS 64-pin plastic LQFP (14 × 14) Special

PD78F0034BGK(A)-9ET 64-pin plastic TQFP (12 × 12) Special

PD78F0034BGB(A)-8EU 64-pin plastic LQFP (10 × 10) Special

Note Under development

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.6 Pin Configuration (Top View)

• 64-pin plastic SDIP (19.05 mm (750))

P40/AD0

P41/AD1

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

VSS0

VDD0

P30

P31

P32

P33

P34/SI31

P35/SO31

P36/SCK31

P20/SI30

P21/SO30

P22/SCK30

P23/RxD0

P24/TxD0

P25/ASCK0

VDD1

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P75/BUZ

P74/PCL

P73/TI51/TO51

P72/TI50/TO50

P71/TI01

P70/TI00/TO0

P03/INTP3/ADTRG

P02/INTP2

P01/INTP1

P00/INTP0

VSS1

IC (VPP)

XT1

XT2

RESET

AVDD

AVREF

P10/ANI0

P11/ANI1

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

P16/ANI6

P17/ANI7

AVSS

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVSS pin to VSS0.

Remarks 1. When the

PD780024A, 780034A Subseries products are used in applications where the noise

generated inside the microcontroller needs to be reduced, the implementation of noise reduction

measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

2. Pin connection in parentheses is intended for the

PD78F0034A.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

• 64-pin plastic QFP (14 × 14)

• 64-pin plastic LQFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

• 64-pin plastic LQFP (10 × 10)

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVSS pin to VSS0.

Remarks 1. When the

PD780024A, 780034A Subseries products are used in applications where the noise

generated inside the microcontroller needs to be reduced, the implementation of noise reduction

measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

2. Pin connection in parentheses is intended for the

PD78F0034A, 78F0034B.

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

VSS0

VDD0

P30

P31

P32

P33

P34/SI31

P35/SO31

P71/TI01

P70/TI00/TO0

P03/INTP3/ADTRG

P02/INTP2

P01/INTP1

P00/INTP0

VSS1

IC (VPP)

XT1

XT2

RESET

AVDD

AVREF

P10/ANI0

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P75/BUZ

P74/PCL

P73/TI51/TO51

P72/TI50/TO50

P36/SCK31

P20/SI30

P21/SO30

P22/SCK30

P23/RxD0

P24/TxD0

P25/ASCK0

VDD1

AVSS

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

Pin No

. Pin Name

Pin No

. Pin Name

Pin No

. Pin Name

Pin No

. Pin Name

Pin No

. Pin Name

A1 NC C1 P52/A10 E1 P57/A15 G1 P33 J1 NC

A2 P46/AD6 C2 P53/A11 E2 VDD0 G2 P32 J2 P36/SCK31

A3 P44/AD4 C3 P45/AD5 E3 P54/A12 G3 P20/SI30 J3 NC

A4 P41/AD1 C4 P42/AD2 E4 − G4 P21/SO30 J4 P25/ASCK0

A5 P67/ASTB C5 P64/RD E5 − G5 P24/TxD0 J5 NC

A6 P65/WR C6 P73/TI51/TO51 E6 − G6 VDD1 J6 P17/ANI7

A7 P74/PCL C7

P03/INTP3/ADTRG

E7 P00/INTP0 G7 P16/ANI6 J7 P12/ANI2

A8 NC C8 P01/INTP1 E8 XT1 G8 AVDD J8 P13/ANI3

A9 NC C9 VSS1 E9 X2 G9 NC J9 NC

B1 P51/A9 D1 P55/A13 F1 P30 H1 P34/SI31

B2 P47/AD7 D2 P56/A14 F2 P31 H2 P35/SO31

B3 P43/AD3 D3 P50/A8 F3 VSS0 H3 P23/RxD0

B4 P40/AD0 D4 NC F4 − H4 P22/SCK30

B5 P66/WAIT D5 − F5 − H5 AVSS

B6 P75/BUZ D6 − F6 − H6 P15/ANI5

B7 P72/TI50/TO51 D7 P02/INTP2 F7 P14/ANI4 H7 P11/ANI1

B8 P71/TI01 D8 IC (VPP) F8 RESET H8 P10/ANI0

B9 P70/TI00/TO0 D9 X1 F9 XT2 H9 AVREF

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVSS pin to VSS0.

Remarks 1. When the

PD780024A, 780034A Subseries products are used in applications where the noise

generated inside the microcontroller needs to be reduced, the implementation of noise reduction

measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

2. Pin connection in parentheses is intended for the

PD78F0034B.

• 73-pin plastic FBGA (9 × 9)

Top View Bottom View

JHGFEDCBAABCDEFGHJ

Index mark

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

A8 to A15: Address bus P64 to P67: Port 6

AD0 to AD7: Address/data bus P70 to P75: Port 7

ADTRG: AD trigger input PCL: Programmable clock

ANI0 to ANI7: Analog input RD: Read strobe

ASCK0: Asynchronous serial clock RESET: Reset

ASTB: Address strobe RxD0: Receive data

AVDD: Analog power supply SCK30, SCK31: Serial clock

AVREF: Analog reference voltage SI30, SI31: Serial input

AVSS: Analog ground SO30, SO31: Serial output

BUZ: Buzzer clock TI00, TI01, TI50, TI51: Timer input

IC: Internally connected TO0, TO50, TO51: Timer output

INTP0 to INTP3: External interrupt input TxD0: Transmit data

NC: Non-connection VDD0, VDD1: Power supply

P00 to P03: Port 0 VPP: Programming power supply

P10 to P17: Port 1 VSS0, VSS1: Ground

P20 to P25: Port 2 WAIT: Wait

P30 to P36: Port 3 WR: Write strobe

P40 to P47: Port 4 X1, X2: Crystal (main system clock)

P50 to P57: Port 5 XT1, XT2: Crystal (subsystem clock)

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.7 78K/0 Series Lineup

The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name.

Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

PD78083

PD78018F PD78018FY

PD78014H EMI-noise reduced version of the PD78018F

Basic subseries for control

On-chip UART, capable of operating at low voltage (1.8 V)

42/44-pin

64-pin

52-pin 52-pin version of the PD780024A

PD780024AS

52-pin 52-pin version of the PD780034A

PD780034AS

PD78054 with IEBus

controller

PD78054 with enhanced serial I/O

PD78078Y with enhanced serial I/O and limited functions

PD78054 with timer and enhanced external interface

64-pin

80-pin

80-pin EMI-noise reduced version of the PD78054

PD78018F with UART and D/A converter, and enhanced I/O

PD780034A

PD780988

PD780034AY

64-pin

PD780024A with expanded RAM

PD780024A with enhanced A/D converter

On-chip inverter controller and UART. EMI-noise reduced.

PD78064

PD78064B

PD780308

100-pin

100-pin PD780308Y

PD78064Y

80-pin

78K/0

Series

LCD drive

PD78064 with enhanced SIO, and expanded ROM and RAM

EMI-noise reduced version of the PD78064

Basic subseries for driving LCDs, on-chip UART

Bus interface supported

µµ

PD78018F with enhanced serial I/O

80-pin

100-pin

Products in mass production Products under development

Y subseries products are compatible with I

C bus.

ROMless version of the PD78078

100-pin

100-pin EMI-noise reduced version of the PD78078

Inverter control

PD780208100-pin

VFD drive

PD78044F with enhanced I/O and VFD C/D. Display output total: 53

PD78098B

100-pin

PD780024A PD780024AY

µµ

80-pin

80-pin PD780852

PD780828B

For automobile meter driver. On-chip CAN controller

100-pin PD780958

For industrial meter control

On-chip automobile meter controller/driver

Meter control

80-pin On-chip IEBus controller

80-pin

On-chip controller compliant with J1850 (Class 2)

PD780833Y

PD780948 On-chip CAN controller

64-pin PD780078 PD780078Y

µµ

PD780034A with timer and enhanced serial I/O

PD78054 PD78054Y

PD78058F PD78058FY

PD780058 PD780058Y

µµ

PD78070A PD78070AY

PD78078 PD78078Y

PD780018AY

Control

PD78075B

PD780065

PD78044H

PD780232

80-pin

80-pin For panel control. On-chip VFD C/D. Display output total: 53

PD78044F with N-ch open-drain I/O. Display output total: 34

PD78044F

80-pin Basic subseries for driving VFD. Display output total: 34

120-pin

PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.

PD780318

PD780328

120-pin

PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.

PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.

PD780338

PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.

On-chip CAN controller

Specialized for CAN controller function

80-pin

PD780703AY

PD780702Y

64-pin PD780816

PD780344 with enhanced A/D converter

100-pin

PD780344 PD780344Y

PD780354 PD780354Y

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

The major functional differences between the subseries are shown below.

• Subseries without the suffix Y

Function ROM Timer 8-Bit 10-Bit 8-Bit Serial Interface I/O

External

Subseries Name Capacity 8-Bit 16-Bit Watch WDT A/D A/D D/A

Expansion

Control

PD78075B

32 KB to 40 KB

4 ch 1 ch 1 ch 1 ch 8 ch –2 ch 3 ch (UART: 1 ch) 88 1.8 V Yes

PD78078

48 KB to 60 KB

PD78070A –61 2.7 V

PD780058

24 KB to 60 KB

2 ch

3 ch (time-division UART: 1 ch)

68 1.8 V

PD78058F

48 KB to 60 KB

3 ch (UART: 1 ch) 69 2.7 V

PD78054

16 KB to 60 KB

2.0 V

PD780065

40 KB to 48 KB

–4 ch (UART: 1 ch) 60 2.7 V

PD780078

48 KB to 60 KB

2 ch –8 ch 3 ch (UART: 2 ch) 52 1.8 V

PD780034A

8 KB to 32 KB

1 ch 3 ch (UART: 1 ch) 51

PD780024A

8 ch –

PD780034AS

–4 ch 39 –

PD780024AS

4 ch –

PD78014H 8 ch 2 ch 53 Yes

PD78018F

8 KB to 60 KB

PD78083

8 KB to 16 KB

–– 1 ch (UART: 1 ch) 33 –

Inverter

PD780988

16 KB to 60 KB

3 ch Note –1 ch –8 ch –3 ch (UART: 2 ch) 47 4.0 V Yes

control

VFD

PD780208

32 KB to 60 KB

2 ch 1 ch 1 ch 1 ch 8 ch ––2 ch 74 2.7 V –

drive

PD780232

16 KB to 24 KB

3 ch –– 4 ch 40 4.5 V

PD78044H

32 KB to 48 KB

2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 V

PD78044F

16 KB to 40 KB

2 ch

LCD

PD780354

24 KB to 32 KB

4 ch 1 ch 1 ch 1 ch –8 ch –3 ch (UART: 1 ch) 66 1.8 V –

drive

PD780344 8 ch –

PD780338

48 KB to 60 KB

3 ch 2 ch –10 ch 1 ch 2 ch (UART: 1 ch) 54

PD780328 62

PD780318 70

PD780308

48 KB to 60 KB

2 ch 1 ch 8 ch ––

3 ch (time-division UART: 1 ch)

57 2.0 V

PD78064B 32 KB 2 ch (UART: 1 ch)

PD78064

16 KB to 32 KB

Bus

PD780948 60 KB 2 ch 2 ch 1 ch 1 ch 8 ch ––3 ch (UART: 1 ch) 79 4.0 V Yes

interface

PD78098B

40 KB to 60 KB

1 ch 2 ch 69 2.7 V –

supported

PD780816

32 KB to 60 KB

2 ch 12 ch –2 ch (UART: 1 ch) 46 4.0 V

Meter control

PD780958

48 KB to 60 KB

4 ch 2 ch –1 ch –––2 ch (UART: 1 ch) 69 2.2 V –

Dashboard

PD780852

32 KB to 40 KB

3 ch 1 ch 1 ch 1 ch 5 ch ––3 ch (UART: 1 ch) 56 4.0 V –

control

PD780828B

32 KB to 60 KB

Note 16-bit timer: 2 channels

10-bit timer: 1 channel

VDD

MIN.

Value

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.8 Block Diagram

16-bit timer/

event counter 0

8-bit timer/

event counter 50

8-bit timer/

event counter 51

Watchdog timer

Watch timer

Serial

interface SIO30

Serial

interface SIO31

UART0

A/D converter

Interrupt control

Clock/buzzer

output control

TI00/TO0/P70

TI01/P71

TI50/TO50/P72

TI51/TO51/P73

SI30/P20

SO30/P21

SCK30/P22

SI31/P34

SO31/P35

SCK31/P36

RxD0/P23

TxD0/P24

ASCK0/P25

AVDD

AVSS

AVREF

BUZ/P75

PCL/P74

ANI0/P10 to

ANI7/P17

INTP0/P00 to

INTP3/P03

VDD0 VDD1 VSS0 VSS1 IC

(VPP)

78K/0

CPU core

ROM

(flash

memory)

RAM

Port 0 P00 to P03

Port 1 P10 to P17

Port 2 P20 to P25

Port 3 P30 to P36

Port 4 P40 to P47

Port 5 P50 to P57

Port 6 P64 to P67

Port 7 P70 to P75

External access

System control

AD0/P40 to

AD7/P47

A8/P50 to

A15/P57

RD/P64

WR/P65

WAIT/P66

ASTB/P67

RESET

XT1

XT2

Remarks 1. The internal ROM and RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the

PD78F0034A, 78F0034B.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.9 Outline of Function

Part Number

PD780021A

PD780022A

PD780023A

PD780024A

PD78F0034A

Item

PD780031A

PD780032A

PD780033A

PD780034A

PD78F0034B

Internal memory ROM 8 KB 16 KB 24 KB 32 KB 32 KBNote

(Mask ROM) (Mask ROM) (Mask ROM) (Mask ROM)

(Flash memory)

High-speed RAM 512 bytes 1024 bytes

1024 bytes

Note

Memory space 64 KB

General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction Minimum instruction execution time changeable function

execution time When main system •0.166

s/0.333

s/0.666

s/1.33

s/2.66

s (@ 12 MHz operation,

clock selected expanded-specification product only)

• 0.238

s/0.477

s/0.954

s/1.90

s/3.81

s (@ 8.38 MHz operation)

When subsystem 122

s (@ 32.768 kHz operation)

clock selected

Instruction set • 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

I/O port Total: 51

• CMOS input: 8

• CMOS I/O: 39

• N-ch open-drain I/O (5 V breakdown): 4

A/D converter • 8-bit resolution × 8 channels (

PD780021A, 780022A, 780023A, 780024A)

• 10-bit resolution × 8 channels (

PD780031A, 780032A, 780033A, 780034A,

78F0034A, 78F0034B)

• Low-voltage operation: AVDD = 1.8 to 5.5 V

Serial interface • 3-wire serial I/O mode: 2 channels

• UART mode: 1 channel

Timer • 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Timer output Three outputs (8-bit PWM output enable: 2)

Clock output •93.7 kHz, 187 kHz, 375 kHz, 750 kHz, 1.5 MHz, 3 MHz, 6 MHz, 12 MHz

(12 MHz with main system clock, expanded-specification product only)

•65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz,

8.38 MHz (8.38 MHz with main system clock)

•32.768 kHz (32.768 kHz with subsystem clock)

Buzzer output •1.46 kHz, 2.92 kHz, 5.85 kHz, 11.7 kHz (12 MHz with main system clock,

expanded-specification product only)

•1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (8.38 MHz with main system clock)

Vectored interrupt Maskable Internal: 13, External: 5

source

Non-maskable

Internal: 1

Software 1

Note The capacities of internal flash memory and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

Part Number

PD780021A

PD780022A

PD780023A

PD780024A

PD78F0034A

Item

PD780031A

PD780032A

PD780033A

PD780034A

PD78F0034B

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Package • 64-pin plastic SDIP (19.05 mm (750))

• 64-pin plastic QFP (14 × 14)

• 64-pin plastic LQFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

• 64-pin plastic LQFP (10 × 10)

• 73-pin plastic FBGA (9 × 9) (standard grade product only)

The outline of the timer/event counter is as follows (for details, see CHAPTER 8 16-BIT TIMER/EVENT COUNTER

0, CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51, CHAPTER 10 WATCH TIMER, and CHAPTER 11

WATCHDOG TIMER).

16-Bit Timer/ 8-Bit Timer/ Watch Timer Watchdog Timer

Event Counter 0

Event Counters 50, 51

Operation Interval timer 1 channel 2 channels 1 channelNote 1 1 channelNote 2

Mode External event counter √√ ––

Function Timer output √√ ––

PPG output √–––

PWM output –√––

Pulse width measurement

√–––

Square-wave output √√ ––

Interrupt request √√ √√

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer can perform either the watchdog timer function or the interval timer function.

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.10 Correspondence Between Mask ROM Versions and Flash Memory Versions

Table 1-1. Correspondence Between Mask ROM Versions and Flash Memory Versions

Mask ROM Version

PD780021A/2A/3A/4A

PD780021A(A)/2A(A)/3A(A)/4A(A)

PD780031A/2A/3A/4A

PD780031A(A)/2A(A)/3A(A)/4A(A)

Conventional Expanded- Conventional Expanded-

Flash Memory Version Products

Specification Products

Products

Specification Products

PD78F0034A √− −−

PD78F0034B −√ −−

PD78F0034B(A) −−√

Note √

Note The

PD78F0034B(A) and the conventional products of the

PD780021A(A), 780022A(A), 780023A(A),

780024A(A), 780031A(A), 780032A(A), 780033A(A), and 780034A(A) differ in the operating frequency.

When replacing a flash memory version with a mask ROM version, note the supply voltage and operating

frequency.

Remarks 1. √: Supported, −: Not supported

2. The

PD780034A and

PD78F0034B, 78F0034B(A) differ in operating frequency ratings and the

communication mode of flash memory programming. See 23.1 Differences Between

PD78F0034A,

78F0034AY and

PD78F0034B, 78F0034BY.

3. Expanded-specification products and conventional products of the

PD780024A and 780034A

Subseries differ in operating frequency ratings. For details, see CHAPTER 25 ELECTRICAL

SPECIFICATIONS (EXPANDED-SPECIFICATION PRODUCTS: fX = 1.0 TO 12 MHz) and CHAPTER

26 ELECTRICAL SPECIFICATIONS (CONVENTIONAL PRODUCTS: fX = 1.0 TO 8.38 MHz).

4. A special grade product of the

PD78F0034A is not available. Only a standard grade product is

available.

1.11 Differences Between Standard Grade Products and Special Grade Products

The differences between standard grade products (

PD780021A, 780022A, 780023A, 780024A, 780031A,

780032A, 780033A, 780034A, 78F0034A, 78F0034B) and special grade products (

PD780021A(A), 780022A(A),

780023A(A), 780024A(A), 780031A(A), 780032A(A), 780033A(A), 780034A(A), 78F0034B(A)) are shown in Table

1-2.

Table 1-2. Differences Between Standard Grade Products and Special Grade Products

PD780021A, 780022A, 780023A,

PD780021A(A), 780022A(A),

780024A, 780031A, 780032A, 780033A, 780023A(A), 780024A(A), 780031A(A),

780034A, 78F0034A, 78F0034B 780032A(A), 780033A(A), 780034A(A),

78F0034B(A)

Quality grade Standard Special

Package See 1.12 Correspondence Between Products and Packages

Other (functions, electrical Same

specifications, etc.)

CHAPTER 1 OUTLINE (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

1.12 Correspondence Between Products and Packages

The following table shows the correspondence between the products and packages.

Table 1-3. Correspondence Between Products and Packages

Mask ROM Version Flash Memory Version

PD780021A/2A/3A/4A

PD78F0034A

PD78F0034B

PD780031A/2A/3A/4A

Standard Special Standard Standard Special

64-pin SDIP (CW type) √√√− −

64-pin QFP (GC-AB8 type) √√√

Note 1 −−

64-pin LQFP (GC-8BS type) √√√√ √

64-pin TQFP (GK-9ET type) √√√√ √

64-pin LQFP (GB-8EU type) √√

Note 2 √√ √

73-pin FBGA (F1-CN3 type) √−−√ −

Notes 1. Maintenance product

2. Under development

Remarks 1. √: Package available, −: Package not available

2. A special grade product of the

PD78F0034A is not available. Only a standard grade product is

available.

1.13 Mask Options

The mask ROM versions (

PD780021A, 780022A, 780023A, 780024A, 780031A, 780032A, 780033A, and

780034A) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor

to a specific port pin when the user places an order for device production. Using the mask option when pull-up resistors

are required reduces the number of components to add to the device, resulting in board space saving.

The mask options provided in the

PD780024A and 780034A Subseries are shown in Table 1-4.

Table 1-4. Mask Options of Mask ROM Versions

Pin Names Mask Option

P30 to P33 Pull-up resistor connection can be specified in 1-bit units.

56 User’s Manual U14046EJ3V0UD

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

2.1 Features

•Internal memory

Type Program Memory Data Memory

Part Number (ROM/Flash Memory) (High-Speed RAM)

PD780021AY, 780031AY 8 KB 512 bytes

PD780022AY, 780032AY 16 KB

PD780023AY, 780033AY 24 KB 1024 bytes

PD780024AY, 780034AY 32 KB

PD78F0034AY, 78F0034BY 32 KBNote 1024 bytesNote

Note The capacities of internal flash memory and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

•External memory expansion space: 64 KB

•Minimum instruction execution time changeable from high speed (0.238

s: @ 8.38 MHz operation with main

system clock) to ultra-low speed (122

s: @ 32.768 kHz operation with subsystem clock)

•Instruction set suited to system control

• Bit manipulation possible in all address spaces

• Multiply and divide instructions

•Fifty-one I/O ports: (Four N-ch open-drain ports)

•8-bit resolution A/D converter: 8 channels (

PD780024AY Subseries only)

•10-bit resolution A/D converter: 8 channels (

PD780034AY Subseries only)

•Serial interface: 3 channels

• 3-wire serial mode: 1 channel

• UART mode: 1 channel

•I

2C mode: 1 channel

•Timer: Five channels

• 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

•Vectored interrupt sources: 20

•Two types of on-chip clock oscillators (main system clock and subsystem clock)

•Power supply voltage: VDD = 1.8 to 5.5 V

Caution Only the conventional products are available in the

PD780024AY and 780034AY Subseries (for

details of conventional products, see 1.1 Expanded-Specification Products and Conventional

Products).

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.2 Applications

PD780021AY, 780022AY, 780023AY, 780024AY

PD780031AY, 780032AY, 780033AY, 780034AY, 78F0034AY, 78F0034BY

Home electric appliances, pagers, AV equipment, car audios, car electric equipment, office automation

equipment, etc.

PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)

PD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A), 78F0034BY(A)

Control of transportation equipment, gas detection breakers, safety devices, etc.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.3 Ordering Information

(1)

PD780024AY Subseries (1/2)

Part Number Package Internal ROM

PD780021AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780021AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780021AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780021AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780021AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780021AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780022AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780022AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780022AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780022AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780022AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780022AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780023AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780023AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780023AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780023AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780023AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780023AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780024AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780024AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780024AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780024AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780024AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780024AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

Remark ××× indicates ROM code suffix.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

(1)

PD780024AY Subseries (2/2)

Part Number Package Internal ROM

PD780021AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780021AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Mask ROM

PD780021AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780021AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780021AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780022AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780022AYGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780022AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780022AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780022AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780023AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780023AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Mask ROM

PD780023AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780023AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780023AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780024AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780024AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Mask ROM

PD780024AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780024AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780024AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

Note Under development

Remark ××× indicates ROM code suffix.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034AY Subseries (1/2)

Part Number Package Internal ROM

PD780031AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780031AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780031AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780031AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780031AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780031AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780032AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780032AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780032AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780032AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780032AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780032AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780033AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780033AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780033AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780033AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780033AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780033AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD780034AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780034AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Mask ROM

PD780034AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD780034AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD780034AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

PD780034AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Mask ROM

PD78F0034AYCW 64-pin plastic SDIP (19.05 mm (750)) Flash memory

PD78F0034AYGC-AB8 64-pin plastic QFP (14 × 14) Flash memory

PD78F0034AYGC-8BS 64-pin plastic LQFP (14 × 14) Flash memory

PD78F0034AYGK-9ET 64-pin plastic TQFP (12 × 12) Flash memory

PD78F0034AYGB-8EU 64-pin plastic LQFP (10 × 10) Flash memory

PD78F0034BYGC-8BS 64-pin plastic LQFP (14 × 14) Flash memory

PD78F0034BYGK-9ET 64-pin plastic TQFP (12 × 12) Flash memory

PD78F0034BYGB-8EU 64-pin plastic LQFP (10 × 10) Flash memory

PD78F0034BYF1-CN3 73-pin plastic FBGA (9 × 9) Flash memory

Remark ××× indicates ROM code suffix.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034AY Subseries (2/2)

Part Number Package Internal ROM

PD780031AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780031AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Mask ROM

PD780031AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780031AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780031AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780032AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780032AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Mask ROM

PD780032AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780032AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780032AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780033AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780033AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Mask ROM

PD780033AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780033AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780033AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD780034AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Mask ROM

PD780034AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Mask ROM

PD780034AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Mask ROM

PD780034AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Mask ROM

PD780034AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Mask ROM

PD78F0034BYGC(A)-8BS 64-pin plastic LQFP (14 × 14) Mask ROM

PD78F0034BYGK(A)-9ET 64-pin plastic TQFP (12 × 12) Mask ROM

PD78F0034BYGB(A)-8EU 64-pin plastic LQFP (10 × 10) Mask ROM

Note Under development

Remark ××× indicates ROM code suffix.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.4 Quality Grade

(1)

PD780024AY Subseries (1/2)

Part Number Package Quality Grades

PD780021AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780021AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780021AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780021AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780021AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780021AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780022AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780022AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780022AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780022AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780022AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780022AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780023AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780023AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780023AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780023AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780023AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780023AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780024AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780024AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780024AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780024AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780024AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780024AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

(1)

PD780024AY Subseries (2/2)

Part Number Package Quality Grades

PD780021AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780021AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Special

PD780021AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780021AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780021AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780022AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780022AYGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) Special

PD780022AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780022AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780022AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780023AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780023AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Special

PD780023AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780023AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780023AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780024AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780024AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Special

PD780024AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780024AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780024AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

Note Under development

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034AY Subseries (1/2)

Part Number Package Quality Grades

PD780031AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780031AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780031AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780031AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780031AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780031AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780032AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780032AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780032AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780032AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780032AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780032AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780033AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780033AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780033AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780033AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780033AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780033AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD780034AYCW-××× 64-pin plastic SDIP (19.05 mm (750)) Standard

PD780034AYGC-×××-AB8 64-pin plastic QFP (14 × 14) Standard

PD780034AYGC-×××-8BS 64-pin plastic LQFP (14 × 14) Standard

PD780034AYGK-×××-9ET 64-pin plastic TQFP (12 × 12) Standard

PD780034AYGB-×××-8EU 64-pin plastic LQFP (10 × 10) Standard

PD780034AYF1-×××-CN3 73-pin plastic FBGA (9 × 9) Standard

PD78F0034AYCW 64-pin plastic SDIP (19.05 mm (750)) Standard

PD78F0034AYGC-AB8 64-pin plastic QFP (14 × 14) Standard

PD78F0034AYGC-8BS 64-pin plastic LQFP (14 × 14) Standard

PD78F0034AYGK-9ET 64-pin plastic TQFP (12 × 12) Standard

PD78F0034AYGB-8EU 64-pin plastic LQFP (10 × 10) Standard

PD78F0034BYGC-8BS 64-pin plastic LQFP (14 × 14) Standard

PD78F0034BYGK-9ET 64-pin plastic TQFP (12 × 12) Standard

PD78F0034BYGB-8EU 64-pin plastic LQFP (10 × 10) Standard

PD78F0034BYF1-CN3 73-pin plastic FBGA (9 × 9) Standard

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

(2)

PD780034AY Subseries (2/2)

Part Number Package Quality Grades

PD780031AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780031AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Special

PD780031AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780031AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780031AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780032AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780032AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Special

PD780032AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780032AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780032AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780033AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780033AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Special

PD780033AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780033AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780033AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD780034AYCW(A)-×××Note 64-pin plastic SDIP (19.05 mm (750)) Special

PD780034AYGC(A)-×××-AB8Note 64-pin plastic QFP (14 × 14) Special

PD780034AYGC(A)-×××-8BSNote 64-pin plastic LQFP (14 × 14) Special

PD780034AYGK(A)-×××-9ETNote 64-pin plastic TQFP (12 × 12) Special

PD780034AYGB(A)-×××-8EUNote 64-pin plastic LQFP (10 × 10) Special

PD78F0034BYGC(A)-8BS 64-pin plastic LQFP (14 × 14) Special

PD78F0034BYGK(A)-9ET 64-pin plastic TQFP (12 × 12) Special

PD78F0034BYGB(A)-8EU 64-pin plastic LQFP (10 × 10) Special

Note Under development

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.5 Pin Configuration (Top View)

• 64-pin plastic SDIP (19.05 mm (750))

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P75/BUZ

P74/PCL

P73/TI51/TO51

P72/TI50/TO50

P71/TI01

P70/TI00/TO0

P03/INTP3/ADTRG

P02/INTP2

P01/INTP1

P00/INTP0

VSS1

IC (VPP)

XT1

XT2

RESET

AVDD

AVREF

P10/ANI0

P11/ANI1

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

P16/ANI6

P17/ANI7

AVSS

P40/AD0

P41/AD1

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

VSS0

VDD0

P30

P31

P32/SDA0

P33/SCL0

P34

P35

P36

P20/SI30

P21/SO30

P22/SCK30

P23/RxD0

P24/TxD0

P25/ASCK0

VDD1

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVSS pin to VSS0.

Remarks 1. When the

PD780024AY, 780034AY Subseries products are used in applications where the noise

generated inside the microcontroller needs to be reduced, the implementation of noise reduction

measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

2. Pin connection in parentheses is intended for the

PD78F0034AY.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

• 64-pin plastic QFP (14 × 14)

• 64-pin plastic LQFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

• 64-pin plastic LQFP (10 × 10)

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVSS pin to VSS0.

Remarks 1. When the

PD780024AY, 780034AY Subseries products are used in applications where the noise

generated inside the microcontroller needs to be reduced, the implementation of noise reduction

measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

2. Pin connection in parentheses is intended for the

PD78F0034AY, 78F0034BY.

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

SS0

DD0

P30

P31

P32/SDA0

P33/SCL0

P34

P35

P36

P20/SI30

P21/SO30

P22/SCK30

P23/RxD0

P24/TxD0

P25/ASCK0

DD1

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P71/TI01

P70/TI00/TO0

P03/INTP3/ADTRG

P02/INTP2

P01/INTP1

P00/INTP0

SS1

IC (V

)

XT1

XT2

RESET

REF

P10/ANI0

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P75/BUZ

P74/PCL

P73/TI51/TO51

P72/TI50/TO50

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

Pin No

. Pin Name

Pin No

. Pin Name

Pin No

. Pin Name

Pin No

. Pin Name

Pin No

. Pin Name

A1 NC C1 P52/A10 E1 P57/A15 G1 P33/SCL0 J1 NC

A2 P46/AD6 C2 P53/A11 E2 VDD0 G2 P32/SDA0 J2 P36

A3 P44/AD4 C3 P45/AD5 E3 P54/A12 G3 P20/SI30 J3 NC

A4 P41/AD1 C4 P42/AD2 E4 − G4 P21/SO30 J4 P25/ASCK0

A5 P67/ASTB C5 P64/RD E5 − G5 P24/TxD0 J5 NC

A6 P65/WR C6 P73/TI51/TO51 E6 − G6 VDD1 J6 P17/ANI7

A7 P74/PCL C7

P03/INTP3/ADTRG

E7 P00/INTP0 G7 P16/ANI6 J7 P12/ANI2

A8 NC C8 P01/INTP1 E8 XT1 G8 AVDD J8 P13/ANI3

A9 NC C9 VSS1 E9 X2 G9 NC J9 NC

B1 P51/A9 D1 P55/A13 F1 P30 H1 P34

B2 P47/AD7 D2 P56/A14 F2 P31 H2 P35

B3 P43/AD3 D3 P50/A8 F3 VSS0 H3 P23/RxD0

B4 P40/AD0 D4 NC F4 − H4 P22/SCK30

B5 P66/WAIT D5 − F5 − H5 AVSS

B6 P75/BUZ D6 − F6 − H6 P15/ANI5

B7 P72/TI50/TO51 D7 P02/INTP2 F7 P14/ANI4 H7 P11/ANI1

B8 P71/TI01 D8 IC (VPP) F8 RESET H8 P10/ANI0

B9 P70/TI00/TO0 D9 X1 F9 XT2 H9 AVREF

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AVSS pin to VSS0.

Remarks 1. When the

PD780024AY, 780034AY Subseries products are used in applications where the noise

generated inside the microcontroller needs to be reduced, the implementation of noise reduction

measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

2. Pin connection in parentheses is intended for the

PD78F0034BY.

• 73-pin plastic FBGA (9 × 9)

Top View Bottom View

JHGFEDCBAABCDEFGHJ

Index mark

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

A8 to A15: Address bus P70 to P75: Port 7

AD0 to AD7: Address/data bus PCL: Programmable clock

ADTRG: AD trigger input RD: Read strobe

ANI0 to ANI7: Analog input RESET: Reset

ASCK0: Asynchronous serial clock RxD0: Receive data

ASTB: Address strobe SCK30: Serial clock

AVDD: Analog power supply SCL0: Serial clock

AVREF: Analog reference voltage SDA0: Serial data

AVSS: Analog ground SI30: Serial input

BUZ: Buzzer clock SO30: Serial output

IC: Internally connected TI00, TI01, TI50, TI51: Timer input

INTP0 to INTP3: External interrupt input TO0, TO50, TO51: Timer output

NC: Non-connection TxD0: Transmit data

P00 to P03: Port 0 VDD0, VDD1: Power supply

P10 to P17: Port 1 VPP: Programming power supply

P20 to P25: Port 2 VSS0, VSS1: Ground

P30 to P36: Port 3 WAIT: Wait

P40 to P47: Port 4 WR: Write strobe

P50 to P57: Port 5 X1, X2: Crystal (main system clock)

P64 to P67: Port 6 XT1, XT2: Crystal (subsystem clock)

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.6 78K/0 Series Lineup

The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name.

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

PD78083

PD78018F PD78018FY

PD78014H EMI-noise reduced version of the PD78018F

Basic subseries for control

On-chip UART, capable of operating at low voltage (1.8 V)

42/44-pin

64-pin

52-pin 52-pin version of the PD780024A

PD780024AS

52-pin 52-pin version of the PD780034A

PD780034AS

PD78054 with IEBus controller

PD78054 with enhanced serial I/O

PD78078Y with enhanced serial I/O and limited functions

PD78054 with timer and enhanced external interface

64-pin

80-pin

80-pin EMI-noise reduced version of the PD78054

PD78018F with UART and D/A converter, and enhanced I/O

PD780034A

PD780988

PD780034AY

64-pin

PD780024A with expanded RAM

PD780024A with enhanced A/D converter

On-chip inverter controller and UART. EMI-noise reduced.

PD78064

PD78064B

PD780308

100-pin

100-pin PD780308Y

PD78064Y

80-pin

78K/0

Series

LCD drive

PD78064 with enhanced SIO, and expanded ROM and RAM

EMI-noise reduced version of the PD78064

Basic subseries for driving LCDs, on-chip UART

Bus interface supported

µµ

PD78018F with enhanced serial I/O

80-pin

100-pin

Products in mass production Products under development

Y subseries products are compatible with I

C bus.

ROMless version of the PD78078

100-pin

100-pin EMI-noise reduced version of the PD78078

Inverter control

PD780208100-pin

VFD drive

PD78044F with enhanced I/O and VFD C/D. Display output total: 53

PD78098B

100-pin

PD780024A PD780024AY

µµ

80-pin

80-pin PD780852

PD780828B

For automobile meter driver. On-chip CAN controller

100-pin PD780958

For industrial meter control

On-chip automobile meter controller/driver

Meter control

80-pin On-chip IEBus controller

80-pin

On-chip controller compliant with J1850 (Class 2)

PD780833Y

PD780948 On-chip CAN controller

64-pin PD780078 PD780078Y

µµ

PD780034A with timer and enhanced serial I/O

PD78054 PD78054Y

PD78058F PD78058FY

PD780058 PD780058Y

µµ

PD78070A PD78070AY

PD78078 PD78078Y

PD780018AY

Control

PD78075B

PD780065

PD78044H

PD780232

80-pin

80-pin For panel control. On-chip VFD C/D. Display output total: 53

PD78044F with N-ch open-drain I/O. Display output total: 34

PD78044F

80-pin Basic subseries for driving VFD. Display output total: 34

120-pin

PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.

PD780318

PD780328

120-pin

PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.

PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.

PD780338

PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.

On-chip CAN controller

Specialized for CAN controller function

80-pin

PD780703AY

PD780702Y

64-pin PD780816

PD780344 with enhanced A/D converter

100-pin

PD780344 PD780344Y

PD780354 PD780354Y

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

The major functional differences between the subseries are shown below.

• Subseries with the suffix Y

Function ROM Timer 8-Bit 10-Bit 8-Bit Serial Interface I/O VDD

External

Subseries Name Capacity 8-Bit 16-Bit

Watch

WDT A/D A/D D/A

MIN. Value Expansion

Control

PD78078Y

48 KB to 60 KB

4 ch 1 ch 1 ch 1 ch 8 ch −2 ch 3 ch (UART: 1 ch, 88 1.8 V Yes

PD78070AY −I2C: 1 ch) 61 2.7 V

PD780018AY

48 KB to 60 KB

−3 ch (I2C: 1 ch) 88

PD780058Y

24 KB to 60 KB

2 ch 2 ch 3 ch (time-division 68 1.8 V

UART: 1 ch, I

C: 1 ch)

PD78058FY

48 KB to 60 KB

3 ch (UART: 1 ch, 69 2.7 V

PD78054Y

16 KB to 60 KB

I2C: 1 ch) 2.0 V

PD780078Y

48 KB to 60 KB

2 ch −8 ch −4 ch (UART: 2 ch, 52 1.8 V

I2C: 1 ch)

PD780034AY

8 KB to 32 KB

1 ch 3 ch (UART: 1 ch, 51

PD780024AY 8 ch −I2C: 1 ch)

PD78018FY

8 KB to 60 KB

2 ch (I2C: 1 ch) 53

LCD

PD780354Y

24 KB to 32 KB

4 ch 1 ch 1 ch 1 ch −8 ch −4 ch (UART: 1 ch, 66 1.8 V −

drive

PD780344Y 8 ch −I2C: 1 ch)

PD780308Y

48 KB to 60 KB

2 ch 3 ch (time-division 57 2.0 V

UART: 1 ch, I

C: 1 ch)

PD78064Y

16 KB to 32 KB

2 ch (UART: 1 ch,

I2C: 1 ch)

Bus

PD780702Y 60 KB 3 ch 2 ch 1 ch 1 ch 16 ch −−4 ch (UART: 1 ch, 67 3.5 V −

interface

PD780703AY 59.5 KB I2C: 1 ch)

supported

PD780833Y 60 KB 65 4.5 V

Remark The functions of the subseries without the suffix Y and the subseries with the suffix Y are the same, except

for the serial interface (if a subseries without the suffix Y is available).

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.7 Block Diagram

TI00/TO0/P70 16-bit timer/

event counter 0

Serial

interface SIO30

Interrupt control

Clock/buzzer

output control

UART0

78K/0

CPU core

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7 P70 to P75

P64 to P67

P50 to P57

P40 to P47

P30 to P36

P20 to P25

P10 to P17

P00 to P03

External access

System control

RESET

XT1

XT2

RD/P64

WR/P65

WAIT/P66

ASTB/P67

AD0/P40 to

AD7/P47

A8/P50 to

A15/P57

ROM

(flash

memory)

RAM

A/D converter

C bus

DD0

DD1

SS0

SS1

)

Watchdog timer

Watch timer

8-bit timer/

event counter 50

8-bit timer/

event counter 51

TI50/TO50/P72

TI51/TO51/P73

SI30/P20

SO30/P21

SCK30/P22

RxD0/P23

TxD0/P24

ASCK0/P25

REF

SDA0/P32

SCL0/P33

BUZ/P75

PCL/P74

ANI0/P10 to

ANI7/P17

INTP0/P00 to

INTP3/P03

TI01/P71

Remarks 1. The internal ROM and RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the

PD78F0034AY, 78F0034BY.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.8 Outline of Function

Part Number

PD780021AY

PD780022AY

PD780023AY

PD780024AY

PD78F0034AY

Item

PD780031AY

PD780032AY

PD780033AY

PD780034AY

PD78F0034BY

Internal memory ROM 8 KB 16 KB 24 KB 32 KB 32 KBNote

(Mask ROM) (Mask ROM) (Mask ROM) (Mask ROM)

(Flash memory)

High-speed RAM 512 bytes 1024 bytes

1024 bytes

Note

Memory space 64 KB

General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction Minimum instruction execution time changeable function

execution time When main system 0.238

s/0.477

s/0.954

s/1.90

s/3.81

s (@ 8.38 MHz operation)

clock selected

When subsystem 122

s (@ 32.768 kHz operation)

clock selected

Instruction set • 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

I/O port Total: 51

• CMOS input: 8

• CMOS I/O: 39

• N-ch open-drain I/O (5 V breakdown): 4

A/D converter •8-bit resolution × 8 channels

(

PD780021AY, 780022AY, 780023AY, 780024AY)

•10-bit resolution × 8 channels (

PD780031AY, 780032AY, 780033AY,

780034AY, 78F0034AY, 78F0034BY)

•Low-voltage operation: AVDD = 1.8 to 5.5 V

Serial interface • 3-wire serial I/O mode: 1 channel

• UART mode: 1 channel

• I2C bus mode: 1 channel

Timer • 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Timer output Three outputs (8-bit PWM output enable: 2)

Clock output •

65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz

(8.38 MHz with main system clock)

• 32.768 kHz (32.768 kHz with subsystem clock)

Buzzer output 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (8.38 MHz with main system clock)

Vectored interrupt Maskable Internal: 13, External: 5

source

Non-maskable

Internal: 1

Software 1

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Package • 64-pin plastic SDIP (19.05 mm (750))

• 64-pin plastic QFP (14 × 14)

• 64-pin plastic LQFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

• 64-pin plastic LQFP (10 × 10)

• 73-pin plastic FBGA (9 × 9) (standard grade product only)

Note The capacities of internal flash memory and internal high-speed RAM can be changed by means of the

memory size switching register (IMS).

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

The outline of the timer/event counter is as follows (for details, see CHAPTER 8 16-BIT TIMER/EVENT COUNTER

0, CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51, CHAPTER 10 WATCH TIMER, and CHAPTER 11

WATCHDOG TIMER).

16-Bit Timer/ 8-Bit Timer/ Watch Timer Watchdog Timer

Event Counter 0

Event Counters 50, 51

Operation Interval timer 1 channel 2 channels 1 channelNote 1 1 channelNote 2

Mode External event counter √√ ––

Function Timer output √√ ––

PPG output √–––

PWM output –√––

Pulse width measurement

√–––

Square-wave output √√ ––

Interrupt request √√ √√

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer can perform either the watchdog timer function or the interval timer function.

2.9 Correspondence Between Mask ROM Versions and Flash Memory Versions

Table 2-1. Correspondence Between Mask ROM Versions and Flash Memory Versions

Mask ROM Version

PD780021AY/2AY/3AY/4AY

PD780021AY(A)/2AY(A)/3AY(A)/4AY(A)

PD780031AY/2AY/3AY/4AY

PD780031AY(A)/2AY(A)/3AY(A)/4AY(A)

Flash Memory Version

PD78F0034AY √−

PD78F0034BY √−

PD78F0034BY(A) −√

Remarks 1. √: Supported, −: Not supported

2. The

PD780034AY and

PD78F0034BY, 78F0034BY(A) differ in the communication mode of flash

memory programming. See 23.1 Differences Between

PD78F0034A, 78F0034AY and

PD78F0034B,

78F0034BY.

3. Expanded-specification products of the

PD780024AY and 780034AY Subseries are not available.

Only conventional products are available.

4. A special grade product of the

PD78F0034AY is not available. Only a standard grade product is

available.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.10 Differences Between Standard Grade Products and Special Grade Products

The differences between standard grade products (

PD780021AY, 780022AY, 780023AY, 780024AY, 780031AY,

780032AY, 780033AY, 780034AY, 78F0034AY, 78F0034BY) and special grade products (

PD780021AY(A),

780022AY(A), 780023AY(A), 780024AY(A), 780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A), 78F0034BY(A))

are shown in Table 2-2.

Table 2-2. Differences Between Standard Grade Products and Special Grade Products

PD780021AY, 780022AY, 780023AY,

PD780021AY(A), 780022AY(A),

780024AY, 780031AY, 780032AY, 780023AY(A), 780024AY(A), 780031AY(A),

780033AY, 780034AY, 78F0034AY, 780032AY(A), 780033AY(A), 780034AY(A),

78F0034BY 78F0034BY(A)

Quality grade Standard Special

Package See 2.11 Correspondence Between Products and Packages

Other (functions, electrical Same

specifications, etc.)

2.11 Correspondence Between Products and Packages

The following table shows the correspondence between the products and packages.

Table 2-3. Correspondence Between Products and Packages

Mask ROM Version Flash Memory Version

PD780021AY/2AY/3AY/4AY

PD78F0034AY

PD78F0034BY

PD780031AY/2AY/3AY/4AY

Standard Special Standard Standard Special

64-pin SDIP (CW type) √√

Note 1 √− −

64-pin QFP (GC-AB8 type) √√

Note 2 √− −

64-pin LQFP (GC-8BS type) √√

Note 1 √√ √

64-pin TQFP (GK-9ET type) √√

Note 1 √√ √

64-pin LQFP (GB-8EU type) √√

Note 1 √√ √

73-pin FBGA (F1-CN3 type) √−−√ −

Notes 1. Under development

2. Only the

PD780022AYGC(A)-AB8 is under mass production. The other models are still under

development.

Remarks 1. √: Package available, −: Package not available

2. A special grade product of the

PD78F0034AY is not available. Only a standard grade product is

available.

CHAPTER 2 OUTLINE (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

2.12 Mask Options

The mask ROM versions (

PD780021AY, 780022AY, 780023AY, 780024AY, 780031AY, 780032AY, 780033AY,

780034AY) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor

to a specific port pin when the user places an order for device production. Using the mask option when pull-up resistors

are required reduces the number of components to add to the device, resulting in board space saving.

The mask options provided in the

PD780024AY and 780034AY Subseries are shown in Table 2-4.

Table 2-4. Mask Options of Mask ROM Versions

Pin Names Mask Option

P30, P31 Pull-up resistor connection can be specified in 1-bit units.

User’s Manual U14046EJ3V0UD

Pin Name I/O Function After Reset Alternate

Function

P00 I/O Input INTP0

P01 INTP1

P02 INTP2

P03 INTP3/ADTRG

P10 to P17 Input Port 1 Input ANI0 to ANI7

8-bit input-only port.

P20 I/O Input SI30

P21 SO30

P22 SCK30

P23 RxD0

P24 TxD0

P25 ASCK0

P30 I/O Input −

P31

P32

P33

P34 SI31

P35 SO31

P36 SCK31

P40 to P47 I/O Port 4 Input AD0 to AD7

8-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Interrupt request flag (KRIF) is set to 1 by falling edge

detection.

P50 to P57 I/O Port 5 Input A8 to A15

8-bit I/O port

LEDs can be driven directly.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

P64 I/O Input RD

P65 WR

P66 WAIT

P67 ASTB

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

3.1 Pin Function List

(1) Port pins (1/2)

Port 0

4-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

Port 2

6-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

Port 3

7-bit I/O port

Input/output mode

can be specified in

1-bit units.

N-ch open-drain I/O port

On-chip pull-up resistor can be

specified by mask option

(mask ROM version only).

LEDs can be driven directly.

An on-chip pull-up resistor can be

used by software settings.

Port 6

4-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

Pin Name I/O Function After Reset Alternate

Function

INTP0 Input Input P00

INTP1 P01

INTP2 P02

INTP3 P03/ADTRG

SI30 Input Serial interface serial data input Input P20

SI31 P34

SO30 Output Serial interface serial data output Input P21

SO31 P35

SCK30 I/O Serial interface serial clock input/output Input P22

SCK31 P36

RxD0 Input Asynchronous serial interface serial data input Input P23

TxD0 Output Asynchronous serial interface serial data output Input P24

ASCK0 Input Asynchronous serial interface serial clock input Input P25

TI00 Input External count clock input to 16-bit timer/event counter 0 Input P70/TO0

Capture trigger input to 16-bit timer/event counter 0 capture

TI01 Capture trigger input to 16-bit timer/event counter 0 P71

capture register (CR00)

TI50 External count clock input to 8-bit timer/event counter 50 P72/TO50

TI51 External count clock input to 8-bit timer/event counter 51 P73/TO51

TO0 Output 16-bit timer/event counter 0 output Input P70/TI00

TO50 8-bit timer/event counter 50 output Input P72/TI50

(also used for 8-bit PWM output)

TO51 8-bit timer/event counter 51 output P73/TI51

(also used for 8-bit PWM output)

PCL Output Clock output (for main system clock and subsystem clock Input P74

trimming)

BUZ Output Buzzer output Input P75

AD0 to AD7 I/O Lower address/data bus when expanding external memory Input P40 to P47

Pin Name I/O Function After Reset Alternate

Function

P70 I/O Input TI00/TO0

P71 TI01

P72 TI50/TO50

P73 TI51/TO51

P74 PCL

P75 BUZ

(2) Non-port pins (1/2)

(1) Port pins (2/2)

External interrupt request input with specifiable valid edges

(rising edge, falling edge, both rising and falling edges)

Port 7

6-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

Pin Name I/O Function After Reset Alternate

Function

A8 to A15 Output Higher address bus when expanding external memory Input P50 to P57

RD Output

Strobe signal output for read operation from external memory

Input P64

Strobe signal output for write operation from external memory

P65

WAIT Input Wait insertion when accessing external memory Input P66

ASTB Output Strobe output externally latching address information Input P67

output to ports 4, 5 to access external memory

ANI0 to ANI7

Input A/D converter analog input Input P10 to P17

ADTRG Input A/D converter trigger signal input Input P03/INTP3

AVREF Input A/D converter reference voltage input −−

AVDD −

A/D converter analog power supply. Connect to V

DD0

or V

DD1

−−

AVSS −A/D converter ground potential. Connect to VSS0 or VSS1.−−

RESET Input System reset input Input −

X1 Input Crystal/ceramic connection for main system clock oscillation −−

X2 −−−

XT1 Input Crystal connection for subsystem clock oscillation −−

XT2 −−−

VDD0 −Positive power supply for ports −−

VDD1 −Positive power supply other than ports −−

VSS0 −Ground potential for ports −−

VSS1 −Ground potential other than ports −−

IC −Internally connected. Connect directly to VSS0 or VSS1.−−

NCNote −Not internally connected. Leave open. −−

VPP −High-voltage application for program write/verify. −−

Note The NC pin is available only for a 73-pin plastic FBGA.

(2) Non-port pins (2/2)

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

3.2 Description of Pin Functions

3.2.1 P00 to P03 (Port 0)

These are 4-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt input, and A/D

converter external trigger input.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 4-bit I/O ports.

P00 to P03 can be specified as input or output ports in 1-bit units with port mode register 0 (PM0). On-chip pull-

up resistors can be used by setting pull-up resistor option register 0 (PU0).

(2) Control mode

These ports function as an external interrupt request input, and A/D converter external trigger input.

(a) INTP0 to INTP3

INTP0 to INTP3 are external interrupt request input pins which can specify valid edges (rising edge, falling

edge, and both rising and falling edges).

(b) ADTRG

A/D converter external trigger input pin.

Caution When P03 is used as an A/D converter external trigger input, specify the valid edge by

bits 1, 2 (EGA00, EGA01) of A/D converter mode register (ADM0) and set interrupt mask

flag (PMK3) to 1.

3.2.2 P10 to P17 (Port 1)

These are 8-bit input-only ports. Besides serving as input ports, they function as an A/D converter analog input.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input-only ports.

(2) Control mode

These ports function as A/D converter analog input pins (ANI0 to ANI7).

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

3.2.3 P20 to P25 (Port 2)

These are 6-bit I/O ports. Besides serving as I/O ports, they function as data I/O and clock I/O of serial interface

SIO30 or UART0.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 6-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

(2) Control mode

These ports function as data I/O and clock I/O of serial interface SIO30 or UART0.

(a) SI30 and SO30

Serial data I/O pins of serial interface SIO30.

(b) SCK30

Serial clock I/O pin of serial interface SIO30.

Serial data I/O pins of serial interface UART0.

(d) ASCK0

Serial clock input pin of serial interface UART0.

3.2.4 P30 to P36 (Port 3)

These are 7-bit I/O ports. Besides serving as I/O ports, they function as data I/O and clock I/O of serial interface

SIO31.

P30 to P33 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 7-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

(mask ROM version only). On-chip pull-up resistors of P34 to P36 can be used by setting pull-up resistor option

(2) Control mode

These ports function as data I/O and clock I/O of serial interface SIO31.

(a) SI31 and SO31

Serial data I/O pins of serial interface SIO31.

(b) SCK31

Serial clock I/O pin of serial interface SIO31.

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

3.2.5 P40 to P47 (Port 4)

These are 8-bit I/O ports. Besides serving as I/O ports, they function as an address/data bus.

The interrupt request flag (KRIF) can be set to 1 by detecting a falling edge.

The following operating mode can be specified in 1-bit units.

Caution When using the falling edge detection interrupt (INTKR), be sure to set the memory expansion

mode register (MEM) to 01H.

(1) Port mode

These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

(2) Control mode

These ports function as lower address/data bus pins (AD0 to AD7) in external memory expansion mode.

3.2.6 P50 to P57 (Port 5)

These are 8-bit I/O ports. Besides serving as I/O ports, they function as an address bus.

Port 5 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

(2) Control mode

These ports function as higher address bus pins (A8 to A15) in external memory expansion mode.

3.2.7 P64 to P67 (Port 6)

These are 4-bit I/O ports. Besides serving as I/O ports, they are used for control in external memory expansion

mode.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 4-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

On-chip pull-up resistors can be used by setting pull-up resistor option register 6 (PU6).

(2) Control mode

These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.

Caution When external wait is not used in external memory expansion mode, P66 can be used as an

I/O port.

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

3.2.8 P70 to P75 (Port 7)

These are 6-bit I/O ports. Besides serving as I/O ports, they function as a timer I/O, clock output, and buzzer output.

The following operating modes can be specified in 1-bit units.

(1) Port mode

Port 7 functions as a 6-bit I/O port. They can be specified as an input port or output port in 1-bit units with port

mode register 7 (PM7). On-chip pull-up resistors can be used by setting pull-up resistor option register 7 (PU7).

P70 and P71 are also 16-bit timer/event counter 0 capture trigger signal input pins with a valid edge input.

(2) Control mode

Port 7 functions as timer I/O, clock output, and buzzer output.

(a) TI00

External count clock input pin to 16-bit timer/event counter 0 and capture trigger signal input pin to 16-bit

timer/event counter capture register (CR01).

(b) TI01

Capture trigger signal input pin to 16-bit timer/event counter 0 capture register (CR00).

External count clock input pins to 8-bit timer/event counters 50 and 51.

(d) TO0, TO50, and TO51

Timer output pins.

(e) PCL

Clock output pin.

(f) BUZ

Buzzer output pin.

3.2.9 AVREF

This is an A/D converter reference voltage input pin.

When no A/D converter is used, connect this pin directly to VSS0 or VSS1.

3.2.10 AVDD

This is an analog power supply pin of A/D converter. Always use the same potential as that of the VDD0 pin or VDD1

pin even when no A/D converter is used.

3.2.11 AVSS

This is a ground potential pin of A/D converter. Always use the same potential as that of the VSS0 pin or VSS1 pin

even when no A/D converter is used.

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

3.2.12 RESET

This is a low-level active system reset input pin.

3.2.13 NC

NC (Non-connection) pin is not internally connected. Leave this pin open.

3.2.14 X1 and X2

Crystal/ceramic resonator connection pins for main system clock oscillation.

For external clock supply, input clock signal to X1 and its inverted signal to X2.

3.2.15 XT1 and XT2

Crystal resonator connection pins for subsystem clock oscillation.

For external clock supply, input the clock signal to XT1 and its inverted signal to XT2.

3.2.16 VDD0 and VDD1

VDD0 is a positive power supply port pin.

VDD1 is a positive power supply pin other than port pin.

3.2.17 VSS0 and VSS1

VSS0 is a ground potential port pin.

VSS1 is a ground potential pin other than port pin.

3.2.18 VPP (flash memory versions only)

High-voltage apply pin for flash memory programming mode setting and program write/verify.

Handle in either of the following ways.

• Independently connect a 10 kΩ pull-down resistor.

• Set the jumper on the board so that this pin is connected directly to the dedicated flash programmer in

programming mode and directly to VSS0 or VSS1 in normal operation mode.

When there is a potential difference between the VPP pin and VSS0 pin or VSS1 pin because the wiring between the

two pins is too long or external noise is input to the VPP pin, the user program may not operate normally.

3.2.19 IC (mask ROM version only)

The IC (Internally Connected) pin is provided to set the test mode to check the

PD780024A, 780034A Subseries

at delivery. Connect it directly to the VSS0 or VSS1 pin with the shortest possible wire in the normal operating mode.

When a potential difference is produced between the IC pin and VSS0 pin or VSS1 pin, because the wiring between

those two pins is too long or an external noise is input to the IC pin, the user’s program may not operate normally.

• Connect IC pins to VSS0 pins or VSS1 pins directly.

As short as possible

ICV

SS0

SS1

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 3-1 shows the types of pin I/O circuit and the recommended connections of unused pins.

See Figure 3-1 for the configuration of the I/O circuit of each type.

Table 3-1. Pin I/O Circuit Types (1/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

P00/INTP0 to P02/INTP2 8-C I/O Input: Independently connect to VSS0 or VSS1 via a

P03/INTP3/ADTRG resistor.

Output: Leave open.

P10/ANI0 to P17/ANI7 25 Input Connect directly to VDD0, VDD1, VSS0, or VSS1.

P20/SI30 8-C I/O Input: Independently connect to VDD0, VDD1, VSS0,

P21/SO30 5-H or VSS1 via a resistor.

P22/SCK30 8-C

Output: Leave open.

P23/RxD0

P24/TxD0 5-H

P25/ASCK0 8-C

P30, P31 13-Q Input: Connect directly to VSS0 or VSS1.

(for mask ROM version) Output: Set the output latch of the port to 0, and

P30, P31 13-P leave these pins open at low level.

(for flash memory version)

P32, P33 13-S

(for mask ROM version)

P32, P33 13-R

(for flash memory version)

P34/SI31 8-C Input: Independently connect to VDD0, VDD1, VSS0,

P35/SO31 5-H or VSS1 via a resistor.

P36/SCK31 8-C

Output: Leave open.

P40/AD0 to P47/AD7 5-H Input: Independently connect to VDD0 or VDD1 via a

resistor.

Output: Leave open.

CHAPTER 3 PIN FUNCTION (

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User’s Manual U14046EJ3V0UD

Table 3-1. Pin I/O Circuit Types (2/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

P50/A8 to P57/A15 5-H I/O Input: Independently connect to VDD0, VDD1, VSS0,

P64/RD or VSS1 via a resistor.

P65/WR

Output: Leave open.

P66/WAIT

P67/ASTB

P70/TI00/TO0 8-C

P71/TI01

P72/TI50/TO50

P73/TI51/TO51

P74/PCL 5-H

P75/BUZ

RESET 2 Input −

NCNote −−Leave open.

XT1 16 Input Connect directly to VDD0 or VDD1.

XT2 −Leave open.

AVDD −Connect directly to VDD0 or VDD1.

AVREF Connect directly to VSS0 or VSS1.

AVSS

IC (for mask ROM version)

VPP Independently connect a 10 kΩ pull-down resistor

(for flash memory version) to this pin, or connect directly to VSS0 or VSS1.

Note The NC pin is available only for a 73-pin plastic FBGA.

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

Figure 3-1. Pin I/O Circuit List (1/2)

Type 2

Schmitt-triggered input with hysteresis characteristics

Type 8-C

Data

Output

disable

P-ch

IN/OUT

DD0

N-ch

P-ch

DD0

Pullup

enable

Type 5-H

Data

Output

disable

P-ch

IN/OUT

DD0

N-ch

Input

enable

P-ch

DD0

Pullup

enable

Type 13-Q

Data

Output disable

IN/OUT

N-ch

DD0

Mask

option













Data

Output disable

IN/OUT

N-ch

Data

Output disable

IN/OUT

N-ch

Type 13-P

Input

enable

SS0

Input

enable

SS0

Type 13-R

SS0

CHAPTER 3 PIN FUNCTION (

PD780024A, 780034A SUBSERIES)

User’s Manual U14046EJ3V0UD

Figure 3-1. Pin I/O Circuit List (2/2)

P-ch

Feedback

cut-off

XT1 XT2

Type 13-S

Type 16

Data

Output disable

IN/OUT

N-ch

Input

enable

Comparator

—

P-ch

N-ch

REF

(threshold voltage)

SS0

Type 25

SS0

DD0

Mask

option













User’s Manual U14046EJ3V0UD

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

4.1 Pin Function List

(1) Port pins (1/2)

Pin Name I/O Function After Reset Alternate

Function

P00 I/O Input INTP0

P01 INTP1

P02 INTP2

P03 INTP3/ADTRG

P10 to P17 Input Port 1 Input ANI0 to ANI7

8-bit input-only port.

P20 I/O Input SI30

P21 SO30

P22 SCK30

P23 RxD0

P24 TxD0

P25 ASCK0

P30 I/O Input −

P31

P32 SDA0

P33 SCL0

P34 −

P35

P36

P40 to P47 I/O Port 4 Input AD0 to AD7

8-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Interrupt request flag (KRIF) is set to 1 by falling edge

detection.

P50 to P57 I/O Port 5 Input A8 to A15

8-bit I/O port

LEDs can be driven directly.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

P64 I/O Input RD

P65 WR

P66 WAIT

P67 ASTB

Port 0

4-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

Port 2

6-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

Port 3

7-bit I/O port

Input/output

mode can be

specified in 1-bit

units.

N-ch open-drain I/O port

On-chip pull-up resistor can be

specified by mask option

(P30 and P31 are mask ROM version only).

LEDs can be driven directly.

An on-chip pull-up resistor can be

used by software settings.

Port 6

4-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

(1) Port pins (2/2)

(2) Non-port pins (1/2)

Pin Name I/O Function After Reset Alternate

Function

P70 I/O Input TI00/TO0

P71 TI01

P72 TI50/TO50

P73 TI51/TO51

P74 PCL

P75 BUZ

Port 7

6-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software

settings.

Pin Name I/O Function After Reset Alternate

Function

INTP0 Input Input P00

INTP1 P01

INTP2 P02

INTP3 P03/ADTRG

SI30 Input Serial interface serial data input Input P20

SO30 Output Serial interface serial data output Input P21

SDA0 I/O Serial interface serial data input/output Input P32

SCK30 I/O Serial interface serial clock input/output Input P22

SCL0 P33

RxD0 Input Asynchronous serial interface serial data input Input P23

TxD0 Output Asynchronous serial interface serial data output Input P24

ASCK0 Input Asynchronous serial interface serial clock input Input P25

TI00 Input External count clock input to 16-bit timer/event counter 0 Input P70/TO0

Capture trigger input to 16-bit timer/event counter 0 capture

TI01 Capture trigger input to 16-bit timer/event counter 0 P71

capture register (CR00)

TI50 External count clock input to 8-bit timer/event counter 50 P72/TO50

TI51 External count clock input to 8-bit timer/event counter 51 P73/TO51

TO0 Output 16-bit timer/event counter 0 output Input P70/TI00

TO50 8-bit timer/event counter 50 output Input P72/TI50

(also used for 8-bit PWM output)

TO51 8-bit timer/event counter 51 output P73/TI51

(also used for 8-bit PWM output)

PCL Output Clock output (for main system clock and subsystem clock Input P74

trimming)

BUZ Output Buzzer output Input P75

AD0 to AD7 I/O Lower address/data bus when expanding external memory Input P40 to P47

A8 to A15 Output Higher address bus when expanding external memory Input P50 to P57

RD Output

Strobe signal output for read operation from external memory

Input P64

Strobe signal output for write operation from external memory

P65

External interrupt request input with specifiable valid edges

(rising edge, falling edge, both rising and falling edges)

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

Pin Name I/O Function After Reset Alternate

Function

WAIT Input Wait insertion when accessing external memory Input P66

ASTB Output Strobe output externally latching address information Input P67

output to ports 4, 5 to access external memory

ANI0 to ANI7

Input A/D converter analog input Input P10 to P17

ADTRG Input A/D converter trigger signal input Input P03/INTP3

AVREF Input A/D converter reference voltage input −−

AVDD −A/D converter analog power supply. Connect to VDD0 or VDD1.−−

AVSS −A/D converter ground potential. Connect to VSS0 or VSS1.−−

RESET Input System reset input Input −

X1 Input Crystal connection for main system clock oscillation −−

X2 −−−

XT1 Input Crystal connection for subsystem clock oscillation −−

XT2 −−−

VDD0 −Positive power supply for ports −−

VDD1 −Positive power supply other than ports −−

VSS0 −Ground potential for ports −−

VSS1 −Ground potential other than ports −−

IC −Internally connected. Connect directly to VSS0 or VSS1.−−

NCNote −Not internally connected. Leave open. −−

VPP −High-voltage application for program write/verify. −−

Note The NC pin is available only for a 73-pin plastic FBGA.

(2) Non-port pins (2/2)

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

4.2 Description of Pin Functions

4.2.1 P00 to P03 (Port 0)

These are 4-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt input, and A/D

converter external trigger input.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 4-bit I/O ports.

P00 to P03 can be specified as input or output ports in 1-bit units with port mode register 0 (PM0). On-chip pull-

up resistors can be used by setting pull-up resistor option register 0 (PU0).

(2) Control mode

These ports function as an external interrupt request input, and A/D converter external trigger input.

(a) INTP0 to INTP3

INTP0 to INTP3 are external interrupt request input pins which can specify valid edges (rising edge, falling

edge, and both rising and falling edges).

(b) ADTRG

A/D converter external trigger input pin.

Caution When P03 is used as an A/D converter external trigger input, specify the valid edge by

bits 1, 2 (EGA00, EGA01) of A/D converter mode register (ADM0) and set interrupt mask

flag (PMK3) to 1.

4.2.2 P10 to P17 (Port 1)

These are 8-bit input-only ports. Besides serving as input ports, they function as an A/D converter analog input.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit input-only ports.

(2) Control mode

These ports function as A/D converter analog input pins (ANI0 to ANI7).

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

4.2.3 P20 to P25 (Port 2)

These are 6-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 6-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

(2) Control mode

These ports function as data I/O and clock I/O of serial interface SIO30 or UART0.

(a) SI30 and SO30

Serial data I/O pins of serial interface SIO30.

(b) SCK30

Serial clock I/O pin of serial interface SIO30.

Serial data I/O pins of serial interface UART0.

(d) ASCK0

Serial clock input pin of serial interface UART0.

4.2.4 P30 to P36 (Port 3)

These are 7-bit I/O ports. Besides serving as I/O ports, they function as data I/O and clock I/O of serial interface

IIC0.

P30 to P33 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 7-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

in P30 and P31 with the mask option. On-chip pull-up resistors of P34 to P36 can be used by setting pull-up

resistor option register 3 (PU3).

(2) Control mode

These ports function as data I/O and clock I/O of serial interface IIC0.

(a) SDA0

Serial data I/O pin of serial interface IIC0.

(b) SCL0

Serial clock I/O pin of serial interface IIC0.

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

4.2.5 P40 to P47 (Port 4)

These are 8-bit I/O ports. Besides serving as I/O ports, they function as an address/data bus.

The interrupt request flag (KRIF) can be set to 1 by detecting a falling edge.

The following operating mode can be specified in 1-bit units.

Caution When using the falling edge detection interrupt (INTKR), be sure to set the memory expansion

mode register (MEM) to 01H.

(1) Port mode

These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

(2) Control mode

These ports function as lower address/data bus pins (AD0 to AD7) in external memory expansion mode.

4.2.6 P50 to P57 (Port 5)

These are 8-bit I/O ports. Besides serving as I/O ports, they function as an address bus.

Port 5 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 8-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

(2) Control mode

These ports function as higher address bus pins (A8 to A15) in external memory expansion mode.

4.2.7 P64 to P67 (Port 6)

These are 4-bit I/O ports. Besides serving as I/O ports, they are used for control in external memory expansion

mode.

The following operating modes can be specified in 1-bit units.

(1) Port mode

These ports function as 4-bit I/O ports. They can be specified as input or output ports in 1-bit units with port mode

On-chip pull-up resistors can be used by setting pull-up resistor option register 6 (PU6).

(2) Control mode

These ports function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.

Caution When external wait is not used in external memory expansion mode, P66 can be used as an

I/O port.

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

4.2.8 P70 to P75 (Port 7)

These are 6-bit I/O ports. Besides serving as I/O ports, they function as a timer I/O, clock output, and buzzer output.

The following operating modes can be specified in 1-bit units.

(1) Port mode

Port 7 functions as a 6-bit I/O port. They can be specified as an input port or output port in 1-bit units with port

mode register 7 (PM7). On-chip pull-up resistors can be used by setting pull-up resistor option register 7 (PU7).

P70 and P71 are also 16-bit timer/event counter 0 capture trigger signal input pins with a valid edge input.

(2) Control mode

Port 7 functions as timer I/O, clock output, and buzzer output.

(a) TI00

External count clock input pin to 16-bit timer/event counter 0 and capture trigger signal input pin to 16-bit

timer/event counter capture register (CR01).

(b) TI01

Capture trigger signal input pin to 16-bit timer/event counter 0 capture register (CR00).

External count clock input pins to 8-bit timer/event counters 50 and 51.

(d) TO0, TO50, and TO51

Timer output pins.

(e) PCL

Clock output pin.

(f) BUZ

Buzzer output pin.

4.2.9 AVREF

This is an A/D converter reference voltage input pin.

When no A/D converter is used, connect this pin directly to VSS0 or VSS1.

4.2.10 AVDD

This is an analog power supply pin of A/D converter. Always use the same potential as that of the VDD0 pin or VDD1

pin even when no A/D converter is used.

4.2.11 AVSS

This is a ground potential pin of A/D converter. Always use the same potential as that of the VSS0 pin or VSS1 pin

even when no A/D converter is used.

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

4.2.12 RESET

This is a low-level active system reset input pin.

4.2.13 NC

NC (Non-connection) pin is not internally connected. Leave this pin open.

4.2.14 X1 and X2

Crystal/ceramic resonator connection pins for main system clock oscillation.

For external clock supply, input the clock signal to X1 and its inverted signal to X2.

4.2.15 XT1 and XT2

Crystal resonator connection pins for subsystem clock oscillation.

For external clock supply, input the clock signal to XT1 and its inverted signal to XT2.

4.2.16 VDD0 and VDD1

VDD0 is a positive power supply pin.

VDD1 is a positive power supply pin other than port pin.

4.2.17 VSS0 and VSS1

VSS0 is a ground potential port pin.

VSS1 is a ground potential pin other than port pin.

4.2.18 VPP (flash memory versions only)

High-voltage apply pin for flash memory programming mode setting and program write/verify.

Handle in either of the following ways.

• Independently connect a 10 kΩ pull-down resistor.

• Set the jumper on the board so that this pin is connected directly to the dedicated flash programmer in

programming mode and directly to VSS0 or VSS1 in normal operation mode.

When there is a potential difference between the VPP pin and VSS0 pin or VSS1 pin because the wiring between the

two pins is too long or external noise is input to the VPP pin, the user program may not operate normally.

4.2.19 IC (mask ROM version only)

The IC (Internally Connected) pin is provided to set the test mode to check the

PD780024AY, 780034AY Subseries

at delivery. Connect it directly to the VSS0 or VSS1 pin with the shortest possible wire in the normal operating mode.

When a potential difference is produced between the IC pin and VSS0 pin or VSS1 pin, because the wiring between

those two pins is too long or an external noise is input to the IC pin, the user’s program may not operate normally.

• Connect IC pins to VSS0 pins or VSS1 pins directly.

As short as possible

ICVSS0 or VSS1

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

4.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 4-1 shows the types of pin I/O circuit and the recommended connections of unused pins.

See Figure 4-1 for the configuration of the I/O circuit of each type.

Table 4-1. Pin I/O Circuit Types (1/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

P00/INTP0 to P02/INTP2 8-C I/O Input: Independently connect to VSS0 or VSS1 via a

P03/INTP3/ADTRG resistor.

Output: Leave open.

P10/ANI0 to P17/ANI7 25 Input Connect directly to VDD0, VDD1, VSS0, or VSS1.

P20/SI30 8-C I/O Input: Independently connect to VDD0, VDD1, VSS0,

P21/SO30 5-H or VSS1 via a resistor.

P22/SCK30 8-C

Output: Leave open.

P23/RxD0

P24/TxD0 5-H

P25/ASCK0 8-C

P30, P31 13-Q Input: Connect directly to VSS0 or VSS1.

(for mask ROM version) Output: Set the output latch of the port to 0, and

P30, P31 13-P leave these pins open at low level.

(for flash memory version)

P32/SDA0 13-R

P33/SCL0

P34 8-C Input: Independently connect to VDD0, VDD1, VSS0,

P35 5-H or VSS1 via a resistor.

P36 8-C

Output: Leave open.

P40/AD0 to P47/AD7 5-H Input: Independently connect to VDD0 or VDD1 via a

resistor.

Output: Leave open.

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

Table 4-1. Pin I/O Circuit Types (2/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

P50/A8 to P57/A15 5-H I/O Input: Independently connect to VDD0, VDD1, VSS0,

P64/RD or VSS1 via a resistor.

P65/WR

Output: Leave open.

P66/WAIT

P67/ASTB

P70/TI00/TO0 8-C

P71/TI01

P72/TI50/TO50

P73/TI51/TO51

P74/PCL 5-H

P75/BUZ

RESET 2 Input −

NCNote −−Leave open.

XT1 16 Input Connect directly to VDD0 or VDD1.

XT2 −Leave open.

AVDD −Connect directly to VDD0 or VDD1.

AVREF Connect directly to VSS0 or VSS1.

AVSS

IC (for mask ROM version)

VPP Independently connect a 10 kΩ pull-down resistor

(for flash memory version) to this pin, or connect directly to VSS0 or VSS1.

Note The NC pin is available only for a 73-pin plastic FBGA.

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

Figure 4-1. Pin I/O Circuit List (1/2)

Type 2

Schmitt-triggered input with hysteresis characteristics

Type 8-C

Data

Output

disable

P-ch

IN/OUT

DD0

N-ch

P-ch

DD0

Pullup

enable

Type 5-H

Data

Output

disable

P-ch

IN/OUT

DD0

N-ch

Input

enable

P-ch

DD0

Pullup

enable

Type 13-Q

Data

Output disable

IN/OUT

N-ch

DD0

Mask

option













Data

Output disable

IN/OUT

N-ch

Data

Output disable

IN/OUT

N-ch

Type 13-P

Input

enable

SS0

Input

enable

SS0

Type 13-R

SS0

100

CHAPTER 4 PIN FUNCTION (

PD780024AY, 780034AY SUBSERIES)

User’s Manual U14046EJ3V0UD

Figure 4-1. Pin I/O Circuit List (2/2)

P-ch

Feedback

cut-off

XT1 XT2

Type 16

Input

enable

Comparator +

—

P-ch

N-ch

REF

(threshold voltage)

Type 25

SS0

101User’s Manual U14046EJ3V0UD

CHAPTER 5 CPU ARCHITECTURE

5.1 Memory Spaces

PD780024A, 780034A, 780024AY, 780034AY Subseries can access 64 KB memory space respectively.

Figures 5-1 to 5-5 show memory maps.

Caution In case of the internal memory capacity, the initial value of memory size switching register (IMS)

of all products (

PD780024A, 780034A, 780024AY, and 780034AY Subseries) is fixed (IMS =

CFH). Therefore, set the value corresponding to each product indicated below.

PD780021A, 780031A, 780021AY, 780031AY: 42H

PD780022A, 780032A, 780022AY, 780032AY: 44H

PD780023A, 780033A, 780023AY, 780033AY: C6H

PD780024A, 780034A, 780024AY, 780034AY: C8H

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY: Value for mask ROM version

Figure 5-1. Memory Map (

PD780021A, 780031A, 780021AY, 780031AY)

0000H

Data memory

space

General-purpose

registers

32 × 8 bits

Internal ROM

8192 × 8 bits

1FFFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

CALLF entry area

CALLT table area

Vector table area

Program area

External memory

55296 × 8 bits

Program

memory

space

2000H

1FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

512 × 8 bits

Special function

registers (SFRs)

256 × 8 bits

Reserved

FD00H

FCFFH

102

CHAPTER 5 CPU ARCHITECTURE

User’s Manual U14046EJ3V0UD

Figure 5-2. Memory Map (

PD780022A, 780032A, 780022AY, 780032AY)

0000H

Data memory

space

General-purpose

registers

32 × 8 bits

Internal ROM

16384 × 8 bits

3FFFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

CALLF entry area

CALLT table area

Vector table area

Program area

External memory

47104 × 8 bits

Program

memory

space

4000H

3FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

512 × 8 bits

Special function

registers (SFRs)

256 × 8 bits

Reserved

FD00H

FCFFH

103

CHAPTER 5 CPU ARCHITECTURE

User’s Manual U14046EJ3V0UD

Figure 5-3. Memory Map (

PD780023A, 780033A, 780023AY, 780033AY)

0000H

Data memory

space

General-purpose

registers

32 × 8 bits

Internal ROM

24576 × 8 bits

5FFFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

CALLF entry area

CALLT table area

Vector table area

Program area

External memory

38912 × 8 bits

Program

memory

space

6000H

5FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

1024 × 8 bits

Special function

registers (SFRs)

256 × 8 bits

Reserved

FB00H

FAFFH

104

CHAPTER 5 CPU ARCHITECTURE

User’s Manual U14046EJ3V0UD

Figure 5-4. Memory Map (

PD780024A, 780034A, 780024AY, 780034AY)

0000H

Data memory

space

Internal ROM

32768 × 8 bits

7FFFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

CALLF entry area

CALLT table area

Vector table area

Program area

External memory

30720 ×8 bits

Program

memory

space

8000H

7FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

1024 × 8 bits

Special function

registers (SFRs)

256 × 8 bits

Reserved

FB00H

FAFFH

General-purpose

registers

32 × 8 bits

105

CHAPTER 5 CPU ARCHITECTURE

User’s Manual U14046EJ3V0UD

Figure 5-5. Memory Map (

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY)

0000H

Data memory

space

General-purpose

registers

32 × 8 bits

Flash memory

32768 × 8 bits

7FFFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

CALLF entry area

CALLT table area

Vector table area

Program area

External memory

30720 × 8 bits

Program

memory

space

8000H

7FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

1024 × 8 bits

Special function

registers (SFRs)

256 × 8 bits

Reserved

FB00H

FAFFH

106

CHAPTER 5 CPU ARCHITECTURE

User’s Manual U14046EJ3V0UD

5.1.1 Internal program memory space

The internal program memory space contains the program and table data. Normally, it is addressed with the

program counter (PC).

The

PD780024A, 780034A, 780024AY, and 780034AY Subseries products incorporate an on-chip ROM (mask

ROM or flash memory), as listed below.

Table 5-1. Internal ROM Capacity

Part Number Type Capacity

PD780021A, 780031A, 780021AY, 780031AY Mask ROM 8192 × 8 bits (0000H to 1FFFH)

PD780022A, 780032A, 780022AY, 780032AY 16384 × 8 bits (0000H to 3FFFH)

PD780023A, 780033A, 780023AY, 780033AY 24576 × 8 bits (0000H to 5FFFH)

PD780024A, 780034A, 780024AY, 780034AY 32768 × 8 bits (0000H to 7FFFH)

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY Flash memory 32768 × 8 bits (0000H to 7FFFH)

The internal program memory space is divided into the following three areas.

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(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start

addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-

bit address, lower 8 bits are stored at even addresses and higher 8 bits are stored at odd addresses.

Table 5-2. Vector Table

Vector Table Address Interrupt Source

0000H RESET input

0004H INTWDT

0006H INTP0

0008H INTP1

000AH INTP2

000CH INTP3

000EH INTSER0

0010H INTSR0

0012H INTST0

0014H INTCSI30

0016H INTCSI31Note 1

0018H INTIIC0Note 2

001AH INTWTI

001CH INTTM00

001EH INTTM01

0020H INTTM50

0022H INTTM51

0024H INTAD0

0026H INTWT

0028H INTKR

003EH BRK

Notes 1.

PD780024A, 780034A Subseries only

PD780024AY, 780034AY Subseries only

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

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5.1.2 Internal data memory space

The

PD780024A, 780034A, 780024AY, and 780034AY Subseries products incorporate an internal high-speed

RAM, as listed below.

Table 5-3. Internal High-Speed RAM Capacity

Part Number Internal High-Speed RAM

PD780021A, 780031A, 780021AY, 780031AY 512 × 8 bits (FD00H to FEFFH)

PD780022A, 780032A, 780022AY, 780032AY

PD780023A, 780033A, 780023AY, 780033AY 1024 × 8 bits (FB00H to FEFFH)

PD780024A, 780034A, 780024AY, 780034AY

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY

The 32-byte area FEE0H to FEFFH is allocated four general-purpose register banks composed of eight 8-bit

registers.

This area cannot be used as a program area in which instructions are written and executed.

The internal high-speed RAM can also be used as a stack memory.

5.1.3 Special function register (SFR) area

An on-chip peripheral hardware special function register (SFR) is allocated in the area FF00H to FFFFH (see 5.2.3

Special function register (SFR) Table 5-5 Special Function Register List).

Caution Do not access addresses where the SFR is not assigned.

5.1.4 External memory space

The external memory space is accessible with memory expansion mode register (MEM). External memory space

can store program, table data, etc., and allocate peripheral devices.

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5.1.5 Data memory addressing

Addressing refers to the method of specifying the address of the instruction to be executed next or the address

of the register or memory relevant to the execution of instructions.

Several addressing modes are provided for addressing the memory relevant to the execution of instructions for

the

PD780024A, 780034A, 780024AY, and 780034AY Subseries, based on operability and other considerations.

For areas containing data memory in particular, special addressing methods designed for the functions of special

function registers (SFR) and general-purpose registers are available for use. Correspondence between data memory

and addressing is illustrated in Figures 5-6 to 5-10. For the details of each addressing mode, see 5.4 Operand

Address Addressing.

Figure 5-6. Correspondence Between Data Memory and Addressing

(

PD780021A, 780031A, 780021AY, 780031AY)

0000H

General-purpose registers

32 × 8 bits

Internal ROM

8192 × 8 bits

External memory

55296 × 8 bits

2000H

1FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

512 × 8 bits

Reserved

FD00H

FCFFH

FF20H

FF1FH

FE20H

FE1FH

Special function

registers (SFRs)

256 × 8 bits SFR addressing

Short direct

addressing

Direct addressing

addressing

Based addressing

Based indexed

addressing

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Figure 5-7. Correspondence Between Data Memory and Addressing

(

PD780022A, 780032A, 780022AY, 780032AY)

0000H

General-purpose registers

32 × 8 bits

Internal ROM

16384 × 8 bits

External memory

47104 × 8 bits

4000H

3FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

512 × 8 bits

Reserved

FD00H

FCFFH

FF20H

FF1FH

FE20H

FE1FH

Special function

registers (SFRs)

256 × 8 bits SFR addressing

Short direct

addressing

Direct addressing

addressing

Based addressing

Based indexed

addressing

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Figure 5-8. Correspondence Between Data Memory and Addressing

(

PD780023A, 780033A, 780023AY, 780033AY)

0000H

General-purpose registers

32 × 8 bits

Internal ROM

24576 × 8 bits

External memory

38912 × 8 bits

6000H

5FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

1024 × 8 bits

Reserved

FB00H

FAFFH

FF20H

FF1FH

FE20H

FE1FH

Special function

registers (SFRs)

256 × 8 bits SFR addressing

Short direct

addressing

Direct addressing

addressing

Based addressing

Based indexed

addressing

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Figure 5-9. Correspondence Between Data Memory and Addressing

(

PD780024A, 780034A, 780024AY, 780034AY)

0000H

General-purpose registers

32 × 8 bits

Internal ROM

32768 ×8 bits

External memory

30720 ×8 bits

8000H

7FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

1024 ×8 bits

Reserved

FB00H

FAFFH

FF20H

FF1FH

FE20H

FE1FH

Special function

registers (SFRs)

256 ×8 bits SFR addressing

Short direct

addressing

Direct addressing

addressing

Based addressing

Based indexed

addressing

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Figure 5-10. Correspondence Between Data Memory and Addressing

(

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY)

0000H

General-purpose registers

32 × 8 bits

Flash memory

32768 × 8 bits

External memory

30720 × 8 bits

8000H

7FFFH

F800H

F7FFH

FEE0H

FEDFH

FF00H

FEFFH

FFFFH

Internal high-speed RAM

1024 × 8 bits

Reserved

FB00H

FAFFH

FF20H

FF1FH

FE20H

FE1FH

Special function

registers (SFRs)

256 × 8 bits SFR addressing

Short direct

addressing

Direct addressing

addressing

Based addressing

Based indexed

addressing

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5.2 Processor Registers

The

PD780024A, 780034A, 780024AY, 780034AY Subseries products incorporate the following processor

registers.

5.2.1 Control registers

The control registers control the program sequence, statuses and stack memory. The control registers consist

of a program counter (PC), a program status word (PSW) and a stack pointer (SP).

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to

be fetched. When a branch instruction is executed, immediate data and register contents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 5-11. Program Counter Format

15 0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction

execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 5-12. Program Status Word Format

PSW IE Z RBS1 AC RBS0 0 ISP CY

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(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledge operations of the CPU.

When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes

acknowledgeable. Other interrupt requests are all disabled.

When 1, the IE is set to the enable interrupt (EI) state and interrupt request acknowledge enable is controlled

with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority

specification flag.

The IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction

execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

These are 2-bit flags to select one of the four register banks.

In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction

execution is stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other

cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-

level vectored interrupt requests specified with a priority specification flag register (PR0L, PR0H, PR1L) (see

19.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) are disabled for acknowledgment.

When it is 1, all interrupts are acknowledgeable. Actual request acknowledgment is controlled with the

interrupt enable flag (IE).

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value

upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction

execution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM

area can be set as the stack area. The internal high-speed RAM areas of each product are as follows.

Table 5-4. Internal High-Speed RAM Area

Part Number Internal High-Speed RAM Area

PD780021A, 780031A, 780021AY, 780031AY FD00H to FEFFH

PD780022A, 780032A, 780022AY, 780032AY

PD780023A, 780033A, 780023AY, 780033AY FB00H to FEFFH

PD780024A, 780034A, 780024AY, 780034AY

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY

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Figure 5-13. Stack Pointer Format

15 0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from

the stack memory.

Each stack operation saves/restores data as shown in Figures 5-14 and 5-15.

Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using

the stack.

Figure 5-14. Data to Be Saved to Stack Memory

(a) PUSH rp instruction (when SP is FEE0H)

(b) CALL, CALLF, CALLT instructions (when SP is FEE0H)

FEE0H FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

FEDEH

FEE0H FEE0H

FEDFH

FEDEH

PSW

PC15 to PC8

FEDDH

SP FEDDH PC7 to PC0

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

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Figure 5-15. Data to Be Restored from Stack Memory

(a) POP rp instruction (when SP is FEDEH)

(b) RET instruction (when SP is FEDEH)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

FEE0H FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

FEDEH

FEE0H FEE0H

FEDFH

FEDEH

PSW

PC15 to PC8

FEDDH

SP FEDDH PC7 to PC0

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5.2.2 General-purpose registers

A general-purpose register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists

of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register

(AX, BC, DE, and HL).

They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names

(R0 to R7 and RP0 to RP3).

of the 4-register bank configuration, an efficient program can be created by switching between a register for normal

processing and a register for interrupts for each bank.

Figure 5-16. General-Purpose Register Configuration

(a) Absolute name

(b) Function name

BANK0

BANK1

BANK2

BANK3

FEFFH

FEF8H

FEE0H

15 0 7 0

16-bit processing 8-bit processing

FEF0H

FEE8H

BANK0

BANK1

BANK2

BANK3

FEFFH

FEF8H

FEE0H

RP3

RP2

RP1

RP0

15 0 7 0

16-bit processing 8-bit processing

FEF0H

FEE8H

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5.2.3 Special function register (SFR)

Unlike a general-purpose register, each special function register has special functions.

It is allocated in the FF00H to FFFFH area.

The special function register can be manipulated like the general-purpose register, with the operation, transfer and

bit manipulation instructions. Manipulatable bit units, 1, 8, and 16, depend on the special function register type.

Each manipulation bit unit can be specified as follows.

•1-bit manipulation

Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit).

This manipulation can also be specified with an address.

•8-bit manipulation

Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr).

This manipulation can also be specified with an address.

•16-bit manipulation

Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp).

When addressing an address, describe an even address.

Table 5-5 gives a list of special function registers. The meaning of items in the table is as follows.

•Symbol

Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined

via the header file “sfrbit.h” in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols

can be written as an instruction operand.

•R/W

Indicates whether the corresponding special function register can be read or written.

R/W: Read/write enable

R: Read only

W: Write only

•Manipulatable bit units

Indicates the manipulatable bit unit (1, 8, or 16). “–” indicates a bit unit for which manipulation is not possible.

•After reset

Indicates each register status upon RESET input.

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Table 5-5. Special Function Register List (1/3)

Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset

1 Bit 8 Bits 16 Bits

FF00H Port 0 P0 R/W √√− 00H

FF01H Port 1 P1 R √√−

FF02H Port 2 P2 R/W √√−

FF03H Port 3 P3 √√−

FF04H Port 4 P4 √√−

FF05H Port 5 P5 √√−

FF06H Port 6 P6 √√−

FF07H Port 7 P7 √√−

FF0AH 16-bit timer capture/compare register 00 CR00 −−√Undefined

FF0BH

FF0CH 16-bit timer capture/compare register 01 CR01 −−√

FF0DH

FF0EH 16-bit timer counter 0 TM0 R −−√0000H

FF0FH

FF10H 8-bit timer compare register 50 CR50 R/W −√−Undefined

FF11H 8-bit timer compare register 51 CR51 −√−

FF12H 8-bit timer counter 50 TM5 TM50 R −√√ 00H

FF13H 8-bit timer counter 51 TM51 −√

FF16H A/D conversion result register 0 ADCR0 −−√

Note 2

FF17H −√

Note 1

FF18H Transmit shift register 0 TXS0 W −√− FFH

Receive buffer register 0 RXB0 R −√−

FF1AH Serial I/O shift register 30 SIO30 R/W −√−Undefined

FF1BH Serial I/O shift register 31Note 3 SIO31 −√−

FF1FH IIC shift register 0Note 4 IIC0 −√− 00H

Notes 1.

PD780024A, 780024AY Subseries only

PD780034A, 780034AY Subseries only, 16-bit access possible

PD780024A, 780034A Subseries only

PD780024AY, 780034AY Subseries only

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Table 5-5. Special Function Register List (2/3)

Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset

1 Bit 8 Bits 16 Bits

FF20H Port mode register 0 PM0 R/W √√− FFH

FF22H Port mode register 2 PM2 √√−

FF23H Port mode register 3 PM3 √√−

FF24H Port mode register 4 PM4 √√−

FF25H Port mode register 5 PM5 √√−

FF26H Port mode register 6 PM6 √√−

FF27H Port mode register 7 PM7 √√−

FF30H Pull-up resistor option register 0 PU0 √√− 00H

FF32H Pull-up resistor option register 2 PU2 √√−

FF33H Pull-up resistor option register 3 PU3 √√−

FF34H Pull-up resistor option register 4 PU4 √√−

FF35H Pull-up resistor option register 5 PU5 √√−

FF36H Pull-up resistor option register 6 PU6 √√−

FF37H Pull-up resistor option register 7 PU7 √√−

FF40H Clock output select register CKS √√−

FF41H Watch timer operation mode register WTM √√−

FF42H Watchdog timer clock select register WDCS −√−

FF47H Memory expansion mode register MEM √√−

FF48H External interrupt rising edge enable register EGP √√−

FF49H External interrupt falling edge enable register EGN √√−

FF60H 16-bit timer mode control register 0 TMC0 √√−

FF61H Prescaler mode register 0 PRM0 −√−

FF62H Capture/compare control register 0 CRC0 √√−

FF63H 16-bit timer output control register 0 TOC0 √√−

FF70H 8-bit timer mode control register 50 TMC50 √√−

FF71H Timer clock select register 50 TCL50 −√−

FF78H 8-bit timer mode control register 51 TMC51 √√−

FF79H Timer clock select register 51 TCL51 −√−

FF80H A/D converter mode register 0 ADM0 √√−

FF81H Analog input channel specification register 0 ADS0 −√−

FFA0H Asynchronous serial interface mode register 0 ASIM0 √√−

FFA1H Asynchronous serial interface status register 0 ASIS0 R −√−

FFA2H Baud rate generator control register 0 BRGC0 R/W −√−

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Table 5-5. Special Function Register List (3/3)

Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit After Reset

1 Bit 8 Bits 16 Bits

FFA8H IIC control register 0Note 1 IICC0 R/W √√− 00H

FFA9H IIC status register 0Note 1 IICS0 R √√−

FFAAH IIC transfer clock select register 0Note 1 IICCL0 R/W √√−

FFABH Slave address register 0Note 1 SVA0 −√−

FFB0H Serial operation mode register 30 CSIM30 √√−

FFB8H Serial operation mode register 31Note 2 CSIM31 √√−

FFE0H Interrupt request flag register 0L IF0 IF0L √√√

FFE1H Interrupt request flag register 0H IF0H √√

FFE2H Interrupt request flag register 1L IF1L √√−

FFE4H Interrupt mask flag register 0L MK0 MK0L √√√ FFH

FFE5H Interrupt mask flag register 0H MK0H √√

FFE6H Interrupt mask flag register 1L MK1L √√−

FFE8H Priority level specification flag register 0L PR0 PR0L √√√

FFE9H Priority level specification flag register 0H PR0H √√

FFEAH Priority level specification flag register 1L PR1L √√−

FFF0H Memory size switching register IMS −√−CFHNote 3

FFF8H Memory expansion wait setting register MM √√− 10H

FFF9H Watchdog timer mode register WDTM √√− 00H

FFFAH Oscillation stabilization time select register OSTS −√− 04H

FFFBH Processor clock control register PCC √√−

Notes 1.

PD780024AY, 780034AY Subseries only

PD780024A, 780034A Subseries only

3. The default is CFH, but set the value corresponding to each respective product as indicated below.

PD780021A, 780031A, 780021AY, 780031AY: 42H

PD780022A, 780032A, 780022AY, 780032AY: 44H

PD780023A, 780033A, 780023AY, 780033AY: C6H

PD780024A, 780034A, 780024AY, 780034AY: C8H

PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY: Value for mask ROM version

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5.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each

byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is

executed. When a branch instruction is executed, the branch destination information is set to the PC and branched

by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).

5.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.

In other words, relative addressing consists in relative branching from the start address of the following instruction

to the –128 to +127 range.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15 0

876

15 0

jdisp8

When S = 0, all bits of are 0.

When S = 1, all bits of are 1.

PC indicates the start address

of the instruction after the BR instruction.

...

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5.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.

CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11

instruction is branched to the 0800H to 0FFFH area.

[Illustration]

In the case of CALL !addr16 and BR !addr16 instructions

In the case of CALLF !addr11 instruction

15 0

10–8

11 10

00001

643

CALLF

7–0

15 0

CALL or BR

Low Addr.

High Addr.

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15 1

15 0

Low Addr.

High Addr.

Memory (Table)

Effective address+1

Effective address 01

00000000

65 0

111

765 10

4–0

Operation code

5.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the

immediate data of an operation code are transferred to the program counter (PC) and branched.

This function is carried out when the CALLT [addr5] instruction is executed.

This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to

the entire memory space.

[Illustration]

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5.3.4 Register addressing

[Function]

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

15 0

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5.4 Operand Address Addressing

The following various methods are available to specify the register and memory (addressing) which undergo

manipulation during instruction execution.

5.4.1 Implied addressing

[Function]

The register which functions as an accumulator (A and AX) in the general-purpose register is automatically

(implicitly) addressed.

Of the

PD780024A, 780034A, 780024AY, 780034AY Subseries instruction words, the following instructions

employ implied addressing.

Instruction Register to Be Specified by Implied Addressing

MULU A register for multiplicand and AX register for product storage

DIVUW AX register for dividend and quotient storage

ADJBA/ADJBS A register for storage of numeric values which become decimal correction targets

ROR4/ROL4 A register for storage of digit data which undergoes digit rotation

[Operand format]

Because implied addressing can be automatically employed with an instruction, no particular operand format is

necessary.

[Description example]

In the case of MULU X

With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,

the A and AX registers are specified by implied addressing.

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5.4.2 Register addressing

[Function]

The general-purpose register to be specified is accessed as an operand with the register specify code (Rn and

RPn) of an instruction word in the registered bank specified with the register bank select flag (RBS0 and RBS1).

8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

[Operand format]

Identifier Description

r X, A, C, B, E, D, L, H

rp AX, BC, DE, HL

‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A,

C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; when selecting C register as r

Operation code 01100010

INCW DE; when selecting DE register pair as rp

Operation code 10000100

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5.4.3 Direct addressing

[Function]

The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand

address.

[Operand format]

Identifier Description

addr16 Label or 16-bit immediate data

[Description example]

MOV A, !0FE00H; when setting !addr16 to FE00H

Operation code 10001110 OP code

00000000 00H

11111110 FEH

[Illustration]

Memory

addr16 (lower)

addr16 (upper)

OP code

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5.4.4 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers

(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

If the SFR area (FF00H to FF1FH) where short direct addressing is applied, ports which are frequently accessed

in a program and compare and capture registers of the timer/event counter are mapped, and these SFRs can

be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to

1FH, bit 8 is set to 1. See the [Illustration] below.

[Operand format]

Identifier Description

saddr Label or immediate data indicating FE20H to FF1FH

saddrp Label or immediate data indicating FE20H to FF1FH (even address only)

[Description example]

MOV 0FE30H, A; when transferring the value in register A to saddr (FE30H)

Operation code 11110010 OP code

00110000 30H (saddr-offset)

[Illustration]

When 8-bit immediate data is 20H to FFH,

= 0

When 8-bit immediate data is 00H to 1FH,

= 1

15 0

Short direct memory

Effective address 1111111

OP code

saddr-offset

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15 0

SFR

Effective address 1111111

OP code

sfr-offset

5.4.5 Special function register (SFR) addressing

[Function]

The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction

word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR

mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier Description

sfr Special function register name

sfrp 16-bit manipulatable special function register name (even address only)

[Description example]

MOV PM0, A; when selecting PM0 (FF20H) as sfr

Operation code 11110110 OP code

00100000 20H (sfr-offset)

[Illustration]

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5.4.6 Register indirect addressing

[Function]

specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the

memory to be manipulated. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

−[DE], [HL]

[Description example]

MOV A, [DE]; when selecting [DE] as register pair

Operation code 10000101

[Illustration]

16 08

7 0

The contents of the memory

addressed are transferred.

Memory

The memory address

specified with the

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5.4.7 Based addressing

[Function]

8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in

an instruction word of the register bank specified by the register bank select flags (RBS0 and RBS1) and the

sum is used to address the memory. Addition is performed by expanding the offset data as a positive number

to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

−[HL + byte]

[Description example]

MOV A, [HL + 10H]; when setting byte to 10H

Operation code 10101110

00010000

[Illustration]

16 0

8 7

Memory

The contents of the

memory addressed

are transferred.

+10

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5.4.8 Based indexed addressing

[Function]

The B or C register contents specified in an instruction word are added to the contents of the base register, that

is, the HL register pair in the register bank specified by the register bank select flags (RBS0 and RBS1) and the

sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive

number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory

spaces.

[Operand format]

Identifier Description

−[HL + B], [HL + C]

[Description example]

In the case of MOV A, [HL + B] (selecting the B register)

Operation code 10101011

[Illustration]

16 0

8 7

Memory











The contents of the

memory addressed

are transferred.

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5.4.9 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions

are executed or the register is saved/reset upon generation of an interrupt request.

Stack addressing can be used to address the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE (saving the DE register)

Operation code 10110101

[Illustration]

FEE0H FEE0H

FEDFH

FEDEH

EFEDEH

70Memory

136 User’s Manual U14046EJ3V0UD

CHAPTER 6 PORT FUNCTIONS

6.1 Port Functions

The

PD780024A, 780034A, 780024AY, and 780034AY Subseries products incorporate eight input ports and 43

I/O ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can

carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware

I/O pins.

Figure 6-1. Port Types











Port 0

P00











Port 1

P10

P17











Port 2

P20

P25











Port 3

P30

P36





















Port 6

Port 5

P50

P57

P64

P67











Port 7

P70

P75











Port 4

P40

P47

P03

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Function

Port 0

4-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 1

8-bit input-only port.

Port 2

6-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 3 N-ch open-drain I/O port.

7-bit I/O port. On-chip pull-up resistor can be specified by mask

Input/output mode can be specified option (mask ROM version only).

in 1-bit units. LEDs can be driven directly.

An on-chip pull-up resistor can be specified by

software settings.

Port 4

8-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by software settings.

Interrupt request flag (KRIF) is set to 1 by falling edge detection.

Port 5

8-bit I/O port.

LEDs can be driven directly.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 6

4-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 7

6-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Table 6-1. Port Functions (

PD780024A, 780034A Subseries)

Pin Name

P00

P01

P02

P03

P10 to P17

P20

P21

P22

P23

P24

P25

P30

P31

P32

P33

P34

P35

P36

P40 to P47

P50 to P57

P64

P65

P66

P67

P70

P71

P72

P73

P74

P75

Alternate

Function

INTP0

INTP1

INTP2

INTP3/ADTRG

ANI0 to ANI7

SI30

SO30

SCK30

RxD0

TxD0

ASCK0

−

SI31

SO31

SCK31

AD0 to AD7

A8 to A15

WAIT

ASTB

TI00/TO0

TI01

TI50/TO50

TI51/TO51

PCL

BUZ

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Table 6-2. Port Functions (

PD780024AY, 780034AY Subseries)

Alternate

Function

INTP0

INTP1

INTP2

INTP3/ADTRG

ANI0 to ANI7

SI30

SO30

SCK30

RxD0

TxD0

ASCK0

−

SDA0

SCL0

−

AD0 to AD7

A8 to A15

WAIT

ASTB

TI00/TO0

TI01

TI50/TO50

TI51/TO51

PCL

BUZ

Pin Name

P00

P01

P02

P03

P10 to P17

P20

P21

P22

P23

P24

P25

P30

P31

P32

P33

P34

P35

P36

P40 to P47

P50 to P57

P64

P65

P66

P67

P70

P71

P72

P73

P74

P75

Function

Port 0

4-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 1

8-bit input-only port.

Port 2

6-bit I/O port

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 3 N-ch open-drain I/O port.

7-bit I/O port. On-chip pull-up resistor can be specified by mask

Input/output mode can be specified option (P30 and P31 are mask ROM version only).

in 1-bit units. LEDs can be driven directly.

An on-chip pull-up resistor can be used by software

settings.

Port 4

8-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Interrupt request flag (KRIF) is set to 1 by falling edge detection.

Port 5

8-bit I/O port.

LEDs can be driven directly.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 6

4-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

Port 7

6-bit I/O port.

Input/output mode can be specified in 1-bit units.

An on-chip pull-up resistor can be used by software settings.

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6.2 Port Configuration

A port consists of the following hardware.

Table 6-3. Port Configuration

Item Configuration

Control register Port mode register (PMm: m = 0, 2 to 7)

Pull-up resistor option register (PUm: m = 0, 2 to 7)

Port Total: 51 ports (8 inputs, 43 inputs/outputs)

Pull-up resistor • Mask ROM version

Total: 43 (software control: 39, mask option: 4Note)

• Flash memory version Total: 39

Note Two mask options for the

PD780024AY and 780034AY Subseries.

6.2.1 Port 0

Port 0 is a 4-bit I/O port with output latch. P00 to P03 pins can specify the input mode/output mode in 1-bit units

with port mode register 0 (PM0). An on-chip pull-up resistor of P00 to P03 pins can be used for them in 1-bit units

with pull-up resistor option register 0 (PU0).

This port can also be used as an external interrupt request input and A/D converter external trigger input.

RESET input sets port 0 to input mode.

Figure 6-2 shows a block diagram of port 0.

Cautions 1. Port 0 functions alternately as an external interrupt request input pin. If the output mode of

the port function is specified and the output level of the port is changed while interrupts are

not disabled by the external interrupt rising edge enable register (EGP) and external interrupt

falling edge enable register (EGN), the interrupt request flag is set. Thus, when the output

mode is used, set the interrupt mask flag to 1.

2. When the external interrupt request function is switched to the port function, edge detection

may be performed. Therefore, clear bit n (EGPn) of EGP and bit n (EGNn) of EGN to 0 before

selecting the port mode.

3. When using P03/INTP3/ADTRG as an A/D converter external trigger input, specify valid edges

by setting bits 1 and 2 (EGA00 and EGA01) of A/D converter mode register 0 (ADM0) and set

the interrupt mask flag (PMK3) to 1.

Remark n = 0 to 3

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Figure 6-2. Block Diagram of P00 to P03

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 0 read signal

WR: Port 0 write signal

DD0

P-ch

P00/INTP0

P02/INTP2,

P03/INTP3/ADTRG

PORT

PU00 to PU03

Alternate

function

Output latch

(P00 to P03)

PM00 to PM03

Internal bus

Selector

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6.2.2 Port 1

Port 1 is an 8-bit input-only port.

This port can also be used as an A/D converter analog input.

Figure 6-3 shows a block diagram of port 1.

Figure 6-3. Block Diagram of P10 to P17

RD: Port 1 read signal

P10/ANI0 to P17/ANI7

A/D converter

Internal bus

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6.2.3 Port 2

Port 2 is a 6-bit I/O port with output latch. P20 to P25 pins can specify the input mode/output mode in 1-bit units

with port mode register 2 (PM2). An on-chip pull-up resistor of P20 to P25 pins can be used for them in 1-bit units

with pull-up resistor option register 2 (PU2).

This port has also alternate functions as serial interface data I/O and clock I/O.

RESET input sets port 2 to input mode.

Figures 6-4 to 6-6 show block diagrams of port 2.

Figure 6-4. Block Diagram of P20, P23, and P25

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

DD0

P-ch

P20/SI30,

P23/RxD0,

P25/ASCK0

PORT

PU20, PU23,

PU25

Alternate

function

Output latch

(P20, P23, P25)

PM20, PM23,

PM25

Internal bus

Selector

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Figure 6-5. Block Diagram of P21 and P24

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

P21/SO30,

P24/TxD0

PORT

PU21, PU24

Output latch

(P21, P24)

PM21, PM24

Alternate

function

DD0

P-ch

Internal bus

Selector

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Figure 6-6. Block Diagram of P22

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

P22/SCK30

PORT

PU22

Output latch

(P22)

PM22

Alternate

function

Alternate

function

DD0

P-ch

Internal bus

Selector

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6.2.4 Port 3 (

PD780024A, 780034A Subseries)

Port 3 is a 7-bit I/O port with output latch. P30 to P36 pins can specify the input mode/output mode in 1-bit units

with port mode register 3 (PM3).

This port has the following functions for pull-up resistors. These functions differ depending on the port’s higher

3-bit/lower 4-bit, and whether the product is a mask ROM version or a flash memory version.

Table 6-4. Pull-Up Resistor of Port 3 (

PD780024A, 780034A Subseries)

Higher 3-Bit (P34 to P36 Pins) Lower 4-Bit (P30 to P33 Pins)

Mask ROM version An on-chip pull-up resistor can be An on-chip pull-up resistor can be specified

connected in 1-bit units by PU3 in 1-bit units by mask option

Flash memory version On-chip pull-up resistor is not provided

PU3: Pull-up resistor option register 3

The P30 to P33 pins can drive LEDs directly.

The P34 to P36 pins can also be used for serial interface data I/O and clock I/O.

RESET input sets port 3 to input mode.

Figures 6-7 to 6-11 show block diagrams of port 3.

Figure 6-7. Block Diagram of P30 and P31 (

PD780024A, 780034A Subseries)

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

PM30, PM31

P30, P31

N-ch

PORT

Output latch

(P30, P31)

DD0

Selector

Internal bus

Mask option resistor













Mask ROM version only

No pull-up resistor for

flash memory version

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Figure 6-8. Block Diagram of P32 and P33 (

PD780024A, 780034A Subseries)

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

PM32, PM33

P32, P33

N-ch

PORT

DD0

Output latch

(P32, P33)

Selector

Internal bus

Mask option resistor













Mask ROM version only

No pull-up resistor for

flash memory version

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Figure 6-9. Block Diagram of P34 (

PD780024A, 780034A Subseries)

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

DD0

P-ch

P34/SI31

PORT

PU34

Alternate

function

Output latch

(P34)

PM34

Selector

Internal bus

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Figure 6-10. Block Diagram of P35 (

PD780024A, 780034A Subseries)

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

P35/SO31

PORT

PU35

Output latch

(P35)

PM35

Alternate

function

DD0

P-ch

Selector

Internal bus

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Figure 6-11. Block Diagram of P36 (

PD780024A, 780034A Subseries)

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

DD0

P-ch

P36/SCK31

PORT

PU36

Alternate

function

Output latch

(P36)

PM36

Alternate

function

Selector

Internal bus

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6.2.5 Port 3 (

PD780024AY, 780034AY Subseries)

Port 3 is a 7-bit I/O port with output latch. P30 to P36 pins can specify the input mode/output mode in 1-bit units

with port mode register 3 (PM3).

This port has the following functions for pull-up resistors. These functions differ depending on port’s bits location

and mask ROM version/flash memory version.

Table 6-5. Pull-Up Resistor of Port 3 (

PD780024AY, 780034AY Subseries)

P34 to P36 Pins P30 and P31 Pins

Mask ROM version An on-chip pull-up resistor can An on-chip pull-up resistor can be specified

be connected in 1-bit units by in 1-bit units by mask option

Flash memory version PU3 On-chip pull-up resistor is not provided

PU3: Pull-up resistor option register 3

Caution P32 and P33 pins have no pull-up resistor.

The P30 to P33 pins can drive LEDs directly.

The P32 and P33 pins can also be used for serial interface data I/O and clock I/O.

RESET input sets port 3 to input mode.

Figures 6-12 to 6-15 show block diagrams of port 3.

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Figure 6-12. Block Diagram of P30 and P31 (

PD780024AY, 780034AY Subseries)

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

Figure 6-13. Block Diagram of P32 and P33 (

PD780024AY, 780034AY Subseries)

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

PM30, PM31

P30, P31

N-ch

WRPORT

WRPM

VDD0

Output latch

(P30, P31)

Selector

Internal bus

Mask option resistor













Mask ROM version only

No pull-up resistor for

flash memory version

PM32, PM33

Alternate

function

P32/SDA0,

P33/SCL0

N-ch

WRPORT

Output latch

(P32, P33)

WRPM

Internal bus

Selector

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Figure 6-14. Block Diagram of P34 and P36 (

PD780024AY, 780034AY Subseries)

VDD0

P-ch

P34, P36

WRPU

WRPORT

WRPM

PU34, PU36

Output latch

(P34, P36)

PM34, PM36

Selector

Internal bus

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

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Figure 6-15. Block Diagram of P35 (

PD780024AY, 780034AY Subseries)

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 3 read signal

WR: Port 3 write signal

P35

WRPU

WRPORT

WRPM

PU35

Output latch

(P35)

PM35

VDD0

P-ch

Internal bus

Selector

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6.2.6 Port 4

Port 4 is an 8-bit I/O port with output latch. The P40 to P47 pins can specify the input mode/output mode in 1-

bit units with port mode register 4 (PM4). An on-chip pull-up resistor of P40 to P47 pins can be used for them in 1-

bit units with pull-up resistor option register 4 (PU4).

The interrupt request flag (KRIF) can be set to 1 by detecting falling edges.

This port can also be used as an address/data bus in external memory expansion mode.

RESET input sets port 4 to input mode.

Figures 6-16 and 6-17 show a block diagram of port 4 and block diagram of the falling edge detector, respectively.

Cautions 1. The internal pull-up resistor is not disconnected even if the external memory expansion mode

is set when PU4n = 1 (n = 0 to 7).

2. When using the falling edge detection interrupt (INTKR), be sure to set the memory expansion

mode register (MEM) to 01H.

Figure 6-16. Block Diagram of P40 to P47

Internal bus

P40/AD0

P47/AD7

P-ch

PORT

PU40 to PU47

Output latch

(P40 to P47)

PM40 to PM47

Alternate

function

Alternate

function

Selector

Memory expansion

mode register (MEM)

DD0

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 4 read signal

WR: Port 4 write signal

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Figure 6-17. Block Diagram of Falling Edge Detector

P40

P41

P42

P43

P44

P45

P46

P47

INTKR

Falling edge detector

“1” when MEM = 01H

6.2.7 Port 5

Port 5 is an 8-bit I/O port with output latch. The P50 to P57 pins can specify the input mode/output mode in 1-

bit units with port mode register 5 (PM5). An on-chip pull-up resistor of P50 to P57 pins can be used for them in 1-

bit units with pull-up resistor option register 5 (PU5).

Port 5 can drive LEDs directly.

This port can also be used as an address bus in external memory expansion mode.

RESET input sets port 5 to input mode.

Figure 6-18 shows a block diagram of port 5.

Caution The internal pull-up resistor is not disconnected even if the external memory expansion mode

is set when PU5n = 1 (n = 0 to 7).

Figure 6-18. Block Diagram of P50 to P57

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 5 read signal

WR: Port 5 write signal

Internal bus

P50/A8

P57/A15

P-ch

PORT

PU50 to PU57

PM50 to PM57

Selector

DD0

Output latch

(P50 to P57)

Alternate

function

Selector

Memory expansion

mode register (MEM)

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6.2.8 Port 6

Port 6 is a 4-bit I/O port with output latch. The P64 to P67 pins can specify the input mode/output mode in 1-bit

units with port mode register 6 (PM6). An on-chip pull-up resistor of P64 to P67 pins can be used for them in 1-bit

units with pull-up resistor option register 6 (PU6).

This port can also be used as a control signal output in external memory expansion mode.

RESET input sets port 6 to input mode.

Figures 6-19 and 6-20 show block diagrams of port 6.

Cautions 1. The internal pull-up resistor is not disconnected even if the external memory expansion mode

is set when PU6n = 1 (n = 4 to 7).

2. When external wait is not used in external memory expansion mode, P66 can be used as an

I/O port.

Figure 6-19. Block Diagram of P64, P65, and P67

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 6 read signal

WR: Port 6 write signal

Internal bus

P64/RD,

P65/WR,

P67/ASTB

P-ch

WRPU

WRPORT

WRPM

PU64, PU65, PU67

PM64, PM65, PM67

VDD0

Output latch

(P64, P65, P67)

Alternate

function

Selector

Memory expansion

mode register (MEM)

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Figure 6-20. Block Diagram of P66

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 6 read signal

WR: Port 6 write signal

Internal bus

P66/WAIT

P-ch

WRPU

WRPORT

WRPM

PU66

PM66

VDD0

Output latch

(P66)

Alternate

function

Selector

Memory expansion

mode register (MEM)

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6.2.9 Port 7

Port 7 is a 6-bit I/O port with output latch. The P70 to P75 pins can specify the input mode/output mode in 1-bit

units with port mode register 7 (PM7). An on-chip pull-up resistor of P70 to P75 pins can be used for them in 1-bit

units with pull-up resistor option register 7 (PU7).

This port can also be used as a timer I/O, clock output, and buzzer output.

RESET input sets the input mode.

Figures 6-21 to 6-23 show block diagrams of port 7.

Figure 6-21. Block Diagram of P70, P72, and P73

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 7 read signal

WR: Port 7 write signal

DD0

P-ch

P70/TI00/TO0,

P72/TI50/TO50,

P73/TI51/TO51

PORT

PU70, PU72, PU73

Alternate

function

Output latch

(P70, P72, P73)

PM70, PM72, PM73

Alternate

function

Internal bus

Selector

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Figure 6-22. Block Diagram of P71

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 7 read signal

WR: Port 7 write signal

DD0

P-ch

P71/TI01

PORT

PU71

PM71

Output latch

(P71)

Alternate

function

Internal bus

Selector

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Figure 6-23. Block Diagram of P74 and P75

PU: Pull-up resistor option register

PM: Port mode register

RD: Port 7 read signal

WR: Port 7 write signal

P74/PCL,

P75/BUZ

PORT

PU74, PU75

Output latch

(P74, P75)

PM74, PM75

Alternate

function

DD0

P-ch

Internal bus

Selector

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6.3 Port Function Control Registers

The following two types of registers control the ports.

•Port mode registers (PM0, PM2 to PM7)

•Pull-up resistor option registers (PU0, PU2 to PU7)

(1) Port mode registers (PM0, PM2 to PM7)

These registers are used to set port input/output in 1-bit units.

PM0 and PM2 to PM7 are independently set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets registers to FFH.

When using a port pin as its alternate-function pin, set the port mode registers and output latches as shown in

Table 6-6.

Cautions 1. Pins P10 to P17 are input-only pins.

2. Port 0 functions alternately as an external interrupt request input pin. If the output mode

of the port function is specified and the output level of the port is changed while interrupts

are not disabled by the external interrupt rising edge enable register (EGP) and external

interrupt falling edge enable register (EGN), the interrupt request flag is set. When the

output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.

3. If a port has an alternate function pin and it is used as an alternate output function, clear

the corresponding output latches (P0 and P2 to P7) to 0.

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Figure 6-24. Format of Port Mode Register (PM0, PM2 to PM7)

Address: FF20H After Reset: FFH R/W

Symbol 76543210

PM0 1111PM03 PM02 PM01 PM00

Address: FF22H After Reset: FFH R/W

Symbol 76543210

PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20

Address: FF23H After Reset: FFH R/W

Symbol 76543210

PM3 1 PM36 PM35 PM34 PM33 PM32 PM31 PM30

Address: FF24H After Reset: FFH R/W

Symbol 76543210

PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40

Address: FF25H After Reset: FFH R/W

Symbol 76543210

PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50

Address: FF26H After Reset: FFH R/W

Symbol 76543210

PM6 PM67 PM66 PM65 PM64 1111

Address: FF27H After Reset: FFH R/W

Symbol 76543210

PM7 1 1 PM75 PM74 PM73 PM72 PM71 PM70

PMmn Pmn Pin I/O Mode Selection (m = 0, 2 to 7; n = 0 to 7)

0 Output mode (Output buffer on)

1 Input mode (Output buffer off)

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×Note 2

Table 6-6. Port Mode Registers and Output Latch Settings When Alternate Function Is Used (1/2)

Pin Name

P00 to P02

P03

P10 to P17

P20

P21

P22

P23

P24

P25

P32

P33

P34

P35

P36

P40 to P47

P50 to P57

P64

P65

P66

P67

Alternate Function PM××

1 (fix)

1Note 2

P××

×Note 2

Name

INTP0 to INTP2

INTP3

ADTRG

ANI0 to ANI7

SI30

SO30

SCK30

RxD0

TxD0

ASCK0

SDA0Note 1

SCL0Note 1

SI31

SO31

SCK31

AD0 to AD7

A8 to A15

WAIT

ASTB

I/O

Input

Output

Input

Output

Input

Output

Input

I/O

Input

Output

Input

Output

I/O

Output

Input

Output

Notes 1.

PD780024AY, 780034AY Subseries only

2. When using the P40 to P47, P50 to P57, and P64 to P67 pins as alternate-function pins, set the function

using the memory expansion mode register (MEM).

Remark ×: Don’t care

PM××: Port mode register

P××: Port output latch

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Table 6-6. Port Mode Registers and Output Latch Settings When Alternate Function Is Used (2/2)

Pin Name

P70

P71

P72

P73

P74

P75

Alternate Function PM××

P××

Name

TI00

TO0

TI01

TI50

TO50

TI51

TO51

PCL

BUZ

I/O

Input

Output

Input

Output

Input

Output

Remark ×: Don’t care

PM××: Port mode register

P××: Port output latch

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(2) Pull-up resistor option registers (PU0, PU2 to PU7)

These registers are used to set whether to use an on-chip pull-up resistor at each port or not. By setting PU0

and PU2 to PU7, the on-chip pull-up resistors of the port pins corresponding to the bits in PU0 and PU2 to PU7

can be used.

PU0 and PU2 to PU7 are independently set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears registers to 00H.

Cautions 1. The P10 to P17 pins do not incorporate a pull-up resistor.

2. Pins P30 to P33 (in

PD780024AY and 780034AY Subseries, P30 and P31 pins) can be used

with pull-up resistor by mask option only for mask ROM version.

3. When PUm is set to 1, the on-chip pull-up resistor is connected irrespective of the input/

output mode. When using in output mode, clear the bit of PUm to 0 (m = 0, 2 to 7).

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Figure 6-25. Format of Pull-Up Resistor Option Register (PU0, PU2 to PU7)

Address: FF30H After Reset: 00H R/W

Symbol 76543210

PU0 0000PU03 PU02 PU01 PU00

Address: FF32H After Reset: 00H R/W

Symbol 76543210

PU2 0 0 PU25 PU24 PU23 PU22 PU21 PU20

Address: FF33H After Reset: 00H R/W

Symbol 76543210

PU3 0 PU36 PU35 PU34 0000

Address: FF34H After Reset: 00H R/W

Symbol 76543210

PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40

Address: FF35H After Reset: 00H R/W

Symbol 76543210

PU5 PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50

Address: FF36H After Reset: 00H R/W

Symbol 76543210

PU6 PU67 PU66 PU65 PU64 0000

Address: FF37H After Reset: 00H R/W

Symbol 76543210

PU7 0 0 PU75 PU74 PU73 PU72 PU71 PU70

PUmn Pmn Pin On-Chip Pull-Up Resistor Selection (m = 0, 2 to 7; n = 0 to 7)

0 On-chip pull-up resistor not used

1 On-chip pull-up resistor used

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6.4 Port Function Operations

Port operations differ depending on whether the input or output mode is set, as shown below.

Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the

port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins,

the output latch contents for pins specified as input are undefined, even for bits other than the

manipulated bit.

6.4.1 Writing to I/O port

(1) Output mode

A value is written to the output latch by a transfer instruction, and the output latch contents are output from the

pin.

Once data is written to the output latch, it is retained until data is written to the output latch again.

The output latch data is cleared by reset.

(2) Input mode

A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does

not change.

Once data is written to the output latch, it is retained until data is written to the output latch again.

6.4.2 Reading from I/O port

(1) Output mode

The output latch contents are read by a transfer instruction. The output latch contents do not change.

(2) Input mode

The pin status is read by a transfer instruction. The output latch contents do not change.

6.4.3 Operations on I/O port

(1) Output mode

An operation is performed on the output latch contents, and the result is written to the output latch. The output

latch contents are output from the pins.

Once data is written to the output latch, it is retained until data is written to the output latch again.

The output latch data is cleared by reset.

(2) Input mode

The output latch contents are undefined, but since the output buffer is off, the pin status does not change.

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6.5 Selection of Mask Option

The following mask option is provided in the mask ROM version. The flash memory versions have no mask options.

Table 6-7. Comparison Between Mask ROM Version and Flash Memory Version

Pin Name Mask ROM Version Flash Memory Version

Mask option for pins P30 to P33Note On-chip pull-up resistors can be specified in An on-chip pull-up resistor is not

1-bit units. provided.

Note For

PD780024AY and 780034AY Subseries products, only the P30 and P31 pins can incorporate a pull-

up resistor.

169User’s Manual U14046EJ3V0UD

CHAPTER 7 CLOCK GENERATOR

7.1 Clock Generator Functions

The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two

types of system clock oscillators are available.

(1) Main system clock oscillator

This circuit oscillates a clock with the following frequencies.

•1.0 to 8.38 MHz: Conventional product of

PD780021A, 780022A, 780023A, 780024A, 780031A, 780032A,

780033A, 780034A and

PD780021AY, 780022AY, 780023AY, 780024AY, 780031AY,

780032AY, 780033AY, 780034AY, 78F0034A, 78F0034AY, 78F0034BY

•1.0 to 12 MHz: Expanded-specification product of

PD780021A, 780022A, 780023A, 780024A, 780031A,

780032A, 780033A, 780034A and

PD78F0034B

Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register

(PCC).

(2) Subsystem clock oscillator

The circuit oscillates a clock with a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem

clock oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register

(PCC). This enables to reduce the power consumption in the STOP mode.

7.2 Clock Generator Configuration

The clock generator consists of the following hardware.

Table 7-1. Clock Generator Configuration

Item Configuration

Control registers Processor clock control register (PCC)

Oscillation stabilization time select register (OSTS)

Oscillators Main system clock oscillator

Subsystem clock oscillator

Controllers Prescaler

Standby controller

Wait controller

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Figure 7-1. Block Diagram of Clock Generator

XT1

XT2

FRC

Subsystem

clock

oscillator

Main system

clock

oscillator f

Prescaler

1/2

Prescaler

Standby

controller

HALT

Wait

controller

STOP MCC FRC CLS

OSTS2 OSTS1 OSTS0

CSS PCC2 PCC1 PCC0

Oscillation stabilization

time select register (OSTS)

Watch timer,

clock output

function

Clock to

peripheral

hardware

CPU clock

CPU

)

Processor clock control register

(PCC)

Internal bus

Selector

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7.3 Clock Generator Control Registers

The clock generator is controlled by the following two registers.

• Processor clock control register (PCC)

• Oscillation stabilization time select register (OSTS)

(1) Processor clock control register (PCC)

This register selects the CPU clock and the division ratio, sets main system clock oscillator operation/stop and

sets whether to use the subsystem clock oscillator internal feedback resistorNote.

PCC is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets the value of PCC to 04H.

Note The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point

is in the middle of the power supply voltage.

When the subsystem clock is not used, the power consumption in the STOP mode can be reduced by setting

bit 6 (FRC) of PCC to 1 (see Figure 7-7 Subsystem Clock Feedback Resistor).

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Figure 7-2. Format of Processor Clock Control Register (PCC)

Address: FFFBH After reset: 04H R/WNote 1

Symbol <7> <6> <5> <4> 3210

PCC MCC FRC CLS CSS 0 PCC2 PCC1 PCC0

MCC Main system clock oscillation controlNote 2

0 Oscillation possible

1 Oscillation stopped

FRC Subsystem clock feedback resistor selection

0 Internal feedback resistor used

1 Internal feedback resistor not usedNote 3

CLS CPU clock status

0 Main system clock

1 Subsystem clock

CSS PCC2 PCC1 PCC0 CPU clock (fCPU) selection

0000fX

001fX/2

010fX/22

011fX/23

100fX/24

1000fXT/2

001

010

011

100

Other than above Setting prohibited

Notes 1. Bit 5 is read-only.

2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock

oscillation. The STOP instruction should not be used.

3. This bit can be set to 1 only when the subsystem clock is not used.

Cautions 1. Be sure to clear bit 3 to 0.

2. When the external clock is input, MCC should not be set.

This is because the X2 pin is connected to VDD1 via a pull-up resistor.

Remarks 1. fX: Main system clock oscillation frequency

2. fXT: Subsystem clock oscillation frequency

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The fastest instructions of the

PD780024A, 780034A, 780024AY, and 780034AY Subseries are carried out in

two CPU clocks. The relationship between the CPU clock (fCPU) and minimum instruction execution time is shown

in Table 7-2.

Table 7-2. Relationship Between CPU Clock and Minimum Instruction Execution Time

CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU

fX = 8.38 MHz fX = 12 MHzNote fXT = 32.768 kHz

fX0.238

s 0.166

s−

fX/2 0.477

s 0.333

s−

fX/220.954

s 0.666

s−

fX/231.90

s 1.33

s−

fX/243.81

s 2.66

s−

fXT/2 −−122

Note Expanded-specification products of

PD780024A, 780034A Subseries only

Remark fX: Main system clock oscillation frequency

fXT: Subsystem clock oscillation frequency

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(2) Oscillation stabilization time select register (OSTS)

This register is used to select the oscillation stabilization time from when reset is effected or STOP mode is

released to when oscillation is stabilized.

OSTS is set by an 8-bit memory manipulation instruction.

RESET input sets OSTS to 04H. Thus, when releasing the STOP mode by RESET input, the time required to

release is 217/fX.

Figure 7-3. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFFAH After reset: 04H R/W

Symbol 76543210

OSTS 00000OSTS2 OSTS1 OSTS0

OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time

fX = 8.38 MHz fX = 12 MHzNote

0002

12/fX488

s 341

0012

14/fX1.95 ms 1.36 ms

0102

15/fX3.91 ms 2.73 ms

0112

16/fX7.82 ms 5.46 ms

1002

17/fX15.6 ms 10.9 ms

Other than the above Setting prohibited

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Caution The wait time when STOP mode is released does not include the time (“a” in the figure below)

from when STOP mode is released until the clock starts oscillation.

This also applies when RESET is input and an interrupt request is generated.

Remark fX: Main system clock oscillation frequency

STOP mode is released

Voltage waveform

of X1 pin

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7.4 System Clock Oscillator

7.4.1 Main system clock oscillator

The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (8.38 MHz TYP.)

connected to the X1 and X2 pins.

External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin

and an inverted-phase clock signal to the X2 pin.

Figure 7-4 shows an external circuit of the main system clock oscillator.

Figure 7-4. External Circuit of Main System Clock Oscillator

(a) Crystal and ceramic oscillation (b) External clock

Crystal resonator or

ceramic resonator

VSS1

External

clock

Caution Do not execute the STOP instruction and do not set MCC (bit 7 of processor clock control

is executed or MCC is set to 1, the main system clock operation stops and the X2 pin is connected

to VDD1 via a pull-up resistor.

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7.4.2 Subsystem clock oscillator

The subsystem clock oscillator oscillates with a crystal resonator (32.768 kHz TYP.) connected to the XT1 and

XT2 pins.

External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin

and an inverted-phase clock signal to the XT2 pin.

Figure 7-5 shows an external circuit of the subsystem clock oscillator.

Figure 7-5. External Circuit of Subsystem Clock Oscillator

(a) Crystal oscillation (b) External clock

32.768

kHz

XT2

XT1

External

clock

XT2

SS1

XT1

Cautions are listed on the next page.

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Caution 1. When using the main system clock oscillator and subsystem clock oscillator, wire as follows

in the area enclosed by broken lines in Figures 7-4 and 7-5 to avoid an adverse effect from

wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS1. Do

not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing

power consumption.

Figure 7-6 shows examples of incorrect oscillator connection.

Figure 7-6. Examples of Incorrect Oscillator Connection (1/2)

(a) Too long wiring (b) Crossed signal line

Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert

resistors in series on the XT2 side.

SS1

X2 X1 X2 X1

PORTn

(n = 0 to 7)

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Figure 7-6. Examples of Incorrect Oscillator Connection (2/2)

oscillator (potential at points A, B, and

C fluctuates)

(e) Signals are fetched

Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert

resistors in series on the XT2 side.

Caution 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1,

resulting in malfunction.

To prevent that from occurring, it is recommended to wire X2 and XT1 so that they are not

in parallel, and to connect the IC pin between X2 and XT1 directly to VSS1.

X2 VSS1X1

High current

X2 X1 VSS1

ABC

Pnm

VDD0

High current

SS1

X2 X1

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7.4.3 When subsystem clock is not used

If it is not necessary to use the subsystem clock for low power consumption operations and watch operations,

connect the XT1 and XT2 pins as follows.

XT1: Connect directly to VDD0 or VDD1

XT2: Leave open

In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator

when the main system clock stops. To minimize leakage current, the above internal feedback resistor can be removed

by setting bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2 pins

as described above.

Figure 7-7. Subsystem Clock Feedback Resistor

FRC

P-ch

Feedback resistor

XT1 XT2

Remark The feedback resistor is required to control the bias point of the oscillation waveform so that the bias

point is in the middle of the power supply voltage.

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7.5 Clock Generator Operations

The clock generator generates the following types of clocks and controls the CPU operating mode including the

standby mode.

•Main system clock fX

•Subsystem clock fXT

•CPU clock fCPU

•Clock to peripheral hardware

The following clock generator functions and operations are determined by the processor clock control register

(PCC).

(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (3.81

s @ 8.38 MHz

operation) is selected (PCC = 04H). Main system clock oscillation stops while a low level is applied to the RESET

pin.

(b) With the main system clock selected, one of the five levels of minimum instruction execution time (0.166

s, 0.333

s, 0.666

s, 1.33

s, 2.66

s: @ 12 MHz operationNote, 0.238

s, 0.476

s, 0.954

s, 1.90

s, 3.81

s: @ 8.38

MHz operation) can be selected by setting PCC.

power consumption in the STOP mode, the subsystem clock feedback resistor can be disconnected to stop the

subsystem clock.

(d) PCC can be used to select the subsystem clock and to operate the system with low power consumption (122

s @ 32.768 kHz operation).

(e) With the subsystem clock selected, main system clock oscillation can be stopped via PCC. The HALT mode

can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.)

(f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to

the watch timer and clock output functions only. Thus the watch function and the clock output function can also

be continued in the standby state. However, since all other peripheral hardware operate with the main system

clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock

operation).

Note Expanded-specification products of

PD780024A, 780034A Subseries only

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7.5.1 Main system clock operations

When operating with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) cleared

to 0), the following operations are carried out by PCC setting.

(a) Because the operation-guaranteed instruction execution speed depends on the power supply voltage, the

minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of PCC.

(b) When bit 4 (CSS) of PCC is set to 1 when operating with the main system clock, if bit 7 (MCC) of PCC is set

to 1 after the operation has been switched to the subsystem clock (CLS = 1), the main system clock oscillation

stops (see Figure 7-8 (1)).

does not stop. When bit 4 (CSS) of PCC is set to 1 and the operation is switched to the subsystem clock (CLS

= 1) after that, the main system clock oscillation stops (see Figure 7-8 (2)).

Figure 7-8. Main System Clock Stop Function

(1) Operation when MCC is set after setting CSS with main system clock operation

MCC

CSS

CLS

Main system clock oscillation

Subsystem clock oscillation

CPU clock

(2) Operation when CSS is set after setting MCC with main system clock operation

Main system clock oscillation

Subsystem clock oscillation

CPU clock

MCC

CSS

CLS

Oscillation does not stop

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7.5.2 Subsystem clock operations

When operating with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to

1), the following operations are carried out.

(a) The minimum instruction execution time remains constant (122

s @ 32.768 kHz operation) irrespective of bits

0 to 2 (PCC0 to PCC2) of PCC.

(b) Watchdog timer counting stops.

Caution Do not execute the STOP instruction while the subsystem clock is in operation.

7.6 Changing System Clock and CPU Clock Settings

7.6.1 Time required for switchover between system clock and CPU clock

The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS)

of the processor clock control register (PCC).

The actual switchover operation is not performed directly after writing to the PCC; operation continues on the pre-

switchover clock for several instructions (see Table 7-3).

Determination as to whether the system is operating on the main system clock or the subsystem clock is performed

by bit 5 (CLS) of the PCC register.

Table 7-3. Maximum Time Required for CPU Clock Switchover

Remark One instruction is the minimum instruction execution time with the pre-switchover CPU clock.

Caution Selection of the CPU clock cycle division ratio (PCC0 to PCC2) and switchover from the main

system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously.

Simultaneous setting is possible, however, for selection of the CPU clock cycle division ratio

(PCC0 to PCC2) and switch over from the subsystem clock to the main system clock (changing

CSS from 1 to 0).

Set Value Before Set Value After Switchover

Switchover

CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0

000000 01001000 1101001×××

0000 16 instructions 16 instructions 16 instructions 16 instructions fX/2fXT instruction

0 0 1 8 instructions 8 instructions 8 instructions 8 instructions fX/4fXT instruction

0 1 0 4 instructions 4 instructions 4 instructions 4 instructions fX/8fXT instruction

0 1 1 2 instructions 2 instructions 2 instructions 2 instructions fX/16fXT instruction

1 0 0 1 instruction 1 instruction 1 instruction 1 instruction fX/32fXT instruction

1××× 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction

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7.6.2 System clock and CPU clock switching procedure

This section describes procedure for switching between the system clock and CPU clock.

Figure 7-9. System Clock and CPU Clock Switching

<1> The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released

by setting the RESET signal to high level, the main system clock starts oscillation. At this time, the oscillation

stabilization time (217/fX) is secured automatically.

After that, the CPU starts executing instructions at the minimum speed of the main system clock (3.81

s @

8.38 MHz operation).

<2> After the lapse of sufficient time for the VDD voltage to increase to enable operation at maximum speeds, PCC

is rewritten and maximum-speed operation is carried out.

<3> Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock is

switched to the subsystem clock (which must be in an oscillation stable state).

<4> Upon detection of VDD voltage reset due to an interrupt, 0 is set to the MCC and oscillation of the main system

clock is started. After the lapse of the time required for stabilization of oscillation, PCC is rewritten and the

maximum-speed operation is resumed.

Caution When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

System clock

CPU clock

Interrupt request signal

RESET

Lowest-

speed

operation

Highest-

speed

operation

Subsystem

clock

operation

High-speed

operation

Wait (15.6 ms: @8.38 MHz operation)

Internal reset operation

184 User’s Manual U14046EJ3V0UD

CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0

8.1 Functions of 16-Bit Timer/Event Counter 0

16-bit timer/event counter 0 has the following functions.

(1) Interval timer

16-bit timer/event counter 0 generates interrupt requests at the preset time interval.

• Number of counts: 2 to 65536

(2) External event counter

16-bit timer/event counter 0 can measure the number of pulses with a high-/low-level width of a signal input

externally.

• Valid level pulse width: 16/fX or more

(3) Pulse width measurement

16-bit timer/event counter 0 can measure the pulse width of an externally input signal.

• Valid level pulse width: 2/fX or more

(4) Square-wave output

16-bit timer/event counter 0 can output a square wave with any selected frequency.

• Cycle: (2 × 2 to 65536 × 2) × count clock cycle

(5) PPG output

16-bit timer/event counter 0 can output a square wave that have arbitrary cycle and pulse width.

• 2 < Pulse width < Cycle ≤ (FFFF + 1) H

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8.2 Configuration of 16-Bit Timer/Event Counter 0

16-bit timer/event counter 0 consists of the following hardware.

Table 8-1. Configuration of 16-Bit Timer/Event Counter 0

Item Configuration

Timer counter 16-bit timer counter 0 (TM0)

Timer input TI00, TI01

Timer output TO0

Control registers 16-bit timer mode control register 0 (TMC0)

Capture/compare control register 0 (CRC0)

16-bit timer output control register 0 (TOC0)

Prescaler mode register 0 (PRM0)

Port mode register 7 (PM7)

Port 7 (P7)

Figure 8-1 shows block diagram of this counter.

Figure 8-1. Block Diagram of 16-Bit Timer/Event Counter 0

Note TI00 input and TO0 output cannot be used at the same time.

Capture/compare control

Prescaler mode

16-bit timer output

control register 0

(TOC0)

16-bit timer mode

control register 0

(TMC0)

Internal bus

TI01/P71

TI00/TO0/P70Note

Noise

elimi-

nator

PRM01 PRM00

CRC02

Match

Clear

Noise

elimi-

nator

Noise

elimi-

nator

CRC02 CRC01 CRC00

INTTM00

TO0/TI00/

P70

Note

INTTM01

Internal bus

TMC03 TMC02

OVF0

TOC04

LVS0 LVR0

TOC01 TOE0

Output latch

(P70)

PM70

Selector

16-bit timer capture/compare

16-bit timer counter 0

(TM0)

16-bit timer capture/compare

Output

controller

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(1) 16-bit timer counter 0 (TM0)

TM0 is a 16-bit read-only register that counts count pulses.

The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read

during operation, input of the count clock is temporarily stopped, and the count value at that point is read. The

count value is reset to 0000H in the following cases.

<1> At RESET input

<2> If TMC03 and TMC02 are cleared

<3> If the valid edge of TI00 is input in the clear & start mode entered by inputting the valid edge of TI00

<4> If TM0 and CR00 match in the clear & start mode entered on a match between TM0 and CR00

(2) 16-bit timer capture/compare register 00 (CR00)

CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether

it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register

0 (CRC0).

• When CR00 is used as a compare register

The value set in CR00 is constantly compared with the 16-bit timer counter 0 (TM0) count value, and an interrupt

request (INTTM00) is generated if they match. It can also be used as the register that holds the interval time

then TM0 is set to interval timer operation.

• When CR00 is used as a capture register

It is possible to select the valid edge of the TI00 pin or the TI01 pin as the capture trigger. Setting of the TI00

or TI01 valid edge is performed by means of prescaler mode register 0 (PRM0) (see Table 8-2).

Table 8-2. CR00 Capture Trigger and Valid Edges of TI00 and TI01 Pins

(1) TI00 pin valid edge selected as capture trigger (CRC01 = 1, CRC00 = 1)

CR00 Capture Trigger TI00 Pin Valid Edge

ES01 ES00

Falling edge Rising edge 0 1

Rising edge Falling edge 0 0

No capture operation Both rising and falling edges 1 1

(2) TI01 pin valid edge selected as capture trigger (CRC01 = 0, CRC00 = 1)

CR00 Capture Trigger TI01 Pin Valid Edge

ES11 ES10

Falling edge Falling edge 0 0

Rising edge Rising edge 0 1

Both rising and falling edges Both rising and falling edges 1 1

Remarks 1. Setting ES01, ES00 = 1, 0 and ES11, ES10 = 1, 0 is prohibited.

2. ES01, ES00: Bits 5 and 4 of prescaler mode register 0 (PRM0)

ES11, ES10: Bits 7 and 6 of prescaler mode register 0 (PRM0)

CRC01, CRC00: Bits 1 and 0 of capture/compare control register 0 (CRC0)

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CR00 is set by a 16-bit memory manipulation instruction.

RESET input makes CR00 undefined.

Cautions 1. Set CR00 to a value other than 0000H in the clear & start mode entered on a match between

TM0 and CR00. However, in the free-running mode and in the clear mode using the valid

edge of TI00, if CR00 is cleared to 0000H, an interrupt request (INTTM00) is generated when

CR00 changes from 0000H to 0001H following overflow (FFFFH).

2. If the new value of CR00 is less than the value of 16-bit timer counter 0 (TM0), TM0 continues

counting, overflows, and then starts counting from 0 again. If the new value of CR00 is less

than the old value, therefore, the timer must be reset to be restarted after the value of CR00

is changed.

3. When P70 is used as the input pin for the valid edge of TI00, it cannot be used as a timer

output (TO0). Moreover, when P70 is used as TO0, it cannot be used as the input pin for

the valid edge of TI00.

(3) 16-bit timer capture/compare register 01 (CR01)

CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is

used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0 (CRC0).

•When CR01 is used as a compare register

The value set in CR01 is constantly compared with the 16-bit timer counter 0 (TM0) count value, and an interrupt

request (INTTM01) is generated if they match.

•When CR01 is used as a capture register

It is possible to select the valid edge of the TI00 pin as the capture trigger. The TI00 valid edge is set by means

of prescaler mode register 0 (PRM0) (see Table 8-3).

Table 8-3. CR01 Capture Trigger and Valid Edge of TI00 Pin (CRC02 = 1)

CR01 Capture Trigger TI00 Pin Valid Edge

ES01 ES00

Falling edge Falling edge 0 0

Rising edge Rising edge 0 1

Both rising and falling edges Both rising and falling edges 1 1

Remarks 1. Setting ES01, ES00 = 1, 0 is prohibited.

2. ES01, ES00: Bits 5 and 4 of prescaler mode register 0 (PRM0)

CRC02: Bit 2 of capture/compare control register 0 (CRC0)

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CR01 is set by a 16-bit memory manipulation instruction.

RESET input makes CR01 undefined.

Caution Set CR01 to other than 0000H in the clear & start mode entered on a match between TM0 and

CR00. However, in the free-running mode and in the clear mode using the valid edge of TI00,

if CR01 is cleared to 0000H, an interrupt request (INTTM01) is generated when CR01 changes

from 0000H to 0001H following overflow (FFFFH).

8.3 Registers to Control 16-Bit Timer/Event Counter 0

The following six types of registers are used to control 16-bit timer/event counter 0.

•16-bit timer mode control register 0 (TMC0)

•Capture/compare control register 0 (CRC0)

•16-bit timer output control register 0 (TOC0)

•Prescaler mode register 0 (PRM0)

•Port mode register 7 (PM7)

•Port 7 (P7)

(1) 16-bit timer mode control register 0 (TMC0)

This register sets the 16-bit timer operating mode, the 16-bit timer counter 0 (TM0) clear mode, and output timing,

and detects an overflow.

TMC0 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC0 to 00H.

Caution 16-bit timer counter 0 (TM0) starts operation at the moment TMC02 and TMC03 (operation stop

mode) are set to a value other than 0, 0, respectively. Clear TMC02 and TMC03 to 0, 0 to stop

the operation.

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Figure 8-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0)

TMC03 TMC02 Operating mode TO0 output timing selection Interrupt request generation

and clear mode selection

0 0 Operation stop No change Not generated

(TM0 cleared to 0)

0 1 Free-running mode Match between TM0 and

CR00 or match between

TM0 and CR01

1 0 Clear & start on TI00 valid −

edgeNote 1

Clear & start on match between

Match between TM0 and

TM0 and CR00Note 2 CR00 or match between

TM0 and CR01

OVF0 Overflow detection of 16-bit timer counter 0 (TM0)

0 Overflow not detected

1 Overflow detected

Notes 1. Set the valid edge of the TI00/TO0/P70 pin with prescaler mode register 0 (PRM0).

2. If the clear & start mode entered on a match between TM0 and CR00 is selected, when the set value

of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, the OVF0 flag is set to 1.

Cautions 1. To write different data to TMC0, stop the timer operation before writing.

2. The timer operation must be stopped before writing to bits other than the OVF0 flag.

Remarks 1. TO0: 16-bit timer/event counter 0 output pin

2. TI00: 16-bit timer/event counter 0 input pin

3. TM0: 16-bit timer counter 0

4. CR00: 16-bit timer capture/compare register 00

5. CR01: 16-bit timer capture/compare register 01

Generated on match

between TM0 and CR00, or

match between TM0 and

CR01

<3>

TMC03

<2>

TMC02

<0>

OVF0

Symbol

TMC0

Address: FF60H After reset: 00H R/W

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(2) Capture/compare control register 0 (CRC0)

This register controls the operation of the 16-bit timer capture/compare registers (CR00, CR01).

CRC0 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CRC0 to 00H.

Figure 8-3. Format of Capture/Compare Control Register 0 (CRC0)

Address: FF62H After reset: 00H R/W

Symbol 76543210

CRC0 00000CRC02 CRC01 CRC00

CRC02 CR01 operating mode selection

0 Operate as compare register

1 Operate as capture register

CRC01 CR00 capture trigger selection

0 Capture on valid edge of TI01

1 Capture on valid edge of TI00 by reverse phaseNote

CRC00 CR00 operating mode selection

0 Operate as compare register

1 Operate as capture register

Note If both the rising and falling edges have been selected as the valid edges of TI00, capture is not performed.

Cautions 1. The timer operation must be stopped before setting CRC0.

2. When the clear & start mode entered on a match between TM0 and CR00 is selected by 16-

bit timer mode control register 0 (TMC0), CR00 should not be specified as a capture register.

3. To ensure the reliability of the capture operation, the capture trigger requires a pulse longer

than two cycles of the count clock selected by prescaler mode register 0 (PRM0) (see Figure

8-31).

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(3) 16-bit timer output control register 0 (TOC0)

This register controls the operation of the 16-bit timer/event counter output controller. It sets R-S type flip-flop (LV0)

set/reset, output inversion enable/disable, and 16-bit timer/event counter timer output enable/disable.

TOC0 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TOC0 to 00H.

Figure 8-4. Format of 16-Bit Timer Output Control Register 0 (TOC0)

Address: FF63H After reset: 00H R/W

Symbol 7654<3><2>1<0>

TOC0 0 0 0 TOC04 LVS0 LVR0 TOC01 TOE0

TOC04 Timer output F/F control by match of CR01 and TM0

0 Inversion operation disabled

1 Inversion operation enabled

LVS0 LVR0 16-bit timer/event counter 0 timer output F/F status setting

0 0 No change

0 1 Timer output F/F reset (0)

1 0 Timer output F/F set (1)

1 1 Setting prohibited

TOC01 Timer output F/F control by match of CR00 and TM0

0 Inversion operation disabled

1 Inversion operation enabled

TOE0 16-bit timer/event counter 0 output control

0 Output disabled (output set to level 0)

1 Output enabled

Cautions 1. The timer operation must be stopped before setting TOC0.

2. If LVS0 and LVR0 are read after data is set, they will be 0.

3. Be sure to clear bits 5 to 7 of TOC0 to 0.

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(4) Prescaler mode register 0 (PRM0)

This register is used to set the 16-bit timer counter 0 (TM0) count clock and TI00, TI01 input valid edges.

PRM0 is set by an 8-bit memory manipulation instruction.

RESET input clears PRM0 to 00H.

Figure 8-5. Format of Prescaler Mode Register 0 (PRM0)

Address: FF61H After reset: 00H R/W

Symbol 76543210

PRM0 ES11 ES10 ES01 ES00 0 0 PRM01 PRM00

ES11 ES10 TI01 valid edge selection

0 0 Falling edge

0 1 Rising edge

1 0 Setting prohibited

1 1 Both falling and rising edges

ES01 ES00 TI00 valid edge selection

0 0 Falling edge

0 1 Rising edge

1 0 Setting prohibited

1 1 Both falling and rising edges

PRM01 PRM00 Count clock selection

fX = 8.38 MHz fX = 12 MHzNote 1

00fX8.38 MHz 12 MHz

01fX/222.09 MHz 3 MHz

10fX/26130 kHz 187 kHz

1 1 TI00 valid edgeNotes 2, 3

Notes 1. Expanded-specification products of

PD780024A, 780034A Subseries only.

2. The external clock requires a pulse longer than two cycles of the internal count clock (fX/23).

3. When the valid edge of TI00 is selected, the main system clock is used as the sampling clock for noise

elimination. The valid edge of TI00 can be used only when the main system clock is operating.

Cautions 1. Always set data to PRM0 after stopping the timer operation.

2. If the valid edge of TI00 is to be set as the count clock, do not set the clear & start mode

and the capture trigger at the valid edge of TI00.

Moreover, do not use the P70/TI00/TO0 pin as a timer output (TO0).

3. If the TI00 or TI01 pin is high level immediately after system reset, the rising edge is

immediately detected after the rising edge or both the rising and falling edges are set as

the valid edge(s) of the TI00 pin or TI01 pin to enable the operation of 16-bit timer counter

0 (TM0). Be careful when pulling up the TI00 pin or the TI01 pin. However, when re-enabling

operation after the operation has been stopped once, the rising edge is not detected.

Remarks 1. fX: Main system clock oscillation frequency

2. TI00, TI01: 16-bit timer/event counter 0 input pin

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(5) Port mode register 7 (PM7)

This register sets port 7 input/output in 1-bit units.

When using the P70/TO0/TI00 pin for timer output, clear PM70 and the output latch of P70 to 0.

When using the P70/TO0/TI00 pin for timer input, set PM70 to 1. At this time, the output latch of P70 can be

either 0 or 1.

PM7 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM7 to FFH.

Figure 8-6. Format of Port Mode Register 7 (PM7)

PM75

PM74

PM73

PM72

PM71

PM70

Symbol

PM7

Address: FF27H After reset: FFH R/W

PM7n

P7n pin I/O mode selection (n = 0 to 5)

Output mode (output buffer on)

Input mode (output buffer off)

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8.4 Operation of 16-Bit Timer/Event Counter 0

8.4.1 Interval timer operation

Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in

Figure 8-7 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value

set in 16-bit timer capture/compare register 00 (CR00) beforehand as the interval.

When the count value of 16-bit timer counter 0 (TM0) matches the value set to CR00, counting continues with the

TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated.

The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM00, PRM01) of prescaler

mode register 0 (PRM0).

Figure 8-7. Control Register Settings for Interval Timer Operation

(a) 16-bit timer mode control register 0 (TMC0)

(b) Capture/compare control register 0 (CRC0)

0000

TMC03

TMC02

OVF0

0TMC0

Clears and starts on match between TM0 and CR00.

00000

CRC02

0/1

CRC01

0/1

CRC00

0CRC0

CR00 used as compare register

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Figure 8-8. Interval Timer Configuration Diagram

16-bit timer capture/compare

16-bit timer counter 0

OVF0

Note

Clear

circuit

INTTM00

TI00/TO0/P70

Selector

Noise

eliminator

Note OVF0 is 1 only when 16-bit timer capture/compare register 00 is set to FFFFH.

Figure 8-9. Timing of Interval Timer Operation

Count clock

TM0 count value

CR00

INTTM00

TO0

0000H

0001H

0000H 0001H

NNNN

Count start Clear Clear

Interrupt acknowledged Interrupt acknowledged

Interval time Interval time

Remark Interval time = (N + 1) × t

N = 0001H to FFFFH

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When the compare register is changed during timer count operation, if the value after 16-bit timer capture/

compare register 00 (CR00) is changed is smaller than that of 16-bit timer counter 0 (TM0), TM0 continues

counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR00 change is smaller

than that (N) before the change, it is necessary to restart the timer after changing CR00.

Figure 8-10. Timing After Change of Compare Register During Timer Count Operation

CR00

Count clock

TM0 count value

X − 1 X FFFFH 0000H 0001H 0002H

Remark N > X > M

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8.4.2 External event counter operation

The external event counter counts the number of external clock pulses to be input to the TI00 pin with using 16-

bit timer counter 0 (TM0).

TM0 is incremented each time the valid edge specified by prescaler mode register 0 (PRM0) is input.

When the TM0 count value matches the 16-bit timer capture/compare register 00 (CR00) value, TM0 is cleared

to 0 and the interrupt request signal (INTTM00) is generated.

Input a value other than 0000H to CR00. (A count operation with a pulse cannot be carried out.)

The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES00 and ES01) of prescaler

mode register 0 (PRM0).

Because an operation is carried out only when the valid edge of the TI00 pin is detected twice after sampling with

the internal clock (fX/23), noise with a short pulse width can be removed.

Caution When used as an external event counter, the P70/TI00/TO0 pin cannot be used as a timer output

(TO0).

Figure 8-11. Control Register Settings in External Event Counter Mode

(a) 16-bit timer mode control register 0 (TMC0)

0000

TMC03

TMC02

OVF0

0TMC0

Clears and starts on match between TM0 and CR00.

(b) Capture/compare control register 0 (CRC0)

00000

CRC02

0/1

CRC01

0/1

CRC00

0CRC0

CR00 used as compare register

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Figure 8-12. External Event Counter Configuration Diagram

16-bit timer capture/compare

16-bit timer counter 0 (TM0)

Internal bus

Match

Clear

OVF0

Note

INTTM00

Noise eliminator

fX/23

Valid edge of TI00

Note OVF0 is 1 only when 16-bit timer capture/compare register 00 is set to FFFFH.

Figure 8-13. External Event Counter Operation Timing (with Rising Edge Specified)

TI00 pin input

TM0 count value

CR00

INTTM00

0000H 0001H 0002H 0003H 0004H 0005H

N − 1N

0000H 0001H 0002H 0003H

Caution When reading the external event counter count value, TM0 should be read.

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8.4.3 Pulse width measurement operations

It is possible to measure the pulse width of the signals input to the TI00 pin and TI01 pin using

16-bit timer counter 0 (TM0).

There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting

the timer in synchronization with the edge of the signal input to the TI00 pin.

(1) Pulse width measurement with free-running counter and one capture register

When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 8-14), and

the edge specified by prescaler mode register 0 (PRM0) is input to the TI00 pin, the value of TM0 is taken into

16-bit timer capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set.

Any of three edges can be selected—rising, falling, or both edges—specified by bits 4 and 5 (ES00 and ES01)

of PRM0.

Sampling is performed with the count clock selected by PRM0, and a capture operation is only performed when

a valid level of the TI00 pin is detected twice, thus eliminating noise with a short pulse width.

Figure 8-14. Control Register Settings for Pulse Width Measurement with Free-Running Counter

and One Capture Register

(a) 16-bit timer mode control register 0 (TMC0)

0000

TMC03

TMC02

OVF0

0TMC0

Free-running mode

(b) Capture/compare control register 0 (CRC0)

00000

CRC02

CRC01

0/1

CRC00

0CRC0

CR00 used as compare register

CR01 used as capture register

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Figure 8-15. Configuration Diagram for Pulse Width Measurement with Free-Running Counter

fX/22

fX/26

TI00/TO0/P70

16-bit timer counter 0 OVF0

16-bit timer capture/compare

Internal bus

INTTM01

Selector

Figure 8-16. Timing of Pulse Width Measurement Operation with Free-Running Counter

and One Capture Register (with Both Edges Specified)

0000H 0000H

FFFFH

0001H

(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t

D1 D2 D3

D2 D3

D0 + 1

D1 + 1

Note

Count clock

TM0 count value

TI00 pin input

CR01 capture value

INTTM01

OVF0

Note OVF0 must be cleared by software.

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(2) Measurement of two pulse widths with free-running counter

When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 8-17), it is

possible to simultaneously measure the pulse widths of the two signals input to the TI00 pin and the TI01 pin.

When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the

TI00 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an interrupt request

signal (INTTM01) is set.

Also, when the edge specified by bits 6 and 7 (ES10 and ES11) of PRM0 is input to the TI01 pin, the value of

TM0 is taken into 16-bit timer capture/compare register 00 (CR00) and an interrupt request signal (INTTM00)

is set.

Any of three edges can be selected—rising, falling, or both edges—as the valid edges for the TI00 pin and the

TI01 pin specified by bits 4 and 5 (ES00 and ES01) and bits 6 and 7 (ES10 and ES11) of PRM0, respectively.

Sampling is performed at the interval selected by prescaler mode register 0 (PRM0), and a capture operation

is only performed when a valid level of the TI00 pin or TI01 pin is detected twice, thus eliminating noise with a

short pulse width.

Figure 8-17. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter

(a) 16-bit timer mode control register 0 (TMC0)

0000

TMC03

TMC02

OVF0

0TMC0

Free-running mode

(b) Capture/compare control register 0 (CRC0)

00000

CRC02

CRC01

CRC00

1CRC0

CR00 used as capture register

Captures valid edge of TI01 pin to CR00

CR01 used as capture register

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Figure 8-18. Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified)

Note OVF0 must be cleared by software.

0000H 0000H

FFFFH

0001H

(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t

(10000H − D1 + (D2 + 1)) × t

D2 + 1D1

D2 D3

D0 + 1

D1 + 1 D2 + 1 D2 + 2

Note

TI01 pin input

CR00 capture value

INTTM01

INTTM00

OVF0

Count clock

TM0 count value

TI00 pin input

CR01 capture value

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(3) Pulse width measurement with free-running counter and two capture registers

When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 8-19), it is

possible to measure the pulse width of the signal input to the TI00 pin.

When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the

TI00 pin, the value of TM0 is taken into 16-bit timer capture/compare register 01 (CR01) and an interrupt request

signal (INTTM01) is set.

Also, when the inverse edge to that of the capture operation to CR01 is input, the value of TM0 is taken into 16-

bit timer capture/compare register 00 (CR00).

Either of two edges can be selected—rising or falling—as the valid edges for the TI00 pin specified by bits 4 and

5 (ES00 and ES01) of prescaler mode register 0 (PRM0).

Sampling is performed at the interval selected by prescaler mode register 0 (PRM0), and a capture operation

is only performed when a valid level of the TI00 pin is detected twice, thus eliminating noise with a short pulse

width.

Caution If the valid edge of TI00 is specified to be both the rising and falling edges, 16-bit timer capture/

compare register 00 (CR00) cannot perform the capture operation.

Figure 8-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter and

Two Capture Registers

(a) 16-bit timer mode control register 0 (TMC0)

0000

TMC03

TMC02

OVF0

0TMC0

Free-running mode

(b) Capture/compare control register 0 (CRC0)

00000

CRC02

CRC01

CRC00

1CRC0

CR00 used as capture register

Captures to CR00 at edge reverse

to valid edge of TI00.

CR01 used as capture register

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Figure 8-20. Timing of Pulse Width Measurement Operation with Free-Running Counter

and Two Capture Registers (with Rising Edge Specified)

0000H 0000H

FFFFH

0001H

D0 D2

D1 D3

D2 D3D1

D0 + 1 D2 + 1D1 + 1

INTTM01

OVF0

CR00 capture value

Count clock

TM0 count value

TI00 pin input

CR01 capture value

(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t

Note

Note OVF0 must be cleared by software.

(4) Pulse width measurement by means of restart

When input of a valid edge to the TI00 pin is detected, the count value of 16-bit timer counter 0 (TM0) is taken

into 16-bit timer capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00

pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-22).

The edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (ES00 and ES01)

of prescaler mode register 0 (PRM0).

Sampling is performed at the interval selected by prescaler mode register 0 (PRM0) and a capture operation is

only performed when a valid level of the TI00 pin is detected twice, thus eliminating noise with a short pulse width.

Caution If the valid edge of TI00 is specified to be both the rising and falling edges, 16-bit timer capture/

compare register 00 (CR00) cannot perform the capture operation.

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Figure 8-21. Control Register Settings for Pulse Width Measurement by Means of Restart

(a) 16-bit timer mode control register 0 (TMC0)

0000

TMC03

TMC02

OVF0

0TMC0

Clears and starts at valid edge of TI00 pin.

(b) Capture/compare control register 0 (CRC0)

00000

CRC02

CRC01

CRC00

1CRC0

CR00 used as capture register

Captures to CR00 at edge reverse to valid edge of TI00.

CR01 used as capture register

Figure 8-22. Timing of Pulse Width Measurement Operation by Means of Restart

(with Rising Edge Specified)

0000H 0001H0000H0001H 0000H 0001H

D0 D2

D2D1

D1 × t

D2 × t

INTTM01

CR00 capture value

Count clock

TM0 count value

TI00 pin input

CR01 capture value

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8.4.4 Square-wave output operation

A square wave with any selected frequency can be output at intervals determined by the count value preset to

16-bit timer capture/compare register 00 (CR00).

The TO0 pin output status is reversed at intervals determined by the count value preset to CR00 by setting bit 0

(TOE0) and bit 1 (TOC01) of 16-bit timer output control register 0 (TOC0) to 1. This enables a square wave with

any selected frequency to be output.

Figure 8-23. Control Register Settings in Square-Wave Output Mode

(a) 16-bit timer mode control register 0 (TMC0)

0000

TMC03

TMC02

OVF0

0TMC0

Clears and starts on match between TM0 and CR00.

(b) Capture/compare control register 0 (CRC0)

00000

CRC02

0/1

CRC01

0/1

CRC00

0CRC0

CR00 used as compare register

000

TOC04

LVS0

0/1

LVR0

0/1

TOC01

TOE0

1TOC0

Enables TO0 output.

Reverses output on match between TM0 and CR00.

Specifies initial value of TO0 output F/F.

Does not reverse output on match between TM0 and CR01.

Figure 8-24. Square-Wave Output Operation Timing

Count clock

TM0 count value

CR00

INTTM00

TO0 pin output

0000H 0001H 0002H

N − 1N

0000H 0001H 0002H

N − 1N

0000H

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8.4.5 PPG output operation

Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in

Figure 8-25 allows operation as PPG (Programmable Pulse Generator) output.

In the PPG output operation, square waves are output from the TO0 pin with the pulse width and the cycle that

correspond to the count values set beforehand in 16-bit timer capture/compare register 01 (CR01) and in 16-bit timer

capture/compare register 00 (CR00), respectively.

Figure 8-25. Control Register Settings for PPG Output Operation

(a) 16-bit timer mode control register 0 (TMC0)

0000

TMC03

TMC02

OVF0

0TMC0

Clears and starts on match between TM0 and CR00.

(b) Capture/compare control register 0 (CRC0)

00000

CRC02

CRC01

CRC00

0CRC0

CR00 used as compare register

CR01 used as compare register

000

TOC04

LVS0

0/1

LVR0

0/1

TOC01

TOE0

1TOC0

Enables TO0 output

Reverses output on match between TM0 and CR00

Specifies initial value of TO0 output F/F

Reverse output on match between TM0 and CR01

Cautions 1. CR00 and CR01 values in the following range should be set to:

0000H < CR01 < CR00 ≤ FFFFH

2. The cycle of the pulse generated via PPG output (CR00 setting value + 1) has a duty of (CR01

setting value + 1)/(CR00 setting value + 1).

Remark ×: Don’t care

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Figure 8-26. PPG Output Configuration Diagram

Figure 8-27. PPG Output Operation Timing

Remark 0000H < M < N ≤ FFFFH

16-bit timer capture/

compare register 00

16-bit timer counter 0 Clear

circuit

16-bit timer capture/compare

TO0/TI00/P70

Selector

Output controller

0000H 0000H

0001H

M − 1

Count clock

TM0 count value

TO0

Pulse width: (M + 1) × t

One cycle: (N + 1) × t

CR00

CR01 M

N − 1

ClearCount start

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8.5 Program List

Caution The following sample program is shown as an example to describe the operation of

semiconductor products and their applications. Therefore, when applying the following

information to your devices, design the devices after performing evaluation under your own

responsibility.

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8.5.1 Interval timer

/*******************************************************************************/

/* */

/* Setting example of timer 0 interval timer mode */

/* Cycle set to 130 as intervalTM0 (at 8.38 MHz for 1 ms) */

/* Variable ppgdata prepared as rewrite data area */

/* : Cycle (if 0000, no change) */

/* ppgdata to be checked at every INTTM00, and changed if required. */

/* Therefore, if change is required, set the change data in ppgdata. */

/* When changed, ppgdata cleared to 0000. */

/* */

/*******************************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#define intervalTM0 130 /* Cycle data to be set to CR00 */

#pragma interrupt INTTM00 intervalint rb2

unsigned int ppgdata; /* Data area to be set to timer 0 */

void main(void)

{

PCC = 0x0; /* Set high-speed operation mode */

ppgdata = 0;

/* Set port */

/* Set the following to output */

P7 = 0b11111110; /* Clear P70 */

PM7.0 = 0; /* Set P70 as output */

/* Set interrupt */

TMMK00 = 0; /* Cancel INTTM00 interrupt mask */

/* Set timer 0 */

PRM0 = 0b00000010; /* Count clock is fx/2^6 */

CRC0 = 0b00000000; /* Set CR00 and CR01 to compare register */

CR00 = intervalTM0; /* Set cycle initial value to CR00 */

TOC0 = 0b00000111; /* Invert on match with CR00, initial value L */

TMC0 = 0b00001100; /* Clear & start on match between TM0 and CR00 */

EI();

while(1); /* Loop as dummy here */

}

/* Timer 0 interrupt function */

void intervalint()

{

unsigned int work;

/***************************************************/

/* */

/* Define variables required for interrupt here */

/* */

/***************************************************/

work = ppgdata;

if (work != 0)

{

CR00 = work;

ppgdata = 0;

if (work == 0xffff)

{

TMC0 = 0b00000000; /* Stop timer */

}

/***********************************************************/

/* */

/* Describe processing required for interrupt below */

/* */

/***********************************************************/

}

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8.5.2 Pulse width measurement by free-running counter and one capture register

/******************************************************************************/

/* */

/* Timer 0 operation sample */

/* Pulse width measurement example by free-running and CR01 */

/* Measurement results to be up to 16 bits and not checked for errors */

/* data[0]: End flag */

/* data[1]: Measurement results (pulse width) */

/* data[2]: Previous read value */

/* */

/******************************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#pragma interrupt INTTM01 intervalint rb2

unsigned int data[3]; /* Data area */

void main(void)

{

unsigned int length;

PCC = 0x0; /* Set high-speed operation mode */

data[0] = 0;

data[1] = 0;

data[2] = 0;

/* Set port */

PM7.0 = 1; /* Set P70 as input */

/* Set interrupt */

TMMK01 = 0; /* Cancel INTTM01 interrupt mask */

/* Set timer 0 */

PRM0 = 0b00110010; /* Both rising and falling edges for TI00 */

/* Count clock is fx/2^6 */

CRC0 = 0b00000100; /* Set CR01 to capture register */

TMC0 = 0b00000100; /* Start in free-run mode */

EI();

while(1){ /* Dummy loop */

while(data[0] == 0); /* Wait for measurement completion */

DI(); /* Prohibit interrupt for exclusive operation */

length = data[1]; /* Read measurement results */

data[0] = 0; /* Clear end flag */

EI(); /* Exclusive operation completed */

}

/* Timer 0 interrupt function */

void intervalint()

{

unsigned int work;

/*****************************************************/

/* */

/* Define variables required for interrupt here */

/* */

/*****************************************************/

work = CR01; /* Read capture value */

data[1] = work - data[2]; /* Calculate and update interval */

data[2] = work; /* Update read value */

data[0] = 0xffff; /* Set measurement completion flag */

/***********************************************************/

/* */

/* Describe processing required for interrupt below */

/* */

/***********************************************************/

}

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8.5.3 Two pulse widths measurement by free-running counter

/******************************************************************************/

/* */

/* Timer 0 operation sample */

/* Two-pulse-width measurement sample by free-running */

/* Measurement results to be up to 16 bits and not checked for errors */

/* Result area at TI00 side */

/* data[0]: End flag */

/* data[1]: Measurement results (pulse width) */

/* data[2]: Previous read value */

/* Result area at TI01 side */

/* data[3]: End flag */

/* data[4]: Measurement results (pulse width) */

/* data[5]: Previous read value */

/* */

/******************************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#pragma interrupt INTTM00 intervalint rb2

#pragma interrupt INTTM01 intervalint2 rb2

unsigned int data[6]; /* Data area */

void main(void)

{

unsigned int length,length2;

PCC = 0x0; /* Set high-speed operation mode */

data[0] = 0; /* Clear data area */

data[1] = 0;

data[2] = 0;

data[3] = 0;

data[4] = 0;

data[5] = 0;

/* Set port */

PM7.0 = 1; /* Set P70 as input */

PM7.1 = 1; /* Set P71 as input */

/* Set interrupt */

TMMK01 = 0; /* Cancel INTTM01 interrupt mask */

TMMK00 = 0; /* Cancel INTTM00 interrupt mask */

/* Set timer 0 */

PRM0 = 0b11110010; /* Both rising and falling edges */

/* Count clock is fx/2^6 */

CRC0 = 0b00000101; /* Set CR00 and CR01 to capture register */

TMC0 = 0b00000100; /* Start in free-run mode */

EI();

while(1){ /* Dummy loop */

if(data[0] != 0) /* TI00 measurement completion check */

{

TMMK01 = 1; /* INTTM01 interrupt prohibited for

exclusive operation */

length = data[1]; /* Read measurement results */

data[0] = 0; /* Clear end flag */

TMMK01 = 0; /* Exclusive operation completed */

}

if(data[3] != 0) /* TI01 measurement completion check */

{

TMMK00 = 1; /* INTTM00 interrupt prohibited for

exclusive operation */

length2 = data[4]; /* Read measurement results */

data[3] = 0; /* Clear end flag */

TMMK00 = 0; /* Exclusive operation completed */

}

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/* INTTM00 interrupt function */

void intervalint()

{

unsigned int work;

/******************************************************/

/* */

/* Define variables required for interrupt here */

/* */

/******************************************************/

work = CR00; /* Read capture value */

data[4] = work - data[5]; /* Calculate and update interval */

data[5] = work; /* Update read value */

data[3] = 0xffff; /* Set measurement completion flag */

/********************************************************/

/* */

/* Describe processing required for interrupt below */

/* */

/********************************************************/

}

/* INTTM01 interrupt function */

void intervalint2()

{

unsigned int work;

/******************************************************/

/* */

/* Define variables required for interrupt here */

/* */

/******************************************************/

work = CR01; /* Read capture value */

data[1] = work - data[2]; /* Calculate and update interval */

data[2] = work; /* Update read value */

data[0] = 0xffff; /* Set measurement completion flag */

/********************************************************/

/* */

/* Describe processing required for interrupt below */

/* */

/********************************************************/

}

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8.5.4 Pulse width measurement by restart

/**************************************************************************/

/* */

/* Timer 0 operation sample */

/* Pulse width measurement example by restart */

/* Measurement results up to 16 bits, not to be checked for errors */

/* data[0]: End flag */

/* data[1]: Measurement results (pulse width) */

/* data[2]: Previous read value */

/* */

/**************************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#pragma interrupt INTTM01 intervalint rb2

unsigned int data[3]; /* Data area */

void main(void)

{

unsigned int length;

PCC = 0x0; /* Set high-speed operation mode */

data[0] = 0;

data[1] = 0;

data[2] = 0;

/* Set port */

PM7.0 = 1; /* Set P70 as input */

/* Set interrupt */

TMMK01 = 0; /* Cancel INTTM01 interrupt mask */

/* Set timer 0 */

PRM0 = 0b00110010; /* Both rising and falling edges */

/* Count clock is fx/2^6 */

CRC0 = 0b00000100; /* Set CR01 to capture register */

TMC0 = 0b00001000; /* Clear & start at TI00 valid edge */

EI();

while(1){ /* Dummy loop */

if(data[0] != 0) /* Wait for TI00 measurement completion */

{

TMMK01 = 1; /* Prohibit INTTM01 interrupt for

exclusive operation */

length = data[1]+data[2]; /* Cycle calculation based on

measurement results */

data[0] = 0; /* Clear end flag */

TMMK01 = 0; /* Exclusive operation completed */

}

/* Timer 0 interrupt function */

void intervalint()

{

/******************************************************/

/* */

/* Define variables required for interrupt here */

/* */

/******************************************************/

data[2] = data[1]; /* Update old data */

data[1] = CR01; /* Update read value */

data[0] = 0xffff; /* Set measurement completion flag */

/********************************************************/

/* */

/* Describe processing required for interrupt below */

/* */

/********************************************************/

}

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8.5.5 PPG output

/******************************************************************************/

/* */

/* Timer 0 PPG mode setting example */

/* Cycle set to 130 as intervalTM0 */

/* Active period set to 65 as active_time */

/* Array ppgdata prepared as data area for rewriting */

/* [0]: Active period (0000: no change, 0xffff: stop) */

/* [1]: Cycle (0000: no change) */

/* ppgdata to be checked at every INTTM00, and changed if required. */

/* Therefore, if change is required, set the change data in ppgdata. */

/* When changed, ppgdata cleared to 0000. */

/* */

/******************************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#define intervalTM0 130 /* Cycle data to be set to CR00 */

#define active_time 65 /* Initial value data of CR01 */

#pragma interrupt INTTM00 ppgint rb2

unsigned int ppgdata[2]; /* Data area to be set to timer 0 */

void main(void)

{

PCC = 0x0; /* Set high-speed operation mode */

ppgdata[0] = 0;

ppgdata[1] = 0;

/* Set port */

P7 = 0b11111110; /* Clear P70 */

PM7.0 = 0; /* Set P70 to output */

/* Set interrupt */

TMMK00 = 0; /* Cancel INTTM00 interrupt mask */

/* Set timer 0 */

PRM0 = 0b00000010; /* Count clock is fx/2^6 */

CRC0 = 0b00000000; /* Set CR00 and CR01 to compare register */

CR00 = intervalTM0; /* Set initial value of cycle */

CR01 = active_time; /* Set initial value of active period */

TOC0 = 0b00010111; /* Inverted on match between CR00 and CR01,

initial value L */

TMC0 = 0b00001100; /* Clear & start on match between TM0 and CR00 */

EI();

while(1);

}

/* Timer 0 interrupt function */

void ppgint()

{

unsigned int work;

work = ppgdata[0];

if (work != 0)

{

CR01 = work;

ppgdata[0] = 0;

if (work == 0xffff)

{

TMC0 = 0b00000000; /* Stop timer */

}

work = ppgdata[1];

if (work != 0)

{

CR00 = work;

ppgdata[1]=0;

}

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8.6 Cautions Related to 16-Bit Timer/Event Counter 0

(1) Timer start errors

An error of up to one clock may occur in the time required for a match signal to be generated after timer start.

This is because 16-bit timer counter 0 (TM0) is started asynchronously to the count clock.

Figure 8-28. Start Timing of 16-Bit Timer Counter 0 (TM0)

TM0 count value

0000H 0001H 0002H 0004H

Count clock

Timer start

0003H

(2) 16-bit timer capture/compare register setting (clear & start mode entered on match between TM0 and

CR00)

Set 16-bit timer capture/compare registers 00, 01 (CR00, CR01) to other than 0000H. This means a 1-pulse

count operation cannot be performed.

(3) Capture register data retention timing

If the valid edge of the TI00 pin is input during 16-bit timer capture/compare register 01 (CR01) read, CR01

performs a capture operation but, the read value at this time is not guaranteed. The interrupt request signal

(INTTM01) is generated upon detection of the valid edge.

Figure 8-29. Capture Register Data Retention Timing

Count clock

TM0 count

Edge input

INTTM01

Capture read signal

CR01 capture value

N N + 1 N + 2 M M + 1 M + 2

X N + 1 M + 1

Read value not guaranteed

though capture operation performed

Capture

(4) Valid edge setting

Set the valid edge of the TI00 pin after clearing bits 2 and 3 (TMC02 and TMC03) of 16-bit timer mode control

and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0).

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(5) Operation of OVF0 flag

<1> The OVF0 flag is also set to 1 in the following case.

Either of the clear & start mode entered on a match between TM0 and CR00, clear & start at the valid edge

of TI00, or free-running mode is selected.

↓

CR00 is set to FFFFH.

↓

When TM0 is counted up from FFFFH to 0000H.

Figure 8-30. Operation Timing of OVF0 Flag

Count clock

CR00

TM0

OVF0

INTTM00

FFFFH

FFFEH FFFFH 0000H 0001H

<2> Even if the OVF0 flag is cleared before the next count clock is counted (before TM0 becomes 0001H) after

the occurrence of a TM0 overflow, the OVF0 flag is reset newly and clear is disabled.

(6) Conflicting operations

When the 16-bit timer capture/compare register (CR00/CR01) is used as a compare register, if the write period

and the match timing of 16-bit timer counter 0 (TM0) conflict, match determination is not successfully done. Do

not perform a write operation of CR00/CR01 near the match timing.

(7) Timer operation

<1> Even if 16-bit timer counter 0 (TM0) is read, the value is not captured by 16-bit timer capture/compare

<2> Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins TI00/TI01 are

not acknowledged.

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(8) Capture operation

<1> If TI00 is specified as the valid edge of the count clock, a capture operation by the capture register specified

as the trigger for TI00 is not possible.

<2> If both the rising and falling edges are selected as the valid edges of TI00, capture is not performed.

<3> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles

of the count clock selected by prescaler mode register 0 (PRM0).

Figure 8-31. CR01 Capture Operation with Rising Edge Specified

Count clock

TM0

TI00

Rising edge detection

CR01

INTTM01

N − 3N − 2N − 1 N N + 1

<4> The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n),

however, occurs at the rise of the next count clock.

(9) Compare operation

<1> When the 16-bit timer capture/compare register (CR00/CR01) is overwritten during timer operation, match

interrupt may be generated or the clear operation may not be performed normally if that value is close to

or large than the timer value.

<2> The capture operation may not be performed for CR00/CR01 set in compare mode even if a capture trigger

is input.

(10) Edge detection

<1> If the TI00 pin or the TI01 pin is high level immediately after system reset and the rising edge or both the

rising and falling edges are specified as the valid edge for the TI00 pin or TI01 pin to enable 16-bit timer

counter 0 (TM0) operation, a rising edge is detected immediately. Be careful when pulling up the TI00 pin

or the TI01 pin. However, the rising edge is not detected at restart after the operation has been stopped

once.

<2> The sampling clock used to remove noise differs when a TI00 valid edge is used as the count clock and

when it is used as a capture trigger. In the former case, the count clock is fX/23, and in the latter case the

count clock is selected by prescaler mode register 0 (PRM0). The capture operation is not performed until

the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse

width.

(11) STOP mode or main system clock stop mode setting

Except when TI00, TI01 input is selected, stop the timer operation before setting STOP mode or main system

clock stop mode; otherwise the timer may malfunction when the main system clock starts.

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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51

9.1 Functions of 8-Bit Timer/Event Counters 50, 51

8-bit timer/event counters 50, 51 (TM50, TM51) have the following two modes.

(1) Mode using 8-bit timer/event counters 50, 51 alone (discrete mode)

The timer operates as 8-bit timer/event counter 50 or 51.

It has the following functions.

<1> Interval timer

Interrupt requests are generated at the preset interval.

• Number of counts: 1 to 256

<2> External event counter

The number of pulses with high/low level widths of the signal input externally can be measured.

<3> Square-wave output

A square wave with an arbitrary frequency can be output.

• Cycle: (1 × 2 to 256 × 2) × Cycles of count clock

<4> PWM output

A pulse with an arbitrary duty ratio can be output.

• Cycle: Count clock × 256

• Duty ratio: Set value of compare register/256

(2) Mode using cascade connection (16-bit resolution: cascade connection mode)

The timer operates as a 16-bit timer/event counter by combining two 8-bit timer/event counters.

It has the following functions.

• Interval timer with 16-bit resolution

• External event counter with 16-bit resolution

• Square-wave output with 16-bit resolution

Figures 9-1 and 9-2 show block diagrams of 8-bit timer/event counters 50 and 51.

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Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 50

Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter 51

Notes 1. The respective combinations, TI50 input and TO50 output, and TI51 input and TO51 output, cannot be

used at the same time.

2. Timer output F/F

3. PWM output F/F

Output latch

(P72)

PM72

TO50/TI50/

P72

Note 1

Internal bus

8-bit timer compare

TI50/TO50/P72

Note 1

Match

Mask circuit

OVF

Clear

Selector

TCL502 TCL501 TCL500

Timer clock select

Internal bus

TCE50

TMC506 TMC504

LVS50 LVR50

TMC501

TOE50

Invert

level

8-bit timer mode control

INV

Selector INTTM50

Note 2

Note 3

Selector

8-bit timer

counter 50 (TM50)

Selector

Output latch

(P73)

PM73

TO51/TI51/

P73

Note 1

Internal bus

TI51/TO51/P73

Note 1

/2 Match

Mask circuit

OVF

Clear

TCL512 TCL511 TCL510

Timer clock select

Internal bus

TCE51

TMC516 TMC514

LVS51 LVR51

TMC511

TOE51

Invert

level

8-bit timer mode control

INV

Selector INTTM51

Selector

8-bit timer

compare register

51 (CR51)

8-bit timer

counter 51

(TM51)

Note 2

Note 3

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9.2 Configuration of 8-Bit Timer/Event Counters 50, 51

8-bit timer/event counters 50, 51 consist of the following hardware.

Table 9-1. Configuration of 8-Bit Timer/Event Counters 50, 51

Item Configuration

Timer counter 8-bit timer counter 5n (TM5n)

Timer input TI5n

Timer output TO5n

Control registers Timer clock select register 5n (TCL5n)

8-bit timer mode control register 5n (TMC5n)

Port mode register 7 (PM7)

Port 7 (P7)

(1) 8-bit timer counter 5n (TM5n: n = 0, 1)

TM5n is an 8-bit read-only register that counts the count pulses.

The counter is incremented in synchronization with the rising edge of the count clock.

When TM50 and TM51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit

memory manipulation instruction. However, since they are connected by an internal 8-bit bus, TM50 and TM51

are read separately twice in that order. Thus, take reading during the count change into consideration and

compare them by reading twice. When the count value is read during operation, the count clock input is

temporarily stoppedNote, and then the count value is read. In the following situations, count value is cleared to

00H.

<1> RESET input

<2> When TCE5n is cleared

<3> When TM5n and CR5n match in the clear & start mode entered on a match between TM5n and CR5n.

Note An error may occur in the count. Select a count clock with a high/low-level waveform longer than two cycles

of the CPU clock.

Caution In cascade connection mode, the count value is reset to 0000H when TCE50 of the lowest timer

is cleared.

(2) 8-bit timer compare register 5n (CR5n: n = 0, 1)

When CR5n is used as a compare register in other than PWM mode, the value set in CR5n is constantly compared

with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match.

In PWM mode, the TO5n pin goes to the active level by the overflow of TM5n. When the values of TM5n and

CR5n match, the TO5n pin goes to the inactive level.

It is possible to rewrite the value of CR5n within 00H to FFH during a count operation.

When TM50 and TM51 can be connected in cascade and used as a 16-bit timer, CR50 and CR51 operate as

a 16-bit compare register. This register compares the count value with the register value, and if the values match,

an interrupt request (INTTM50) is generated. The INTTM51 interrupt request is also generated at this time. Thus,

mask the INTTM51 interrupt request. CR5n is set by an 8-bit memory manipulation instruction. RESET input

makes CR5n undefined.

Caution In cascade connection mode, stop the timer operation before setting data.

Remark n = 0, 1

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9.3 Registers to Control 8-Bit Timer/Event Counters 50, 51

The following four types of registers are used to control 8-bit timer/event counters 50, 51.

•Timer clock select register 5n (TCL5n)

•8-bit timer mode control register 5n (TMC5n)

•Port mode register 7 (PM7)

•Port 7 (P7)

Remark n = 0, 1

(1) Timer clock select register 5n (TCL5n: n = 0, 1)

This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of TI50, TI51 input.

TCL5n is set by an 8-bit memory manipulation instruction.

RESET input clears TCL5n to 00H.

Figure 9-3. Format of Timer Clock Select Register 50 (TCL50)

Address: FF71H After reset: 00H R/W

Symbol 76543210

TCL50 00000TCL502 TCL501 TCL500

TCL502 TCL501 TCL500 Count clock selection

fX = 8.38 MHz fX = 12 MHzNote

0 0 0 TI50 falling edge −−

0 0 1 TI50 rising edge −−

010fX8.38 MHz 12 MHz

011fX/222.09 MHz 3 MHz

100fX/24523 kHz 750 kHz

101fX/26131 kHz 187 kHz

110fX/2832.7 kHz 46.8 kHz

111fX/210 8.18 kHz 11.7 kHz

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.

2. Be sure to clear bits 3 to 7 to 0.

Remarks 1. When cascade connection is used, only TCL50 is valid for count clock setting.

2. fX: Main system clock oscillation frequency

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Figure 9-4. Format of Timer Clock Select Register 51 (TCL51)

Address: FF79H After reset: 00H R/W

Symbol 76543210

TCL51 00000TCL512 TCL511 TCL510

TCL512 TCL511 TCL510 Count clock selection

fX = 8.38 MHz fX = 12 MHzNote

0 0 0 TI51 falling edge −−

0 0 1 TI51 rising edge −−

010fX/2 4.19 MHz 6 MHz

011fX/231.04 MHz 1.5 MHz

100fX/25261 kHz 375 kHz

101fX/2765.4 kHz 93.7 kHz

110fX/2916.3 kHz 23.4 kHz

111fX/211 4.09 kHz 5.85 kHz

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.

2. Be sure to clear bits 3 to 7 to 0.

Remarks 1. When cascade connection is used, only TCL50 is valid for count clock setting.

2. fX: Main system clock oscillation frequency

(2) 8-bit timer mode control register 5n (TMC5n: n = 0, 1)

TMC5n is a register that makes the following six settings.

<1> 8-bit timer counter 5n (TM5n) count operation control

<2> 8-bit timer counter 5n (TM5n) operating mode selection

<3> Discrete mode/cascade connection mode selection (TMC51 only)

<4> Timer output F/F (flip-flop) status setting

<5> Active level selection in timer F/F control or PWM (free-running) mode.

<6> Timer output control

TMC5n is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC5n to 00H.

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Figure 9-5. Format of 8-Bit Timer Mode Control Register 50 (TMC50)

Address: FF70H After reset: 00H R/W

Symbol <7> 6 5 4 <3> <2> 1 <0>

TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50

TCE50 TM50 count operation control

0 After clearing to 0, count operation disabled (prescaler disabled)

1 Count operation start

TMC506 TM50 operating mode selection

0 Clear and start mode by match between TM50 and CR50

1 PWM (free-running) mode

LVS50 LVR50 Timer output F/F status setting

0 0 No change

0 1 Timer output F/F reset (0)

1 0 Timer output F/F set (1)

1 1 Setting prohibited

TMC501 In other modes (TMC506 = 0) In PWM mode (TMC506 = 1)

Timer F/F control Active level selection

0 Inversion operation disabled Active high

1 Inversion operation enabled Active low

TOE50 Timer output control

0 Output disabled (port mode)

1 Output enabled

Remarks 1. In PWM mode, PWM output will be inactive because TCE50 = 0.

2. If LVS50 and LVR50 are read after data is set, 0 is read.

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Figure 9-6. Format of 8-Bit Timer Mode Control Register 51 (TMC51)

Address: FF78H After reset: 00H R/W

Symbol <7> 6 5 4 <3> <2> 1 <0>

TMC51 TCE51 TMC516 0 TMC514 LVS51 LVR51 TMC511 TOE51

TCE51 TM51 count operation control

0 After clearing to 0, count operation disabled (prescaler disabled)

1 Count operation start

TMC516 TM51 operating mode selection

0 Clear and start mode by match between TM51 and CR51

1 PWM (free-running) mode

TMC514 Discrete mode/cascade connection mode selection

0 Discrete mode

1 Cascade connection mode (TM50: Lower timer, TM51: Higher timer)

LVS51 LVR51 Timer output F/F status setting

0 0 No change

0 1 Timer output F/F reset (0)

1 0 Timer output F/F set (1)

1 1 Setting prohibited

TMC511 In other modes (TMC516 = 0) In PWM mode (TMC516 = 1)

Timer F/F control Active level selection

0 Inversion operation disabled Active high

1 Inversion operation enabled Active low

TOE51 Timer output control

0 Output disabled (port mode)

1 Output enabled

Remarks 1. In PWM mode, PWM output will be inactive because TCE51 = 0.

2. If LVS51 and LVR51 are read after data is set, 0 is read.

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(3) Port mode register 7 (PM7)

This register sets port 7 input/output in 1-bit units.

When using the P72/TO50/TI50 and P73/TI51/TO51 pins for timer output, clear PM72, PM73, and the output

latches of P72 and P73 to 0.

When using the P72/TO50/TI50 and P73/TI51/TO51 pins for timer input, set PM72 and PM73 to 1. At this time,

the output latches of P72 and P73 can be either 0 or 1.

PM7 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM7 to FFH.

Figure 9-7. Format of Port Mode Register 7 (PM7)

Address: FF27H After reset: FFH R/W

Symbol 7 6 5 4 3 2 1 0

PM7 1 1 PM75 PM74 PM73 PM72 PM71 PM70

PM7n P7n pin I/O mode selection (n = 0 to 5)

0 Output mode (output buffer on)

1 Input mode (output buffer off)

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9.4 Operation of 8-Bit Timer/Event Counters 50, 51

9.4.1 8-bit interval timer operation

The 8-bit timer/event counters operate as interval timers that generate interrupt requests repeatedly at intervals

of the count value preset to 8-bit timer compare register 5n (CR5n).

When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with

the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.

The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock select register 5n

(TCL5n).

[Setting]

<1> Set the registers.

•TCL5n: Select count clock.

•CR5n: Compare value

•TMC5n: Count operation stop, clear & start mode on match between TM5n and CR5n.

(TMC5n = 0000×××0B × = don’t care)

<2> After TCE5n = 1 is set, count operation starts.

<3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).

<4> INTTM5n is generated repeatedly at the same interval. Clear TCE5n to 0 to stop the count operation.

Remark n = 0, 1

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Figure 9-8. Interval Timer Operation Timing (1/3)

(a) Basic operation

Count clock

TM5n count value

CR5n

TCE5n

INTTM5n

TO5n

Start count Clear Clear

00H 01H N 00H 01H N 00H 01H N

NNNN

Interrupt acknowledged Interrupt acknowledged

Interval timeInterval time

Remarks 1. Interval time = (N + 1) × t

N = 00H to FFH

2. n = 0, 1

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Figure 9-8. Interval Timer Operation Timing (2/3)

(b) When CR5n = 00H

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n

Interval time

00H 00H 00H

00H 00H

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n

01H FEH FFH 00H FEH FFH 00H

FFHFFHFFH

Interval time

Interrupt

acknowledged

Interrupt acknowledged

Remark n = 0, 1

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Figure 9-8. Interval Timer Operation Timing (3/3)

(d) Operated by CR5n transition (M < N)

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n

00HN

M N FFH 00H M 00H

CR5n transition TM5n overflows since M < N

(e) Operated by CR5n transition (M > N)

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n

N − 1N

00H 01H N M − 1 M 00H 01H

CR5n transition

Remark n = 0, 1

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9.4.2 External event counter operation

The external event counter counts the number of external clock pulses to be input to TI5n using 8-bit timer counter

5n (TM5n).

TM5n is incremented each time the valid edge specified by timer clock select register 5n (TCL5n) is input. Either

the rising or falling edge can be selected.

When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0

and an interrupt request signal (INTTM5n) is generated.

Whenever the TM5n count value matches the value of CR5n, INTTM5n is generated.

[Setting]

<1> Set each register

•TCL5n: Edge selection of TI5n input

Falling edge of TI5n → TCL5n = 00H

Rising edge of TI5n → TCL5n = 01H

•CR5n: Compare value

•TMC5n: Count operation stop, clear & start mode on match between TM5n and CR5n, timer F/F inverted

operation disable, timer output disable

(TMC5n = 0000××00B, × = don’t care)

<2> When TCE5n = 1 is set, the number of pulses input from TI5n is counted.

<3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).

<4> Each time the values of TM5n and CR5n match, INTTM5n is generated.

Figure 9-9. External Event Counter Operation Timing (with Rising Edge Specified)

TI5n

TM5n count value

CR5n

INTTM5n

00H 01H 02H 03H 04H 05H N − 1 N 00H 01H 02H 03H

Remarks 1. N = 00H to FFH

2. n = 0, 1

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9.4.3 Square-wave output (8-bit resolution) operation

A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer

compare register 5n (CR5n).

The TO5n pin output status is reversed at intervals determined by the count value preset to CR5n by setting bit

0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected

frequency to be output (duty = 50%).

[Setting]

<1> Set each register

•Clear port latches (P72, P73)Note and port mode registers (PM72, PM73)Note to 0.

•TCL5n: Select count clock

•CR5n: Compare value

•TMC5n: Count operation stop, clear & start mode on match between TM5n and CR5n

LVS5n LVR5n Timer Output F/F Status Setting

1 0 High-level output

0 1 Low-level output

Timer output F/F reverse enable

Timer output enable → TOE5n = 1

(TMC5n = 00001011B or 00000111B)

<2> After TCE5n = 1 is set, the count operation starts.

<3> Timer output F/F is reversed by match between TM5n and CR5n. After INTTM5n is generated, TM5n is

cleared to 00H.

<4> Timer output F/F is reversed at the same interval and a square wave is output from TO5n.

The frequency is as follows.

•Frequency = fCNT/2 (N + 1)

(N = 00H to FFH, fCNT: Count clock)

Note 8-bit timer/event counter 50: P72, PM72

8-bit timer/event counter 51: P73, PM73

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Figure 9-10. Square-Wave Output Operation Timing

Count clock

TM5n count value

CR5n

TO5nNote

Count start

00H 01H 02H

N − 1N

00H 01H 02H

N − 1N

00H

Note The TO5n output initial value can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register

5n (TMC5n).

Remarks 1. N = 00H to FFH

2. n = 0, 1

9.4.4 8-bit PWM output operation

The 8-bit timer/event counter operates as PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register

5n (TMC5n) is set to 1.

The duty ratio pulse is determined by the value set to 8-bit timer compare register 5n (CR5n).

Set the active level width of the PWM pulse to CR5n. The active level can be selected with bit 1 (TMC5n1) of TMC5n.

The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock select register 5n (TCL5n).

PWM output enable/disable can be selected with bit 0 (TOE5n) of TMC5n.

•Cycle = Count clock × 256

Set value of compare register

•Duty ratio = 256

Caution CR5n can be rewritten in PWM mode only once per cycle.

Remark n = 0, 1

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(1) PWM output basic operation

[Setting]

<1> Set each register.

• Clear port latches (P72, P73)Note and port mode registers (PM72, PM73)Note to 0.

• TCL5n: Count clock selection

• CR5n: Compare value

• TMC5n: Count operation stop, PWM mode selection, timer output F/F not changed

TMC5n1 Active Level Selection

0 Active high

1 Active low

Timer output enabled

(TMC5n = 01000001B or 01000011B)

<2> When TCE5n = 1 is set, the count operation is started.

To stop the count operation, clear TCE5n to 0.

Note 8-bit timer/event counter 50: P72, PM72

8-bit timer/event counter 51: P73, PM73

[PWM output operation]

<1> PWM output (output from TO5n) outputs an inactive level after the count operation starts until an overflow

occurs.

<2> When an overflow occurs, the active level is output.

The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n).

<3> After CR5n matches the count value, PWM output outputs the inactive level again until an overflow occurs.

<4> Operations <2> and <3> are repeated until the count operation stops.

<5> When the count operation is stopped by setting TCE5n = 0, PWM output becomes the inactive level.

Remark n = 0, 1

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Figure 9-11. PWM Output Operation Timing

(a) Basic operation (active level = H)

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n

00H 01H FFH 00H 01H 02H

N + 1

FFH 00H 01H 02H

00H

Active level Active levelInactive level

(b) CR5n = 0

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n L

Inactive level Inactive level

01H00H FFH 00H 01H 02H

N + 1

FFH 00H 01H 02H

00H

N + 2

TM5n

Count clock

CR5n

TCE5n

INTTM5n

TO5n

01H00H FFH 00H 01H 02H

N + 1

FFH 00H 01H 02H

00H

FFH

N + 2

Inactive level Active level

Inactive level

Active level Inactive level

Remark n = 0, 1

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(2) Operated by CR5n transition

Figure 9-12. Timing of Operation by Change of CR5n

(a) CR5n value is changed from N to M when TM5n > CR5n

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n

CR5n transition (N → M)

N + 1 N + 2

FFH 00H 01H

M + 1 M + 2

FFH 00H 01H 02H

M + 1 M + 2

02H

(b) CR5n value is changed from N to M when TM5n < CR5n

Count clock

TM5n

CR5n

TCE5n

INTTM5n

TO5n

N + 1 N + 2

FFH 00H 01H

N + 1 N + 2

FFH 00H 01H 02H

02H

03H

M + 1 M + 2

CR5n transition (N → M)

Remark n = 0, 1

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9.4.5 Interval timer (16-bit) operations

When bit 4 (TMC514) of 8-bit timer mode control register 51 (TMC51) is set to 1, the 16-bit resolution timer/counter

mode is entered.

The 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals

of the count value preset to the 8-bit timer compare registers (CR50, CR51).

[Setting]

<1> Set each register

TCL50: Select count clock for TM50.

Cascade-connected TM51 need not be selected.

CR50, CR51: Compare value (each value can be set to 00H to FFH)

TMC50, TMC51: Select the clear & start mode entered on a match between TM50 and CR50 (TM51 and

CR51).

TM50 → TMC50 = 0000×××0B ×: don’t care

TM51 → TMC51 = 0001×××0B ×: don’t care

<2> When TMC51 is set to TCE51 = 1 and then TMC50 is set to TCE50 = 1, the count operation starts.

<3> When the values of TM50 and CR50 of the cascade-connected timer match, INTTM50 of TM50 is generated

(TM50 and TM51 are cleared to 00H).

<4> INTTM50 is generated repeatedly at the same interval.

Cautions 1. Stop the timer operation without fail before setting the compare registers (CR50, CR51).

2. INTTM51 of TM51 is generated when the TM51 count value matches CR51, even if cascade

connection is used. Be sure to mask TM51 to disable interrupts.

3. Set TCE50 and TCE51 in order of TM51 then TM50.

4. Count restart/stop can only be controlled by setting TCE50 of TM50 to 1/0.

Figure 9-13 shows an example of 16-bit resolution cascade connection mode timing.

Figure 9-13. 16-Bit Resolution Cascade Connection Mode

Count clock

TM50

TM51

CR50

CR51

TCE50

TCE51

INTTM50

TO50

Operation enable

Count start

Interval time

00H 01H

N + 1 FFH 00H FFH 00H FFH 00H 01H

00H 01H

00H

00H 01H 02H M − 1

00H

Interrupt request

generation

Level reverse

Counter clear

Operation

stop

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9.5 Program List

Caution The following sample program is shown as an example to describe the operation of semiconductor

products and their applications. Therefore, when applying the following information to your

devices, design the devices after performing evaluation under your own responsibility.

9.5.1 Interval timer (8-bit)

/*************************************************************************************/

/* */

/* Timer 50 operation sample */

/* Interval timer setting example (cycle change by interrupt servicing) */

/* data[0]: Data set flag (value changed when other than 00) */

/* data[1]: Set data */

/* */

/*************************************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#pragma interrupt INTTM50 intervalint rb2

unsigned char data[2]; /* Data area */

void main(void)

{

PCC = 0x0; /* Set high-speed operation mode */

data[0] = 0; /* Clear data area */

data[1] = 0;

/* Set port */

P7 = 0b11111011; /* When using TO50 */

PM7.2 = 0; /* Set P72 to output */

/* Set interrupt */

TMMK50 = 0; /* Clear INTTM50 interrupt mask */

/* Set timer 50 */

TMC50 = 0b00000111; /* Clear & start mode, initial value L */

TCL50 = 0b00000101; /* Both rising and falling edges */

/* Count clock is fx/2^6 */

CR50 = 131; /* Set interval to 1 ms as initial value */

TCE50 = 1; /* Timer start */

EI();

while(1); /* Dummy loop */

}

/* INTTM50 interrupt function */

void intervalint()

{

if(data[0] != 0)

{

CR50 = data[1]; /* Set new set value */

data[0] = 0; /* Clear request flag */

}

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9.5.2 External event counter

/***************************************************************/

/* */

/* Timer 50 operation sample */

/* Event counter setting example */

/* data: Count up flag */

/* */

/***************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#pragma interrupt INTTM50 intervalint rb2

unsigned char data; /* Data area */

void main(void)

{

PCC = 0x0; /* Set high-speed operation mode */

data = 0; /* Clear data area */

/* Set port */

PM7.2 = 1; /* Set P72 to input */

/* Set interrupt */

TMMK50 = 0; /* Clear INTTM50 interrupt mask */

/* Set timer 50 */

TMC50 = 0b00000000; /* Clear & start mode */

TCL50 = 0b00000001; /* Specify rising edge of TI50 */

CR50 = 0x10; /* Set N = 16 as initial value */

TCE50 = 1; /* Timer start */

EI();

/*************************************************************/

/* */

/* Describe the processing to be executed */

/* */

/*************************************************************/

while(data == 0); /* Wait for count up */

/*************************************************************/

/* */

/* Describe the processing after count up below */

/* */

/*************************************************************/

}

/* INTTM50 interrupt function */

void intervalint()

{

data = 0xff; /* Set count up flag */

TCE50 = 0; /* Timer stop */

}

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9.5.3 Interval timer (16-bit)

/***************************************************************/

/* */

/* Timer 5 operation sample */

/* Cascade connection setting example */

/* */

/***************************************************************/

#pragma sfr

#pragma EI

#pragma DI

#define intervalTM5 130 /* Cycle data to be set to CR */

#pragma interrupt INTTM50 ppgint rb2

unsigned char ppgdata[2]; /* Data area to be set to timer 5 */

void main(void)

{

int interval;

interval = intervalTM5;

PCC = 0x0; /* Select high-speed operation mode */

ppgdata[0] = 0; /* Clear CR50 data */

ppgdata[1] = 0; /* Clear CR51 data */

/* Set port */

P7 = 0b11111011; /* Clear P72 */

PM7.2 = 0; /* Set P72 to output */

/* Set interrupt */

TMMK50 = 0; /* Clear INTTM50 interrupt mask */

TMMK51 = 1; /* Set INTTM51 interrupt mask */

/* Set timer 5 */

TCL50 = 0b00000101; /* Count clock is fx/2^6 */

CR50 = interval & 0xff; /* Set lower compare register to CR50 */

CR51 = interval >> 8; /* Set higher compare register to CR51 */

TMC50 = 0b00000111; /* Inverted on match, initial value L */

TMC51 = 0b00010000; /* Cascade mode */

TCE51 = 1;

TCE50 = 1; /* Timer starts */

EI();

while(1);

}

/* Timer 5 interrupt function */

void ppgint()

{

unsigned int work;

work = ppgdata[0]+ppgdata[1]*0x100;

if (work != 0)

{

TCE50 =0;

CR51 = work >> 8;

CR50 = work & 0xff;

ppgdata[0] = 0;

ppgdata[1] = 0;

if (work != 0xffff)

{

TCE50 = 1; /* Timer resumes */

}

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User’s Manual U14046EJ3V0UD

9.6 Cautions Related to 8-Bit Timer/Event Counters 50, 51

(1) Timer start errors

An error of up to one clock may occur in the time required for a match signal to be generated after timer start.

This is because 8-bit timer counter 5n (TM5n) is started asynchronously to the count pulse.

Figure 9-14. Start Timing of 8-Bit Timer Counter 5n (TM5n)

Count pulse

TM5n count 00H 01H 02H 03H 04H

Timer start

(2) Setting STOP mode or main system clock stop mode

Except when TI5n input is selected, always set TCE5n = 0 before setting the STOP mode or main system clock

stop mode.

The timer may malfunction when the main system clock starts oscillating.

(3) TM5n (n = 0, 1) reading during timer operation

When reading TM5n during operation, the count clock stops temporarily, so select a count clock with a high/low-

level waveform longer than two cycles of the CPU clock. For example, in the case where the CPU clock (fCPU)

is fX, when the selected count clock is fX/4 or below, it can be read.

Remark n = 0, 1

242 User’s Manual U14046EJ3V0UD

CHAPTER 10 WATCH TIMER

10.1 Watch Timer Functions

The watch timer has the following functions.

(1) Watch timer

When the main system clock or subsystem clock is used, interrupt requests (INTWT) are generated at 214/fW

second intervals.

(2) Interval timer

Interrupt requests (INTWTI) are generated at the preset time interval.

For the interval time, see Table 10-2.

The watch timer and the interval timer can be used simultaneously.

Figure 10-1 shows the watch timer block diagram.

Figure 10-1. Watch Timer Block Diagram

Remark fW: Watch timer clock frequency (fX/27 or fXT)

fX: Main system clock oscillation frequency

fXT: Subsystem clock oscillation frequency

Clear

9-bit prescaler

Clear

5-bit counter INTWT

INTWTI

WTM7 WTM6 WTM5 WTM4 WTM1 WTM0

Watch timer operation

mode register (WTM)

Internal bus

Selector

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10.2 Watch Timer Configuration

The watch timer consists of the following hardware.

Table 10-1. Watch Timer Configuration

Item Configuration

Counter 5 bits × 1

Prescaler 9 bits × 1

Control register Watch timer operation mode register (WTM)

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10.3 Register to Control Watch Timer

The watch timer is controlled by the watch timer operation mode register (WTM).

• Watch timer operation mode register (WTM)

This register sets the watch timer count clock, enables/disables operation, sets the prescaler interval time, and

controls the 5-bit counter operation.

WTM is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WTM to 00H.

Figure 10-2. Format of Watch Timer Operation Mode Register (WTM)

Address: FF41H After reset: 00H R/W

Symbol 765432<1><0>

WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0

WTM7 Watch timer count clock selection

0fX/27 (65.4 kHz: fX = 8.38 MHz, 93.7 kHz: fX = 12 MHzNote)

1fXT (32.768 kHz: fXT = 32.768 kHz)

WTM6 WTM5 WTM4 Prescaler interval time selection

0002

4/fW

0012

5/fW

0102

6/fW

0112

7/fW

1002

8/fW

1012

9/fW

Other than above Setting prohibited

WTM1 5-bit counter operation control

0 Clear after operation stop

1 Start

WTM0 Watch timer operation enable

0 Operation stopped (both prescaler and timer cleared)

1 Operation enabled

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Caution Do not change the count clock and interval time (by using bits 4 to 7 (WTM4 to WTM7) of WTM)

while the watch timer is operating.

Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT)

2. fX: Main system clock oscillation frequency

3. fXT: Subsystem clock oscillation frequency

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10.4 Watch Timer Operations

10.4.1 Watch timer operation

The watch timer generates an interrupt request (INTWT) at specific time intervals (214/fW seconds) by using the

main system clock or subsystem clock. The interrupt request is generated at the following time intervals:

•If main system clock (8.38 MHz) is selected: 0.25 seconds

•If subsystem clock (32.768 kHz) is selected: 0.5 seconds

When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count

operation starts, and when these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops.

When the interval timer is simultaneously operated, a zero-second start can be achieved for the watch timer by

setting WTM1 to 1 after clearing it to 0. In this case, however, the 9-bit prescaler is not cleared. Therefore, an error

up to 29/fW seconds occurs in the first overflow (INTWT) after the zero-second start.

Remark fW: Watch timer clock frequency (fX/27 or fXT)

10.4.2 Interval timer operation

The watch timer operates as interval timer that generates interrupt requests (INTWTI) repeatedly at an interval

of the preset count value.

The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register

(WTM).

Table 10-2. Interval Timer Interval Time

WTM6 WTM5 WTM4 Interval When Operated at When Operated at When Operated at When Operated at

Time fX = 12 MHzNote fX = 8.38 MHz fX = 4.19 MHz fXT = 32.768 kHz

0002

4/fW170

s 244

s 488

0012

5/fW341

s 488

s 977

s 976

0102

6/fW682

s 977

s 1.95 ms 1.95 ms

0112

7/fW1.36 ms 1.95 ms 3.91 ms 3.90 ms

1002

8/fW2.73 ms 3.91 ms 7.82 ms 7.81 ms

1012

9/fW5.46 ms 7.82 ms 15.6 ms 15.6 ms

Other than above Setting prohibited

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Remark fW: Watch timer clock frequency (fX/27 or fXT)

fX: Main system clock oscillation frequency

fXT: Subsystem clock oscillation frequency

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Figure 10-3. Operation Timing of Watch Timer/Interval Timer

Caution If the watch timer and 5-bit counter are enabled by the watch timer mode control register (WTM)

(by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the time from this setting to the occurrence

of the first interrupt request (INTWT) is not exactly the value set by bit 3 (WTM3) of WTM. This

is because the 5-bit counter is late by one output cycle of the 9-bit prescaler in starting counting.

The second INTWT signal and those that follow are generated exactly at the set time.

Remark fW: Watch timer clock frequency (fX/27 or fXT)

n: The number of interval timer operations

Figures in parentheses are for operation with fW = 32.768 kHz.

Start Overflow Overflow

5-bit counter

Count clock

Watch timer

interrupt INTWT

Interval timer

interrupt INTWTI

Interrupt time of watch timer

(0.5 s)

Interval time

(T)

Interrupt time of watch timer

(0.5 s)

n x T n x T

247User’s Manual U14046EJ3V0UD

CHAPTER 11 WATCHDOG TIMER

11.1 Watchdog Timer Functions

The watchdog timer has the following functions.

(1) Watchdog timer

The watchdog timer detects a program loop. Upon detection of a program loop, a non-maskable interrupt request

or RESET can be generated.

For the loop detection time, see Table 11-2.

(2) Interval timer

Interrupt requests are generated at the preset time intervals.

For the interval time, see Table 11-3.

Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode

Figure 11-1 shows a block diagram of the watchdog timer.

Figure 11-1. Watchdog Timer Block Diagram

WDT mode signal

Watchdog timer clock

select register (WDCS)

Watchdog timer mode

RUN

INTWDT

RESET

WDCS2 WDCS1 WDCS0

RUN

WDTM4 WDTM3

Clock

input

controller

Divider

circuit

Divided

clock

selector Output

controller

Division mode

selector

Internal bus

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11.2 Watchdog Timer Configuration

The watchdog timer consists of the following hardware.

Table 11-1. Watchdog Timer Configuration

Item Configuration

Control registers Watchdog timer clock select register (WDCS)

Watchdog timer mode register (WDTM)

11.3 Registers to Control Watchdog Timer

The following two registers are used to control the watchdog timer.

•Watchdog timer clock select register (WDCS)

•Watchdog timer mode register (WDTM)

(1) Watchdog timer clock select register (WDCS)

This register sets the overflow time of the watchdog timer and the interval timer.

WDCS is set by an 8-bit memory manipulation instruction.

RESET input clears WDCS to 00H.

Figure 11-2. Format of Watchdog Timer Clock Select Register (WDCS)

Address: FF42H After reset: 00H R/W

Symbol 76543210

WDCS 00000WDCS2 WDCS1 WDCS0

WDCS2 WDCS1 WDCS0 Overflow time of watchdog timer/interval timer

fX = 8.38 MHz fX = 12 MHzNote

0002

12/fX488

s 341

0012

13/fX977

s 682

0102

14/fX1.95 ms 1.36 ms

0112

15/fX3.91 ms 2.73 ms

1002

16/fX7.82 ms 5.46 ms

1012

17/fX15.6 ms 10.9 ms

1102

18/fX31.2 ms 21.8 ms

1112

20/fX125 ms 87.3 ms

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Remark fX: Main system clock oscillation frequency

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(2) Watchdog timer mode register (WDTM)

This register sets the watchdog timer operating mode and enables/disables counting.

WDTM is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WDTM to 00H.

Figure 11-3. Format of Watchdog Timer Mode Register (WDTM)

Address: FFF9H After reset: 00H R/W

Symbol <7> 6543210

WDTM RUN 0 0 WDTM4 WDTM3 0 0 0

RUN Watchdog timer operation mode selectionNote 1

0 Count stop

1 Counter is cleared and counting starts

WDTM4 WDTM3 Watchdog timer operation mode selectionNote 2

0×Interval timer modeNote 3

(Maskable interrupt request occurs upon generation of overflow)

1 0 Watchdog timer mode 1

(Non-maskable interrupt request occurs upon generation of overflow)

1 1 Watchdog timer mode 2

(Reset operation is activated upon generation of overflow)

Notes 1. Once set to 1, RUN cannot be cleared to 0 by software.

Thus, once counting starts, it can only be stopped by RESET input.

2. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.

3. The watchdog timer starts operation as an interval timer when RUN is set to 1.

Caution When RUN is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to

28/fX seconds shorter than the time set by the watchdog timer clock select register (WDCS).

Remark ×: Don’t care

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11.4 Watchdog Timer Operations

11.4.1 Watchdog timer operation

When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to

detect a program loop.

The loop detection time interval is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select

set RUN to 1 within the set loop time interval. The watchdog timer can be cleared and counting is started by setting

RUN to 1.

If RUN is not set to 1 and the loop detection time is exceeded, system reset or a non-maskable interrupt request

is generated according to the value of WDTM bit 3 (WDTM3).

The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1

before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.

Cautions 1. The actual loop detection time may be shorter than the set time by up to 28/fX seconds.

2. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation

is stopped.

Table 11-2. Watchdog Timer Loop Detection Time

Loop Detection Time When Operated at When Operated at

fX = 8.38 MHz fX = 12 MHzNote

212/fX488

s 341

213/fX977

s 682

214/fX1.95 ms 1.36 ms

215/fX3.91 ms 2.73 ms

216/fX7.82 ms 5.46 ms

217/fX15.6 ms 10.9 ms

218/fX31.2 ms 21.8 ms

220/fX125 ms 87.3 ms

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Remark fX: Main system clock oscillation frequency

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11.4.2 Interval timer operation

The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the

preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is cleared to 0.

The interval time of the interval timer is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock

select register (WDCS). When bit 7 (RUN) of WDTM is set to 1, the watchdog timer operates as an interval timer.

When the watchdog timer operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification

flag (WDTPR) are validated and the maskable interrupt request (INTWDT) can be generated. Among the maskable

interrupts, INTWDT has the highest priority at default.

The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set RUN to 1 before

the STOP mode is set, clear the interval timer and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (this selects the watchdog timer mode), the interval

timer mode is not set unless RESET is input.

2. The interval time just after setting WDTM may be shorter than the set time by up to 28/fX

seconds.

3. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation

is stopped.

Table 11-3. Interval Timer Interval Time

Interval Time When Operated at When Operated at

fX = 8.38 MHz fX = 12 MHzNote

212/fX488

s 341

213/fX977

s 682

214/fX1.95 ms 1.36 ms

215/fX3.91 ms 2.73 ms

216/fX7.82 ms 5.46 ms

217/fX15.6 ms 10.9 ms

218/fX31.2 ms 21.8 ms

220/fX125 ms 87.3 ms

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Remark fX: Main system clock oscillation frequency

252 User’s Manual U14046EJ3V0UD

CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER

12.1 Clock Output/Buzzer Output Controller Functions

Clock output is used for carrier output during remote controlled transmission and clock output for supply to

peripheral ICs. The clock selected by the clock output select register (CKS) is output.

In addition, buzzer output is used for square-wave output of the buzzer frequency selected by CKS.

Figure 12-1 shows the block diagram of the clock output/buzzer output controller.

Figure 12-1. Block Diagram of Clock Output/Buzzer Output Controller

to f

BZOE BCS1 BCS0 CLOE

CLOE

BZOE

PCL/P74

BUZ/P75

BCS0, BCS1

Clock

controller

Prescaler

Selector

Internal bus

CCS3

Clock output select register (CKS)

CCS2 CCS1 CCS0

Output latch

(P75) PM75

Output latch

(P74) PM74

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12.2 Configuration of Clock Output/Buzzer Output Controller

The clock output/buzzer output controller consists of the following hardware.

Table 12-1. Configuration of Clock Output/Buzzer Output Controller

Item Configuration

Control registers Clock output select register (CKS)

Port mode register (PM7)

Port 7 (P7)

12.3 Register to Control Clock Output/Buzzer Output Controller

The following three registers are used to control the clock output/buzzer output controller.

•Clock output select register (CKS)

•Port mode register (PM7)

•Port 7 (P7)

(1) Clock output select register (CKS)

This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and

sets the output clock.

CKS is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CKS to 00H.

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Figure 12-2. Format of Clock Output Select Register (CKS)

Address: FF40H After reset: 00H R/W

Symbol <7> 6 5 <4> 3210

CKS BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0

BZOE BUZ output enable/disable specification

0 Stop clock divider operation. BUZ fixed to low level.

1 Enable clock divider operation. BUZ output enabled.

BCS1 BCS0 BUZ output clock selection

fX = 8.38 MHz fX = 12 MHzNote

00fX/210 8.18 kHz 11.7 kHz

01fX/211 4.09 kHz 5.85 kHz

10fX/212 2.04 kHz 2.92 kHz

11fX/213 1.02 kHz 1.46 kHz

CLOE PCL output enable/disable specification

0 Stop clock divider operation. PCL fixed to low level.

1 Enable clock divider operation. PCL output enabled.

CCS3 CCS2 CCS1 CCS0 PCL output clock selection

fX = 8.38 MHz fX = 12 MHzNote

0000fX8.38 MHz 12 MHz

0001fX/2 4.19 MHz 6 MHz

0010fX/222.09 MHz 3 MHz

0011fX/231.04 MHz 1.5 MHz

0100fX/24523 kHz 750 kHz

0101fX/25261 kHz 375 kHz

0110fX/26130 kHz 187 kHz

0111fX/2765.4 kHz 93.7 kHz

1000fXT (32.768 kHz)

Other than above Setting prohibited

Note Expanded-specification products of

PD780024A, 780034A Subseries only.

Remarks 1. fX: Main system clock oscillation frequency

2. fXT: Subsystem clock oscillation frequency

3. Figures in parentheses are for operation with fXT = 32.768 kHz.

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(2) Port mode register (PM7)

This register sets port 7 input/output in 1-bit units.

When using the P74/PCL pin for clock output and the P75/BUZ pin for buzzer output, clear PM74, PM75 and

the output latches of P74 and P75 to 0.

PM7 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM7 to FFH.

Figure 12-3. Format of Port Mode Register 7 (PM7)

Address: FF27H After reset: FFH R/W

Symbol 7 6 5 4 3 2 1 0

PM7 1 1 PM75 PM74 PM73 PM72 PM71 PM70

PM7n P7n pin I/O mode selection (n = 0 to 5)

0 Output mode (output buffer on)

1 Input mode (output buffer off)

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12.4 Operation of Clock Output/Buzzer Output Controller

12.4.1 Operation as clock output

The clock pulse is output using the following procedure.

<1> Select the clock pulse output frequency using bits 0 to 3 (CCS0 to CCS3) of the clock output select register

(CKS) (clock pulse output in disabled state).

<2> Set bit 4 (CLOE) of CKS to 1, and enable clock output.

Remark The clock output controller is designed not to output pulses with a small width during output enable/

disable switching of the clock output. As shown in Figure 12-4, be sure to start output from the low period

of the clock (marked with * in the figure). When stopping output, do so after securing the high level of

the clock.

Figure 12-4. Remote Control Output Application Example

CLOE

Clock output

12.4.2 Operation as buzzer output

The buzzer frequency is output using the following procedure.

<1> Select the buzzer output frequency using bits 5 and 6 (BCS0, BCS1) of the clock output select register (CKS)

(buzzer output in disabled state).

<2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output.

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CHAPTER 13 8-BIT A/D CONVERTER (

PD780024A, 780024AY SUBSERIES)

13.1 A/D Converter Functions

A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to

8 analog input channels (ANI0 to ANI7).

(1) Hardware start

Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can be

specified).

(2) Software start

Conversion is started by setting A/D converter mode register 0 (ADM0).

Select one channel for analog input from ANI0 to ANI7 to perform A/D conversion. In the case of hardware start,

A/D conversion stops when an A/D conversion operation ends and an interrupt request (INTAD0) is generated. In

the case of software start, A/D conversion is repeated. Each time an A/D conversion operation ends, an interrupt

request (INTAD0) is generated.

Caution Although the

PD78F0034A, 78F0034B, 78F0034AY, and 78F0034BY incorporate a 10-bit A/D

converter, this converter can be operated as an 8-bit A/D converter by using the device file

DF780024.

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Figure 13-1. 8-Bit A/D Converter Block Diagram

Note The valid edge of external interrupt is specified by bit 3 of the EGP and EGN registers (see Figure 19-5

Format of External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge

Enable Register (EGN)).

ANI0/P10

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

Sample & hold circuit

Voltage comparator

Successive

approximation

Controller

Edge

detector

ADTRG/INTP3/P03

A/D conversion result

REF

INTAD0

INTP3

Trigger enable

A/D converter

mode register 0 (ADM0)

Analog input channel

specification register 0 (ADS0)

Internal bus

ADS02 ADS01 ADS00

ADSC0

TRG0 FR02 FR01 FR00

EGA01 EGA00

Selector

Tap selector

Edge

detector

Note

Series resistor string

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13.2 A/D Converter Configuration

The A/D converter consists of the following hardware.

Table 13-1. A/D Converter Configuration

Item Configuration

Analog input 8 channels (ANI0 to ANI7)

Hardware trigger input 1 (ADTRG)

Registers Successive approximation register (SAR)

A/D conversion result register 0 (ADCR0)

Control registers A/D converter mode register 0 (ADM0)

Analog input channel specification register 0 (ADS0)

(1) Successive approximation register (SAR)

This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from

the series resistor string, and holds the result from the most significant bit (MSB).

When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to

A/D conversion result register 0 (ADCR0).

(2) A/D conversion result register 0 (ADCR0)

The ADCR0 is an 8-bit register that stores the A/D conversion result. Each time A/D conversion ends, the

conversion result is loaded from the successive approximation register.

ADCR0 is read by an 8-bit memory manipulation instruction.

RESET input clears ADCR0 to 00H.

Caution When writing is performed to A/D converter mode register 0 (ADM0) and analog input channel

specification register 0 (ADS0), the contents of ADCR0 may become undefined. Read the

conversion result following conversion completion before writing to ADM0, ADS0. Using a

timing other than the above may cause an incorrect conversion result to be read.

(3) Sample & hold circuit

The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D

conversion is started and holds the sampled analog input voltage value during A/D conversion.

(4) Voltage comparator

The voltage comparator compares the sampled analog input voltage to the series resistor string output voltage.

(5) Series resistor string

The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared to

the analog input.

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(6) ANI0 to ANI7 pins

These are eight analog input pins to input analog signals to undergo A/D conversion to the A/D converter. ANI0

to ANI7 are alternate-function pins that can also be used for digital input.

Cautions 1. Use ANI0 to ANI7 input voltages within the specification range. If a voltage higher than

AVREF or lower than AVSS is applied (even if within the absolute maximum rating range), the

conversion value of that channel will be undefined and the conversion values of other

channels may also be affected.

2. Analog input (ANI0 to ANI7) pins are alternate function pins that can also be used as input

port (P10 to P17) pins. When A/D conversion is performed by selecting any one of ANI0

to ANI7, do not access port 1 during conversion. It may cause the lower conversion

resolution.

3. When a digital pulse is applied to a pin adjacent to the pin in the process of A/D conversion,

A/D conversion values may not be obtained as expected due to coupling noise. Thus, do

not apply any pulse to a pin adjacent to the pin in the process of A/D conversion.

(7) AVREF pin

This pin inputs the A/D converter reference voltage.

It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF and

AVSS.

Caution A series resistor string of several 10 kΩ is connected between the AVREF pin and AVSS pin.

Therefore, when the output impedance of the reference voltage is too high, it seems as if the

AVREF pin and the series resistor string are connected in series. This may cause a greater

reference voltage error.

(8) AVSS pin

This is the ground potential pin of the A/D converter. Always keep it at the same potential as the VSS0 or VSS1

pin even when not using the A/D converter.

(9) AVDD pin

This is the A/D converter analog power supply pin. Always keep it at the same potential as the VDD0 or VDD1 pin

even when not using the A/D converter.

(10) ADTRG pin

This pin is a pin used to start the A/D converter by hardware.

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13.3 Registers to Control A/D Converter

The following 2 types of registers are used to control the A/D converter.

•A/D converter mode register 0 (ADM0)

•Analog input channel specification register 0 (ADS0)

(1) A/D converter mode register 0 (ADM0)

This register sets the conversion time for analog input to be A/D converted, conversion start/stop, and external

trigger.

ADM0 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ADM0 to 00H.

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Figure 13-2. Format of A/D Converter Mode Register 0 (ADM0)

Address: FF80H After reset: 00H R/W

Symbol <7> <6> 543210

ADM0 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 0

ADCS0 A/D conversion operation control

0 Stop conversion operation.

1 Enable conversion operation.

TRG0 Software start/hardware start selection

0 Software start

1 Hardware start

FR02 FR01 FR00 Conversion time selectionNote 1

fX = 8.38 MHz fX = 12 MHzNote 2

0 0 0 144/fX17.1

s 12.0

0 0 1 120/fX14.3

s 10.0

sNote 4

0 1 0 96/fX11.4

sNote 3 8.0

sNote 4

1 0 0 72/fX8.5

sNote 3 6.0

sNote 4

1 0 1 60/fX7.1

sNote 3 5.0

sNote 4

1 1 0 48/fX5.7

sNote 3 4.0

sNote 4

Other than above Setting prohibited

EGA01 EGA00 External trigger signal, edge specification

0 0 No edge detection

0 1 Falling edge detection

1 0 Rising edge detection

1 1 Both falling and rising edge detection

Notes 1. Set the A/D conversion time as follows.

• When operated at fX = 12 MHz (VDD = 4.5 to 5.5 V): 12

s or more

• When operated at fX = 8.38 MHz (VDD = 4.0 to 5.5 V): 14

s or more

2. Expanded-specification products of

PD780024A Subseries only.

3. Setting is prohibited because the A/D conversion time is less than 14

4. Setting is prohibited because the A/D conversion time is less than 12

Caution When rewriting FR00 to FR02 to other than the same data, stop A/D conversion operations

once prior to performing rewrite.

Remark fX: Main system clock oscillation frequency

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(2) Analog input channel specification register 0 (ADS0)

This register specifies the analog voltage input port for A/D conversion.

ADS0 is set by an 8-bit memory manipulation instruction.

RESET input clears ADS0 to 00H.

Figure 13-3. Format of Analog Input Channel Specification Register 0 (ADS0)

Address: FF81H After reset: 00H R/W

Symbol 76543210

ADS0 00000ADS02 ADS01 ADS00

ADS02 ADS01 ADS00 Analog input channel specification

0 0 0 ANI0

0 0 1 ANI1

0 1 0 ANI2

0 1 1 ANI3

1 0 0 ANI4

1 0 1 ANI5

1 1 0 ANI6

1 1 1 ANI7

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13.4 A/D Converter Operations

13.4.1 Basic operations of A/D converter

<1> Select one channel for A/D conversion with analog input channel specification register 0 (ADS0).

<2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.

<3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and

the input analog voltage is held until the A/D conversion operation is ended.

<4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to

(1/2) AVREF by the tap selector.

<5> The voltage difference between the series resistor string voltage tap and analog input is compared by the

voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set. If the analog

input is smaller than (1/2) AVREF, the MSB is reset.

<6> Next, bit 6 of SAR is automatically set, and the operation proceeds to the next comparison. The series resistor

string voltage tap is selected according to the preset value of bit 7, as described below.

•Bit 7 = 1: (3/4) AVREF

•Bit 7 = 0: (1/4) AVREF

The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as follows.

•Analog input voltage ≥ Voltage tap: Bit 6 = 1

•Analog input voltage < Voltage tap: Bit 6 = 0

<7> Comparison is continued in this way up to bit 0 of SAR.

<8> Upon completion of the comparison of 8 bits, an effective digital result value remains in SAR, and the result

value is transferred to and latched in A/D conversion result register 0 (ADCR0).

At the same time, the A/D conversion end interrupt request (INTAD0) can also be generated.

Cautions 1. The first A/D conversion value immediately after A/D conversion has been started may not

satisfy the rated value. Take measures such as polling the A/D conversion end interrupt

request (INTAD0) and removing the first conversion results.

2. The A/D converter stops operation in standby mode.

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Figure 13-4. Basic Operation of 8-Bit A/D Converter

Sampling time

Setting ADCS0 to 1, external trigger,

or overwriting ADS0

A/D conversion start delay time

Sampling A/D conversion

Undefined 80H

C0H

40H

Conversion

result

Conversion

result

A/D converter

operation

SAR

ADCR0

INTAD0

ADCS0

Conversion time

A/D conversion operations are performed continuously until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0)

is reset (0) by software.

RESET input clears A/D conversion result register 0 (ADCR0) to 00H.

Confirm the conversion results by referring to the A/D conversion end interrupt request flag (ADIF0).

The sampling time of the A/D converter varies depending on the values set in A/D converter mode register 0 (ADM0).

There is a delay time from when the A/D converter is enabled for operation until sampling is actually performed.

For the sets in which a strict A/D conversion time is required, note the contents described in Table 13-2.

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Table 13-2. Sampling Time and A/D Conversion Start Delay Time of A/D Converter

FR02 FR01 FR00 Conversion TimeNote 1 Sampling Time A/D Conversion Start Delay Time

MIN. MAX.

0 0 0 144/fX20/fX0.5/fCPU + 6/fX0.5/fCPU + 8/fX

0 0 1 120/fX16/fX

0 1 0 96/fX12/fX

1 0 0 72/fX10/fX0.5/fCPU + 3/fX0.5/fCPU + 4/fX

1 0 1 60/fX8/fX

1 1 0 48/fX6/fX

Other than above Setting prohibited −−−

Notes 1. Set the A/D conversion time as follows.

• When operated at fX = 12 MHzNote 2 (VDD = 4.5 to 5.5 V): 12

s or more

• When operated at fX = 8.38 MHz (VDD = 4.0 to 5.5 V): 14

s or more

2. Expanded-specification products of

PD780024A Subseries only.

Remark fX: Main system clock oscillation frequency

fCPU: CPU clock frequency

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13.4.2 Input voltage and conversion results

The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical

A/D conversion result (stored in A/D conversion result register 0 (ADCR0)) is shown by the following expression.

ADCR0 = INT ( VIN × 256 + 0.5)

AVREF

(ADCR0 – 0.5) × AVREF ≤ VIN < (ADCR0 + 0.5) × AVREF

256 256

where, INT( ): Function which returns integer part of value in parentheses

VIN: Analog input voltage

AVREF:AVREF pin voltage

ADCR0: A/D conversion result register 0 (ADCR0) value

Figure 13-5 shows the relationship between the analog input voltage and the A/D conversion result.

Figure 13-5. Relationship Between Analog Input Voltage and A/D Conversion Result

255

254

253

A/D conversion result

(ADCR0)

512

256

512

256

512

256

507

512

254

256

509

512

255

256

511

512

Input voltage/AV

REF

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13.4.3 A/D converter operation mode

Select one analog input channel from among ANI0 to ANI7 using analog input channel specification register 0

(ADS0) to start A/D conversion.

A/D conversion can be started in either of the following two ways.

•Hardware start: Conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges

enabled).

•Software start: Conversion is started by setting A/D converter mode register 0 (ADM0).

When A/D conversion is complete, the interrupt request signal (INTAD0) is generated.

(1) A/D conversion by hardware start

When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 1, the A/D conversion

standby state is set. When the external trigger signal (ADTRG) is input, A/D conversion of the voltage applied

to the analog input pin specified by analog input channel specification register 0 (ADS0) starts.

Upon the end of A/D conversion, the conversion result is stored in A/D conversion result register 0 (ADCR0),

and the interrupt request signal (INTAD0) is generated. After one A/D conversion operation is started and

finished, the next conversion operation is not started until a new external trigger signal is input.

If ADS0 is rewritten during A/D conversion, the converter suspends A/D conversion and waits for a new external

trigger signal to be input. When the external trigger input signal is reinput, A/D conversion is carried out from

the beginning. If ADS0 is rewritten during A/D conversion standby, A/D conversion starts when the following

external trigger input signal is input.

If 1 is written to ADCS0 again during A/D conversion, the A/D conversion in progress is discontinued and a new

A/D conversion is started when the next external trigger input signal is input.

If 0 is written to ADCS0 during A/D conversion, the A/D conversion operation stops immediately.

Caution When P03/INTP3/ADTRG is used as the external trigger input (ADTRG), specify the valid edge

using bits 1, 2 (EGA00, EGA01) of A/D converter mode register 0 (ADM0) and set the interrupt

mask flag (PMK3) to 1.

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Figure 13-6. A/D Conversion by Hardware Start (When Falling Edge Is Specified)

Remarks 1. n = 0, 1, ......, 7

2. m = 0, 1, ......, 7

A/D conversion

ADCR0

ADTRG

INTAD0

ADM0 set

ADCS0 = 1, TRG0 = 1 ADS0 rewrite

Standby

state ANIn ANIn

Standby

state

ANIn Standby

state ANIm ANIm ANIm

ANIn ANIn UndefinedANIn ANIm ANIm

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(2) A/D conversion by software start

When bit 6 (TRG0) and bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) are set to 0 and 1, respectively,

A/D conversion of the voltage applied to the analog input pin specified by analog input channel specification

Upon the end of the A/D conversion, the conversion result is stored in A/D conversion result register 0 (ADCR0),

and the interrupt request signal (INTAD0) is generated. After one A/D conversion operation is started and ended,

the next conversion operation is immediately started. A/D conversion operations are repeated until new data

is written to ADS0.

If ADS0 is rewritten during A/D conversion, the converter suspends A/D conversion and A/D conversion of the

newly selected analog input channel is started.

If 1 is written to ADCS0 again during A/D conversion, the A/D conversion in progress is discontinued and a new

A/D conversion is started.

If 0 is written to ADCS0 during A/D conversion, the A/D conversion operation stops immediately.

Figure 13-7. A/D Conversion by Software Start

Remarks 1. n = 0, 1, ......, 7

2. m = 0, 1, ......, 7

ADM0 set

ADCS0 = 1, TRG0 = 0 ADS0 rewrite ADCS0 = 0

A/D conversion

ADCR0

INTAD0

ANIn ANIn ANIn ANIm ANIm

Stop

ANIn UndefinedANIn ANIm

Conversion suspended;

Conversion results are not stored

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13.5 How to Read A/D Converter Characteristics Table

Here we will explain the special terms unique to A/D converters.

(1) Resolution

This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage

per 1 bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full

scale is expressed by %FSR (Full Scale Range).

When the resolution is 8 bits,

1LSB = 1/28 = 1/256

= 0.4%FSR

Accuracy has no relation to resolution, but is determined by overall error.

(2) Overall error

This shows the maximum error value between the actual measured value and the theoretical value.

Zero scale error, full scale error, integral linearity error, differential linearity error and errors which are

combinations of these express overall error.

Furthermore, quantization error is not included in overall error in the characteristics table.

(3) Quantization error

When analog values are converted to digital values, there naturally occurs a ±1/2LSB error. In an A/D converter,

an analog input voltage in a range of ±1/2LSB are converted to the same digital code, so a quantization error

cannot be avoided.

Furthermore, it is not included in the overall error, zero scale error, full scale error, integral linearity error, and

differential linearity error in the characteristics table.

Figure 13-8. Overall Error Figure 13-9. Quantization Error

Ideal line

0……0

1……1

Digital output

Overall

error

Analog input

REF

0……0

1……1

Digital output

Quantization error

1/2LSB

Analog input

REF

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(4) Zero scale error

This shows the difference between the actual measured value of the analog input voltage and the theoretical

value (1/2LSB) when the digital output changes from 0……000 to 0……001. If the actual measured value is

greater than the theoretical value, it shows the difference between the actual measured value of the analog input

voltage and the theoretical value (3/2LSB) when the digital output changes from 0……001 to 0……010.

(5) Full scale error

This shows the difference between the actual measured value of the analog input voltage and the theoretical

value (full scale –3/2LSB) when the digital output changes from 1……110 to 1……111.

(6) Integral linearity error

This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It

expresses the maximum value of the difference between the actual measured value and the ideal straight line

when the zero scale error and full scale error are 0.

(7) Differential linearity error

Although the ideal output width for a given code is 1LSB, this value shows the difference between the actual

measured value and the ideal value of the width when outputting a particular code.

Figure 13-10. Zero Scale Error Figure 13-11. Full Scale Error

Figure 13-12. Integral Linearity Error Figure 13-13. Differential Linearity Error

111

011

010

001 Zero scale error

Ideal line

000

012 3 AV

REF

Digital output (lower 3 bits)

Analog input (LSB)

111

110

101

000

REFAVREF−1AVREF−2AVREF−3

Digital output (lower 3 bits)

Analog input (LSB)

Ideal line

Full scale error

AVREF

Digital output

Analog input

Integral

linearity

error

Ideal line

1……1

0……0

0AV

REF

Digital output

1......1

0......0

Ideal width of 1LSB

Differential

linearity error

Analog input

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(8) Conversion time

This expresses the time from when the sampling was started to the time when the digital output was obtained.

Sampling time is included in the conversion time in the characteristics table.

(9) Sampling time

This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.

Sampling

time Conversion time

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13.6 A/D Converter Cautions

(1) Power consumption in standby mode

A/D converter stops operating in the standby mode. At this time, power consumption can be reduced by stopping

the conversion operation (by clearing bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 0).

Figure 13-14 shows the circuit configuration of a series resistor string.

Figure 13-14. Circuit Configuration of Series Resistor String

AVREF

AVSS

P-ch

Series resistor string

ADCS0

(2) Input range of ANI0 to ANI7

The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage higher

than AVREF or lower than AVSS is input (even if within the absolute maximum rating range), the conversion value

of that channel will be undefined and the conversion values of other channels may also be affected.

(3) Contending operations

<1> Contention between A/D conversion result register 0 (ADCR0) write and ADCR0 read by instruction upon

the end of conversion

ADCR0 read is given priority. After the read operation, the new conversion result is written to ADCR0.

<2> Contention between ADCR0 write and external trigger signal input upon the end of conversion

The external trigger signal is not accepted during A/D conversion. Therefore, the external trigger signal

is not accepted during ADCR0 write.

<3> Contention between ADCR0 write and A/D converter mode register 0 (ADM0) write or analog input channel

specification register 0 (ADS0) write upon the end of conversion

ADM0 or ADS0 write is given priority. ADCR0 write is not performed, nor is the conversion end interrupt

request signal (INTAD0) generated.

(4) ANI0/P10 to ANI7/P17

<1> The analog input pins (ANI0 to ANI7) also function as input port pins (P10 to P17).

When A/D conversion is performed with any of pins ANI0 to ANI7 selected, do not access port 1 while

conversion is in progress, as this may reduce the conversion resolution.

<2> If digital pulses are applied to the pin adjacent to a pin in the process of A/D conversion, the expected

A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to

the pin adjacent to a pin undergoing A/D conversion.

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(5) AVREF pin input impedance

A series resistor string is connected between the AVREF pin and the AVSS pin.

Therefore, when the output impedance of the reference voltage is too high, it seems as if the AVREF pin and the

series resistor string are connected in series. This may cause a greater reference voltage error.

(6) Interrupt request flag (ADIF0)

The interrupt request flag (ADIF0) is not cleared even if analog input channel specification register 0 (ADS0) is

changed.

Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and conversion

end interrupt request flag for the pre-change analog input may be set just before the ADS0 rewrite. Caution is

therefore required since, at this time, when ADIF0 is read immediately just after the ADS0 rewrite, ADIF0 is set

despite the fact that the A/D conversion for the post-change analog input has not finished.

When A/D conversion is restarted after it is stopped, clear ADIF0 before restart.

Figure 13-15. A/D Conversion End Interrupt Request Generation Timing

Remarks 1. n = 0, 1, ......, 7

2. m = 0, 1, ......, 7

(7) Conversion results just after A/D conversion start

The A/D conversion value immediately after A/D conversion has been started may not satisfy the rated value.

Take measures such as polling the A/D conversion end interrupt request (INTAD0) and removing the first

conversion results.

(8) A/D conversion result register 0 (ADCR0) read operation

When A/D converter mode register 0 (ADM0) and analog input channel specification register 0 (ADS0) are written,

the contents of ADCR0 may become undefined. Read the conversion result following conversion completion

before writing to ADM0 and ADS0. Using a timing other than the above may cause an incorrect conversion result

to be read.

ADM0 rewrite

(start of ANIn conversion)

ADS0 rewrite

(start of ANIm conversion)

ADIF is set but ANIm

conversion has not finished.

A/D conversion

ADCR0

INTAD0

ANIn ANIn ANIm ANIm

ANIn Undefined ANIm ANIm

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Normal conversion result Undefined value

A/D conversion completes A/D conversion completes

Normal conversion result is read. A/D conversion

is stopped.

Undefined value

is read.

ADCR0

INTAD0

ADCS0

(9) Timing at which A/D conversion result is undefined

The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of

stopping the A/D conversion conflict with each other. Therefore, read the A/D conversion result before stopping

the A/D conversion operation.

Figure 13-16 shows the timing of reading the conversion result.

Figure 13-16. Timing of Reading Conversion Result (When Conversion Result Is Undefined)

(10) Notes on board design

Locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may

be affected by the noise of the digital circuits. In particular, do not cross an analog signal line with a digital signal

line, or wire an analog signal line in the vicinity of a digital signal line. Otherwise, the A/D conversion

characteristics may be affected by the noise of the digital line.

Connect AVSS0 and VSS0 at one location on the board where the voltages are stable.

(11) AVDD pin

The AVDD pin is the analog circuit power supply pin. It supplies power to the input circuits of the ANI0 to ANI7

pins.

Therefore, be sure to apply the same potential as VDD0 to this pin even for applications designed to switch to

a backup battery for power supply.

Figure 13-17. AVDD Pin Connection

Main power supply Capacitor

for backup

REF

DD0

SS0

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(12) AVREF pin

Connect a capacitor to the AVREF pin to minimize conversion errors due to noise. If an A/D conversion operation

has been stopped and then is started, the voltage applied to the AVREF pin becomes unstable, causing the

accuracy of the A/D conversion to drop. To prevent this, also connect a capacitor to the AVREF pin.

Figure 13-18 shows an example of connecting a capacitor.

Figure 13-18. Example of Connecting Capacitor to AVREF Pin

Remark C1: 4.7

F to 10

F (reference value)

C2: 0.01

F to 0.1

F (reference value)

Connect C2 as close to the pin as possible.

(13) Internal equivalent circuit of ANI0 to ANI7 pins and permissible signal source impedance

To complete sampling within the sampling time with sufficient A/D conversion accuracy, the impedance of the

signal source such as a sensor must be sufficiently low. Figure 13-19 shows the internal equivalent circuit of

the ANI0 to ANI7 pins.

If the impedance of the signal source is high, connect capacitors with a high capacitance to the pins ANI0 to ANI7.

An example of this is shown in Figure 13-20. In this case, however, the microcontroller cannot follow an analog

signal with a high differential coefficient because a lowpass filter is created.

To convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance

buffer.

Figure 13-19. Internal Equivalent Circuit of Pins ANI0 to ANI7

Remark n = 0 to 7

AVREF

AVDD

Clamp using a diode with a low

VF (0.3 V or lower).

AVSS

C2C1

C3C2

R2R1

ANIn

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Table 13-3. Resistances and Capacitances of Equivalent Circuit (Reference Values)

(TYP.)

AVREF R1 R2 C1 C2 C3

2.7 V 12 kΩ8.0 kΩ3.0 pF 3.0 pF 2.0 pF

4.5 V 4 kΩ2.7 kΩ3.0 pF 1.4 pF 2.0 pF

Caution The resistances and capacitances in Table 13-3 are not guaranteed values.

Figure 13-20. Example of Connection If Signal Source Impedance Is High

Remark n = 0 to 7

(14) Input impedance of ANI0 to ANI7 pins

This A/D converter executes sampling by charging the internal sampling capacitor for approximately 1/10 of the

conversion time.

Therefore, only the leakage current flows during other than sampling, and the current for charging the capacitor

flows during sampling. The input impedance therefore varies and has no meaning.

To achieve sufficient sampling, it is recommended that the output impedance of the analog input source be 10

kΩ or less, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 13-20).

C3C2

R2R1

If a noise of AVREF or higher or AVSS or lower

may be generated, clamp using a diode with

a low VF (0.3 V or lower).

ANIn

AVREF

Lowpass filter

is created.

Output impedance

of sensor

C0 ≤ 0.1 F

Reference

voltage input

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CHAPTER 14 10-BIT A/D CONVERTER (

PD780034A, 780034AY SUBSERIES)

14.1 A/D Converter Functions

A/D converter is a 10-bit resolution converter that converts analog inputs into digital signals. It can control up to

8 analog input channels (ANI0 to ANI7).

(1) Hardware start

Conversion is started by trigger input (ADTRG: rising edge, falling edge, or both rising and falling edges can

be specified).

(2) Software start

Conversion is started by setting A/D converter mode register 0 (ADM0).

Select one channel for analog input from ANI0 to ANI7 to start A/D conversion. In the case of hardware start, the

A/D converter stops when A/D conversion is completed, and an interrupt request (INTAD0) is generated. In the case

of software start, A/D conversion is repeated. Each time as A/D conversion operation ends, an interrupt request

(INTAD0) is generated.

Caution Although the

PD78F0034A, 78F0034B, 78F0034AY, and 78F0034BY incorporate a 10-bit A/D

converter, this converter can be operated as an 8-bit A/D converter by using the device file

DF780024.

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Figure 14-1. 10-Bit A/D Converter Block Diagram

Note The valid edge of external interrupt is specified by bit 3 of the EGP and EGN registers (see Figure 19-5

Format of External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge

Enable Register (EGN)).

ANI0/P10

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

Sample & hold circuit

Series resistor string

Voltage comparator

Controller

Edge

detector

ADTRG/INTP3/P03

A/D conversion result

AVDD

AVREF

AVSS

INTAD0

INTP3

Trigger enable

A/D converter

mode register 0 (ADM0)

Analog input channel

specification register 0 (ADS0)

Internal bus

ADS02 ADS01 ADS00

ADCS0

TRG0 FR02 FR01 FR00

EGA01 EGA00

Selector

Tap selector

Edge

detector

Note

Successive

approximation

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14.2 A/D Converter Configuration

The A/D converter consists of the following hardware.

Table 14-1. A/D Converter Configuration

Item Configuration

Analog input 8 channels (ANI0 to ANI7)

Hardware trigger 1 (ADTRG)

input

Registers Successive approximation register (SAR)

A/D conversion result register 0 (ADCR0)

Control registers A/D converter mode register 0 (ADM0)

Analog input channel specification register 0 (ADS0)

(1) Successive approximation register (SAR)

This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from

the series resistor string, and holds the result from the most significant bit (MSB).

When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to

A/D conversion result register 0 (ADCR0).

(2) A/D conversion result register 0 (ADCR0)

This is a 16-bit register that stores the A/D conversion results. The lower 6 bits are fixed to 0. Each time A/

D conversion ends, the conversion result is loaded from the successive approximation register (SAR) and held

by this register. The most significant bit (MSB) is stored in ADCR0 first. The higher 8 bits of the conversion results

are stored in FF17H. The lower 2 bits of the conversion results are stored in FF16H.

ADCR0 is read by a 16-bit memory manipulation instruction.

RESET input clears ADCR0 to 0000H.

Figure 14-2. Format of A/D Conversion Result Register 0 (ADCR0)

Caution When A/D converter mode register 0 (ADM0) and analog input channel specification register

0 (ADS0) are written, the contents of ADCR0 may become undefined. Read the conversion

result following conversion completion before writing to ADM0 and ADS0. Using a timing

other than the above may cause an incorrect conversion result to be read.

(3) Sample & hold circuit

The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D

conversion is started and holds the sampled analog input voltage value during A/D conversion.

000000ADCR0

Symbol

FF17H FF16H

Address: FF16H, FF17H After reset: 0000H R

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(4) Voltage comparator

The voltage comparator compares the sampled analog input voltage to the series resistor string output voltage.

(5) Series resistor string

The series resistor string is connected between AVREF and AVSS, and generates the voltage to be compared to

the analog input.

(6) ANI0 to ANI7 pins

These are eight analog input pins used to input analog signals to undergo A/D conversion to the A/D converter.

ANI0 to ANI7 are alternate-function pins that can also be used for digital input.

Cautions 1. Use ANI0 to ANI7 input voltages within the specification range. If a voltage higher than or

equal to AVREF or lower than or equal to AVSS is applied (even if within the absolute maximum

rating range), the conversion value of that or equal to channel will be undefined and the

conversion values of other channels may also be affected.

2. Analog input (ANI0 to ANI7) pins are alternate-function pins that can also be used as input

port pins (P10 to P17). When A/D conversion is performed by selecting any one of ANI0

through ANI7, do not access port 1 during conversion, as this may cause a lower conversion

resolution.

3. When a digital pulse is applied to a pin adjacent to the pin in the process of A/D conversion,

A/D conversion values may not be obtained as expected due to coupling noise. Thus, do

not apply a pulse to a pin adjacent to the pin in the process of A/D conversion.

(7) AVREF pin

This is the A/D converter reference voltage pin and also the analog power supply pin.

It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF and

AVSS.

Caution A series resistor string is connected between the AVREF and AVSS pins. Therefore, when the

output impedance of the reference voltage is too high, it seems as if the AVREF pin and the

series resistor string are connected in series. This may cause a greater reference voltage

error.

(8) AVSS pin

This is the ground potential pin of the A/D converter. Always keep it at the same potential as the VSS0 or VSS1

pin even when not using the A/D converter.

(9) AVDD pin

This is the A/D converter analog power supply pin. Always keep it at the same potential as the VDD0 or VDD1 pin

even when not using the A/D converter.

(10) ADTRG pin

This pin is a pin used to start the A/D converter by hardware.

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14.3 Registers to Control A/D Converter

The following 2 types of registers are used to control the A/D converter.

•A/D converter mode register 0 (ADM0)

•Analog input channel specification register 0 (ADS0)

(1) A/D converter mode register 0 (ADM0)

This register sets the conversion time for analog input to be A/D converted, conversion start/stop, and external

trigger.

ADM0 is set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears ADM0 to 00H.

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Figure 14-3. Format of A/D Converter Mode Register 0 (ADM0)

Address: FF80H After reset: 00H R/W

Symbol <7> <6> 543210

ADM0 ADCS0 TRG0 FR02 FR01 FR00 EGA01 EGA00 0

ADCS0 A/D conversion operation control

0 Stop conversion operation.

1 Enable conversion operation.

TRG0 Software start/hardware start selection

0 Software start

1 Hardware start

FR02 FR01 FR00 Conversion time selectionNote 1

fX = 8.38 MHz fX = 12 MHzNote 2

0 0 0 144/fX17.1

s 12.0

0 0 1 120/fX14.3

s 10.0

sNote 4

0 1 0 96/fX11.4

sNote 3 8.0

sNote 4

1 0 0 72/fX8.5

sNote 3 6.0

sNote 4

1 0 1 60/fX7.1

sNote 3 5.0

sNote 4

1 1 0 48/fX5.7

sNote 3 4.0

sNote 4

Other than above Setting prohibited

EGA01 EGA00 External trigger signal, edge specification

0 0 No edge detection

0 1 Falling edge detection

1 0 Rising edge detection

1 1 Both falling and rising edge detection

Notes 1. Set the A/D conversion time as follows.

• When operated at fX = 12 MHz (VDD = 4.5 to 5.5 V): 12

s or more

• When operated at fX = 8.38 MHz (VDD = 4.0 to 5.5 V): 14

s or more

2. Expanded-specification products of

PD780034A Subseries only.

3. Setting is prohibited because the A/D conversion time is less than 14

4. Setting is prohibited because the A/D conversion time is less than 12

Caution When rewriting FR00 to FR02 to other than the same data, stop A/D conversion operations

once prior to performing rewrite.

Remark fX: Main system clock oscillation frequency

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(2) Analog input channel specification register 0 (ADS0)

This register specifies the analog voltage input port for A/D conversion.

ADS0 is set by an 8-bit memory manipulation instruction.

RESET input clears ADS0 to 00H.

Figure 14-4. Format of Analog Input Channel Specification Register 0 (ADS0)

Address: FF81H After reset: 00H R/W

Symbol 76543210

ADS0 00000ADS02 ADS01 ADS00

ADS02 ADS01 ADS00 Analog input channel specification

0 0 0 ANI0

0 0 1 ANI1

0 1 0 ANI2

0 1 1 ANI3

1 0 0 ANI4

1 0 1 ANI5

1 1 0 ANI6

1 1 1 ANI7

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14.4 A/D Converter Operation

14.4.1 Basic operations of A/D converter

<1> Select one channel for A/D conversion with analog input channel specification register 0 (ADS0).

<2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.

<3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and

the input analog voltage is held until the A/D conversion operation is ended.

<4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to

(1/2) AVREF by the tap selector.

<5> The voltage difference between the series resistor string voltage tap and analog input is compared by the

voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set. If the analog

input is smaller than (1/2) AVREF, the MSB is reset.

<6> Next, bit 8 of SAR is automatically set, and the operation proceeds to the next comparison. The series resistor

string voltage tap is selected according to the preset value of bit 9, as described below.

•Bit 9 = 1: (3/4) AVREF

•Bit 9 = 0: (1/4) AVREF

The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.

•Analog input voltage ≥ Voltage tap: Bit 8 = 1

•Analog input voltage < Voltage tap: Bit 8 = 0

<7> Comparison is continued in this way up to bit 0 of SAR.

<8> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result

value is transferred to and latched in A/D conversion result register 0 (ADCR0).

At the same time, the A/D conversion end interrupt request (INTAD0) can also be generated.

Cautions 1. The first A/D conversion value immediately after A/D conversion has been started may not

satisfy the rated value. Take measures such as polling the A/D conversion end interrupt

request (INTAD0) and removing the first conversion results.

2. The A/D converter stops operation in standby mode.

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Figure 14-5. Basic Operation of 10-Bit A/D Converter

A/D conversion operations are performed continuously until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0)

is reset (0) by software.

RESET input clears A/D conversion result register 0 (ADCR0) to 00H.

Confirm the conversion results by referring to the A/D conversion end interrupt request flag (ADIF0).

The sampling time of the A/D converter varies depending on the values set in A/D converter mode register 0 (ADM0).

There is a delay time from when the A/D converter is enabled for operation until sampling is actually performed.

For the sets in which a strict A/D conversion time is required, note the contents described in Table 14-2.

Conversion time

Setting ADCS0 to 1, external trigger,

or overwriting ADS0

A/D conversion start delay time

Sampling A/D conversion

Undefined Conversion

result

Conversion

result

A/D converter

operation

SAR

ADCR0

INTAD0

ADCS0

Sampling time

200H 300H

100H

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Table 14-2. Sampling Time and A/D Conversion Start Delay Time of A/D Converter

FR02 FR01 FR00 Conversion TimeNote 1 Sampling Time A/D Conversion Start Delay Time

MIN. MAX.

0 0 0 144/fX20/fX0.5/fCPU + 6/fX0.5/fCPU + 8/fX

0 0 1 120/fX16/fX

0 1 0 96/fX12/fX

1 0 0 72/fX10/fX0.5/fCPU + 3/fX0.5/fCPU + 4/fX

1 0 1 60/fX8/fX

1 1 0 48/fX6/fX

Other than above Setting prohibited −−−

Notes 1. Set the A/D conversion time as follows.

• When operated at fX = 12 MHzNote 2 (VDD = 4.5 to 5.5 V): 12

s or more

• When operated at fX = 8.38 MHz (VDD = 4.0 to 5.5 V): 14

s or more

2. Expanded-specification products of

PD780034A Subseries only.

Remark fX: Main system clock oscillation frequency

fCPU: CPU clock frequency

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14.4.2 Input voltage and conversion results

The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical

A/D conversion result (stored in A/D conversion result register 0 (ADCR0)) is shown by the following expression.

ADCR0 = INT ( VIN × 1024 + 0.5)

AVREF

(ADCR0 – 0.5) × AVREF ≤ VIN < (ADCR0 + 0.5) × AVREF

1024 1024

where, INT( ): Function which returns integer part of value in parentheses

VIN: Analog input voltage

AVREF:AVREF pin voltage

ADCR0: A/D conversion result register 0 (ADCR0) value

Figure 14-6 shows the relationship between the analog input voltage and the A/D conversion result.

Figure 14-6. Relationship Between Analog Input Voltage and A/D Conversion Result

1023 × 26

1022 × 26

1021 × 26

3 × 26

2 × 26

1 × 26

A/D conversion result

(ADCR0)

2048

1024

2048

1024

2048

1024

2043

2048

1022

1024

2045

2048

1023

1024

2047

2048

Input voltage/AVREF

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14.4.3 A/D converter operation mode