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1. Product profile
1.1 General description
The IP4786CZ32 is designed to protect High-Definition Multimedia Interface (HDMI)
transmitter host interfaces. It includes HDMI 5 V overcurrent / overvoltage protection,
Display Data Channel ( DDC) buffering and decoupling, hot plug detect, backdrive
protection, Consumer Electronic Control (CEC) buffering and decoupling, and 12 kV
contact ElectroStatic Discharge (ESD) protection for all I/Os, exceeding the
IEC 61000-4-2 level 4 standard.
The IP4786CZ32 incorporates Transmission Line Clamping (TLC) technology on the
high-speed Transition Minimized Differential Signaling (TMDS) lines to simplify routing
and help reduce impedance discontinuities. All TMDS lines are protected by an
impedance-matched diode configuration that minimizes impedance discontinuities caused
by typical shunt diodes.
The enhanced 60 mA overcurrent / overvoltage linear regulator guarantees
HDMI-compliant 5 V output voltage levels with up to 6.5 V inputs.
The DDC lines use a new buffering concept which decouples the internal capacitive load
from the external capacitive load for use with standard Complementary Metal Oxide
Semiconductor (CMOS) or Low Voltage Transistor-Transistor Logic (LVTTL) I/O cells
down to 1.8 V. This buffering also redrives the DDC and CEC signals, allowing the use of
longer or cheaper HDMI cables with a higher capacitance. The internal hot plug detect
module simplifies the application of the HDMI transmitter to control the hot plug signal.
All lines provide appropri ate integrated pull-ups and pull-downs for HDMI compliance and
backdrive protection to guarantee that HDMI interface signals are not pulled down if the
system is powered down or enters Standby mode. Only a single external capacitor is
required for operation.
1.2 Features and benefits
HDMI 2.0 and all back war d compatible standards ar e su pp orte d
6.0 Gbps TMDS Bit Rate (600 Mcsc TMDS Character Rate) compatible
Supports UHD 4k (2160p) 60 Hz display modes
Impedance matched 100 diff erential transmission line ESD protection for
TMDS lines (10 ). No Printed-Circuit Board (PCB) pre-compensation required
Simplified flow-through routing utilizing less overall PCB space
DDC capacitive decoupling between system side and HDMI connector side and
buffering to drive cable with high capacitive load (> 700 pF/25 m)
IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection,
DDC/CEC buffering, hot plug detect and backdrive protection
Rev. 5 — 24 June 2014 Product data sheet
HVQFN32
IP4786CZ32 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 June 2014 2 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
All external I/O lines with ESD protection of at least 12 kV, exceeding the
IEC 61000-4-2, level 4 standard
Hot plug detect module
CEC buffering and isolation, with integrated backdrive-protected 26 k pull-up
Robust ESD protec tio n with ou t de gr ad a tio n after repea te d ESD str ikes
Highest integration in a small footprint, PCB level, optimized RF routing,
32-pin HVQFN leadless package
1.3 Applications
The IP4786CZ32 can be used for a wide range of HDMI source devices, consumer
and computing electronics:
Standard-Definition (SD) and High-Definition (HD) DVD player
Set-top box
PC graphic card
Game console
HDMI picture performance quality enhancer module
Digital Visual Interface (D VI)
2. Pinning information
2.1 Pinning
Fig 1. Pin configuration IP4 7 86C Z3 2
018aaa083
IP4786CZ32
Transparent top view
TMDS_CK–_CON
TMDS_CK+_SYS
TMDS_CK–_SYS
TMDS_CK+_CON
TMDS_D0–_SYS TMDS_D0–_CON
TMDS_D0+_SYS TMDS_D0+_CON
TMDS_D1–_SYS TMDS_D1–_CON
TMDS_D1+_SYS TMDS_D1+_CON
TMDS_D2–_SYS TMDS_D2–_CON
TMDS_D2+_SYS TMDS_D2+_CON
DDC_CLK_SYS
DDC_DAT_SYS
V
CC(5V0)
HOTPLUG_DET_CON
HDMI_5V0_CON
DDC_DAT_CON
DDC_CLK_CON
UTILITY_CON
HOTPLUG_DET_SYS
n.c.
n.c.
CEC_SYS
CEC_STBY
V
CC(SYS)
ESD_BYPASS
CEC_CON
817
718
619
520
421
322
223
124
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
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Product data sheet Rev. 5 — 24 June 2014 3 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
2.2 Pin description
Table 1. Pin description
Pin Name Description
1 TMDS_D2+_SYS TMDS to ASIC inside system
2TMDS_D2_SYS TMDS to ASIC inside system
3 TMDS_D1+_SYS TMDS to ASIC inside system
4TMDS_D1_SYS TMDS to ASIC inside system
5 TMDS_D0+_SYS TMDS to ASIC inside system
6TMDS_D0_SYS TMDS to ASIC inside system
7 TMDS_CK+_SYS TMDS to ASIC inside system
8TMDS_CK_SYS TMDS to ASIC inside system
9 DDC_CLK_SYS DDC clock system side
10 DDC_DAT_SYS DDC data system side
11 VCC(5V0) 5 V supply input
12 HOTPLUG_DET_CON hot plug detect connector side
13 HDMI_5V0_CON 5 V overcurrent out to connector
14 DDC_DAT_CON DDC data connector side
15 DDC_CLK_CON DDC clock connector side
16 UTILITY_CON utility line ESD protection
17 TMDS_CK_CON TMDS ESD protection to connector
18 TMDS_CK+_CON TMDS ESD protection to connector
19 TMDS_D0_CON TMDS ESD protection to connector
20 TMDS_D0+_CON TMDS ESD protection to connector
21 TMDS_D1_CON TMDS ESD protection to connector
22 TMDS_D1+_CON TMDS ESD protection to connector
23 TMDS_D2_CON TMDS ESD protection to connector
24 TMDS_D2+_CON TMDS ESD protection to connector
25 CEC_CON CEC signal connector side
26 ESD_BYPASS ESD bias voltage
27 VCC(SYS) supply voltage for level shifting
28 CEC_STBY CEC Standby mode control (LOW for lowest
power, CEC-only mode)
29 CEC_SYS CEC I/O signal system side
30 n.c. not connected
31 n.c. not connected
32 HOTPLUG_DET_SYS hot plug detect system side
ground pad GND ground
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Product data sheet Rev. 5 — 24 June 2014 4 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
3. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
IP4786CZ32 HVQFN32 plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5 50.85 mm SOT617-3
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Product data sheet Rev. 5 — 24 June 2014 5 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
4. Functional diagram
Fig 2. Functional diagram
n
m
aaa-013776
CEC driver
ESD
ESD
TMDS_CK–_SYS TMDS_CK–_CON
CEC_CONCEC_SYS
26 kΩ
10 kΩ
3.3 V VOLTAGE
REGULATOR
ESD
DDC driver
ESDHDMI_5V0_CON
HDMI_5V0_CON
ESD
DDC_CLK_CONDDC_CLK_SYS
1.85 kΩ3.65 kΩ
DDC driver ESD
ESD
DDC_DAT_CONDDC_DAT_SYS
1.85 kΩ3.65 kΩ
Hot plug ESD
ESD
HOTPLUG_DET_CONHOTPLUG_DET_SYS
100 kΩ
100 kΩ
100 kΩ
enable
enCEC enLim
enRef
CURRENT LIMITER
ESD
ESD
HDMI_5V0_CON
POWER
MANAGEMENT UNIT
ESD
main
clamp
ESD_BYPASS
ESD
ESD
CEC_STBY
TMDS_CK+_SYS TMDS_CK+_CON
TMDS_D0–_SYS TMDS_D0–_CON
TMDS_D0+_SYS TMDS_D0+_CON
TMDS_D1–_SYS TMDS_D1–_CON
TMDS_D1+_SYS TMDS_D1+_CON
TMDS_D2–_SYS TMDS_D2–_CON
TMDS_D2+_SYS TMDS_D2+_CON
100 kΩ
ibias 1..n
vref 1..m
CURRENT-/VOLTAGE-
REFERENCES
ESD
UTILITY_CON
VCC(5V0)
VCC(SYS)
VCC(SYS)
VCC(SYS)
VCC(5V0)
VCC(5V0)
VCC(SYS)
VCC(SYS)
VCC(5V0)
VCC(SYS)
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Product data sheet Rev. 5 — 24 June 2014 6 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
5. Limiting values
[1] Connector-side pins (typically denoted with “_CON” suffix) to ground.
[2] System-side pins: CEC_SYS, DDC_DAT_SYS, DDC_CLK_SYS, HOTPLUG_DET_SYS, CEC_STBY, VCC(SYS) and VCC(5V0).
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC(5V0) supply voltage (5.0 V) GND 0.5 6.5 V
VIinput voltage I/O pins GND 0.5 5.5 V
VESD electrostatic discharge
voltage IEC 61000-4-2, level 4 (contact) [1] -12 kV
IEC 61000-4-2, level 1 (contact) [2] -2kV
Ptot total power dissipation DDC operating at 100 kHz;
CEC operating at 1 kHz;
50 % duty cycle; CEC_STBY = HIGH;
no current at HDMI_5V0_CON
-50mW
DDC and CEC bus in idle mode;
CEC_STBY = HIGH;
no current at HDMI_5V0_CON
-3.0mW
DDC and CEC bus in idle mode;
CEC_STBY = LOW -1.0mW
Tamb ambient temperature 25 +85 C
Tstg storage temperature 55 +125 C
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Product data sheet Rev. 5 — 24 June 2014 7 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
6. Static characteristics
[1] The IP4786CZ32 contains a 5 V voltage regulator function for higher input voltages.
Any input voltage of 4.925 V < VCC(5V0) < 6.50 V will provide HDMI-compliant output levels of 4.8 V to 5.3 V
on HDMI_5V0_CON.
[1] This parameter is guaranteed by design.
[2] Capacitive dip at HDMI Time Domain Reflectometer (TDR) measurement conditions.
[3] ANSI-ESDSP5.5.1-2004, ESD sensitivity testing Transmission Line Pulse (TLP) component level
method 50 TDR.
[4] Signal pins:
TMDS_D0+_CON, TMDS_D0_CON, TMDS_D1+_CON, TMDS_D1_CON, TMDS_D2+_CON,
TMDS_D2_CON, TMDS_CK+_CON, TMDS_CK_CON,
TMDS_D0+_SYS, TMDS_D0_SYS, TMDS_D1+_SYS, TMDS_D1_SYS, TMDS_D2+_SYS,
TMDS_D2_SYS, TMDS_CK+_SYS and TMDS_CK_SYS.
[5] Backdrive current from TMDS_x_SYS and TMDS_x_CON pins to local VCC(5V0) bias rail at power-down.
Device does not block backdrive current leakage through the device to/from ASIC I/O pins connected
to TMDS_x_SYS pins.
Table 4. Supplies
Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCC(5V0) supply voltage (5.0 V) [1] 4.55.06.5V
VCC(SYS) system supply voltage 1.62 3.3 5.5 V
Table 5. TMDS protection circui t
Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TMDS channel
Zi(dif) differential input
impedance TDR measured;
tr=200ps 90 100 110
Ceff effective capacitance equi valent shunt
capacit a nce for TDR
minimum; tr=200ps
[1][2] -0.6-pF
Protection diode
VBRzd Zener diode breakdown
voltage I=1.0mA 6.0 - 9.0 V
rdyn dynamic resistance surge; I = 1.0 A;
IEC 61000-4-5/9
positive transient - 1.0 -
negative transient - 1.0 -
TLP
positive transient [3] -1.0-
negative transient [3] -1.0-
Ibck back current VCC(5V0) <V
ch(TMDS) [4][5] -0.11.0A
ILR reverse leakage current VI=3.0V - 1.0 - A
VFforward voltage - 0.7 - V
VCL(ch)trt(pos) positive transient channel
clamping voltage 100 ns TLP;
50 pulser at 50 ns -8.0-V
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Product data sheet Rev. 5 — 24 June 2014 8 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
[1] ANSI-ESDSP5.5.1-2004, ESD sensitivity testing TLP component level method 50 TDR.
[2] The IP4786CZ32 contains a 5 V voltage regulator function for higher input voltages.
Any input voltage of 4.925 V < VCC(5V0) < 6.50 V will provide HDMI-compliant output levels of 4.8 V to 5.3 V
on HDMI_5V0_CON.
[1] ANSI-ESDSP5.5.1-2004, ESD sensitivity testing TLP component level method 50 TDR.
Table 6. HDMI_5V0_CON
Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
rdyn dynamic resistance TLP
positive transient [1] -1.0-
negative transient [1] -1.0-
VCL clamping voltage 100 ns TLP;
50 pulser at 50 ns -8-V
IO(max) maximum output current V(HDMI_5V0_CON) =4.8V 55--mA
Ibck back current VCC(5V0) <V
(HDMI_5V0_CON) --10A
IO(sc) short-circuit output current V(HDMI_5V0_CON) = 0 V - 125 175 mA
Vdo dropout voltage 4.5 V < VCC(5V0) <4.925V;
DDC = LOW [2]
IO=10mA - 70 - mV
IO=55mA - - 125 mV
VO(LDO) LDO output voltage IO55 mA;
4.925 V < VCC(5V0) <6.5V;
DDC = LOW
[2] 4.8 5.05 5.3 V
Table 7. UTILITY_CON
Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies: pins VCC(5V0) and VCC(SYS)
rdyn dynamic resistance TLP
positive transient [1] -1.0-
negative transient [1] -1.0-
VCL clamping voltage 100 ns TLP;
50 pulser at 50 ns -8.0-V
Ciinput capacitance VCC(5V0) =0V;
VCC(SYS) =0V; V
bias =2.5V;
AC input = 3.5 V(p-p);
f=100kHz
-8.010pF
Rpd pull-down resistance 60 100 140 k
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Product data sheet Rev. 5 — 24 June 2014 9 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
Table 8. Static ch aracteristics
Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
DDC buffer on connector side[1]
VIH HIGH-level input voltage 0.5
V(HDMI_5V0_CON)
-6.5 V
VIL LOW-level input voltage 0.5 - 0.3
V(HDMI_5V0_CON)
V
VOH HIGH-level output voltage [2] V(HDMI_5V0_CON)
0.02 -V
(HDMI_5V0_CON)
+0.02 V
VOL LOW-level output voltage internal pull-up and
external sink - 100 200 mV
VIK input clamping voltage II=18 mA - - 1.0 V
CIO input/output capacitance VCC(5V0) =5.0V;
VCC(SYS) =3.3V;
CEC_STBY = HIGH
[2][3] -8.010pF
Rpu pull-up resistance 1.6 1.8 2.0 k
DDC buffer on system side[1][4]
VIH HIGH-level input voltage VCC(SYS) =1.8V 450 - - mV
VCC(SYS) =2.5V 620 - - mV
VCC(SYS) =3.3V 760 - - mV
VCC(SYS) =5.0V 800 - - mV
VIL LOW-level input voltage VCC(SYS) = 1.8 V - - 330 mV
VCC(SYS) = 2.5 V - - 380 mV
VCC(SYS) = 3.3 V - - 400 mV
VCC(SYS) = 5.0 V - - 420 mV
VOH HIGH-level output voltage [2] VCC(SYS) 0.02 - VCC(SYS) +0.02 V
VOL LOW-level output voltage VCC(SYS) =1.8V [5] - 490 500 mV
VCC(SYS) =2.5V [5] - 640 690 mV
VCC(SYS) =3.3V [5] - 685 790 mV
VCC(SYS) =5.0V [5] - 720 820 mV
VIK input clamping voltage II=18 mA - - 1.0 V
CIO input/output capacitance VCC(5V0) =0V;
VCC(SYS) =0V;
Vbias =2.5V;
AC input = 3.5 V(p-p);
f=100kHz
[2] -6.08.0pF
Rpu pull-up resistance 3.2 3.65 4.1 k
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Product data sheet Rev. 5 — 24 June 2014 10 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
CEC_CON[1]
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.80 V
VOH HIGH-level output voltage 2.88 3.3 3.63 V
VOL LOW-level output voltage IOL = 1.5 mA - 100 200 mV
CIO input/output capacitance VCC(5V0) =0V;
VCC(SYS) =0V;
Vbias = 1.65 V;
AC input = 2.5 V(p-p);
f=100kHz
[2] -8.010pF
Rpu pull-up resistance 23.4 26.0 28.6 k
Ileak(CEC) CEC leakage current VCC(5V0) =0V;
VCC(SYS) =0V;
CEC_CON connected
to 3.63 V via 27 k
--0.1A
CEC_SYS[1][4]
VIH HIGH-level input voltage VCC(SYS) =1.8V 450 - - mV
VCC(SYS) =2.5V 620 - - mV
VCC(SYS) =3.3V 760 - - mV
VCC(SYS) =5.0V 800 - - mV
VIL LOW-level input voltage VCC(SYS) = 1.8 V - - 330 mV
VCC(SYS) = 2.5 V - - 380 mV
VCC(SYS) = 3.3 V - - 400 mV
VCC(SYS) = 5.0 V - - 420 mV
VOH HIGH-level output voltage [2] VCC(SYS) 0.02 - VCC(SYS) +0.02 V
VOL LOW-level output voltage VCC(SYS) =1.8V [5] - 490 500 mV
VCC(SYS) =2.5V [5] - 640 690 mV
VCC(SYS) =3.3V [5] - 675 770 mV
VCC(SYS) =5.0V [5] - 710 800 mV
CIO input/output capacitance VCC(5V0) =0V;
VCC(SYS) =0V;
Vbias = 1.65 V;
AC input = 2.5 V(p-p);
f=100kHz
[2] -6.07.0pF
Rpu pull-up resistance 8.5 10 11.5 k
HOTPLUG_DET_CON[1]
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
Rpd pull-down resistance 60 100 140 k
Ciinput capacitance VCC(5V0) =0V;
VCC(SYS) =0V;
Vbias =2.5V;
AC input = 3.5 V(p-p);
f=100kHz
[2] -8.010pF
Table 8. Static ch aracteristics …continued
Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 5 — 24 June 2014 11 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
[1] The device is active if the input voltage at pin CEC_STBY is above the HIGH level.
[2] This parameter is guaranteed by design.
[3] Capacitive load measured at power-on.
[4] No external pull-up resistor attached.
[5] Typical value at Tamb = +25 °C.
[1] The CEC_STBY pin should be connected permanently to VCC(5V0) or VCC(SYS) if no enable control is needed.
[2] DDC buffers, Hot Plug Detect (HPD) buffer, and HDMI_5V0_CON out enabled; CEC buffer enabled.
[3] DDC buffers, HPD buffer, and HDMI_5V0_CON out disabled; CEC buffer enabled.
HOTPLUG_DET_SYS[1]
VOH HIGH-level output voltage IOL =1mA 0.7VCC(SYS) -- V
VOL LOW-level output voltage IOL =1 mA - 200 300 mV
Rpd pull-down resistance 60 100 140 k
Table 8. Static ch aracteristics …continued
Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 9. CEC_STBY power management circuit
VCC(SYS) = 1.62 V to 5.5 V; VCC(5V0) = 4.5 V to 6.5 V; GND = 0 V; Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Board side: input pin CEC_STBY[1]
VIH HIGH-level input voltage HIGH = active [2] 1.2 - 6.5 V
VIL LOW-level input voltage LOW = standby [3] 0.5 - 0.8 V
Rpd pull-down resistance 60 100 140 k
Ciinput capacitance VI=3V or 0V - 67pF
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Product data sheet Rev. 5 — 24 June 2014 12 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
7. Dynamic characteristics
[1] All dynamic measurements are done with a 75 pF load. Rise times are determined by internal pull-up resistors.
Table 10. Dynamic char acteristics
VCC(5V0) =5.0V; V
CC(SYS) = 1.8 V; GND = 0 V; Tamb =
25
C to +85
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
DDC_DAT_SYS, DDC_CLK_SYS, DDC_DAT_CON, DDC_CLK_CON[1]
tPLH LOW to HIGH propagation delay system side to connector side Figure 16 -80-ns
tPHL HIGH to LOW propagation delay system side to connector side Figure 16 -60-ns
tPLH LOW to HIGH propagation delay connector side to system side Figure 17 -120-ns
tPHL HIGH to LOW propagation delay connector side to system side Figure 17 -80-ns
tTLH LOW to HIGH transition time connector side Figure 18 -150-ns
tTHL HIGH to LOW transition time connector side Figure 18 -100-ns
tTLH LOW to HIGH transition time system side Figure 19 -250-ns
tTHL HIGH to LOW transition time system side Figure 19 -80-ns
tr= 200 ps; no filter; VCC(5V0) =5 V
100 differential (CH1 + CH2)
Fig 3. Differential TDR plot
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




WLPHQV
=GLI
ȍ
70'6B&.
70'6B'
70'6B'
70'6B'
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Product data sheet Rev. 5 — 24 June 2014 13 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
(1) Sdd21
(2) Scc21
Normalized to 100 ; differential pairs at signal pins.
Fig 4. Mixed-mode differential and common-mode insertion loss; typical values
(1) Sdd21; Near End Crosstalk (NEXT)
(2) Sdd21; Far End Crosstalk (FEXT)
normalized to 100 ; differential pairs CH1/CH2 versus CH3/CH4
Fig 5. Mixed-mode dif fere nti al and common-mode NEXT / FEXT; typical values
018aaa086
f (Hz)
1061010
109
107108
–9
–3
3
Sdd21;
Scc21
(dB)
–15
(1)
(2)
018aaa087
f (Hz)
1061010
109
107108
–9
–3
3
Sdd21
(dB)
–15
(1)
(2)
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Product data sheet Rev. 5 — 24 June 2014 14 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
227 MHz pixel clock
Horizontal scale: 90 ps/div
Vertical scale: 200 mV/div
Offset: 42.6 mV
Fig 6. Eye diagram using IP4786CZ32 (1080p, 12 bit)
297 MHz pixel clock
Horizontal scale: 67.5 ps/div
Vertical scale: 200 mV/div
Offset: 42.6 mV
Fig 7. Eye diagram using IP4786CZ32 (1080p, 16 bit)
DDD
DDD
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Product data sheet Rev. 5 — 24 June 2014 15 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
148.5 MHz test frequency
Horizontal scale: 53.8 ps/div
Vertical scale: 200 mV/div
Measured at TP2 with worst cable emulator, reference cable equalizer and
worst case negative skew
Fig 8. Eye diagram using IP4786CZ32 (2160p, 60 Hz)
Deviation from typical capacitance normalized at Vbias =2.5V
Fig 9. Line capacitance as a function of bias voltage; typical values
aaa-013775
Vbias (V)
–1.0 7.05.01.0 3.0
018aaa090
0.0
–0.2
0.2
0.4
Cline
(pF)
–0.4
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Product data sheet Rev. 5 — 24 June 2014 16 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
IEC 61000-4-5; tp=8/20s; positive pulse IEC 61000-4-5; tp=8/20s; negative pulse
Fig 10. Dynamic resistance with positive clamping Fig 11. Dynamic resistance with negative clamping
tp= 100 ns; TLP; signal pins; typical values tp= 100 ns; TLP; signal pins; typical values
Fig 12. Dynamic resistance with positive clamping Fig 13. Dynamic resistance with negative clamping
I (A)
1.21.00.6 1.10.90.70.5 0.8
018aaa091
3.50
3.25
3.75
4.00
VCL
(V)
3.00
I (A)
0.4 1.21.00.6 0.8
018aaa092
1.5
2.0
2.5
VCL
(V)
1.0
VCL (V)
6221810 14
018aaa093
8
10
6
4
2
12
14
I
(A)
0
VCL (V)
–12 0–4–8
018aaa094
0
I
(A)
–14
–12
–10
–8
–6
–4
–2
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Product data sheet Rev. 5 — 24 June 2014 17 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
(1) 5.3 V; maximum values; HDMI CTS TID 7-11
(2) 4.8 V; minimum values; HDMI CTS TID 7-11
(3) I = 0 mA
(4) I = 55 mA
(5) VCC(5V0) supply input; 4.925 V to 6.5 V
(1) VCC(5V0) =4.5V
(2) VCC(5V0) =5.0V
(3) VCC(5V0) =5.5V
(4) VCC(5V0) =6.5V
Fig 14. Overvoltage limiter function (HDMI_5V0_CON) Fig 15. Overcurrent limiter function (HDMI_5V0_CON)
018aaa095
VCC(5V0) (V)
5.0 6.56.05.5
5.5
5.0
6.0
6.5
VI
(V)
4.5
(1)
(5)
(4)
(3)
(2)
IO (A)
0.00 0.04 0.08 0.12 0.140.100.060.02
018aaa096
2.0
4.0
6.0
VO
(V)
0.0
(1)
(4)
(3)
(2)
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Product data sheet Rev. 5 — 24 June 2014 18 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
8. AC waveforms
8.1 DDC propagation delay
Fig 16. Propagation delay DDC, DDC system side to DDC connector side
Fig 17. Propagation delay DDC, DDC connector side to DDC system side
018aaa097
DDC system side
DDC connector side
VCC(SYS)
0.5 V(HDMI_5V0_CON)
0.28 VCC(SYS)
VOL
VOL
0.5 V(HDMI_5V0_CON)
tPHL tPLH
0.5 VCC(SYS)
V(HDMI_5V0_CON)
018aaa098
DDC system side
DDC connector side
V
CC(SYS)
0.5 V
(HDMI_5V0_CON)
V
OL
V
OL
0.5 V
(HDMI_5V0_CON)
t
PHL
t
PLH
0.5 V
CC(SYS)
0.5 V
CC(SYS)
V
(HDMI_5V0_CON)
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Product data sheet Rev. 5 — 24 June 2014 19 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
8.2 DDC transition time
Fig 18. Transition time DDC connector side
Fig 19. Transition time DDC system side
018aaa100
DDC system side
DDC connector side
V
CC(SYS)
80 % V
CC(SYS)
20 % V
CC(SYS)
V
OL
V
OL
t
PHL
t
PLH
V
(HDMI_5V0_CON)
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Product data sheet Rev. 5 — 24 June 2014 20 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9. Application information
9.1 TMDS ESD
To protect the TMDS lines and also to comply with the impedance requirements of the
HDMI specification, the IP4786CZ32 provides ESD protection with matched
TLC ESD structures. Typical Dual Rail Clamp (DRC) or rail-to-rail shunt structures are
common for low-capacitance ESD protection (as shown on the left side of Figure 20)
where the dominant factor for the TMDS line impedance dip is determined by the
capacitive load to ground. Parasitic lead inductances of the packaging in this case works
against the ESD clamping performance by includ ing the I/t react ance of th e induct ance
into the path of the ESD shunt.
The IP4786CZ32 utilizes these inherent inductances in series with the transmission line in
order to present an effective capacitive load of roughly only 0.7 pF. This TLC structure
minimizes the capacitive dip, for ideal signal integrity (Figure 20; right side) without
complicated PCB pre-compensation. As a beneficial side effect, this enhances the
ESD performance of the device as well, since the reactance of the series inductance
attenuates the fast initial peak of the ESD pulse, for a lower residual pulse delivered to the
Application Specific Integrated Circuit (ASIC).
a. Classic parallel ESD shunt protection b. Improved series shunt TLC clamping
Fig 20. TLC ESD protection of TMDS lines
018aaa101
018aaa102
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Product data sheet Rev. 5 — 24 June 2014 21 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9.2 DDC circuit
The DDC bus circuit integrates all required pull-ups, and provides full capacitive
decoupling between the HDMI connector and the DDC bus lines on the PCB. The
capacitive decoupling ensures that the maximum capacitive load is well within the 50 pF
maximum of the HDMI specification. No extern al pull-ups or pull-downs are required.
The bidirectional buffers support high-capacitive load on the HDMI cable-side. Various
non-compliant but prevalent low-cost cab les have been observed with a capacitive loa d of
up to 6 nF on the DDC lines, far exceeding the 700 pF HDMI limit. The IP4786CZ32 can
easily decouple this from the weaker ASIC I/O buffers, and drive th e rogue cable
successfully.
a. DDC clock b. DDC data
Fig 21. DDC circuit
1.85 kΩ 3.65 kΩ
ESD_BYPASS
DDC_CLK_CON DDC_CLK_SYS
HDMI_5V0_CON VCC(SYS)
018aaa103
1.85 kΩ 3.65 kΩ
ESD_BYPASS
DDC_DAT_CON DDC_DAT_SYS
HDMI_5V0_CON V
CC(SYS)
018aaa104
(1) Valid I2C signaling example on the cable (connector side) from 5 V (HIGH) to approximately 1 V (LOW).
(2) Valid logic-level signaling example to the ASIC (system side) from 1.8 V (HIGH) to approximately 0.5 V (LOW).
Fig 22. DDC level shifting waveform example
5
4
3
2
1
0
time
V
(1)
(2)
018aaa105
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Product data sheet Rev. 5 — 24 June 2014 22 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9.3 Logic low I2C voltage shifter
The DDC buffers provide an additional feature commonly required for high-integration
HDMI ASICs which are limited to CMOS or LVTTL LOW-level input voltage (VIL) on thei r
available I/O buffer cells. These I/Os are not strictly compliant with the 0.3 VDD threshold
voltage levels of I2C and may miss intended logic low levels on the cable between 0.8 V
and 1.5 V (typical values).
This feature is also in cluded in the CEC buf fer, and thus allo ws standa rd I/O buf fer cells to
be used in ASICs and microcontrollers.
(1) VOL(max) driven to system (ASIC) side when I2C logic low (less than 0.3 HDMI_5V0_CON)
(2) VIH(min) threshold on system (ASIC) side to drive I2C logic high
(3) VIL(max) threshold on system (ASIC) side to drive I2C logic low
Fig 23. Logic voltage thresholds as a functio n of supply voltage on system side
018aaa106
VCC(SYS) (V)
1.6 5.64.63.62.6
0.5
0.7
0.9
VOL;VIH;
VIL
(V)
0.3
(1)
(3)
(2)
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Product data sheet Rev. 5 — 24 June 2014 23 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9.4 Hot plug detect circuit and HEAC support
The IP4786CZ32 includes a hot plug detect circuit that simplifies the hot plug ap plication .
The circuit generates a standard logic level from the hot plug signal.
The hot plug detect circuit is pulling down the signal to avoid any floating signal.
The comparator guarantees a save detection of the 2 V hot plug signal without any
glitches or oscillation at the hot plug output.
The IP4786CZ32 also provides an additional ESD pin to protect the reserved / HEAC pin
along with hot plug detect to 12 kV, exceeding IEC 61000-4-2 level 4.
9.5 CEC
The logical multidrop topology of the CEC bus can include complex physical stubs,
loading cables, and interconnects that may deteriorate signal quality.
The IP4786CZ32 includes a full bidirectional buffer to drive the CEC bus and isolate
the CEC microcontroller or ASIC General-Purpose Input/Output (GPIO).
The CEC buf fer derives power from an on- board 3.3 V regulator from the VCC(5V0) domain
(see Figure 25). This allows extensive system power management configurations and
guarantees an HDMI-compliant V(CEC_CON) on the connector, as well as the
backdrive-protected 125 A nominal CEC pull-up which does not degrade the bus when
powered down.
By placing the CEC microcontroller and VCC(5V0) input on a 5 V rail as shown in Figure 28,
the CEC microcontroller can communicate over CEC for power commands, and then
enable the HDMI port via the CEC_STBY pin, a s well as the re st of the system as needed.
If IP4786CZ32 Standby modes are not required, or if the Power-down modes are not
desired, the CEC_STBY pin ca n be pulled HIGH to V CC(5V0) or VCC(SYS) for continuous
HDMI and CEC operation.
Strapping the CEC_STBY = VCC(SYS) =V
DD of ASIC guarantees that all interface signals
ending with the suf fix “_SYS” on the system side will be disabled when VCC(SYS) goes low,
protecting the ASIC I/O signals from exceeding it s local VDD. In this mode, even if VCC(5V0)
is powered, HDMI_5V0_CON go active and hot plug events can be detected only when
the ASIC power supply rail is on.
Strapping CEC_STBY = VCC(5V0) is the most basic configuration where the buffers are
enabled whenever the local VCC(5V0) and VCC(SYS) supplies reach minimum operating
levels.
Fig 24. Hot plug detect circuit
100 kΩ 100 kΩ
ESD_BYPASS
HOTPLUG_DET_CON HOTPLUG_DET_SYS
V
CC(5V0)
018aaa107
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Product data sheet Rev. 5 — 24 June 2014 24 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9.6 Backdrive protection
The HDMI connector contains various signals which can partly supply current into an
HDMI device that is powered down.
Typically, the DDC lines and the CEC signals can force significant current back into the
powered-down rails as shown in Figure 26, causing power-on reset problems with the
system, and possible damage. The IP4786CZ32 prevents this backdrive condition
whenever the I/O voltage is greater than the local supply.
Fig 25. CEC module
V
CC(5V0)
10 kΩ
26 kΩ
ESD_BYPASS
CEC_CON CEC_SYS
V
CC(SYS)
3V3
018aaa108
Fig 26. Gener a lized backdrive protection
018aaa109
HDMI ASIC
HDMI source
supply off 5 V
backdrive current
I2C-bus ASIC
HDMI sink
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Product data sheet Rev. 5 — 24 June 2014 25 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9.7 55 mA overcurrent / overvoltage LDO function
The IP4786CZ32 integrates a complete linear output overcurrent protection to isolate
faults from the source power supply, while still meeting HDMI output specifications.
The Low DropOut (LDO) design provides a low-cost solution requiring just a single output
capacitor (1 F or higher , Equivalent Se ries Resistance (ESR) < 1 ), eliminating start-up
and ripple conce r ns (s ee Figure 27).
A typical 100 mV Vdo overcurren t-only solution would require a 5.1 V 3 % input supply to
guarantee 4.8 V to 5.3 V over 0 mA to 55 mA at the HDMI connector.
The overcurrent / overvoltage feature of the IP4786CZ32 allows the use of wider
tolerance input supplies up to 6.5 V while still meeting the 4.8 V-to-5.3 V output limit
required by HDMI. This means, for example, a cost-reduced 5.2 V 5 % or even
a5.5V10 % supply can be used with the IP4786CZ32.
As with all the I/O pins, this block is ESD-protected and also provides backdrive protection
when a rogue HDMI sink powers the HDMI cable unexpectedly.
Fig 27. 5 V LDO with overcurrent / overvoltage protection
ESD_BYPASS
HDMI_5V0_CON
018aaa110
DDC/HPD
buffers
60 mA
overcurrent
control
CEC
3V3
regulator
CEC
buffer
VCC(5V0)
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Product data sheet Rev. 5 — 24 June 2014 26 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9.8 Schematic view of application
Only a single external component (CO=1F) is required to protect and interface the
ASIC to a complete and compliant HDMI port. The 100 nF ESD bypass capacitor is
optional.
Fig 28. Schematic view of IP4786CZ32 application
CEC
μC
HDMI
CONNECTOR
HDMI
ASIC
IP4786CZ32
CEC_STBY CEC_SYS
28 29 26
24
23
22
21
20
19
18
17
25
15
16
13
12
14
PAD
4
5
6
7
8
9
10
32
1
2
3
11
27
UTILITY_CON
TMDS_D2+_CON
TMDS_D1+_CON
TMDS_D2–_CON
TMDS_D1–_CON
TMDS_D0+_CON
TMDS_D0–_CON
TMDS_CK+_CON
TMDS_CK–_CON
CEC_CON
DDC_CLK_CON
DDC_DAT_CON
HOTPLUG_DET_CON
HDMI_5V0_CON
DDC_CLK_SYS
DDC_DAT_SYS
HOTPLUG_DET_SYS
TMDS_D2+_SYS
TMDS_D1+_SYS
TMDS_D2–_SYS
TMDS_D1–_SYS
TMDS_D0+_SYS
TMDS_D0–_SYS
TMDS_CK+_SYS
TMDS_CK–_SYS
VDD
+1.62 V to 5.5 V
SUPPLY
+4.5 V to 6.5 V SUPPLY
CO1 μF
100 nF
ESD
bypass
(optional)
018aaa111
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Product data sheet Rev. 5 — 24 June 2014 27 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
9.9 Typical application
The IP4786CZ32 is designed to simplify routing to the HDMI connector, and ease the
incorporation of high-level ESD protection into delicately balanced high-speed
TMDS lines. These lines rely on tightly controlled micr ostrip or stri pline transmission lines
with minimal impedance discontinuities, which can deteriorate return loss, increase
deterministic jitter and generally erode overall link signal integrity.
Normally when designing the PCB with stan dard shunt ESD clamps, careful considera tion
must be given to manual pre-compensation of the additional load of the added
ESD component. With the IP4786CZ32 TLCs, the ESD suppressor is designed to
mainta in the char acteristic impedan ce of the PCB microstrip o r striplin e, and there fore the
designer needs only be concerned with the standard-controlled impedance of the
unloaded PCB lines. This simplifies the task of the PCB designer, and minimizes the
tuning cycles, which are sometimes required when pre-compensation misses the mark.
A basic application diagram for the ESD protection of an HDMI interface is shown in
Figure 29 and Figure 30 for type-A and type-D HDMI connector versions.
The optimized HVQFN32 pinning simplifies the PCB desig n to keep the ESD protection
close to the connector where it can minimize the coupling of th e ESD pulse onto other
lines in the system during a strike.
Due to the integrated pull-up and pull-down resistors, only two external capacitors are
required to implement a fully compliant HDMI port.
Fig 29. Application of the IP4786CZ32 showing optimized single-layer HDMI type-A
connector routin g
001aan367
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Product data sheet Rev. 5 — 24 June 2014 28 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
Fig 30. Application of the IP4786 CZ32 showing op timiz ed HDMI type-D conne ctor routing
001aan368
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Product data sheet Rev. 5 — 24 June 2014 29 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
10. Package outline
Fig 31. Package outline SOT617-3 (HVQFN32)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT617-3 MO-220
sot617-3_po
11-06-14
11-06-21
Unit(1)
mm
max
nom
min
0.85
0.05
0.00
0.2
5.1
4.9
3.75
3.45
5.1
4.9
3.75
3.45
0.5 3.5
A1
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm SOT617-3
bc
0.30
0.18
D(1)
A(1) DhE(1) Ehee
1e2L
3.5
vw
0.1 0.1
y
0.05
0.5
0.3
y1
0.05
0 2.5 5 mm
scale
1/2 e
AC B
v
Cw
terminal 1
index area
A
A1
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
916
32 25
24
17
8
1
X
D
E
C
BA
e2
terminal 1
index area
1/2 e
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Product data sheet Rev. 5 — 24 June 2014 30 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
11. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
11.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
11.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
11.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
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Product data sheet Rev. 5 — 24 June 2014 31 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
11.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 32) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and 12
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
Table 11. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 12. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
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Product data sheet Rev. 5 — 24 June 2014 32 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
12. Glossary
HDMI sink — Device which receives HDMI signals e.g. a TV set.
HDMI source — Device which transmit HDMI signal e.g. DVD player.
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
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Product data sheet Rev. 5 — 24 June 2014 33 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
13. Revision history
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
IP4786CZ32 v.5 20140624 Product data sheet - IP4786CZ32 v.4
Modifications: •Added support for HDMI 2.0 display modes; updated ESD robustne s s
IP4786CZ32 v.4 20120705 Product data sheet - IP4786CZ32 v.3
IP4786CZ32 v.3 20120608 Product data sheet - IP4786CZ32 v.2
IP4786CZ32 v.2 20120321 Product data sheet - IP4786CZ32 v.1
IP4786CZ32 v.1 20110415 Product data sheet - -
IP4786CZ32 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 June 2014 34 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
14.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liabili ty towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environme ntal
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Te rms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
IP4786CZ32 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 24 June 2014 35 of 36
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specificatio ns, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims result ing from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specificat ions.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors IP4786CZ32
DVI and HDMI interface ESD and overcurrent protection
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 June 2014
Document identifier: IP4786CZ32
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 4
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
7 Dynamic characteristics . . . . . . . . . . . . . . . . . 12
8 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1 DDC propagation delay . . . . . . . . . . . . . . . . . 18
8.2 DDC transition time . . . . . . . . . . . . . . . . . . . . 19
9 Application information. . . . . . . . . . . . . . . . . . 20
9.1 TMDS ESD. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.2 DDC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.3 Logic low I2C voltage shifter. . . . . . . . . . . . . . 22
9.4 Hot plug detect circuit and HEAC support . . . 23
9.5 CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.6 Backdrive protection. . . . . . . . . . . . . . . . . . . . 24
9.7 55 mA overcurrent / overvoltage LDO function 25
9.8 Schematic view of application . . . . . . . . . . . . 26
9.9 Typical application . . . . . . . . . . . . . . . . . . . . . 27
10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29
11 Soldering of SMD packages . . . . . . . . . . . . . . 30
11.1 Introductio n to soldering . . . . . . . . . . . . . . . . . 30
11.2 Wave and reflow soldering . . . . . . . . . . . . . . . 30
11.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 30
11.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 31
12 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 33
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 34
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15 Contact information. . . . . . . . . . . . . . . . . . . . . 35
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36