A6250V1PS16B - Swatch Group

R

A6250

High Efficiency Linear Power Supply with

Power Surveillance and Software Monitoring

Description

The A6250 offers a high level of integration by combining

voltage regulation, voltage monitoring and software

monitoring in a 16 lead package. The voltage regulator has

a low dropout voltage (typ. 260 mV at 250 mA) and a low

quiescent current (175 µA). The quiescent current increases

only slightly in dropout prolonging battery life. Built-in

protection includes a positive transient absorber for up to

60V (load dump) and the ability to survive an unregulated

input voltage of –20 V (reverse battery). The input may be

connected to ground or a reverse voltage without reverse

current flow from the output to the input. A comparator

monitors the voltage applied at the VIN input comparing it

with an internal 1.52 V reference. The power-on reset

function is initialized after VIN reaches 1.52 V and takes the

reset output inactive after TPOR depending of external

resistance. The reset output goes active low when the VIN

voltage is less than 1.52 V. The RES and EN outputs are

guaranteed to be in a correct state for a regulated output

voltage as low as 1.2 V. The watchdog function monitors

software cycle time and execution. If software clears the

watchdog too quickly (incorrect cycle time) or too slowly

(incorrect execution) it will cause the system to be reset.

The system enable output prevents critical control functions

being activated until software has successfully cleared the

watchdog three times. Such a security could be used to

prevent motor controls being energized on repeated resets

of a faulty system.

Features

 Highly accurate 5 V, 250 mA guaranteed output

 Low dropout voltage, typically 260 mV at 250 mA

 Low quiescent current, typically 175 µA

 Standby mode, maximum current 340 µA (with 100 µA

load on OUTPUT )

 Unregulated DC input can withstand –20 V reverse

battery and + 60 V power transients

 Fully operational for unregulated DC input voltage up to

40 V and regulated output voltage down to 3.0 V

 Reset output guaranteed for regulated output voltage

down to 1.2 V

 No reverse output current

 Very low temperature coefficient for the regulated output

 Current limiting

 Comparator for voltage monitoring, voltage reference

1.52 V

 Programmable reset voltage monitoring

 Programmable power on reset (POR ) delay

 Watchdog with programmable time windows guarantees

a minimum time and a maximum time between software

clearing of the watchdog

 Time base accuracy ± 10%

 System enable output offers added security

 TTL/CMOS compatible

 -40 to +125 °C temperature range

 PSOP2-16 package

Applications

 Industrial electronics

 Cellular telephones

 Security systems

 Battery powered products

 High efficiency linear power supplies

 Automotive electronics

Typical Operating Configuration

RES

EN

TCL

Fig. 1

Pin Assignment

VSS

R

PSOP2-16

OUTPUT

INPUT

RES

EN

TCL

VIN

A6250

NC

NC NC

NC

Fig. 2

EM MICROELECTRONIC - MARIN SA

R

A6250

Absolute Maximum Ratings

Parameter Symbol Conditions

Continuous voltage at INPUT

to VSS VINPUT - 0.3 to + 45V

Transients on INPUT for

t < 100 ms and duty cycle 1% VTRANS up to + 60V

Reverse supply voltage on

INPUT VREV - 20 V

Max. voltage at any signal pin VMAX OUTPUT + 0.3V

Min. voltage at any signal pin VMIN V

SS – 0.3V

Storage temperature TSTO - 65 to + 150 °C

Operating junction

temperature TJ max. 150 °C

Electrostatic discharge max.

to MIL-STD-883C method

3015.7 with ref. to VSS VSmax 1000V

Max. soldering conditions TSmax 250 °C x 10s

Max. output current IOUTPUTmax 300mA

Table 1

Stresses above these listed maximum ratings may cause

permanent damages to the device. Exposure beyond

specified operating conditions may affect device reliability or

cause malfunc tion.

Decoupling Methods

The input capacitor is necessary to compensate the line

influences. A resistor of approx. 1 Ω connected in series

with the input capacitor may be used to damp the oscillation

of the input capacitor and input inductivity. The ESR value

of the capacitor plays a major role regarding the efficiency of

the decoupling. It is recommended also to connect a

ceramic capacitor (100 nF) directly at the IC's pins. In

general the user must assure that pulses on the input line

have slew rates lower than 1 V/µs. On the output side, the

capacitor is necessary for the stability of the regulation

circuit. The stability is guaranteed for values of 22 µF or

bigger. It is especially important to choose a capacitor with

a low ESR value. Tantal capacitors are recommended.

See the notes related to Table 2. Special care must be

taken in disturbed environments (automotive, proximity of

motors and relays, etc.).

Handling Procedures

This device has built-in protection against high static

voltages or electric fields; however, it is advised that normal

precautions be taken as for any other CMOS component.

Unless otherwise specified, proper operation can only occur

when all terminal voltages are kept within the voltage range.

Unused inputs must always be tied to a defined logic

voltage level.

Operating Conditions

Parameter Symbol Min. Max. Units

Operating junction

temperature 1) TJ -40 +125 °C

INPUT voltage 2) VINPUT 2.3 40 V

OUTPUT voltage 2)3) V

OUTPUT 1.2 V

RES & EN guaranteed 4) VOUTPUT 1.2 V

OUTPUT current 5) I

OUTPUT 250 mA

Comparator input voltage VIN 0 VOUTPUT V

RC-oscillator programming

6) R 10 1000 kΩ

Thermal resistance from

junction to ambient 7)

- PSOP2-16 Rth(j-a) 30 90 °C/W

Table 2

1)

The maximum operating temperature is confirmed by

sampling at initial device qualification. In production, all

devices are tested at +125 °C.

2) Full operation guaranteed. To achieve the load regulation

specified in Table 3 a 22 µF capacitor or greater is

required on the INPUT, see Fig. 8. The 22 µF must have

an effective resistance ≤ 5 Ω and a resonant frequency

above 500 kHz.

3) A 10 µF load capacitor and a 100 nF decoupling capacitor

are required on the regulator OUTPUT for stability. The

10 µF must have an effective series resistance of ≤ 5 Ω

and a resonant frequency above 500 kHz.

4) RES must be pulled up externally to VOUTPUT even if it is

unused. (Note: RES and EN are used as inputs by EM

test).

5) The OUTPUT current will not apply for all possible

combinations of input voltage and output current.

Combinations that would require the A6250 to work above

the maximum junction temperature (+125 °C) must be

avoided.

6) Resistor values close to 1000 kΩ are not recommended

for applications working at 125 °C.

7) The thermal resistance specified assumes the package is

soldered to a PCB. The thermal resistance's value

depends on the PCB's structure. A typical value of 51

°C/W has been obtained with a dual layer board, with the

slug soldered to the heat-sink area of the PCB (see Fig.

22).

R

A6250

Electrical Characteristics

VINPUT = 6.0 V, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to +125 °C, unle ss oth erwise specified

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Supply current in standby mode ISS R

EXT = don’t care, TCL = VOUTPUT,

VIN = 0 V, IL = 100 µA 140 340 µA

Supply current 1) ISS R

EXT = 100 kΩ, I/PS at VOUTPUT,

O/PS 1 MΩ to VOUTPUT, IL = 100 µA 175 400 µA

Supply current 1) ISS R

EXT = 100 kΩ, I/PS at VOUTPUT,

VINPUT =8.0 V, O/PS 1 MΩ to VOUTPUT,

IL = 100 mA

1.7

4.2

mA

I

L = 250 mA 7 15 mA

Output voltage VOUTPUT I

L = 100 µA 4.85 5.15 V

Output voltage VOUTPUT 100 µA ≤ IL ≤ 250 mA, 4.85 5.15 V

Output voltage temperature

coefficient 2) Vth(coeff) 100 ppm/°C

Line regulation 3) VLINE 6 V ≤ VINPUT ≤35 V, IL = 1 mA, TJ = +125 °C 0.2 0.8 %

Load regulation 3) V

L 100 µA ≤ IL ≤ 100 mA 0.2 0.7 %

Load regulation 3) V

L 5 mA ≤ IL ≤ 250 mA 0.9 1.45 %

Dropout voltage 4) V

DROPOUT I

L = 100 µA 40 170 mV

Dropout voltage 4) V

DROPOUT I

L = 100 mA 160 380 5) mV

Dropout voltage 4) V

DROPOUT I

L = 250 mA 260 650 mV

Dropout supply current ISS V

INPUT = 4.5 V, IL = 100 µA,

REXT = 100 kΩ, O/PS 1 MΩ to

VOUTPUT, I/PS at VOUTPUT

1.2 1.8 mA

Current limit ILmax OUTPUT tied to VSS 450 mA

OUTPUT noise, 10Hz to 100kHz VNOISE 200 µV rms

4.5 ≤ VOUTPUT ≤ 5.5 V, IL = 100 µ A, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to +125 °C, unless otherwise specified

RES & EN

Output Low Voltage VOL V

OUTPUT = 4.5 V, IOL= 20 mA 0.4 V

V

OL V

OUTPUT = 4.5 V, IOL = 8 mA 0.2 0.4 V

V

OL V

OUTPUT = 2.0 V, IOL = 4 mA 0.2 0.4 V

V

OL V

OUTPUT = 1.2 V, IOL = 0.5 mA 0.06 0.2 V

EN

Output High Voltage VOH V

OUTPUT = 4.5 V, IOH= -1 mA 3.5 4.1 V

V

OH V

OUTPUT = 2.0 V, IOH= -100 µA 1.8 1.9 V

V

OH V

OUTPUT = 1.2 V, IOH= -30 µA 1.0 1.1 V

TCL and VIN

TCL Input Low Level VIL V

SS 0.8 V

TCL Input High Level VIH 2.0 VOUTPUT V

Leakage current TCL input ILI V

SS ≤ VTCL ≤ VOUTPUT 0.05 1 µA

VIN input resistance RVIN 100 MΩ

Comparator reference 6)7) VREF T

J = +25 °C 1.474 1.52 1.566 V

V

REF 1.436 1.620 V

V

REF -40 °C ≤TJ ≤+125 °C 1.420 1.620 V

Comparator hysteresis 7) V

HY 2 mV

Table 3

1) If INPUT is connected to VSS, no reverse current will flow from the OUTPUT to the INPUT, however the supply current s pecified will be sank

by the OUTPUT to supply the A6250.

2) The OUTPUT volt age temperature coefficient is defined as the worst case voltage change divided by the total temperature range.

3) Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in OUTPUT voltage due to

heating effect s are covered i n t h e specificat i on for thermal regulation.

4) The dropout vol t age is defi ned as the INPUT to OUTPUT differential, measured with t he input voltage equal to 5.0 V.

5) Not tested

6) The c omparator and the voltage regulator have separate voltage ref erences (see “Block Diagram” Fig. 7).

7) The comparator reference i s the power-down res et t hreshol d. The power-on reset t hreshol d equals the comparat or referenc e voltag e plus the

comparator hysteresis (see Fig. 4).

R

A6250

Timing Characteristics

VINPUT = 6.0 V, IL = 100 µA, CL = 10 µF + 100 nF, CINPUT = 22 µF, TJ = -40 to + 125 °C, unless otherwise specified

Parameter Symbol Test Conditions Min. Typ. Max. Units

Propagation delays:

TCL to Output Pins TDIDO 250 500 ns

VIN sensitivity TSEN 1 5 20 µs

Logic Transition Times on all Output Pins TTR Load 10 kΩ, 50 pF 30 100 ns

Power-on Reset delay TPOR R

EXT = 123 kΩ ±1% 90 100 110 ms

Watchdog Time TWD R

EXT = 123 kΩ ±1% 90 100 110 ms

Open Window Percentage O WP ±0.2 TWD

Closed Window Time TCW 0.8 TWD

T

CW R

EXT = 123 kΩ ±1% 72 80 88 ms

Open Win dow Time TOW 0.4 TWD

T

OW R

EXT = 123 kΩ ±1% 36 40 44 ms

Watchdog Reset Pulse TWDR T

WD/40

T

WDR R

EXT = 123 kΩ ±1% 2.5 ms

TCL Input Pulse Width TTCL 150 ns

Table 4

Timing Waveforms

Watchdog Timeout Period

Fig. 3

Voltage Monitoring

Fig. 4

TSEN TSEN TSEN TSEN

TPOR TPOR

RES

VIN

VREF

VHY Conditions:

VOUTPUT ≥ 3 V

No timeout

Fig. 4

R

A6250

Timer Reaction

Fig. 5

Combined Voltage and Timer Reaction

Fig. 6

Block Diagram

RES

EN

TCL

Voltage

Regulator

Voltage

Reference

Voltage

Reference

Current

Controlled

Oscillator

-

+

VREF Comparator Reset

Control

Timer

Enable

Logic

INPUT

VIN

R

OUTPUT

Open dr ain

output RES

Fig. 7

R

A6250

Pin Description

Pin Name Function

2 EN Push-pull active low enable output

3 RES Open drain active low reset output.

RES must be pulled up to VOUTPUT

even if unused

4 TCL Watchdog timer clear input signal

5 VSS GND terminal

12 INPUT Voltage regulator input

13 OUTPUT Voltage regulator output

14 R REXT input for RC oscillator tuning

15 VIN Voltage comparator input Table 5

Functional Description

Voltage Regulator

The A6250 has a 5 V ± 2%, 250 mA, low dropout voltage

regulator. The low supply current (typ.155 µA) makes the

A6250 particularly suited to automotive systems then remain

energized 24 hours a day. The input voltage range is 2.3 V

to 40 V for operation and the input protection includes both

reverse battery (20 V below ground) and load dump

(positive transients up to 60 V). There is no reverse current

flow from the OUTPUT to the INPUT when the INPUT

equals VSS. This feature is important for systems which

need to implement (with capacitance) a minimum power

supply hold-up time in the event of power failure. To achieve

good load regulation a 22 µF capacitor (or greater) is

needed on the INPUT (see Fig. 8). Tantalum or aluminium

electrolytics are adequate for the 22 µF capacitor; film types

will work but are relatively expensive. Many aluminium

electrolytics have electrolytes that freeze at about –30 °C,

so tantalums are recommended for operation below –25 °C.

The important parameters of the 22 µF capacitor are an

effective series resistance of ≤ 5 Ω and a resonant

frequency above 500 kHz.

A 10 µF capacitor (or greater) and a 100 nF capacitor are

required on the OUTPUT to prevent oscillations due to

instability. The specification of the 10 µF capacitor is as per

the 22 µF capacitor on the INPUT (see previous paragraph).

The A6250 will remain stable and in regulation with no

external load and the dropout voltage is typically constant as

the input voltage fall to below its minimum level (see Table

2). These features are especially important in CMOS RAM

keep-alive applications.

Care must be taken not to exceed the maximum junction

temperature (+ 125 °C). The power dissipation within the

A6250 is given by the formula:

PTOTAL = (VINPUT – VOUTPUT) * IOUTPUT + (VINPUT) * ISS

The maximum continuous power dissipation at a given

temperature can be calculated using the formula:

P

MAX = ( 125 °C – TA) / Rth(j-a)

where Rth(j-a) is the thermal resistance from the junction to

the ambient and is specified in Table 2. Note the Rth(j-a)

given in Table 2 assumes that the package is soldered to a

PCB. The above formula for maximum power dissipation

assumes a constant load (ie.≥100 s). The transient thermal

resistance for a single pulse is much lower than the

continuous value.

VIN Monitoring

The power-on reset and the power-down reset are

generated as a response to the external voltage level

applied on the VIN input. The external voltage level is

typically obtained from a voltage divider as shown on Fig. 8.

The user uses the external voltage divider to set the desired

threshold level for power-on reset and power-down reset in

his system. The internal comparator reference voltage is

typically 1.52 V.

At power-up the reset output (RES ) is held low (see Fig. 4).

After INPUT reaches 3.36 V (and so OUTPUT reaches at

least 3 V) and VIN becomes greater than VREF, the RES

output is held low for an additional power-on-reset (POR)

delay which is equal to the watchdog time TWD (typically 100

ms with an external resistor of 123 kΩ connected at R pin).

The POR delay prevents repeated toggling of RES even if

VIN and the INPUT voltage drops out and recovers. The

POR delay allows the microprocessor’s crystal oscillator

time to start and stabilize and ensures correct recognition of

the reset signal to the micr opr ocessor.

The RES output goes active low generating the power-

down reset whenever VIN falls below VREF. The sensitivity or

reaction time of the internal comparator to the vol-tage level

on VIN is typically 5 µs.

Timer Programming

The on-chip oscillator with an external resistor REXT

connected between the R pin and VSS (see Fig. 8) allows

the user to adjust the power-on reset (POR) delay,

watchdog time TWD and with this also the closed and open

time windows as well as the watchdog reset pulse width

(TWD/40).

With REXT = 123 kΩ typical values are:

-Power-on reset delay: TPOR is 100 ms

-Watchdog time: TWD is 100 ms

-Closed window: TCW is 80 ms

-Open window: TOW is 40 ms

-Watchdog reset: TWDR is 2.5 ms

Note the current consumption increases as the frequency

increases.

R

A6250

Watchdog Timeout Period Description

The watchdog timeout period is divided into two parts, a

“closed” window and an “open” window (see Fig. 3) and is

defined by two parameters, TWD and the Open Window

Percentage (OWP).

The closed window starts just after the watchdog timer

resets and is defined by TCW = TWD – OWP(TWD).

The open window starts after the closed time window

finishes and lasts till TWD + OWP(TWD).The open window

time is defined by TOW = 2 x OWP (TWD)

For example if TWD = 100 ms (actual value) and OWP = ±

20% this means the closed window lasts during first the

80 ms (TCW = 80 ms = 100ms – 0.2 (100 ms)) and the open

window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40 ms).

The watchdog can be serviced between 80 ms and 120 ms

after the timer reset. However as the time base is ± 10%

accurate, software must use the following calculation as the

limits for servici ng sig nal TCL during the open window:

Related to curves (Fig. 10 to Fig. 20), especially Fig. 19 and

Fig. 20, the relation between TWD and REXT could easily be

defined. Let us take an example describing the variations

due to producti on and temperature:

1. Choice, TWD = 26 ms.

2. Related to Fig. 20, the coefficient (TWD to REXT) is 1. 125

where REXT is in kΩ and TWD in ms.

3. REXT (typ.) = 26 x 1.155 = 30.0 kΩ.

4. The ratio between TWD = 26 ms and the ( TCL period)

= 25.4 ms is 0.975.

Then the relation over the production and the full

temperature range is,

TCL period = 0.975 x TWD 0.975 x REXT or

TCL period = 1.155

R x 0.975 EXT , as typical value.

a) ±10% while PRODUCTION value unknown for the

customer when REXT ≠ 123 kΩ.

b) ±5% while operating TEMPERATURE range

-40 °C ≤ TJ ≤ +125 °C.

5. If you fixed a TCL period = 26 ms

⇒ REXT = 0.975

1.155 x 26 = 30.8 kΩ.

If during your production the TWD time can be measured at

TJ = + 25 °C and the µC can adjust the TCL period, then

the TCL period range will be much larger for the full

operating temperat ure.

TWD versus VOUTPUT at TJ = +25 °C

Fig. 8

TWD versus R at TJ = +25 °C

Fig. 9

10’000

1000

100

10

1 3 4 5

VOUTPUT [V]

TWD [ms]

6

R

=

10 M

Ω

R = 1 MΩ

R = 100 kΩ

R

=

10 k

Ω

R = 1 kΩ

0.1 110 100 1000 10’000

1

10

100

1000

10’000

TWD [ms]

R[kΩ]

3 V

4.8 V

5 V

5.2 V

6 V

R

A6250

TWD versus R at TJ = +25 °C

Fig. 10

1

10

100

1000

TWD [ms]

0

.1 1 10 100 1000 10’000

R[kΩ]

3 V

4.8 V

5 V

5.2 V

6 V

10’000

R

A6250

TWD versus VOUTPUT at TJ = +85 °C TWD versus R at TJ = +85 °C

Fig. 11 Fig. 12

TWD versus VOUTPUT at TJ = -40 °C TWD versus R at TJ = -40 °C

Fig. 13 Fig. 14

0.1 10 100 1000 10’000

1

10

100

1000

10’000

TWD [ms]

R[kΩ]

1

3 V

4.8 V

5 V

5.2 V

6 V

10’000

1000

100

10

1 3 4 5

V

OUTPUT

[

V

]

TWD [ms]

6

R = 10 MΩ

R = 1 MΩ

R = 100 kΩ

R = 10 kΩ

R = 1 kΩ

10’000

1000

100

10

1 3 4 5

V

OUTPUT

[

V

]

TWD [ms]

6

R = 10 MΩ

R = 1 MΩ

R = 100 kΩ

R = 10 kΩ

R = 1 kΩ

0.1 10 100 1000 10’000

1

10

100

1000

1

R[kΩ]

0.1

TWD [ms]

3 V

4.8 V

5 V

5.2 V

6 V

10'000

R

A6250

TWD versus temperature at 5 V T WD versus R at 5 V

Fig. 15 Fig. 16

Maximum OUTPUT Current versus INPUT Voltage

Fig. 17

10’000

1000

100

10

1

-40 0 +40

TJ [°C]

TWD [ms]

+80

R = 10 MΩ

-20 +20 +60

R = 1 MΩ

R = 100 kΩ

R = 10 kΩ

R = 1 kΩ

0.1 10 100 1000 10’000

1

10

100

1000

10’000

TWD [ms]

R[kΩ]

1

-40 °C

-20 °C

+25 °C

+70 °C

+85 °C

R

A6250

Timer Clearing and RES Action

The watchdog circuit monitors the activity of the processor.

If the user’s software does not send a pulse to the TCL

input within the programmed open window timeout period a

short watchdog RES pulse is generated which is equal to

TWD /40 = 2.5 ms typically (see Fig. 5).

With the open window constraint new security is added to

conventional watchdogs by monitoring both software cycle

time and execution. Should software clear the watchdog too

quickly (incorrect cycle time) or too slowly (incorrect

execution) it will cause the system to be reset. If software is

stuck in a loop which includes the routine to clear the

watchdog then a conventional watchdog would not make a

system reset even though software is malfunctioning; the

A6250 would make a system reset because the watchdog

would be cleared too quickly.

If no TCL signal is applied before the closed and open

windows expire, RES will start to generate square waves of

period (TCW + TOW + TWDR). The watchdog will remain in this

state until the next TCL falling edge appears during an

open window, or until a fresh power-up sequence. The

system enable output, EN , can be used to prevent critical

control functions being activated in the event of the system

going into this failure mode (see section “Enable-EN

Output”).

The RES output must be pulled up to VOUTPUT even if the

output is not used by the system (see Fig 8).

Combined Voltage and Timer Action

The combination of voltage and timer actions is illustrated by

the sequence of events shown in Fig. 6. On power-up, when

the voltage at VIN reaches VREF, the power-on-reset, POR,

delay is initialized and holds RES active for the time of the

POR delay. A TCL pulse will have no effect until this

power-on-reset delay is completed. After the POR delay has

elapsed, RES goes inactive and the watchdog timer starts

acting. If no TCL pulse occurs, RES goes active low for a

short time TWDR after each closed and open window period.

A TCL pulse coming during the open window clears the

watchdog timer. When the TCL pulse occurs too early

(during the closed window), RES goes active and a new

timeout sequence starts. A voltage drop below the VREF level

for longer than typically 5µs overrides the timer and

immediately forces RES active and EN inactive. Any

further TCL pulse has no effect until the next power-up

sequence has completed.

Enable - EN Output

The system enable output, EN ,is inactive always when

RES is active and remains inactive after a RES pulse until

the watchdog is serviced correctly 3 consecutive times (ie.

the TCL pulse must come in the open window). After three

consecutive services of the watchdog with TCL during the

open window, the EN goes active low.

A malfunctioning system would be repeatedly reset by the

watchdog. In a conventional system critical motor controls

could be energized each time reset goes inactive (time

allowed for the system to restart) and in this way the

electrical motors driven by the system could function out of

control. The A6250 prevents the above failure mode by

using the EN output to disable the motor controls until

software has successfully cleared the watchdog three times

(ie. the system has correctly re-started after a reset

condition).

Typical Appl ication

Fig. 18

INPUT OUTPUT

A6250

R

VSS

22

µ

F

+

Regulated voltage

Unregulated voltage

GND

100 kΩ

100 nF

10

µ

FR1

R2

Address

decoder

Microprocessor

RES

EN

VIN

TCL

RE

S

EN

100 kΩ

Motor

Controls

R

A6250

TWD Coefficient versus REXT at TJ = + 25 °C

Fig. 19

REXT Coefficient versus TWD at TJ = + 25 °C

Fig. 20

0.96

0.94

0.92

0.90

0.88

0.86

0.84

0.82

0.80

0.78

0.76

TWD Coefficient

10 1000

100

REXT

[

kΩ

]

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

1.12

1.10

1.08

1.06

1.04

REXT Coefficient

10 100 1000

TWD [ms]

R

A6250

Package and Ordering Information

Dimensions of PSOP2-16 Package

Fig. 21

Dual Layer PCB

Fig. 22

Ordering Information

When ordering, plea se sp eci fy the complet e part number.

Part Number Package Delivery Form Package Marking

(first line)

A6250V1PS16B 16-pin PSOP2 Tape & Reel A62500116W

EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an

EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without

notice at any tim e. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.