FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO Data Sheet 1.0 Features * Very low phase noise PLL * Use with "pullable" 14pF crystals - no external padding capacitors required * Small circuit board footprint (8-pin 0.150" SOIC) * Custom frequency selections available - contact your local AMIS Sales Representative for more information * Phase-locked loop (PLL) device synthesizes output clock frequency from crystal oscillator or external reference clock * On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning * Typically used for generation of MPEG-2 decoder clock * 3.3V supply voltage 2.0 Description A high-resolution phase-locked loop generates an output clock (CLK) through a post-divider. The CLK frequency is ratiometrically derived from the VCXO frequency. The locking of the CLK frequency to other system reference frequencies can eliminate unpredictable artifacts in video systems and reduce electromagnetic interference (EMI) due to frequency harmonic stacking. The FS6128 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems. At the core of the FS6128 is circuitry that implements a voltage-controlled crystal oscillator (VCXO) when an external resonator (nominally 13.5MHz) is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. Table 1: Crystal / Output Frequencies Device FS6128-04 fXIN (MHz) 13.500 CLK (MHz) 27.000 Note: Contact AMIS for custom PLL frequencies. Figure 1: Pin Configuration Figure 2: Block Diagram AMI Semiconductor www.amis.com 1 FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO Data Sheet Table 2: Pin Descriptions Pin 1 2 3 4 5 6 7 8 Type AI P AI P DO DO AO Name XIN VDD XTUNE VSS CLK n/c VSS XOUT Description VCXO Feedback Power Supply (+3.3V) VCXO Tune Ground Clock Output No Connection Ground VCXO Drive Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input With Internal PullUp; DID = Input With Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low Pin 3.0 Functional Block Diagram EXAMPLE: A crystal with the following parameters is used: C 1 = 0.025pF and C 0 = 6pF. Using the minimum and maximum CL1 = 10pF, and CL2 = 20pF, the tuning range (peak-to-peak) is: 3.1 Voltage-Controlled Crystal Oscillator (VCXO) The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6128 system components. Loading capacitance for the crystal is internal to the FS6128. No external components (other than the resonator itself) are required for operation of the VCXO. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The value of this voltage controls the effective capacitance presented to the crystal. The actual amount that this load capacitance change will alter the oscillator frequency depends on the characteristics of the crystal as well as the oscillator circuit itself. 3.2 Phase-Locked Loop (PLL) The on-chip PLL is a standard frequency- and phaselocked loop architecture. The PLL multiplies the reference oscillator frequency to the desired output frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (unless otherwise specified). It is important that the crystal load capacitance is specified correctly to "center" the tuning range. See Table 5. A simple formula to obtain the "pulling" capability of a crystal oscillator is: where: C0 = the shunt (or holder) capacitance of the crystal C1 = the motional capacitance of the crystal CL1 and CL2 = the two extremes (minimum and maximum) of the applied load capacitance presented by the FS6128. AMI Semiconductor www.amis.com 2 FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO Data Sheet 4.0 Electrical Specifications Table 3: Absolute Maximum Ratings Parameter Supply Voltage (VSS = ground) Input Voltage, DC Output Voltage, DC Input Clamp Current, DC (VI < 0 or VI > VDD) Output Clamp Current, DC (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Reflow Solder Profile Symbol VDD VI VO IIK IOK TS TA TJ Min VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 Max 7 VDD+0.5 VDD+0.5 50 50 150 125 125 Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 Units V V V mA mA C C C per IPC/JEDEC J-STD-020B kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a highenergy electrostatic discharge. Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability. Table 4: Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Symbol VDD TA fXTAL Conditions/Descriptions 3.3V 10% 0 Fundamental Mode Min 3.0 Typ. 3.3 12 13.5 Max 3.6 70 18 Units V C MHz Max Units Table 5: DC Electrical Specifications Parameter Symbol Conditions/Descriptions Min Typ. Overall Supply Current, Dynamic, With Loaded Outputs IDD fXTAL = 13.5MHz; CL = 10pF, VDD = 3.6V 30 Supply Current, Static IDD XIN = 0V, VDD = 3.6V 3 Voltage-Controlled Crystal Oscillator (contact factory for approved crystal sources or other application assistance) Crystal Loading Capacitance at Center Order crystal for this capacitance (parallel CL(xtal) Tuning Voltage load) at desired center frequency 14 Specified motional capacitance of the Crystal Resonator Motional Capacitance C1 crystal will affect pullability (see text) 25 XTUNE Effective Range 0 Synthesized Load Capacitance Min. CL1 @V(XTUNE)=minimum value 10 Synthesized Load Capacitance Max. CL2 @V(XTUNE)=maximum value 20 fXTAL = 13.5MHz; CL(xtal) = 14pF; VCXO Tuning Range 300 C1(xtal) = 25fF (peak-to-peak) Note: positive change of XTUNE = VCXO Tuning Characteristic 150 positive change of VCXO frequency Crystal Drive Level RXTAL=20; CL = 20pF 200 Clock Output (CLK) High-Level Output Source Current * IOH VO = 2.0V -40 Low-Level Output Sink Current * IOL VO = 0.4V 17 zOH VO = 0.1VDD; output driving high 25 Output Impedance * zOL VO = 0.1VDD; output driving low 25 Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max -55 Short Circuit Sink Current * IOSL VO = 3.3V; shorted for 30s, max 55 Note: Unless otherwise stated VDD = 3.3V 10% no load on any output and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk (*) represent nominal characterization data AMI Semiconductor www.amis.com mA mA pF 3 fF V pF pF ppm ppm/V W mA mA mA mA and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. 3 FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO Data Sheet Table 6: AC Timing Specifications Parameter Symbol Conditions/Descriptions tVCXOSTB tPLLSTB From power valid From VCXO stable (Unless otherwise noted in frequency table) Min Typ. Max Units Overall VCXO Stabilization Time * PLL Stabilization Time * Synthesis Error Clock Output (CLK) Duty Cycle * Jitter, Period (peak-peak) * tj(P) Jitter, Long Term (y() * tj(LT) Rise Time * Fall Time * tr tf Ratio of high pulse width (as measured from rising edge to next falling edge at VDD/2) to one clock period From rising edge to next rising edge at VDD/2, CL =10pF 200 ps From 0-500s at VDD/2, CL = 10pF compared to ideal clock source VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF Note: Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk (*) represent nominal 10 100 0 45 ms s ppm 55 % 200 ps 100 ps 1.7 1.7 ns ns characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. 5.0 Package Information - For Both `Green' and `Non-Green' Table 7: 8-pin SOIC (0.150") Package Dimensions Table 8: 8-pin SOIC (0.150") Package Characteristics Parameter Symbol Conditions/Descriptions Typ. Units Thermal Impedance, Junction to Free-Air 8-pin 0.150" SOIC JA Air flow = 0 m/s 110 C/W Lead Inductance, Self L11 Lead Inductance, Mutual Lead Capacitance, Bulk L12 C11 Corner lead Center lead Any lead to any adjacent lead Any lead to VSS 2.0 1.6 0.4 0.27 AMI Semiconductor www.amis.com 4 nH nH pF FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO Data Sheet 6.0 Ordering Information Table 9: Device Ordering Codes Ordering Code Device Number 11640-825 FS6128-04 11640-892 FS6128-04g Package Type 8-pin (0.150") SOIC (Small Outline Package) 8-pin (0.150") SOIC (Small Outline Package) `Green'or Lead-Free Packaging Operating Temperature Range Shipping Configuration 0C to 70C (Commercial) Tape and Reel 0C to 70C (Commercial) Tape and Reel AMI Semiconductor www.amis.com (c) Copyright 2004 AMI Semiconductor - All rights reserved. Information furnished is believed to be accurate and reliable. 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