11640-825 - ON Semiconductor L.L.C.

• Phase-locked loop (PLL) device synthesizes output clock

frequency from crystal oscillator or external reference

clock

• On-chip tunable voltage-controlled crystal oscillator

(VCXO) allows precise system frequency tuning

• Typically used for generation of MPEG-2 decoder clock

• 3.3V supply voltage

• Very low phase noise PLL

• Use with “pullable” 14pF crystals – no external padding

capacitors required

• Small circuit board footprint (8-pin 0.150” SOIC)

• Custom frequency selections available - contact your local

AMIS Sales Representative for more information

1.0 Features

The FS6128 is a monolithic CMOS clock generator IC

designed to minimize cost and component count in digital

video/audio systems.

At the core of the FS6128 is circuitry that implements a

voltage-controlled crystal oscillator (VCXO) when an

external resonator (nominally 13.5MHz) is attached. The

VCXO allows device frequencies to be precisely adjusted

for use in systems that have frequency matching

requirements, such as digital satellite receivers.

A high-resolution phase-locked loop generates an output

clock (CLK) through a post-divider. The CLK frequency is

ratiometrically derived from the VCXO frequency. The

locking of the CLK frequency to other system reference

frequencies can eliminate unpredictable artifacts in video

systems and reduce electromagnetic interference (EMI) due

to frequency harmonic stacking.

2.0 Description

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FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO

Data Sheet

Figure 1: Pin Configuration

Figure 2: Block Diagram

Note: Contact AMIS for custom PLL frequencies.

Table 1: Crystal / Output Frequencies

Device fXIN (MHz) CLK (MHz)

FS6128-04 13.500 27.000

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3.0 Functional Block Diagram

Table 2: Pin Descriptions

Pin Type Name Description

1 AI XIN VCXO Feedback

2 P VDD Power Supply (+3.3V)

3 AI XTUNE VCXO Tune

4 P VSS Ground

5 DO CLK Clock Output

6 - n/c No Connection

7 DO VSS Ground

8 AO XOUT VCXO Drive

FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO

Data Sheet

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU= Input With Internal Pull-

Up; DID= Input With Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital

Input, DO = Digital Output; P = Power/Ground; # = Active Low Pin

3.1 Voltage-Controlled Crystal Oscillator (VCXO)

The VCXO provides a tunable, low-jitter frequency

reference for the rest of the FS6128 system components.

Loading capacitance for the crystal is internal to the

FS6128. No external components (other than the resonator

itself) are required for operation of the VCXO.

Continuous fine-tuning of the VCXO frequency is

accomplished by varying the voltage on the XTUNE pin.

The value of this voltage controls the effective capacitance

presented to the crystal. The actual amount that this load

capacitance change will alter the oscillator frequency

depends on the characteristics of the crystal as well as the

oscillator circuit itself.

It is important that the crystal load capacitance is specified

correctly to “center” the tuning range. See Table 5.

A simple formula to obtain the “pulling” capability of a

crystal oscillator is:

where:

C0= the shunt (or holder) capacitance of the crystal

C1= the motional capacitance of the crystal

CL1 and CL2 = the two extremes (minimum and maximum)

of the applied load capacitance presented by the

FS6128.

EXAMPLE: A crystal with the following parameters is used:

C1= 0.025pF and C0= 6pF. Using the minimum and

maximum CL1 = 10pF, and CL2 = 20pF, the tuning range

(peak-to-peak) is:

3.2 Phase-Locked Loop (PLL)

The on-chip PLL is a standard frequency- and phaselocked

loop architecture. The PLL multiplies the reference oscillator

frequency to the desired output frequency by a ratio of

integers. The frequency multiplication is exact with a zero

synthesis error (unless otherwise specified).

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4.0 Electrical Specifications

Parameter Symbol Min Max Units

Supply Voltage (VSS = ground) VDD VSS-0.5 7 V

Input Voltage, DC VIVSS-0.5 VDD+0.5 V

Output Voltage, DC VOVSS-0.5 VDD+0.5 V

Input Clamp Current, DC (VI< 0 or VI> VDD) IIK -50 50 mA

Output Clamp Current, DC (VI< 0 or VI> VDD) IOK -50 50 mA

Storage Temperature Range (non-condensing) TS-65 150 °C

Ambient Temperature Range, Under Bias TA-55 125 °C

Junction Temperature TJ125 °C

Reflow Solder Profile per IPC/JEDEC

J-STD-020B

Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV

Table 3: Absolute Maximum Ratings

Parameter Symbol Conditions/Descriptions Min Typ. Max Units

Supply Voltage VDD 3.3V ± 10% 3.0 3.3 3.6 V

Ambient Operating Temperature Range TA0 70 °C

Crystal Resonator Frequency fXTAL Fundamental Mode 12 13.5 18 MHz

Table 4: Operating Conditions

Parameter Symbol Conditions/Descriptions Min Typ. Max Units

Overall

Supply Current, Dynamic, With Loaded Outputs IDD fXTAL = 13.5MHz; CL= 10pF, VDD = 3.6V 30 mA

Supply Current, Static IDD XIN = 0V, VDD = 3.6V 3 mA

Voltage-Controlled Crystal Oscillator (contact factory for approved crystal sources or other application assistance)

Crystal Loading Capacitance at Center Order crystal for this capacitance (parallel

Tuning Voltage CL(xtal) load) at desired center frequency 14 pF

Crystal Resonator Motional Capacitance C1Specified motional capacitance of the

crystal will affect pullability (see text) 25 fF

XTUNE Effective Range 0 3 V

Synthesized Load Capacitance Min. CL1 @V(XTUNE)=minimum value 10 pF

Synthesized Load Capacitance Max. CL2 @V(XTUNE)=maximum value 20 pF

VCXO Tuning Range fXTAL = 13.5MHz; CL(xtal) = 14pF; 300 ppm

C1(xtal) = 25fF (peak-to-peak)

VCXO Tuning Characteristic Note: positive change of XTUNE = 150 ppm/V

positive change of VCXO frequency

Crystal Drive Level RXTAL=20Ω; CL= 20pF 200 µW

Clock Output (CLK)

High-Level Output Source Current * IOH VO= 2.0V -40 mA

Low-Level Output Sink Current * IOL VO= 0.4V 17 mA

Output Impedance * zOH VO= 0.1VDD; output driving high 25 Ω

zOL VO= 0.1VDD; output driving low 25

Short Circuit Source Current * IOSH VO= 0V; shorted for 30s, max -55 mA

Short Circuit Sink Current * IOSL VO= 3.3V; shorted for 30s, max 55 mA

Table 5: DC Electrical Specifications

FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO

Data Sheet

Note: Stresses above those listed under Absolute Maximum

Ratings may cause permanent damage to the device. These

conditions represent a stress rating only and functional

operation of the device at these or any other conditions

above the operational limits noted in this specification is not

implied. Exposure to maximum rating conditions for extended

conditions may affect device performance, functionality and

reliability.

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage resulting in a loss of functionality or

performance may occur if this device is subjected to a high-

energy electrostatic discharge.

Note: Unless otherwise stated VDD = 3.3V ±10% no load on any

output and ambient temperature range TA= 0°C to 70°C. Parameters

denoted with an asterisk (*) represent nominal characterization data

and are not production tested to any specific limits. Where given,

MIN and MAX characterization data are ±3σfrom typical. Negative

currents indicate current flows out of the device.

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FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO

Data Sheet

Parameter Symbol Conditions/Descriptions Min Typ. Max Units

Overall

VCXO Stabilization Time * tVCXOSTB From power valid 10 ms

PLL Stabilization Time * tPLLSTB From VCXO stable 100 µs

Synthesis Error (Unless otherwise noted in frequency table) 0 ppm

Clock Output (CLK)

Ratio of high pulse width (as measured

Duty Cycle * from rising edge to next falling 45 55 %

edge at VDD/2) to one clock period

Jitter, Period (peak-peak) * tj(∆P) From rising edge to next rising edge at 200 ps

VDD/2, CL =10pF 200 ps

Jitter, Long Term (σy(τ) * tj(LT) From 0-500µs at VDD/2, CL = 10pF 100 ps

compared to ideal clock source

Rise Time * trVDD = 3.3V; VO= 0.3V to 3.0V; CL= 10pF 1.7 ns

Fall Time * tfVDD = 3.3V; VO= 3.0V to 0.3V; CL= 10pF 1.7 ns

Table 6: AC Timing Specifications

Parameter Symbol Conditions/Descriptions Typ. Units

Thermal Impedance, Junction to ΘJA Air flow = 0 m/s 110 °C/W

Free-Air 8-pin 0.150” SOIC

Lead Inductance, Self L11 Corner lead 2.0 nH

Center lead 1.6

Lead Inductance, Mutual L12 Any lead to any adjacent lead 0.4 nH

Lead Capacitance, Bulk C11 Any lead to VSS 0.27 pF

Table 8: 8-pin SOIC (0.150”) Package Characteristics

Note: Unless otherwise stated, VDD = 3.3V ±10%, no load on

any output, and ambient temperature range TA= 0°C to 70°C.

Parameters denoted with an asterisk (*) represent nominal

characterization data and are not production tested to any

specific limits. Where given, MIN and MAX characterization

data are ±3σfrom typical.

5.0 Package Information - For Both ‘Green’ and ‘Non-Green’

Table 7: 8-pin SOIC (0.150”) Package Dimensions

FS6128-04/FS6128-04g PLL Clock Generator IC With VCXO

Data Sheet

Ordering Code Device Number Package Type Operating Shipping

Temperature Range Configuration

11640-825 FS6128-04

8-pin (0.150”) SOIC 0°C to 70°C (Commercial) Tape and Reel

(Small Outline Package)

8-pin (0.150”) SOIC

11640-892 FS6128-04g (Small Outline Package) 0°C to 70°C (Commercial) Tape and Reel

‘Green’or Lead-Free Packaging

6.0 Ordering Information

Table 9: Device Ordering Codes

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