AD national Semiconductor 54F/74F 181 4-Bit Arithmetic Logic Unit General Description Features The 'F181 is a 4-bit Arithmetic logic Unit (ALU) which can = Full lookahead for high-speed arithmetic operation on perform ail the possible 16 logic operations on two variables long words and a variety of arithmetic operations. It is 40% faster than the Schottky ALU and only consumes 30% as much power. @ Guaranteed 4000V minimum ESD protection Ordering Code: see section 11 Commercial - Military Facksoe Package Description 74F181PC N24A 24-Lead (0.600" Wide) Molded Dual-In-Line 74F181SPC N24C 24-Lead (0.300" Wide) Molded Dual-In-Line 54F181DM (Note 2} J24A 24-Lead Ceramic Dual-In-Line 54F181SDM (Note 2) J24F 24-Lead (0.300" ) Ceramic Dual-In-Line 74F181SC (Note 1) M24B 24-Lead (0.300 ) Molded Smail Outline, JEDEC 54F181FM (Note 2) W24C 24-Lead Cerpack 54F181LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also availabie in 13 reel. Use suffix = SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB. Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak / By=4!1 24 Vor Ag=|2 23 Ay S343 22-8, S44 21P Ay s;-45 20 By So46 19 Ay C7 18 = By w18 176 Fom19 16 Cosy Fy10 1S =P Fomqii 14 P= A= GND 412 13,;Fs TL/F/9491=1 Pin Assignment for LCC C, NC Sq Sy Sp &) (3) Fo M fo {hl} zi Caog 6 Bz NC Ag By Ay TL/F/9491-2 b50lle2e 0082293 345 7-143 LSI181 Logic Symbols Active-HIGH Operands Active-LOW Operands JEEE/IEC $444444hd pitti ttt Sfoy Ag Bo Ay By Ay By As By Creaf as, Ag Bo Ay By Az By As Bs Ce Ss (0...15) CP F s s Sq M3, (0..15)cc =o s, A=B 45, A=br Ss B(P=Q) & Pp Aas 4s, clo~ Ss, gf u (0...18) COf Crag 2 {s. c, cl j8s Fo Fy OFS PO- WSs Fp OF, Fg OFS oe inofe 7 q) po Fo 7 7 ? fo y Ff 50 TL/F/9491-3 TL/F/9491-4 A, Dap @) Lg 3,10 ' . . eo lw bh F, Unit Loading/Fan Out: see section 2 for U.L. definitions : = : 54F/74F 5, do @) Pp Fs Pin Names Description U.L. Input liy/lie TL/F/9491-10 HIGH/LOW | Output Ion/loL Ao-Ag A Operand Inputs (Activa LOW) 1.0/3.0 120 pA/-1.8mA Bo-By 8 Operand inputs (Active LOW) 1.0/3.0 | 20 pA/1.8mA So-S3 Function Select Inputs 1.0/4.0 120 pA/-2.4mA M Mode Control Input 1.0/1.0 |20 pA/0.6 mA Ch Carry input 1.0/5.0 | 20 pA/3.0mA Fo-F3 Function Outputs (Active LOW) 0/33.3 1mA/20 mA A= Camparator Output 0C*/33.3 */20 mA G Carry Generate Output (Active LOW) 50/33.3 1 mA/20 mA P Carry Propagate Output (Active LOW)| 50/33.3. | 1mA/20mA Chia Carry Output 0/33.3 1mA/20 mA *OC-Open Collector Functional Description Function Table lists these operations. P (Carry Propagate) and G (Carry Generate). In The F181 is a 4-bit high-speed parailel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (Sg-S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands. The When the Mode Control input (M) is HIGH, all internal car- ries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cy + 4 output, or for carry lookahead between packages using the signais the Add mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the Subtract mode P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed require- ments are not stringent, the "F181 can be used in a simple Ripple Carry mode by connecting the Carry output (C, + 4) signa! to the Carry input (C,) of the next unit. For high speed operation the device is used in conjunction with a carry jook- ahead circuit. One carry lookahead package is required for each group of four F181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A=B output from the device goes HIGH when ail four F outputs are HIGH and can be used to indicate logic equiva- lence over four bits when the unit is in the Subtract mode. The A=B output is open collector and can be wired AND with other A= B outputs to give a comparison for more than four bits. The A=B signal can also be used with the Ch+4 signal to indicate A>B and A<B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus t (2s complement notation) without a carry in and generates A minus B when a carry is applied. Be- cause subtraction is actually performed by complementary addition (1s complemeni), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underfiow. As indicated, this de- vice can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the oper- ations that are performed to the operands labeled inside the logic symbol. BM b501lee 004e294 2hl 7-144"F181 Operation Table ESL Logic Arithmetic Arithmetic So S; So S3 (M=4) (M=L, Cop = Inactive) (M=L, Co= Active) L L L L A A minus 1 A 4 4 H L L L AeB AB minus 1 AeB L H L L A+B AB minus 1 AsB Ic, Ag Bo Ay By Az Bz Az 83 a H H L L Logic 1 Minus 1 (2s comp.) Zero Sy mea L L H L ATSB Aplus (A + B) Aplus (A + 8) plus 1 4s, A=pBh | H L H L B AB plus (A + B) A*B plus (A + B) plus 1 "F181 L H H L AB Aminus B minus 1 Aminus B s sO-| oH H H L A+B A+B A + Bolus 1 52 L L L H Aes Aplus (A + B) Aplus (A + Bplus 1 ss om of m "PT) H LF LH A@B Aplus B _Aplus 8 plus 1 ? ? 9 ? L H L H B AB plus (A + B) ABoplus (A + B) plus 1 H H L H A+B A+B A+ Bplusi a. All Input Data Inverted L L H H Logic 0 Aplus A (2 X A) Aplus A (2 x A) plus 1 H L H H Aen AplusA*B Aplus AB plus 1 L H H H AeB AplusAeB Aplus A *B plus 1 H H H H A A Aplus 1 L L L L ry A Aplus 1 H L L L ATB A+B A+ Bolus 1 L H L L AeB A+B A+ Bplus1 | | | | | | | | H H L L Lagic 0 minus 1 (2s comp.) Zero By A; By A> By Az B L L H L AeB Aplus (A B) Aplus AB plus 1 Oc, fo Bo A Oh ho Be ts * Cres O H L H L B AB plus (A + B) A Bolus (A + B) plus 1 _* L H H L A@B A minus B minus 1 A minus B 150 MO) OH UHL AeB AeB minus 1 AB Ss, mat g-| & -L bk H A+8 Aplus A*B Aplus AB plus 1 4s, H L L H AGB AplisB A plus B plus 1 4; pL L H L H 8 A Bolus (A + B) A Bolus (A + B) plus 1 Bf H H L H AB AB minus 1 AeB ; | } | L L H H Logic 1 Aplus A (2 x A) Aplus A(2 x A) plus 4 H L H H A+B Aplus (A +B) Aplus (A+B) plus 1 b. All Input Data True L H H H A+B Aplus (A + B) Aplus (A+B) plus 1 H H H H A Aminus 1 A L L L L A Aminus 1 A dlaidaldl H L L L A+B AeB minus 1 AeB mde Ad Bo Ay By Ap By Ay BS L H L L AeB A#B minus 1 AeB n Cue H H L L Logic 1 minus 1 (2s comp.) Zero * L L H L AeB Aplus (A + B) Aplus (A + B} plus 1 50 eT Hk HL B AB plus (A + B) Ae B plus (A + B) plus 1 4s, F481 dlo-| H H L A@B Aplus B Aplus 8 plus 1 Hs, H H H L A+B A+B _ A+ Bolus 1 4s, fo F, fy Fs FIO L L L H A+B A plus (A + B) Aplus (A + B) plus 1 H L L H A A minus B minus 1 Aminus B PF Fy F L H L H B A*B plus (A + B) AB plus (A + B)plus 1 H H L H A+B A+B A+ Boplus 1 c. A Input Data inverted; L L H H Logic o" Aplus A (2 x A) Aplus A (2 X A) plus 1 B Input Data True H L H H AeB Aplus A eB Aplus AB plus 1 L H H H Aes AplusAB Aplus AB plus 1 H H H H A A Aplus 1 L L L L A A Aplus 1 H L L L Aes A+B A+ Bplus1 | alata L H L L ATS A+B A+ Bplus 1 H H L L Logic 0 minus 1 (2s comp.) Zero Ofc, o Bo Ar 8 Az Br As Bs CregfO 1 L L H L A+B Aplus Ae B Aplus AB plus 1 _ H L H L B A* Bolus (A + B) A*B plus (A + B) plus1 Ss, Aer H H L ROB Aplus B Aplus B plus 1 s, FABt | H H L AeB AB minus 1 AeB 4s, L L L H AeB AplusAeB Aplus A B plus 1 = H L L H A@B A minus B minus 1 A minus B Bs fo Fy Fes L H L H B AeBplus {A + B) A*B plus (A + B) plus 1 i | | | H H L H AeB AeBminus 1 AeB L L H H Logic 1 Aplus A (2 * A) Aplus A (2 x A) plus 4 d. A input Data True; H L H H A+B Aplus (A +B) Aplus (A+B) plus 1 B Input Date Inverted L H H H A+B Aplus (A + B) A plus (A+B) plus 1 H H H H A Aminus 1 A MH b50ble2 0082295 116 MH rsssheep uogebedosd ayeuS9 0] pasn eq jou Pinoys pu suoqaedo or60; Jo Buipus}suepun ey} 40) AJUO PeplAosd S| LEUBeip Sup BU] B]0U Estee S~}6r6/4/L 9 teu, d 84 a av | %4 | Agia? *g fy % Logic Diagram Pe < Ss fe = bSh 7-146 b5041e2 008226 O54Absolute Maximum Ratings (note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature 65C to + 150C Ambient Temperature under Bias ~ 56C to + 125C Junction Temperature under Bias 55C to + 175C Current Applied to Output in LOW State (Max) twice the rated Io, (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Plastic 55C to + 150C Voc Pin Potential to o6V to +70v Recommended Operating round Pin O0.5V to +7, og: Input Voltage (Note 2) 0.5V to +7.0V Conditions t _ ree Air Ambient Temperature Input Current (Note 2) 30 mA to +5.0 mA Military 55C to +128C Voltage Applied to Output Commercial OC to + 70C in HIGH State (with Voo = OV) Standard Output 0.5V to Voc Siniten +4.5V to +5.5V TRI-STATE Output 0.5V to +5.5V Commercial +4.8V to +5.5V DC Electrical Characteristics 7 Symbol! Parameter S4F/74F Units | Vec Conditions Min Typ Max VIH Input HIGH Voltage 2.0 Vv Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 Recognized as a LOW Signal Vop Input Clamp Diode Voltage 1.2 v Min | lin = 18mA VoH Output HIGH 54F 10% Voc 25 lon = 1mA Voltage 74F 10% Voc 2.56 Vv Min | low = 1mA 74F 5% Veco 27 lon = 1mA VoL Output LOW 54F 10% Voc 0.5 Vv Min lo. = 20mA Voltage 74F 10% Voc 0.5 lo. = 20mA li Input HIGH 54F 20.0 Vin = 2.7V Current 74F 5.0 HA Max IBv Input HIGH Current = 54F 100 VIN = 7.0V Breakdown Test 74F 7.0 pA Max Icex Output HIGH 54F 250 A | Max | Vout = Voc (Fn. G, P, Ch 44) Leakage Current 74F 50 Vip Input Leakage lip = 1.9 pA Test 74F 4.78 v 0.0 All Other Pins Grounded lop Output Leakage Viop = 150 mV Circuit Current 74F 3.75 pA 0.0 All Other Pins Grounded Ne input LOW Current 0.6 Vin = 0.5V (M) ~1.8 Vin = 0.5V (Ag, Ay, Ag, Bo, By, Bg) A M a -24 ]| | Ving = 0.5V (Sp, Ao, Bo) -3.0 Vin = 0.5V (Cy) los Output Short-Circuit Current 60 150 mA Max | Vout = OV (F,, G, P, Cy 44) loHc Open Collector, Output . Vo = Voc (A = B) OFF Leakage Test 250 uA Min IocH Power Supply Current 43 65.0 mA Max | Vo = HIGH loco. Power Supply Current 43 65.0 mA Max | Vo = LOW 7-147 6501122 0062297 TI0 om L8L181 AC Electrical Characteristics: see Section 2 for Waveforms and Load Configurations 74F 54F 74F Ta = +26C Ta; Vee = Milt Ta, Voc = Com Fig. Symbol! Parameter Vec = +5.0V ~ ~ Units C= 50 pF C. = 50 pF CL = 50 pF No. Path Mode Min Typ Max Min Max Min Max teLH Propagation Delay 3.0 6.4 6.5 3.0 10.0 3.0 9.5 ns 2-3 tpHL Cyto Cy + 4 3.0 64 8.0 3.0 9.5 3.0 9.0 teLH Propagation Delay 5.0 10.0 13.0 5.0 15.5 5.0 14.0 ns 2-3 teHL AorBtoCy + 4 Sum 4.0 9.4 12.0 3.5 16.5 4.0 13.0 TPLH Propagation Delay 5.0 10.8 14.0 5.0 17.0 5.0 15.0 ns 2-93 tPHL AorBtoC, +4 Dif 5.0 10.0 13.0 4.0 15.0 5.0 14.0 teLH Propagation Delay 3.0 6.7 8.5 25 16.0 3.0 9.5 ns 2-3 tpHL Cp toF Any 3.0 6.5 8.5 2.5 12.0 3.0 9.5 tpLH Propagation Delay 3.0 5.7 7.5 2.5 9.0 3.0 8.5 ns | 2-3 tpHL AorBorG Sum 3.0 5.8 75 25 9.5 3.0 8.5 teLH Propagation Delay 3.0 6.5 8.5 2.5 41.5 3.0 9.5 ns 2-3 tPHL AorBtoG Dif 3.0 7.3 9.5 25 11.0 3.0 10.5 ~ teLH Propagation Delay 3.0 5.0 7.0 2.5 8.5 3.0 8.0 ns 2-3 teHL AorBtoP Sum 3.0 5.5 7.5 3.0 9.5 3.0 8.5 teLH Propagation Delay 3.0 5.8 7.5 25 11.0 3.0 8.5 ns | 2-3 teu Aor B toP Dit 4.0 6.5 8.5 3.0 11.0 4.0 9.5 tPLH Propagation Delay 3.0 7.0 9.0 3.0 14.5 3.0 10.0 ns 2-3 teHL Aj or 6; to F; Sum 3.0 7.2 10.0 3.0 14.5 3.0 10.0 teLH Propagation Delay 3.0 8.2 11.0 3.0 17.5 3.0 12.0 ns 2-3 tPHL A, or 8; to F; Dif | 3.0 5.0 11.0 3.0 14.5 3.0 12.0 tPLH Propagation Delay 4.0 8.0 10.5 3.5 16.5 4.0 11.5 ns 2-3 teu Any AorBtoAnyF Sum 4.0 78 10.0 4.0 13.5 4.0 41.0 tpLH Propagation Delay 45 9.4 12.0 3.5 17.5 4.56 13.0 ns 2-4 tpHe AnyAorBtoAnyF Dif 3.5 9.4 12.0 3.0 14.0 3.5 13.0 tpLy Propagation Delay 4.0 6.0 9.0 3.5 14.5 4.0 10.0 ns 2-3 teHL AorBtoF Logic 4.0 6.0 10.0 3.0 15.5 4.0 11.0 teLH Propagation Delay 11.0 18.5 27.0 8.0 35.0 11.0 29.0 ns 2-3 tPHL AorBtoA =B Dif 6.0 9.8 12.5 5.5 21.0 6.0 13.5 ~ Mi 6501122 004622948 927 7-148