PRELIMINARY HXSR06432 2M x 32 STATIC RAM The Multi-Chip Module (MCM), radiation hardened 64M Honeywell's state-of-the-art S150 technology is bit Static Random Access Memory (SRAM) in a 2M x radiation hardened through the use of advanced and 32 configuration is a high performance 2,097, 152 word proprietary design, layout and process hardening x 32 bit SRAM MCM consisting of four 512kx32 SRAM techniques. There is no internal EDAC implemented. monolithic chips fabricated with Honeywell's 150nm silicon-on-insulator CMOS (S150) technology. It is It is a low power process with a minimum drawn feature designed for use in low voltage systems operating in size of 150 nm. It consumes less than 400mW typical radiation sensitive environments. The RAM operates power at 40MHz operation. over the full military temperature range and requires a asynchronous with a typical access time of 13 ns at core supply voltage of 1.8V +/- 0.15V and an I/O supply 3.3V. A seven transistor (7T) memory cell is used for voltage of 3.3V 0.3V or 2.5V 0.2V. superior single event upset hardening, while four layer The SRAM is fully metal power busing and the low collection volume SOI substrate provide improved dose rate hardening. FEATURES * Fabricated on S150 Silicon On Insulator (SOI) CMOS * 150 nm Process (Leff = 110 nm) * Read Cycle Times Typical =13 ns Worst case = 22 ns * Write Cycle Times Typical = 9 ns Worst case = 15 ns * Asynchronous Operation 6 * Total Dose =1X10 rad(Si) * No Latch up * Soft Error Rate Heavy Ion =1x10 day Proton =2x10 -12 14 * Neutron = 1x10 -12 Upsets/bit- Upsets/bit-day cm -2 12 =1x10 * I/O Power Supply 3.3 V 0.3 V 2.5 V 0.2 V 10 * Dose Rate Upset =1x10 rad(Si)/s * Dose Rate Survivability * Core Power Supply 1.8 V 0.15 V * Operating Range is -55C to +125C * 86-Lead Flat Pack Package rad(Si)/s * CMOS Compatible I/O FUNCTIONAL DIAGRAM 86 LEAD FLAT PACK PINOUT HXSR06432 A<0-8> A<9-18> PRELIMINARY Row Driver 2,097,152 X 32 Memory Array Column Decoder Data Input/Output NWE NOE CE NCS<0-3> NBE<0-3> 2 DQ<0-31> Note 1: Pin 1 and Pin 86 shall be connected to VSS on the circuit board. HXSR06432 Top View 86 85 Note 1 Cathode VSS VDD 1 2 3 84 Anode VSS VDD A0 A1 A2 A3 4 5 6 7 83 82 81 80 A18 A17 A16 VSS A4 8 VSS 9 VDD2 10 DQ0 11 79 78 77 76 VDD2 DQ31 DQ30 DQ29 DQ1 12 DQ2 13 DQ3 14 75 74 73 DQ28 DQ27 DQ26 DQ4 DQ5 VSS VDD2 15 16 17 18 72 71 70 69 NOE VDD2 NBE3 NCS3 NBE0 NCS0 DQ6 DQ7 19 20 21 22 68 67 66 65 DQ25 DQ24 DQ23 DQ22 DQ8 DQ9 NCS1 NBE1 23 24 25 26 64 63 62 61 NCS2 CE NBE2 VDD2 VDD2 27 NWE 28 DQ10 29 60 59 58 VSS DQ21 DQ20 DQ11 DQ12 DQ13 DQ14 30 31 32 33 57 56 55 54 DQ19 DQ18 DQ17 DQ16 DQ15 VDD2 VSS A5 34 35 36 37 53 52 51 50 VDD2 VSS A15 A14 A6 A7 A8 A9 38 39 40 41 49 48 47 46 A13 A12 A11 A10 VDD 42 VSS 43 45 44 VDD VSS www.honeywell.com/radhard HXSR06432 PRELIMINARY SIGNAL DEFINITIONS A (0-18) DQ (0-31) NCS(0-3) NWE NOE CE NBE (0-3) VDD VDD2 Cathode and Anode Address input signals. Used to select a particular 32 bit word within the active die memory array. Bi-directional data signals. These function as data outputs during a read operation and as data inputs during a write operation. Negative chip selects, one NCS is at a low level, allows normal read or write operation of one SRAM die. Only one NCS at a low level at a time. When NCS (0-3) are at a high level, the SRAM chips are forced to a pre-charge condition and the data output drivers are held in a high impedance state. The dynamic and DC IDD2 chip current contribution from all other input circuits caused by input pins transitioning, and/or at VDD2 or VSS is reduced. Negative Write Enable input signal. Setting to a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level it allows normal read operation. Negative Output Enable input signal. Setting to a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NBE, CE and NWE. If this signal is not used, it must be connected to VSS. Chip Enable input signal. When set to a high level, the SRAM is in normal read or write operation. When at a low level, it defaults the SRAM to a pre-charge condition and holds the data output drivers in a high impedance state. If the CE signal is not used, it must be connected to VDD2. Not Byte Enable input signal. When set to a low level, enables a read or write operation on a specific byte within the 32 bit (4 byte) word. When at a high level, the write operation of a specific byte is disabled and during a read operation the 8 data outputs of the specific byte are held in a high impedance state. SRAM Core operating voltage (typical 1.8V) I/O Operating voltage (typical 3.3V OR 2.5V) These signals are used for manufacturing test only. They shall be connected to VSS. TRUTH TABLE * CE L X H H H H H H H H H 0 X H L L L L L L L L L NCS 1 2 X X H H H H H H H H H H H H H H H H H H H H NWE 3 X H H H H H H H H H H X X H H H H H L L L L NOE X X L L L L L H H H H 0 X X L H H H L L H H H NBE 1 2 X X X X H H L H H L H H L L H H L H H L H H Mode 3 X X H H H L L H H H L Disable De-select Read Read Read Read Read Write Write Write Write 0-7 Hi-Z Hi-Z DO Hi-Z Hi-Z Hi-Z DO DI X X X H L H H H L H L L L L Write DI X: VI = VIH or VIL, NOE = VIH: High Z output state maintained for NCS = X, CE = X, NWE = X, NBE = X * NCS(0-3): only one NCS can be L, others remain H www.honeywell.com/radhard 3 8-15 Hi-Z Hi-Z Hi-Z DO Hi-Z Hi-Z DO X DI X X DI DQ 16-23 Hi-Z Hi-Z Hi-Z Hi-Z DO Hi-Z DO X X DI X DI 24-31 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DO DO X X X DI DI HXSR06432 PRELIMINARY RADIATION CHARACTERISTICS Total Ionizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications, post rebound (based on extrapolation), after an operational period of 10 years. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 KeV X-ray. Transistor gate threshold shift correlations have been made between 10 KeV X-rays applied at a 6 dose rate of 1x10 rad(SiO2)/min at T= 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. exceed the normal operating levels. The application design must accommodate these effects. Neutron Radiation The SRAM will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Soft Error Rate The SRAM is capable of meeting the specified Soft Error Rate (SER), under recommended operating conditions. The specification applies to both heavy ion and proton. This heavy ion hardness level is defined by the Adams 90% worst case cosmic ray environment for geosynchronous orbits. Transient Pulse Ionizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse, up to the specified transient dose rate upset specification, when applied under recommended operating conditions. It is recommended to provide external power supply decoupling capacitors to maintain VDD and VDD2 voltage levels during transient events. The SRAM will meet any functional or electrical specification after exposure to a radiation pulse up to the transient dose rate survivability specification, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SOI substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs. RADIATION-HARDNESS RATINGS (1) Parameter Limits Units Test Conditions Total Dose 6 =1X10 rads(Si) TA=25C, VDD2=3.6V, VDD=1.95V Transient Dose Rate Upset =1X10 10 rads(Si)/s Transient Dose Rate Survivability =1X10 12 rads(Si)/s Soft Error Rate <1X10 -12 <2X10 -12 Upsets/bit-day Pulse width = 50 ns,X-ray, VDD2 = 3.0V, VDD=1.65V, TC =25C Pulse width = 50 ns,X-ray, VDD2 = 3.6V, VDD=1.95V, TA=25C VDD2=3.0V, VDD=1.95V, TC = -55 and 125C, Adams 90% worst case environment 14 N/cm Neutron Fluence (1) 4 Heavy Ion Proton =1X10 2 1MeV equivalent energy, Unbiased, TA=25C Device will not latch up due to any of the specified radiation exposure conditions. www.honeywell.com/radhard HXSR06432 PRELIMINARY ABSOLUTE MAXIMUM RATINGS (1) Rating Symbol Parameter VDD VDD2 VPIN IOUT PD VPROT TSTORE TSOLDER Supply Voltage (core) (2) Supply Voltage (I/O) (2) Voltage on Any Pin (2) Average Output Current Maximum Power Dissipation (3) Electrostatic Discharge Protection Voltage (4) Storage Temperature Soldering Temperature (5) TJ Maximum Junction Temperature PJC Package Thermal Resistance (Junction-toCase) Min -0.5 -0.5 -0.5 Max 2.5 4.4 VDD2+0.5 15 2.5 2000 -65 86 Pin FP Units 125 270 Volts Volts Volts mA W V C C 150 C 5.0 C/W (1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) RAM power dissipation including output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883, Method 3015 (5) Maximum soldering temp of 270C can be maintained for no more than 5 seconds. RECOMMENDED OPERATING CONDITIONS (1) Description Symbol Parameter Min Typ Max Units VDD Supply Voltage (core) VDD2 Supply Voltage (I/O) TC External Package Temperature 1.65 3.0 2.3 -55 1.80 3.3 2.5 25 1.95 3.6 2.7 125 Volts Volts Volts C VPIN Voltage on Any Pin -0.3 VDD2+0.3 Volts VDD2/VDD Ramp Time Supply Voltages Ramp Time 1E-5 1.0 Second VDD2/ VDD PDT (2) Power Supply Power Down Time 5 msec (1) Voltages referenced to Vss. (2) Power Supplies must be turned off for power down time before turned back on. DC ELECTRICAL CHARACTERISTICS (1) Symbol IDDSB (4) Parameter Min Max Units Test Conditions IDD IDD2 12 18 160 1.2 1.2 1.2 mA mA mA VDD=max, Iout=0mA, Inputs Stable 0.4 0.8 mA 8 20 mA VDD=max, Iout=0mA, F=1MHz, NCS=VIH (3) VDD=max, Iout=0mA, F=40MHz, NCS=VIH (3) Static Supply Current TA=-55C TA =25C TA=125C IDDOP1 Dynamic Supply Current - Deselected IDDOP3 Operating Current - Disabled www.honeywell.com/radhard 5 HXSR06432 IDDOPW IDDOPR IDR Symbol II IOZ VIL VIH VOL VOH (1) (2) (3) (4) PRELIMINARY Dynamic Supply Current, Selected (Write) 1 MHz 2 MHz 10 MHz 25 MHz 40 MHz Dynamic Supply Current, Selected (Read) 1 MHz 2 MHz 10 MHz 25 MHz 40 MHz Data Retention Current TA=25C TA=125C Parameter 5.6 10.3 50.3 125.3 200.3 0.95 1.9 7.6 18.3 29 mA mA mA mA mA VDD2 and VDD=max, Iout=0mA, NCS=VIL (1) (2) (3) 3.0 5.0 20.3 50.3 80.3 0.8 1.6 6.1 14.5 23.0 mA mA mA mA mA VDD2 and VDD=max, Iout=0mA, NCS=VIL (1) (3) 0.8 mA mA VDD=1V, VDD2=2V 80 Min Max Units Test Conditions Input Leakage Current -10 10 A Output Leakage Current -20 20 A Output = high Z Low-Level Input Voltage 0.25xVDD2 V VDD2=3.0V to 3.6V High-Level Input Voltage 0.75xVDD2 V VDD2=3.0V to 3.6V Low-Level Output Voltage 0.4 V VDD2=3.0V, IOL = 10mA High-Level Output Voltage 2.7 V VDD2=3.0V, IOH = 5mA Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, -55C to +125C, post total dose at 25C. All inputs switching. DC average current. All dynamic operating mode current measurements (IDDOPx) exclude standby mode current (IDDSB) See graph below for typical static current values. Typical IDD Standby Current Current (mA) 100 80 60 40 20 0 0 20 40 60 80 100 120 140 Temperature (Degrees C) 6 www.honeywell.com/radhard HXSR06432 PRELIMINARY CAPACITANCE (1) Symbol Parameter CA CC CD Address Input Capacitance NCS, NOE, NWE Input Capacitance Data I/O, NBE Capacitance Worst Case (1) Min Max 25 35 25 Units Test Conditions pF pF pF VIN=VDD or VSS, f=1 MHz VIN=VDD or VSS, f=1 MHz VIN=VDD or VSS, f=1 MHz (1) This parameter is tested during initial qualification only. READ CYCLE AC TIMING CHARACTERISTICS (1)(2) VDD2 = 3.3V or 2.5V Min Max Symbol Parameter TAVAVR TAVQV TAXQX TSLQV TSLQX TSHQZ TEHQV TEHQX TELQZ TBLQV TBLQX TBHQZ TGLQV TGLQX TGHQZ Read Cycle Time (3) Address Access Time (3) Address Change to Output Invalid Time Chip Select Access Time (3) Chip Select Output Enable Time Chip Select Output Disable Time Chip Enable Access Time (3) Chip Enable Output Enable Time Chip Enable Output Disable Time Byte Enable Access Time Byte Enable Output Enable Time Byte Enable Output Disable Time Output Enable Access Time Output Enable Output Enable Time Output Enable Output Disable Time 20, 22 20, 22 4 21, 22 0 4.0 21, 22 0 4.8 6 0 4 6.2 0 4.8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (1) Test conditions: VIL/VIH=0V/Vdd. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics diagrams. Capacitive output loading C L=5 pF for TSHQZ and TGHQZ. (2) Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, TA=-55C to 125C, post total dose at 25C. (3) Values shown for 3.3V and 2.5V VDD2, respectively. READ CYCLE TIMING TAVAVR ADDRESS TAVQV TAXQX TSLQV NCS TSHQZ TSLQX DATA OUT HIGH IMPEDANCE DATA VALID TEHQX TEHQV TELQZ CE TGLQX TGLQV TGHQZ NOE TBLQX TBLQV TBHQZ NBE NWE = HIGH www.honeywell.com/radhard 7 HXSR06432 PRELIMINARY WRITE CYCLE AC TIMING CHARACTERISTICS (1) Symbol TAVAVW TWLWH TSLWH TEHWH TDVWH TAVWH TWHDX TAVWL TWHAX TWLQZ TWHQX TWHWL TBLWH Parameter Write Cycle Time (2) Write Enable Write Pulse Width Chip Select to End of Write Time Chip Enable to End of Write Time Data Valid to End of Write Time Address Valid to End of Write Time Data Hold after End of Write Time Address Valid Setup to Start of Write Time Address Valid Hold after End of Write Time Write Enable to Output Disable Time Write Disable to Output Enable Time Write Disable to Write Enable Pulse Width (3) Byte Enable to End of Write Time VDD2 = 3.3V or 2.5V Min Max 15 7 10 10 6 12 0 0 0 4.2 0 5 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns (1) Test conditions: VIL/VIH=0V/VDD. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics diagrams. Capacitive output loading C L=5 pF for TWLQZ. Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, -55C to 125C, post total dose 25C (2) TAVAVW = T WLWH + TWHWL (3) Guaranteed but not tested WRITE CYCLE TIMING TAVAVW ADDRESS TAVWH TWHAX TAVWL TWLWH TWHWL NWE TWHQX TWLQZ DATA OUT HIGH IMPEDANCE TDVWH DATA IN TWHDX DATA VALID TSLWH NCS TEHWH CE NBE 8 TBLWH www.honeywell.com/radhard HXSR06432 PRELIMINARY DYNAMIC ELECTRICAL OPERATION Asynchronous Operation The RAM is asynchronous in operation. Read and Write cycles are controlled by NWE, NCS (0-3), CE, NBE(0-3) and Address signals. NBE(0-3) is used to control which of the 4 bytes is written to or read from. These can be used independently. When set to a low level, the signals enable a normal read or write operation. When at a high level, the write operation of a specific byte is disabled and during a read operation, the 8 data outputs of the specific byte are held in a high impedance state. NCS (0-3) is used to control which of the 4 SRAM die is written to or read from One and only one signal line of NCS(0-3) can be active (low) at a time. NCS(X) refers to the one active low signal of NCS(0-3). Read Operation To perform a valid read operation, NCS(X), NBE(0-3) and NOE must be low and NWE and CE must be high. The output drivers can be controlled independently by the NOE signal. Although not required, it is recommended to delay NOE slightly relative to the address and other control lines at the beginning of the read cycle. This is done to minimize the potential for coupling noise from the outputs back into the inputs since up to 32 outputs can switch when NOE is activated. It is important to have the address bus free of noise and glitches, which can cause inadvertent read operations. The control and address signals should have rising and falling edges that are fast (<5 ns) and have good signal integrity (free of noise, ringing or steps associated reflections). The read mode can be controlled via two different control signals: CE and NCS(0-3). Both modes of control are similar, except the signals are of opposite polarity. To control a read cycle with NCS (0-3), all addresses must be valid prior to or coincident with the enabling NCS (X) edge transition. Address edge transitions can occur later than the specified setup times to NCS(X); however, the valid data access time will be delayed. Any address edge transition which occurs during the time when NCS(X) is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. www.honeywell.com/radhard For an address activated read cycle, NCS(X) must be valid prior to or coincident with the address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAVR . When the RAM is operated at the minimum address activated read cycle time, the data outputs will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. To perform consecutive read operations, NCS (X) is required to be held continuously low, and the toggling of the addresses will start the new read cycle. Write Operation To perform a write operation, NWE, NCS(X) and NBE(0-3) must be low and CE must be high. The write mode can be controlled via three different control signals: NWE, CE and NCS(0-3). All modes of control are similar. Only the NWE controlled mode is shown in the table and diagram on the previous page for simplicity; however, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To write data into the RAM, NWE and NCS(X) must be held low for at least TWLWH/TSLWH/TEHWH time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. The DATA IN must be valid TDVWH time prior to switching high. Consecutive write cycles can be performed by toggling one of the control signals while the other remains in their "write" state (NWE or NCS(X) held continuously low). At least one of the control signals must transition to the opposite state between consecutive write operations. For consecutive write operations, write pulses (NWE) must be separated by the minimum specified TWHWL/TSHSL time. Address inputs must be valid at least TAVWL time before the enabling NWE/NCS edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH, and an address valid to end of write time of TAVWH also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS(X) edge transition must be a minimum of TWHAX time and TWHDX time, respectively. The minimum write cycle time is TAVAVW . 9 HXSR06432 PRELIMINARY TESTER AC TIMING CHARACTERISTICS TESTER EQUIVALENT LOAD CIRCUIT VDD2 - 0.5 V Input Levels* VDD2/2 0.5 V VDD2/2 V VDD 2/ 2 249 DUT Output VDD 2- 0.4 V Output Sense Levels V1 V2 Valid High Output Valid Low Output CL < 50 pf High Z 0.4 V High Z + 100mV High Z = VDD2/2 High Z - 100mV * Input rise and fall times < 5 ns RELIABILITY For more than 15 years Honeywell has been producing integrated circuits that meet the stringent reliability requirements of space and defense systems. Honeywell has delivered thousands of QML parts since first becoming QML qualified in 1990. Using this proven approach Honeywell will assure the reliability of the SRAMs manufactured with the S150 process technology. This approach includes adhering to Honeywell's General Manufacturing Standards for: * Designing in reliability by establishing electrical rules based on wear out mechanism characterization performed on specially designed test structures (electromigration, TDDB, hot carriers, negative bias temperature instability, radiation) * Utilizing a structured and controlled design process * A statistically controlled wafer fabrication process with a continuous defect reduction process * Individual wafer lot acceptance through process monitor testing (includes radiation testing) * The use of characterized and qualified packages * A thorough product testing program based on MIL-PRF-38535 and MIL-STD 883. QUALIFICATION AND SCREENING 10 The S150 technology was qualified by Honeywell after meeting the criteria of the General Manufacturing Standards and is QML Qualified. This approval is the culmination of years of development and requires a considerable amount of testing, documentation, and review. The test flow includes screening units with the defined flow (Class V and Q equivalent) and the appropriate periodic or lot conformance testing (Groups B, C, D, and E). Both the S150 process and the SRAM products are subject to period or lot based Technology Conformance Inspection (TCI) and Quality Conformance Inspection (QCI) tests, respectively. Group A Group B Group C Group D Group E General Electrical Tests Mechanical - Dimensions, bond strength, solvents, die shear, solderability, Lead Integrity, seal, acceleration Life Tests - 1000 hours at 125C or equivalent Package related mechanical tests Shock, Vibration, Accel, salt, seal, lead finish adhesion, lid torque, thermal shock, moisture resistance Radiation Tests Honeywell delivers products that are tested to meet your requirements. Products can be screened to several levels including Proof of Design (POD), Engineering Models, and Flight Units. PODs and EMs are available with limited screening for prototype development and evaluation testing. www.honeywell.com/radhard HXSR06432 PRELIMINARY PACKAGING The 512K x 32 SRAM is offered in an 86-lead flat pack. This package is constructed of multi-layer ceramic (Al2O3) and contains internal power and ground planes. The package lid material is Kovar and the finish is in accordance with the requirements of MILPRF-38535. The finished, packaged part weighs TBD grams. VDD AND VDD2 CAPACITORS VDD The SRAM has four external capacitors as power supply decoupling on VDD and VDD2. These are adhered to the package using epoxy (conductive on capacitor leads and non-conductive on the body) during assembly. C VDD2 C C C C = 0.1F 10% PACKAGE OUTLINE 11 www.honeywell.com/radhard HXSR06432 PRELIMINARY HXSR06432 PRELIMINARY ORDERING INFORMATION (1) H X SR06432 D V SCREEN LEVEL PROCESS X = SOI PART NUMBER Source H = Honeywell V = QML Class V Q = QML Class Q Z = Class V Equivalent (4) Y = Class Q+ Equivalent (5) E = Eng. Model (2) PACKAGE DESIGNATION D = 86 Lead Flatpack - = Bare Die (3) (1) (2) (3) (4) (5) H TOTAL DOSE HARDNESS H = 1x106 rad (Si) N = No Level Guaranteed (2) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-763-954-2474 for further information. Engineering Device Description: Parameters are tested -55C to 125C, 24 hour burn-in, no radiation guaranteed. Bare die do not receive any reliability screening. These receive the Class V screening and QCI is included. Customer must specify QCI requirements. These receive the Class V screening but do not have QCI included. STANDARD MICROCIRCUIT DRAWING The QML Certified SRAM can also be ordered under the SMD drawing TBD. FIND OUT MORE For more information about Honeywell's family of radiation hardened products and technology, visit www.honeywell.com/radhard. Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. This product and related technical data is subject to the U.S. Department of State International Traffic in Arms Regulations (ITAR) 22 CFR 120-130 and may not be exported, as defined by the ITAR, without the appropriate prior authorization from the Directorate of Defense Trade Controls, United States Department of State. Diversion contrary to U.S. export laws and regulations is prohibited. This datasheet includes only basic marketing information on the function of the product and therefore is not considered technical data as defined in 22CFR 120.10. Honeywell 12001 Highway 55 Plymouth, MN 55441 1-800-323-8295 www.honeywell.com/radhard www.honeywell.com/radhard Form #900363 July 2009 (c)2009 Honeywell International Inc. 13