The Multi-Chip Module (MCM), radiation hardened 64M
bit Static Random Access Memory (SRAM) in a 2M x
32 configuration is a high performance 2,097,152 word
x 32 bit SRAM MCM consisting of four 512kx32 SRAM
monolithic chips fabricated with Honeywell’s 150nm
silicon-on-insulator CMOS (S150) technology. It is
designed for use in low voltage systems operating in
radiation sensitive environments. The RAM operates
over the full military temperature range and requires a
core supply voltage of 1.8V +/- 0.15V and an I/O supply
voltage of 3.3V ± 0.3V or 2.5V ± 0.2V.
Honeywell’s state-of-the-art S150 technology is
radiation hardened through the use of advanced and
proprietary design, layout and process hardening
techniques. There is no internal EDAC implemented.
It is a low power process with a minimum drawn feature
size of 150 nm. It consumes less than 400mW typical
power at 40MHz operation. The SRAM is fully
asynchronous with a typical access time of 13 ns at
3.3V. A seven transistor (7T) memory cell is used for
superior single event upset hardening, while four layer
metal power busing and the low collection volume SOI
substrate provide improved dose rate hardening.
• Fabricated on S150 Silicon On
Insulator (SOI) CMOS
• 150 nm Process (Leff = 110 nm)
• Read Cycle Times
Typical =13 ns
Worst case = 22 ns
• Write Cycle Times
Typical = 9 ns
Worst case = 15 ns
• Asynchronous Operation
• CMOS Compatible I/O
• Total Dose =1X106 rad(Si)
• Soft Error Rate
Heavy Ion =1x10-12 Upsets/bit-
day
Proton =2x10-12 Upsets/bit-day
• Neutron = 1x1014 cm-2
• Dose Rate Upset =1x1010
rad(Si)/s
• Dose Rate Survivability
=1x1012 rad(Si)/s
• No Latch up
• Core Power Supply
1.8 V ± 0.15 V
• I/O Power Supply
3.3 V ± 0.3 V
2.5 V ± 0.2 V
• Operating Range is
-55°C to +125°C
• 86-Lead Flat Pack Package
FUNCTIONAL DIAGRAM 86 LEAD FLAT PACK PINOUT
FEATURES
HXSR0
64
32
2M x 32 STATIC RAM
PRELIMINARY
HXSR06432 PRELIMINARY
2 www.honeywell.com/radhard
Column Decoder
Data Input/Output
Driver
A<0-8>
A<9-18>
DQ<0-31>
NWE
NOE
CE
NCS<0-3>
NBE<0
-
3>
2,097,152
Memory Array
Note 1:
Pin 1 and Pin 86 shall be connected
to VSS on the circuit board.
HXSR06432
Top View
Note 1
Cathode 1
VSS 2
VDD 3
A0 4
A1 5
A2 6
A3 7
A4 8
VSS 9
VDD2 10
DQ0 11
DQ1 12
DQ2 13
DQ3 14
DQ4 15
DQ5 16
VSS 17
VDD2 18
NBE0 19
NCS0 20
DQ6 21
DQ7 22
DQ8 23
DQ9 24
NCS1 25
NBE1 26
VDD2 27
NWE 28
DQ10 29
DQ11 30
DQ12 31
DQ13 32
DQ14 33
DQ15 34
VDD2 35
VSS 36
A5 37
A6 38
A7 39
A8 40
A9 41
VDD 42
VSS 43
86 Anode
85 VSS
84 VDD
83 A18
82 A17
81 A16
80 VSS
79 VDD2
78 DQ31
77 DQ30
76 DQ29
75 DQ28
74 DQ27
73 DQ26
72 NOE
71 VDD2
70 NBE3
69 NCS3
68 DQ25
67 DQ24
66 DQ23
65 DQ22
64 NCS2
63 CE
62 NBE2
61 VDD2
60 VSS
59 DQ21
58 DQ20
57 DQ19
56 DQ18
55 DQ17
54 DQ16
53 VDD2
52 VSS
51 A15
50 A14
49 A13
48 A12
47 A11
46 A10
45 VDD
44 VSS
HXSR06432 PRELIMINARY
www.honeywell.com/radhard
3
SIGNAL DEFINITIONS
A (0-18) Address input signals. Used to select a particular 32 bit word within the
active die memory array.
DQ (0-31) Bi-directional data signals. These function as data outputs during a read
operation and as data inputs during a write operation.
NCS(0-3) Negative chip selects, one NCS is at a low level, allows normal read or
write operation of one SRAM die. Only one NCS at a low level at a
time. When NCS (0-3) are at a high level, the SRAM chips are forced
to a pre-charge condition and the data output drivers are held in a high
impedance state. The dynamic and DC IDD2 chip current contribution
from all other input circuits caused by input pins transitioning, and/or at
VDD2 or VSS is reduced.
NWE Negative Write Enable input signal. Setting to a low level activates a
write operation and holds the data output drivers in a high impedance
state. When at a high level it allows normal read operation.
NOE Negative Output Enable input signal. Setting to a high level holds the
data output drivers in a high impedance state. When at a low level, the
data output driver state is defined by NCS, NBE, CE and NWE. If this
signal is not used, it must be connected to VSS.
CE Chip Enable input signal. When set to a high level, the SRAM is in
normal read or write operation. When at a low level, it defaults the
SRAM to a pre-charge condition and holds the data output drivers in a
high impedance state. If the CE signal is not used, it must be
connected to VDD2.
NBE (0-3) Not Byte Enable input signal. When set to a low level, enables a read
or write operation on a specific byte within the 32 bit (4 byte) word.
When at a high level, the write operation of a specific byte is disabled
and during a read operation the 8 data outputs of the specific byte are
held in a high impedance state.
VDD SRAM Core operating voltage (typical 1.8V)
VDD2 I/O Operating voltage (typical 3.3V OR 2.5V)
Cathode and
Anode These signals are used for manufacturing test only. They shall be
connected to VSS.
TRUTH TABLE
NCS
*
NWE
NOE
NBE
Mode
DQ
0
1
2
3
0
1
2
3
0
-
7
8
-
15
16
-
23
24
-
31
L
X
X
X
X
X
X
X
X
X
X
Disable
Hi
-
Z
Hi
-
Z
Hi
-
Z
Hi
-
Z
X
H
H
H
H
X
X
X
X
X
X
De
-
select
Hi
-
Z
Hi
-
Z
H
i
-
Z
Hi
-
Z
H
L
H
H
H
H
L
L
H
H
H
Read
DO
Hi
-
Z
Hi
-
Z
Hi
-
Z
H
L
H
H
H
H
L
H
L
H
H
Read
Hi
-
Z
DO
Hi
-
Z
Hi
-
Z
H
L
H
H
H
H
L
H
H
L
H
Read
Hi
-
Z
Hi
-
Z
DO
Hi
-
Z
H
L
H
H
H
H
L
H
H
H
L
Read
Hi
-
Z
Hi
-
Z
Hi
-
Z
DO
H
L
H
H
H
H
L
L
L
L
L
Read
DO
DO
DO
DO
H
L
H
H
H
L
H
L
H
H
H
Write
DI
X
X
X
H
L
H
H
H
L
H
H
L
H
H
Write
X
DI
X
X
H
L
H
H
H
L
H
H
H
L
H
Write
X
X
DI
X
H
L
H
H
H
L
H
H
H
H
L
Write
X
X
X
DI
H
L
H
H
H
L
H
L
L
L
L
Write
DI
DI
DI
DI
X: VI = VIH or VIL,
NOE = VIH: High Z output state maintained for NCS = X, CE = X, NWE = X, NBE = X
*NCS(0-3): only one NCS can be L, others remain H
HXSR06432 PRELIMINARY
4 www.honeywell.com/radhard
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will
remain within specifications, post rebound (based on
extrapolation), after an operational period of 10 years.
Total dose hardness is assured by wafer level testing of
process monitor transistors and RAM product using 10
KeV X-ray. Transistor gate threshold shift correlations
have been made between 10 KeV X-rays applied at a
dose rate of 1x106 rad(SiO2)/min at T= 25°C and
gamma rays (Cobalt 60 source) to ensure that wafer
level X-ray testing is consistent with standard military
radiation test environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD and VDD2 voltage levels during transient
events. The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to
the transient dose rate survivability specification, when
applied under recommended operating con ditions. Note
that the current conducted during the pulse by the RAM
inputs, outputs, and power supply may significantly
exceed the normal operating levels. The application
design must accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes an equivalent neutron energy
of 1 MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft
Error Rate (SER), under recommended operating
conditions. The specification applies to both heavy ion
and proton. This heavy ion hardness level is defined by
the Adams 90% worst case cosmic ray environment for
geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with
the SOI substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and
n-channel substrates are made to ensure no
source/drain snapback occurs.
RADIATION-HARDNESS RATINGS (1)
Parameter Limits Units Test Conditions
Total Dose
=1X10
6
rads(Si) TA=25°C, VDD2=3.6V, VDD=1.95V
Transient Dose Rate Upset
=1X10
10
rads(Si)/s Pulse width = 50 ns,X-ray, VDD2 = 3.0V,
VDD=1.65V, T
C
=25°C
Transient Dose Rate Survivability
=1X10
12
rads(Si)/s Pulse width = 50 ns,X-ray, VDD2 = 3.6V,
VDD=1.95V, T
A
=25°C
Soft Error Rate Heavy Ion
Proton
<1X10
-
1
2
<2X10-12 Upsets/bit-day VDD2=3.0V, VDD=1.95V, TC= -55 and 125°C,
Adams 90% worst case environment
Neutron Fluence
=1X10
14
N/cm
2
1MeV equivalent energy, Unbiased, T
A
=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
HXSR06432 PRELIMINARY
www.honeywell.com/radhard 5
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter
Rating
Units
Min
Max
V
DD
Supply Voltage (core) (2)
-
2.
5
Volts
V
DD2
Supply Voltage (I/O) (2)
-
Volts
V
PIN
Voltage on Any
Pin (2)
-
VDD2
+0.5
Volts
I
Average Output Current
15
mA
P
D
Maximum Power Dissipation (3)
W
V
PROT
Electrostatic Discharge Protection Voltage (4)
2000
V
T
STORE
Storage Temperature
-
65
125
°C
T
SOLDER
Soldering Temperature (5)
270
°C
T
J
Maximum Junction Temperature
150
°C
PJC
Package Thermal Resistance (Junction
-
to
-
Case) 86 Pin FP 5.0 °C/W
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings
only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect
device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation including output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883, Method 3015
(5) Maximum soldering temp of 270°C can be maintained for no more than 5 seconds.
RECOMMENDED OPERATING CONDITIONS (1)
Symbol
Parameter
Description
Units
Min Typ Max
VDD Supply Voltage (core) 1.65 1.80 1.95 Volts
VDD2
Supply Voltage (I/O)
2.3
2.5
2.7
Volts
Volts
TC External Package Temperature -55 25 125 °C
VPIN Voltage on Any Pin -0.3 VDD2+0.3 Volts
VDD2/VDD Ramp Time Supply Voltages Ramp Time 1E-5 1.0 Second
V
DD2
/ V
DD
PDT (2)
Power Supply
P
ower
D
own
T
5
m
(1) Voltages referenced to Vss.
(2) Power Supplies must be turned off for power down time before turned back on.
DC ELECTRICAL CHARACTERISTICS (1)
Symbol
Param
eter
Min
Max
Units
Test Conditions
I
DD
I
DD2
IDDSB (4) Static Supply Current TA=-55°C
TA =25°C
TA=125°C
12
18
160
1.2
1.2
1.2
mA
mA
mA
VDD=max, Iout=0mA,
Inputs Stable
IDDOP1 Dynamic Supply Current –
Deselected 0.4 0.8 mA VDD=max, Iout=0mA,
F=1MHz,
NCS=VIH (3)
IDDOP3 Operating Current – Disabled 8 20 mA VDD=max, Iout=0mA,
F=40MHz,
NCS=VIH (3)
HXSR06432 PRELIMINARY
6 www.honeywell.com/radhard
IDDOPW Dynamic Supply Current, Selected
(Write) 1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
5.6
10.3
50.3
125.3
200.3
0.95
1.9
7.6
18.3
29
mA
mA
mA
mA
mA
VDD2 and VDD=max,
Iout=0mA, NCS=VIL (1)
(2) (3)
IDDOPR Dynamic Supply Current, Selected
(Read) 1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
3.0
5.0
20.3
50.3
80.3
0.8
1.6
6.1
14.5
23.0
mA
mA
mA
mA
mA
VDD2 and VDD=max,
Iout=0mA, NCS=VIL (1)
(3)
IDR Data Retention Current TA=25°C
TA=125°C
80
0.8
mA
mA
VDD=1V, VDD2=2V
Symbol Parameter Min Max Units Test Conditions
II Input Leakage Current -10 10 µA
IOZ Output Leakage Current -20 20 µA Output = high Z
VIL Low-Level Input Voltage 0.25xVDD2 V VDD2=3.0V to 3.6V
VIH High-Level Input Voltage 0.75xVDD2 V VDD2=3.0V to 3.6V
VOL Low-Level Output Voltage 0.4 V VDD2=3.0V, IOL = 10mA
VOH High-Level Output Voltage 2.7 V VDD2=3.0V, IOH = 5mA
(1) Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, -55°C to +125°C, post total dose at 25°C.
(2) All inputs switching. DC average current.
(3) All dynamic operating mode current measurements (IDDOPx) exclude standby mode current (IDDSB)
(4) See graph below for typical static current values.
Typical IDD Standby C
urrent
0
20
4
0
60
8
0
100
0
20
40
60
80
100
120
140
Temperature (Degrees C)
Current (mA)
HXSR06432 PRELIMINARY
www.honeywell.com/radhard 7
CAPACITANCE (1)
Symbol Parameter
Worst Case (1)
Units Test Conditions
Min
Max
C
A
Address Input Capacitance
25
pF
V
IN
=V
DD
or V
SS
, f=1 MHz
C
C
NCS, NOE, NWE Input Capacitance
3
5
pF
V
IN
=V
DD
or V
SS
, f=1 MHz
C
D
Data I/O, NBE Capacitance
25
pF
V
IN
=V
DD
or V
SS
, f=1 MHz
(1) This parameter is tested during initial qualification only.
READ CYCLE AC TIMING CHARACTERISTICS (1)(2)
Symbol
Parameter VDD2 = 3.3V or 2.5V
Min Max Units
T
AVAVR
Read Cycle Time (3) 20, 22 ns
T
AVQV
Address Access Time (3) 20, 22 ns
T
AXQX
Address Change to Output Invalid Time 4 ns
T
SLQV
Chip Select Access Time (3) 21, 22 ns
T
SLQX
Chip Select Output Enable Time 0 ns
T
SHQZ
Chip Select Output Disable Time 4.0 ns
T
EHQV
Chip Enable Access Time (3) 21, 22 ns
T
EHQX
Chip Enable Output Enable Time 0 ns
T
ELQZ
Chip Enable Output Disable Time 4.8 ns
T
BLQV
Byte Enable Access Time 6
ns
T
BLQX
Byte Enable Output Enable Time 0
ns
T
BHQZ
Byte Enable Output Disable Time 4
ns
T
GLQV
Output Enable Access Time 6.2 ns
T
GLQX
Output Enable Output Enable Time 0 ns
T
GHQZ
Output Enable Output Disable Time 4.8 ns
(1) Test conditions: VIL/VIH=0V/Vdd. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics
diagrams. Capacitive output loading CL=5 pF for TSHQZ and TGHQZ.
(2) Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, TA=-55°C to 125°C, post total dose at 25°C.
(3) Values shown for 3.3V and 2.5V VDD2, respectively.
READ CYCLE TIMING
ADDRESS
DATA OUT
TAVAVR
TAVQV
TSLQV
TSLQX
NCS
TSHQZ
TEHQX
CE
DATA VALID
TAXQX
HIGH
IMPEDANCE
TELQZ
TEHQV
NOE
TGHQZ
TGLQX
TGLQV
NWE = HIGH
TBHQZ
TBLQV
TBLQX
HXSR06432 PRELIMINARY
8 www.honeywell.com/radhard
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
Parameter
V
DD2
= 3.3V
or
2.5V
Min
Max
Units
T
AVAVW
Write Cycle Time (2) 15 ns
T
WLWH
Write Enable Write Pulse Width 7 ns
T
SLWH
Chip Select to End of Write Time 10 ns
T
EHWH
Chip Enable to End of Write Time 10 ns
T
DVWH
Data Valid to End of Write Time 6 ns
T
AVWH
Address Valid to End of Write Time 12 ns
T
WHDX
Data Hold after End of Write Time 0 ns
T
AVWL
Address Valid Setup to Start of Write Time 0 ns
T
WHAX
Address Valid Hold after End of Write Time 0 ns
T
WLQZ
Write Enable to Output Disable Time 4.2 ns
T
WHQX
Write Disable to Output Enable Time 0 ns
T
WHWL
Write Disable to Write Enable Pulse Width (3) 5 ns
T
BLWH
Byte Enable to End of Write Time 10 ns
(1) Test conditions: VIL/VIH=0V/VDD. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics
diagrams. Capacitive output loading CL=5 pF for TWLQZ. Worst case operating conditions: VDD2=2.3V to 3.6V,
VDD=1.65V to 1.95V, -55°C to 125°C, post total dose 25°C
(2) TAVAVW = TWLWH + TWHWL
(3) Guaranteed but not tested
WRITE CYCLE TIMING
ADDRESS
DATA
OUT
TAVAVW
TAVWH
TWLQZ
NCS
TWHDX
CE
DATA VALID
TWHAX
HIGH
IMPEDANCE
TEHWH
NWE
TAVWL
TWHWL
TWLWH
TWHQX
DATA IN
TDVWH
TSLWH
NBE
TBLWH
HXSR06432 PRELIMINARY
www.honeywell.com/radhard 9
DYNAMIC ELECTRICAL OPERATION
Asynchronous Operation
The RAM is asynchronous in operation. Read and
Write cycles are controlled by NWE, NCS(0-3), CE,
NBE(0-3) and Address signals.
NBE(0-3) is used to control which of the 4 bytes is
written to or read from. These can be used
independently. When set to a low level, the signals
enable a normal read or write operation. When at a
high level, the write operation of a specific byte is
disabled and during a read operation, the 8 data
outputs of the specific byte are held in a high
impedance state.
NCS(0-3) is used to control which of the 4 SRAM die is
written to or read from One and only one signal line of
NCS(0-3) can be active (low) at a time. NCS(X) refers
to the one active low signal of NCS(0-3).
Read Operation
To perform a valid read operation, NCS(X), NBE(0-3)
and NOE must be low and NWE and CE must be high.
The output drivers can be controlled independently by
the NOE signal. Although not required, it is
recommended to delay NOE slightly relative to the
address and other control lines at the beginning of the
read cycle. This is done to minimize the potential for
coupling noise from the outputs back into the inputs
since up to 32 outputs can switch when NOE is
activated.
It is important to have the address bus free of noise and
glitches, which can cause inadvertent read operations.
The control and addr ess signals should have rising and
falling edges that are fast (<5 ns) and have good signal
integrity (free of noise, ringing or steps associated
reflections).
The read mode can be controlled via two different
control signals: CE and NCS(0-3). Both modes of
control are similar, except the signals are of opposite
polarity.
To control a read cycle with NCS(0-3), all addresses
must be valid prior to or coincident with the enabling
NCS(X) edge transition. Address edge transitions can
occur later than the specified setup times to NCS(X);
however, the valid data access time will be delayed.
Any address edge transition which occurs during the
time when NCS(X) is low, will initiate a new read
access, and data outputs will not become valid until
TAVQV time following the address edge transition. Data
outputs will enter a high impedance state T
SHQZ time
following a disabling NCS edge transition.
For an address activated read cycle, NCS(X) must be
valid prior to or coincident with the address edge
transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid TAVQV time following the latest
occurring address edge transition. The minimum
address activated read cycle time is T
AVAVR. When the
RAM is operated at the minimum address activated
read cycle time, the data outputs will remain valid on
the RAM I/O until T
AXQX
time following the next
sequential address transition.
To perform consecutive read operations, NCS(X) is
required to be held continuously low, and the toggling
of the addresses will start the new read cycle.
Write Operation
To perform a write operation, NWE, NCS(X) and
NBE(0-3) must be low and CE must be high.
The write mode can be controlled via three different
control signals: NWE, CE and NCS(0-3). All modes of
control are similar. Only the NWE controlled mode is
shown in the table and diagram on the previous page
for simplicity; however, each mode of control provides
the same write cycle timing characteristics. Thus, some
of the parameter names referenced below are not
shown in the write cycle table or diagram, but indicate
which control pin is in control as it switches high or low.
To write data into the RAM, NWE and NCS (X) must be
held low for at least T
WLWH/TSLWH/TEHWH time. Any
amount of edge skew between the signals can be
tolerated, and any one of the control signals can initiate
or terminate the write operation. The DATA IN must be
valid TDVWH time prior to switching high.
Consecutive write cycles can be performed by toggling
one of the control signals while the other remains in
their “write” state (NWE or NCS(X) held continuously
low). At least one of the control signals must transition
to the opposite state between consecutive write
operations.
For consecutive write operations, write pulses (NWE)
must be separated by the minimum specified
TWHWL
/TSHSL time. Address inputs must be valid at least
TAVWL time before the enabling NWE/NCS edge
transition, and must remain valid during the entire write
time. A valid data overlap of write pulse width time of
TDVWH, and an address valid to end of write time of
TAVWH also must be provided for during the write
operation. Hold times for address inputs and data
inputs with respect to the disabling NWE/NCS(X) edge
transition must be a minimum of T
WHAX time and T
WHDX
time, respectively. The minimum write cycle time is
TAVAVW.
HXSR06432 PRELIMINARY
10 www.honeywell.com/radhard
TESTER AC TIMING CHARACTERISTICS
VDD2/2
VDD 2/2
VDD
2
-
0.4 V
0.4 V
High Z
VDD2
-
0.5 V
High Z + 100mV
High Z
–
100mV
High Z = VDD
2
/2
Input
Levels*
* Input rise and fall times < 5 ns
Output
Sense
Levels
TESTER EQUIVALENT LOAD CIRCUIT
RELIABILITY
For more than 15 years Honeywell has been producing
integrated circuits that meet the stringent reliability
requirements of space and defense systems.
Honeywell has delivered thousands of QML parts since
first becoming QML qualified in 1990.
Using this proven approach Honeywell will assure the
reliability of the SRAMs manufactured with the S150
process technology. This approach includes adhering
to Honeywell’s General Manufacturing Standards for:
• Designing in reliability by establishing electrical
rules based on wear out mechanism
characterization performed on specially
designed test structures (electromigration,
TDDB, hot carriers, negative bias temperature
instability, radiation)
• Utilizing a structured and controlled design
process
• A statistically controlled wafer fabrication
process with a continuous defect reduction
process
• Individual wafer lot acceptance through process
monitor testing (includes radiation testing)
• The use of characterized and qualified packages
• A thorough product testing program based on
MIL-PRF-38535 and MIL-STD 883.
QUALIFICATION AND SCREENING
The S150 technology was qualified by Honeywell after
meeting the criteria of the General Manufacturing
Standards and is QML Qualified. This approval is the
culmination of years of development and requires a
considerable amount of testing, documentation, and
review.
The test flow includes screening units with the defined
flow (Class V and Q equivalent) and the appropriate
periodic or lot conformance testing (Groups B, C, D,
and E). Both the S150 process and the SRAM
products are subject to period or lot based Technology
Conformance Inspection (TCI) and Quality
Conformance Inspection (QCI) tests, respectively.
Group A
General Electrical Tests
Group B
Mechanical
-
Dimensions, bond strength,
solvents, die shear, solderability, Lead
Integrity, seal, acceleration
Group C
Life Tests
-
1000 hours at 125C or
equivalent
Group D
Package related mechanical tests
-
Shock, Vibration, Accel, salt, seal, lead
finish adhesion, lid torque, thermal
shock, moisture resistance
Group E
Radiation Tests
Honeywell delivers products that are tested to meet
your requirements. Products can be screened to
several levels including Proof of Design (POD),
Engineering Models, and Flight Units. PODs and EMs
are available with limited screening for prototype
development and evaluation testing.
DUT
Output
Valid Low
Output
Valid High
Output
VDD
2
/2
V
249
V1
V2
C
L
< 50 pf
HXSR06432 PRELIMINARY
11 www.honeywell.com/radhard
PACKAGING
The 512K x 32 SRAM is offered in an 86-lead flat pack.
This package is constructed of multi-layer ceramic
(Al2O3) and contains internal power and ground
planes. The package lid material is Kovar and the finish
is in accordance with the requirements of MIL-
PRF-38535. The finished, packaged part weighs
TBD grams.
VDD AND VDD2 CAPACITORS
The SRAM has four external capacitors as power
supply decoupling on VDD and VDD2. These are
adhered to the package using epoxy (conductive on
capacitor leads and non-conductive on the body) during
assembly.
C
= 0.1
µ
F
±
10%
VDD
C
C
VDD
2
C
C
PACKAGE OUTLINE
HXSR06432 PRELIMINARY
HXSR06432 PRELIMINARY
www.honeywell.com/radhard 13
ORDERING INFORMATION (1)
(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-763-954-2474 for further information.
(2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, no radiation guaranteed.
(3) Bare die do not receive any reliability screening.
(4) These receive the Class V screening and QCI is included. Customer must specify QCI requirements.
(5) These receive the Class V screening but do not have QCI included.
STANDARD MICROCIRCUIT DRAWING
The QML Certified SRAM can also be ordered under the SMD drawing TBD.
FIND OUT MORE
For more information about Honeywell’s family of radiation hardened products and technology, visit
www.honeywell.com/radhard.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others.
This product and related technical data is subject to the U.S. Department of State International Traffic in Arms Regulations (ITAR) 22 CFR 120-
130 and may
not be exported, as defined by the ITAR, without the appropriate prior authorization from the Directorate of Defense Trade
Controls, United States Department
of State. Diversion contrary to U.S. export laws and regulations is prohibited.
This datasheet includes only basic marketing information on the function of the
product and therefore is not considered technical data as defined in 22CFR 120.10.
H X
SR0
64
32
V H D
Source
H = Honeywell
PROCESS
X = SOI
PACKAGE DESIGNATION
D = 86 Lead Flatpack
- = Bare Die (3)
PART NUMBER
SCREEN LEVEL
V = QML Class V
Q = QML Class Q
Z = Class V Equivalent (4)
Y = Class Q+ Equivalent (5)
E = Eng. Model (2)
TOTAL DOSE HARDNESS
H = 1x106 rad (Si)
N = No Level Guaranteed (2)
Honeywell
12001 Highway 55
Plymouth, MN 55441
1-800-323-8295
www.honeywell.com/radhard
Form #900
363
July 2009
©200
9
Honeywell International Inc.