K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 1 - Mar. 2004
Document Title
256Kx16 Bit High Speed Static RAM(3.3V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMS UNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you hav e any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 0.3
Rev. 0.4
Rev. 1.0
Rev. 2.0
Rev. 2.1
Rev. 2.2
Rev. 2.3
Rev. 3.0
Rev. 4.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
Final
Final
Final
Final
History
Initial release with Preliminary.
Add Low Ver.
Package dimensions modify on page 11.
Change ICC , ISB, ISB1
1. Correct AC parameters : Read & Write Cycle
2. Change Data Retention Current :
from 0.45mA to 1.1mA when Vcc=3.0V
from 0.35mA to 0.9mA when Vcc=2.0V
3. Limit L-Ver. to 48 TBGA Package
1. Delete 12ns,15ns speed bin.
2. Change Icc for Industrial mode.
1. Add tBA,tBLZ,tBHZ,tBW AC parematers.
1. Correct the Package dimensions(48-TBGA)
1. Add the tPU and tPD into the waveform.
1. Change the current parameters (Isb1 L-ver, Idr)
1. Add the Lead Free Package type.
1. Change the Idr parameters
previous Current
Idr(2V) 1.2mA 1.4mA
Idr(3V) 1.8mA 2.0mA
Item Previous Current
ICC(Commercial)
8ns 110mA 80mA
10ns 90mA 65mA
12ns 80mA 55mA
15ns 70mA 45mA
ICC(Industrial)
8ns 130mA 100mA
10ns 115mA 85mA
12ns 100mA 75mA
15ns 85mA 65mA
ISB 30mA 20mA
ISB1(L-ver.) 0.5mA 1.2mA
Item Previous Current
ICC(Industrial) 8ns 100mA 90mA
10ns 85mA 75mA
Draft Data
Aug. 20. 2001
Sep. 19. 2001
Sep. 28. 2001
Oct. 09. 2001
Nov.23. 2001
Dec.18. 2001
Feb. 14. 2002
Oct. 23. 2002
Mar. 10, 2003
June. 12, 2003
June. 20, 2003
Mar. 15, 2004
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 2 - Mar. 2004
4Mb Async. Fast SRAM Ordering Information
Org. Part Number VDD(V) Speed ( ns ) PKG Temp . & Power
1M x4 K6R4004C1D-J(K)C(I) 10 5 10 J : 32-SOJ
K : 32-SOJ(LF) C : Commercial Temperature
,Normal Power Range
I : Ind u s trial Te mper a ture
,Normal Power Range
L : Commercial Temperature
,Low Power Range
P : Industrial Temperature
,Low Power Range
K6R4004V1D-J(K)C(I) 08/10 3.3 8/10
512K x8 K6R4008C1D-J(K,T,U)C(I) 10 5 10 J : 36-SOJ
K : 36-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
K6R4008V1D-J(K,T,U)C(I) 08/10 3.3 8/10
256K x16
K6R4016C1D-J(K,T,U,E)C(I) 10 5 10 J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10 3.3 8/10
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 3 - Mar. 2004
256K x 16 Bit High-Speed CMOS Static RAM
The K6R4016V1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 262,144 words by 16 bits. The
K6R4016V1D uses 16 comm on input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control(UB, LB). The device is fabri-
cated using SAMSUNG′s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The K6R4016V1D is packaged in a 400mil 44-pin plastic SOJ
or TSOP(II) forward or 48 TBGA.
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA( Max.)
(CMOS) : 5mA(Max.)
1.2mA(Max.)L-Ver. only.
Operating K6R4016V1D-08 : 80mA(Max.)
K6R4016V1D-10 : 65mA(Max .)
• Single 3.3 ±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three St ate Outputs
• 2V Minimum Data Retention: L-Ver. only.
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16
• Standard Pin Configuration
K6R4016V1D-J : 44-SOJ-400
K6R4016V1D-K : 44-SOJ-400(Lead-Free)
K6R4016V1D-T : 44-TSOP2-400BF
K6R4016V1D-U : 44-TSOP2-400BF (Lead-Free)
K6R4016V1D-E : 48-TBGA with 0.75 Ball pitch
(7mm X 9mm)
• Operating in Commercial and Industrial Temperature range.
Clk Gen.
I/O1~I/O8
OE
UB
CS
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont. Column Select
CLK
Gen.
Pre-Charge Circuit
Memo ry Array
1024 Rows
256 x 16 Columns
I/O Cir cui t &
I/O9~I/O16 Data
Cont.
WE
LB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 A11 A12 A13 A14 A15 A16 A17
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 4 - Mar. 2004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
PIN CONFIGURATION (Top View)
SOJ/
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A14
A13
A12
A11
A10
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
TSOP2
LB OE A0 A1 A2 N.C
I/O1 UB A3 A4 CS I/O9
I/O2 I/O3 A5 A6 I/O11 I/O10
Vss I/O4 A17 A7 I/O12 Vcc
Vcc I/O5 N.C A16 I/O13 Vss
I/O7 I/O6 A14 A15 I/O14 I/O15
I/O8 N.C A12 A13 WE I/O16
N.C A8 A9 A10 A11 N.C
1 2 3 4 5 6
A
B
C
D
E
F
G
H
48-TBGA
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Ab solute Maximu m Ratings" may cause per manent damag e to the device. This is a stres s rating only and
funct ional operatio n of the device at the se or any other condit ions above th ose indicated in the operating sect ions of this specification is not imp lied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Volt age on Any Pin Relative to VSS VIN, VOUT -0.5 to 4.6 V
Volt age on VCC Supply Relative to VSS VCC -0.5 to 4.6 V
Power Dissipation PD1.0 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA0 to 70 °C
Industrial TA-40 to 85 °C
PIN FUNCTION
Pin Name Pin Function
A0 - A17 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
LB Lower-byte Control(I/O1~I/O8)
UB Upper-byte Control(I/O9~I/O16)
I/O1 ~ I/O16 Data Inputs/ Outputs
VCC Power(+3.3V)
VSS Ground
N.C No Connection
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 5 - Mar. 2004
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
* The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 3.0 3.3 3.6 V
Ground VSS 000V
Input High Voltage VIH 2.0 - VCC+0.3*** V
Input Low Voltage VIL -0.3** - 0.8 V
CAPACITANCE*(TA=25°C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item Symbol Test Conditions TYP Max Unit
Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN VIN=0V - 6 pF
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
** L-var is only suppor ted with TB GA package type.
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN=VSS to VCC -2 2 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC -2 2 µA
Operating Current ICC Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA Com. 8ns - 80 mA
10ns - 65
Ind. 8ns - 90
10ns - 75
Standby Current ISB Min. Cycle, CS=VIH -20mA
ISB1 f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V Normal - 5
L-ver.** - 2.4
Output Low V oltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 6 - Mar. 2004
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter Value
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)
Output Loads(B)
DOUT
5pF*
319Ω
353Ω
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
DOUT RL = 50Ω
ZO = 50Ω
VL = 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
READ CYCL E *
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol K6R4016V1D-08 K6R4016V1D-10 Unit
Min Max Min Max
Read Cycle Time tRC 8-10-ns
Address Acc ess Time tAA -8-10ns
Chip Select to Output tCO -8-10ns
Output Enable to Valid Output tOE -4-5ns
UB, LB Access Time tBA -4-5ns
Chip Enable to Low-Z Output tLZ 3-3-ns
Output Enable to Low-Z Output tOLZ 0-0-ns
UB, LB Enable to Low-Z Output tBLZ 0-0-
ns
Chip Disable to High-Z Output tHZ 0405
ns
Output Disable to High-Z Output tOHZ 0405
ns
UB, LB Disable to High-Z Output tBHZ 0405ns
Output Hold from Address Change tOH 3-3-ns
Chip Selection to Power Up Time tPU 0-0-ns
Chip Selection to Power DownTime tPD -8-10ns
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 7 - Mar. 2004
Address
Data Out Previous Valid Data Valid Data
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Cont rol le d, CS=OE=VIL, WE=VIH, UB, LB=VIL)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Valid Dat a
High-Z
tRC
CS
Address
UB, LB
OE
Dat a out
tHZ(3,4,5)
tAA
tCO
tBA
tOE
tOLZ
tLZ(4,5) tOH
tOHZ
tBHZ(3,4,5)
tBLZ(4,5)
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol K6R4016V1D-08 K6R4016V1D-10 Unit
Min Max Min Max
Write Cycle Time tWC 8-10-ns
Chip Select to End of Write tCW 6-7-ns
Address Set-up Time tAS 0-0-
ns
Address Valid to End of Write tAW 6-7-
ns
Write Pulse Width(OE High) tWP 6-7-
ns
Write Pulse Width(OE Low) tWP1 8-10-ns
UB, LB Valid to End of Write tBW 6-7-ns
Write Recovery Time tWR 0-0-ns
Write to Output High-Z tWHZ 0405ns
Data to Write Time Overlap tDW 4-5-ns
Data Hold from Write Time tDH 0-0-
ns
End of Write to Output Low-Z tOW 3-3-ns
tPU tPD
50%
50%
VCC
Current
ICC
ISB
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 8 - Mar. 2004
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE Clock)
Address
CS
UB, LB
WE
Data in
Dat a out
tWC
tCW(3)
tBW
tWP(2)tAS(4)
tDH
tDW
tOHZ(6)
High-Z High-Z
Valid Dat a
OE
tAW tWR(5)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low fixed)
Address
CS
UB, LB
WE
Data in
Dat a out
tWC
tCW(3)
tBW
tWP1(2)
tDH
tDW
tWR(5)
tAS(4)
tOW
tWHZ(6) (10) (9)
High-Z
Valid Data
tAW
High-Z
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 9 - Mar. 2004
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A wri te occurs during the over lap of a low CS,WE,LB and UB. A write begin s at the latest transitio n CS going low and WE
going low ; A write ends at the earliest transition CS going hig h or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not . be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or afte r WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. Wh en CS is low : I/O p i ns ar e in th e o utput sta te. T he inpu t sign als in th e o ppo site p hase lead ing to th e ou tpu t sho uld n ot be
applied.
Address
CS
Valid Data
UB, LB
WE
Data in
Data out
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC
tCW(3)
tBW
tWP(2)
tDH
tDW
tWR(5)
tAW
tAS(4)
High-Z High-Z(8)
tBLZ tWHZ(6)
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
Address
CS
tAW
tDW tDH
Valid Dat a
WE
Data in
Dat a out High-Z High-Z(8)
UB, LB
tCW(3)
tWP(2)
tAS(4)
tWC
tWR(5)
High-Z
High-Z
tLZ tWHZ(6)
tBW
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 10 Mar. 2004
FUNCTIONAL DESCRIPTION
* X means Don′t Care.
CS WE OE LB UB Mode I/O Pin Supply Curr e nt
I/O1~I/O8I/O9~I/O16
H X X* X X Not Select High-Z High-Z ISB, ISB1
L H H X X Output Disable High-Z High-Z ICC
LXXHH
L H L L H Read DOUT High-Z ICC
HL High-Z DOUT
LL DOUT DOUT
LLXLH Write DIN High-Z ICC
HL High-Z DIN
LL DIN DIN
DATA RETENTION WAVE FORM
CS controlled
VCC
3.0V
VIH
VDR
CS
GND
Data Retention Mode
CS≥VCC - 0.2V
tSDR tRDR
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
Parameter Symbol Test Condition Min. Typ. Max. Unit
VCC for Data Retention VDR CS ≥VCC - 0.2V 2.0 - 3.6 V
Data Retention Current IDR VCC=3.0V, CS≥VCC - 0.2V
VIN ≥ VCC - 0.2V or VIN≤0.2V --2.0
mA
VCC=2.0V, CS≥VCC - 0.2V
VIN≥VCC - 0.2V or VIN≤0.2V --1.4
Data Retention Set-Up Time tSDR See Data Retention
Wave form(below) 0--ns
Recovery Time tRDR 5--ms
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 11 Mar. 2004
#1
44-SOJ-400
#44
25.58 ±0.12
1.125 ±0.005
MAX
28.98
1.141
MAX
0.148
3.76
1.19
( )
0.047
1.27
( )
0.050
0.95
( )
0.0375
+0.10
0.43 -0.05
+0.004
0.017 -0.002
+0.10
0.71 -0.05
+0.004
0.028 -0.002
1.27
0.050
10.16
0.400
+0.10
0.20 -0.05
+0.004
0.008 -0.002
9.40 ±0.25
0.370 ±0.010
MIN
0.69
0.027
#22
#23
0.004
0.10 MAX
11.18 ±0.12
0.440 ±0.005
PACKAGE DIMENSIONS Units:millimeters/Inches
1.00 ±0.10
0.039 ±0.004
44-TSOP2-400BF
0.002
#1
0.05
#22
#23
0.30
0.012 0.80
0.0315 MIN
0.047
1.20 MAX
0.741
18.81MAX
18.41 ±0.10
0.725 ±0.004
11.76 ±0.20
0.463 ±0.008
+ 0.075
- 0.035
0.50
+ 0.003
- 0.001
0.125
0.005
0.020
10.16
0.400
0.10
0.004
0~8°
0.45 ~0.75
0.018 ~ 0.030
( )
0.805
0.032
( ) MAX
Units:millimeters/Inches
#44
0.25
0.010TYP
+0.10
−0.05
+0.004
−0.002
K6R4016V1D CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 4.0
- 12 Mar. 2004
C1/2
PACKAGE DIMENSIONS Units : millimeter.
654321
A
B
C
D
E
F
G
H
C
B/2
B
C1
B
C
Bottom ViewTop View
D
E2
E1
E
C
Side View
0.55/Typ.
0.35/Typ.
A
Y
Detail A
Min Typ Max
A - 0.75 -
B 6.90 7.00 7.10
B1 - 3.75 -
C 8.90 9.00 9.10
C1 - 5.25 -
D 0.40 0.45 0.50
E 0.80 0.90 1.00
E1 - 0.55 -
E2 0.30 0.35 0.40
Y--0.08
0.50
0.50
B1
#A1
0.30
A1 INDEX MARK
Notes.
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity: 0.08(Max)
