Semiconductor Components Industries, LLC, 2013
April, 2013 − Rev. 1
1Publication Order Number:
NCP81172/D
NCP81172
2-Phase Synchronous Buck
Controller with Integrated
Gate Drivers and PWM VID
Interface
The NCP81172, a general−purpose two−phase synchronous buck
controller, integrates gate drivers and PWM VID interface in a
QFN−24 package and provides a compact−footprint power
management solution for new generation computing processors. It
receives power save command (PSI) from processors and operates in
1−phase diode emulation mode to obtain high efficiency in light−load
condition. Operating in high switching frequency up to 800 kHz
allows employing small size inductor and capacitors. The part is able
to support all−ceramic−capacitor applications.
Features
4.5 V to 24 V Input Voltage Range
Output Voltage up to 2.0 V with PWM VID Interface
Differential Output Voltage Sense
Integrated Gate Drivers
200 kHz ~ 800 kHz Switching Frequency
Power Saving Interface (PSI)
Power Good Output
Programmable Over Current Protection
Over Voltage Protection
Under Voltage Protection
Temperature Sense and Alert Output
Thermal Shutdown Protection
QFN−24, 4 x 4 mm, 0.5 mm Pitch Package
This is a Pb−Free Device
Typical Applications
GPU and CPU Power
Graphics Card Applications
Desktop and Notebook Applications
QFN24
CASE 485L
MARKING DIAGRAM
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Device Package Shipping†
ORDERING INFORMATION
NCP81172MNTXG QFN24
(Pb−Free)
4000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
PH219
LG220
PVCC21
PGND22
LG123
PH124
COMP
FB
FBRTN
FS
VREF
REFIN
12
11
10
9
8
7
654321
BST1
HG1
EN
PSI
VID
VIDBUF
131415161718
BST2
HG2
PGOOD
VCC
TALERT#
TSNS
25
GND
(Top View)
PINOUT
24
1
81172 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
81172
ALYWG
G
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NCP81172
21PVCC
2HG1
1BST1
24PH1
23LG1
VIN
17HG2
18BST2
19PH2
20LG2
VIN
10FBRTN
11FB
12COMP
25 GND
VOUT
+5 V
15 VCC
+5 V
6 VIDBUF
7 REFIN
8 VREF
13 TSNS
5
3
4
16
14
VID
PG
PSI
EN
TALT
EN
PSI
PGOOD
TALERT#
VID
+3.3 V
22PGND
9 FS
Figure 1. Typical Application Circuit with PWM−VID Interface
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NCP81172
21PVCC
2HG1
1BST1
24PH1
23LG1
VIN
17HG2
18BST2
19PH2
20LG2
VIN
10FBRTN
11FB
12COMP
25 GND
VOUT
+5 V
15 VCC
+5 V
6 VIDBUF
7 REFIN
8 VREF
13 TSNS
5
3
4
16
14
PG
PSI
EN
TALT
EN
PSI
PGOOD
TALERT#
VID
+3.3 V
22PGND
9 FS
Figure 2. Typical Application Circuit without PWM−VID Interface
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2
Gate Drive
1PVCC
HG1
PGND
23
LG1
24
PH1
21
PVCC
1
BST1
17
Gate Drive
2PVCC
HG2
20
LG2
19
PH2
18
BST2
PVCC
2/1 Phase
PWM
Control
PWM1
PWM2
Thermal
Management
UVLO
PSI
Control
22
PGND
Ramp
Generator
Reference
Voltage
15 VCC
16 PGOOD
9FS
3EN
13 TSNS
14 TALERT#
4PSI
8VREF
5VID
6VIDBUF
7REFIN
11 FB
10 FBRTN
25 GND
12 COMP
Current
Sense
PWM1
PH1
LG1
CS1
PWM2
PH2
LG2
CS2
RAMP1
RAMP2
GND
PH1
Figure 3. Functional Block Diagram
FAULT
&
PGOOD
&
Protections
(OVP, UVP, OCP)
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PIN DESCRIPTION
Pin Name Type Description
1 BST1 Analog Power Bootstrap 1. Provides bootstrap voltage for the high−side gate drive of phase 1.
A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH1 (pin 24).
2 HG1 Analog Output High−Side Gate 1. Directly connected with the gate of the high−side power MOSFET
of phase 1.
3 EN Logic Input Enable. Logic high enables the device and logic low makes the device in standby
mode.
4 PSI Logic Input Power Saving Interface. Logic high enables 2 phase CCM operation, mid level
enables 1−phase CCM operation, and logic low enables 1−phase CCM/DCM
operation.
5 VID Logic Input Voltage ID. Voltage ID input from processor.
6 VIDBUF Analog Output Voltage ID Buffer. VID PWM pulse output from an internal buffer.
7 REFIN Analog Input Reference Input. Reference voltage input for output voltage regulation. The pin is
connected to a non−inverting input of internal error amplifier.
8 VREF Analog Output Output Reference Voltage. Precise 2 V reference voltage output. A 10 nF ceramic
capacitor is required from this pin to GND.
9 FS Analog Input Frequency Selection. A resistor from this pin to ground programs switching frequency.
10 FBRTN Analog Input Voltage Feedback Return Input. An inverting input of internal error amplifier.
11 FB Analog Input Feedback. An inverting input of internal error amplifier.
12 COMP Analog Output Compensation. Output pin of error amplifier.
13 TSNS Analog Input Temperature Sensing. Temperature sensing input.
14 TALERT# Logic Output Thermal Alert. Open drain output and active low indicates over temperature.
15 VCC Analog Power Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger
ceramic capacitor bypasses this input to GND. This capacitor should be placed as
close as possible to this pin.
16 PGOOD Logic Output Power GOOD. Open−drain output. Provides a logic high valid power good output
signal, indicating the regulator’s output is in regulation window.
17 HG2 Analog Output High−Side Gate 2. Connected with the gate of the high−side power MOSFET in
phase 2.
18 BST2 Analog Power Bootstrap 2. Provides bootstrap voltage for the high−side gate drive of phase 2.
A 0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH2 (pin 19).
19 PH2 Analog Input Phase Node 2. Connected to interconnection between high−side MOSFET and
low−side MOSFET in phase 2.
20 LG2 Analog Output Low−Side Gate 2. Connected with the gate of the low−side power MOSFET in
phase 2.
21 PVCC Analog Power Voltage Supply of Gate Drivers. Power supply input pin of internal gate drivers.
A 4.7 mF or larger ceramic capacitor bypasses this input to ground. This capacitor
should be placed as close as possible to this pin.
22 PGND Analog Ground Power Ground. Power ground of internal gate drivers. Must be connected to the
system ground.
23 LG1 Analog Output Low−Side Gate 1. Connected with the gate of the low−side power MOSFET in
phase 1.
A resistor may be applied between this pin and GND to program OCP threshold.
24 PH1 Analog Input Phase Node 1. Connected to interconnection between high−side MOSFET and
low−side MOSFET in phase 1.
25 THERM/GND Analog Ground Thermal Pad and Analog Ground. Ground of internal control circuits. Must be
connected to the system ground.
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MAXIMUM RATINGS
Rating Symbol
Value
Unit
MIN MAX
PH to PGND VPH −2
−8 (<100 ns)
30 V
Gate Driver Supply Voltage PVCC to GND VPVCC −0.3 6.5 V
Supply Voltage VCC to GND VVCC −0.3 6.5 V
BST to PGND VBST_PGND −0.3 35 V
BST to PH VBST_PH −0.3 6.5 V
HG to PH VHG −0.3
−2 (<200 ns)
BST+0.3 V
LG to GND VLG −0.3
−2 (<200 ns)
PVCC+0.3 V
PGND to GND VPGND −0.3 0.3 V
FBRTN to GND VFBRTN −0.3 0.3 V
Other Pins to GND −0.3 VCC+0.3 V
Human Body Model (HBM) ESD Rating Are (Note 1) ESD HBM 2000 V
Machine Model (MM) ESD Rating Are (Note 1) ESD MM 200 V
Latch up Current: (Note 2)
All pins, except digital pins
Digital pins
ILU −100
−10
100
10
mA
Operating Junction Temperature Range (Note 4) TJ−40 125 C
Operating Ambient Temperature Range TA−40 100 C
Storage Temperature Range TSTG −40 150 C
Thermal Resistance Junction to Top Case (Note 5) RΨJC 6.0 C/W
Thermal Resistance Junction to Board (Note 5) RΨJB 7.5 C/W
Thermal Resistance Junction to Ambient (Note 4) RJA 50 C/W
Power Dissipation (Note 6) PD2.0 W
Moisture Sensitivity Level (Note 7) MSL 1 −
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. The thermal shutdown set to 150C (typical) avoids potential irreversible damage on the device due to power dissipation.
4. EDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM.
5. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM. For checking junction temperature using external measurement.
6. The maximum power dissipation (PD) is dependent on input voltage, maximum output current and external components selected. T ambient
= 25C, Tjunc_max = 125C, PD = (Tjunc_max−T_amb)/Theta JA
7. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are
referenced to TJ from −40C to 100C. unless other noted)
Characteristics Test Conditions Symbol Min Typ Max Unit
SUPPLY VOLTAGE
VIN Supply Voltage
Range
(Note 8) VIN 4.5 12 24 V
VCC Supply Voltage
Range
(Note 8) VCC 4.5 5 5.5 V
8. Guaranteed by design, not tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are
referenced to TJ from −40C to 100C. unless other noted)
Characteristics UnitMaxTypMinSymbolTest Conditions
SUPPLY VOLTAGE
PVCC Supply Voltage
Range
(Note 8) VPCC 4.5 5 5.5 V
VCC Under−Voltage
(UVLO) Threshold
VCC falling VCCUV−4.0 4.05 4.2 V
VCC OK Threshold VCC rising VCCOK 4.2 4.25 4.4 V
SUPPLY CURRENT
VCC Quiescent Current EN high, no switching, PS0
EN high, no switching, PS1/PS2 ICC
−
−
9
9
15
15
mA
mA
VCC Shutdown Current EN low IsdCC −30 50 mA
PVCC Quiescent Supply
Current
EN high, no switching, PS0
EN high, no switching, PS1/PS2 IPCC
−
−
0.35
0.35
0.6
0.6
mA
mA
PVCC Shutdown Current EN low IsdPCC − − 2.0 mA
SWITCHING FREQUENCY SETTING
PS0 Switching Frequency
Range
(Note 8) FSW 200 800 kHz
FS Voltage RFS = 39.2 kWVFS 2.0 V
VOLTAGE REFERENCE
VREF Reference Voltage IREF = 1 mA VVREF 1.98 2.0 2.02 V
PWM MODULATION
Minimum On Time (Note 8) Ton_min 50 ns
Minimum Off Time (Note 8) Toff_min 250 ns
Maximum Duty Cycle (Note 8) Dmax −100 −%
VOLTAGE ERROR AMPLIFIER
Open−Loop DC Gain (Note 8) GAINEA 80 dB
Unity Gain Bandwidth (Note 8) GBWEA 20 MHz
Slew Rate (Note 8) SRCOMP 20 V/ms
COMP Voltage Swing
ICOMP(source) = 2 mA VmaxCOMP 3.2 3.4 −V
ICOMP(sink) = 2 mA VminCOMP −1.05 1.15 V
FB, REFIN Bias Current VFB = VREFIN = 1.0 V IFB −400 400 nA
Input Offset Voltage VosEA = VREFIN − VFB (Note 8) VosEA −4 4 mV
REFIN Discharge Switch
ON−Resistance
IREFIN (sink) = 2 mA 6.25 W
CURRENT−SENSE AMPLIFIER
Closed−Loop DC Gain GAINCA −5.5 V/V
−3dB Gain Bandwidth (Note 8) BWCA 10 MHz
Input Offset Voltage VosCS = VPH − VPGND (Note 8) VosCS −500 −500 uV
ENABLE
EN High Threshold VhighEN 1.6 − − V
EN Low Threshold VlowEN − − 0.8 V
EN Input Bias Current External 1k pull−up to 3.3 V IbiasEN − − 1.0 mA
8. Guaranteed by design, not tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are
referenced to TJ from −40C to 100C. unless other noted)
Characteristics UnitMaxTypMinSymbolTest Conditions
POWER SAVE INPUT
PSI High Threshold Rising
Falling VhighPSI 2.05
2.4
2.2
2.55 V
PSI Low Threshold Rising
Falling
VlowPSI 0.5
0.8
0.6
0.95 V
PSI Input Bias Current IbiasPSI − − 1.0 mA
SOFT START AND PGOOD
Vout Startup Delay Measured from EN to Vout Start up from 0 V 1.15 ms
Cout Startup Slew Rate 3.0 V/ms
PGOOD Startup Delay Measured from EN to PGOOD assertion 2.0 ms
PGOOD Shutdown Delay Measured from EN to PGOOD de−assertion 125 ns
PGOOD Low Voltage IPGOOD= 4 mA (sink) VlPGOOD − − 0.3 V
PGOOD Leakage Current PGOOD = 5 V IlkgPGOOD − − 1.0 mA
PROTECTION
Current Limit Threshold
Measured from PGND to Phx
(RILMT(1%) is connected from LG1
to GND)
RILMT is open
VOCTH
110 122 134
mV
RILMT = 6.98 kW72 82 92
RILMT = 21.0 kW89 100 111
RILMT = 35.7 kW146 163 180
RILMT = 49.9 kWOCP is disabled −
Fast Under Voltage
Protection (FUVP)
Threshold
Voltage from FB to GND 0.15 0.2 0.25 V
Faster Under Voltage
Protection (FUVP) Delay
(Note 8) 2.0 ms
Slow Under Voltage
Protection (SUVP)
Threshold
Voltage from COMP to GND 3.0 V
Slow Under Voltage
Protection (SUVP) Delay
(Note 8) 50 us
Over Voltage Protection
(OVP) Threshold Voltage from FB to GND 1.85 2.0 2.15 V
Over Voltage Protection
(OVP) Delay
(Note 8) 2.0 ms
Over Temperature
Protection (OTP)
Threshold
(Note 8)
Tsd 140 150 C
Recovery Temperature
Threshold
(Note 8) Trec 125 C
Over Temperature
Protection (OTP) Delay (Note 8) 125 ns
OUTPUT DISCHARGE
Output Discharge
Resistance per Phase Measured from PHx to PGND when EN is low (Note 8) Rdischrg 2kW
8. Guaranteed by design, not tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12 V, VVCC = VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 3.3 V, typical values are referenced to TJ = 25C, Min and Max values are
referenced to TJ from −40C to 100C. unless other noted)
Characteristics UnitMaxTypMinSymbolTest Conditions
TSENSE and ALERT
TALERT# Assert
Threshold
Measured at TSNS (Temperature Rising) VlowTSNS 0.99 1.00 1.01 V
TALERT# De−Assert
Threshold
Measured at TSNS (Temperature Falling) VhighTSNS −1.05 −V
TALERT# Low Voltage IALERT= 4 mA (sink) VlowALERT − − 0.3 V
TALERT# Leakage
Current
TALERT# = 5 V IlkgALERT − − 1.0 mA
PWM−VID BUFFER
VID Input Threshold 1.4 V
Buffer Output Rise Time Tr3 ns
Buffer Output Fall Time Tf3 ns
Rising and Falling Edge
Delay
T = | Tr − Tf | (Note 8) T 0.5 ns
Propagation Delay Tpd = TpHL =TpLH Tpd 8 ns
Propagation Delay Error Tpd = TpHL – TpLH (Note 8) Tpd 0.5 ns
INTERNAL HIGH−SIDE GATE DRIVE
Pull−High Drive ON
Resistance
VBST – VPH = 5 V, IHG = 2 mA (source) RDRV_HH −1.5 −W
Pull−Low Drive ON
Resistance
VBST – VPH = 5 V, IHG = 2 mA (sink) RDRV_HL −1.0 −W
HG Propagation Delay
Time
From LG off to HG on TpdHG 16 ns
INTERNAL LOW−SIDE GATE DRIVE
Pull−High Drive ON
Resistance
VPVCC – VPGND = 5 V, ILG = 2 mA (source) RDRV_LH −1.0 −W
Pull−Low Drive ON
Resistance
VPVCC – VPGND = 5 V, ILG = 2 mA (sink) RDRV_LL −0.5 −W
LG Propagation Delay
Time
From HG off to LG on TpdLG 10 ns
BOOTSTRAP
On Resistance of
Rectifier Switch
VPVCC = 5 V, Id = 2 mA, TA = 25CRBST 5.0 14 20 W
Rectifier Switch Leakage
Current
VPVCC = 5 V, EN = 0 V IlkgBST − − 3mA
8. Guaranteed by design, not tested in production.
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DETAILED DESCRIPTION
General
The NCP81172, a 2−phase synchronous buck controller,
integrates gate drivers and PWM VID interface in a QFN−24
package and provides a compact−footprint power
management solution for new generation computing
processors. It receives power save input (PSI) from
processors and operates in 1−phase diode emulation mode
to obtain high efficiency in light−load condition. Operating
in high switching frequency up to 800 kHz allows
employing small size inductor and capacitors. Introduction
of multi−phase current−mode RPM control results in fast
transient response and good dynamic current balance. It is
able to support all−ceramic−capacitor applications.
Operation Modes
The NCP81172 has three power operation modes
responding to PSI levels as shown in Table 1. The operation
mode can be changed on the fly. In 1−phase operation, no
switching in phase 2.
Table 1. POWER SAVING INTERFACE (PSI) CONFIGURATION
PSI Level Power Mode Phase Configuration
High (PSI 2.4 V) PS0 2−Phase, FCCM
Intermediate (0.8 V < PSI < 2.4 V) PS1 1−Phase, FCCM
Low (PSI 0.8 V) PS2 1−Phase, Auto CCM/DCM
The NCP81172 is also able to support pure single−phase
applications without a need to stuff components for phase 2.
In this configuration, the four pins including BST2, HG2,
LG2, and PH2 can be float, but make sure the voltage at PSI
pin is never in high level.
Remote Voltage Sense
A high performance and high input impedance
differential error amplifier, as shown in Figure 4, provides
an accurate sense for the output voltage of the regulator. The
output voltage and FBRTN inputs should be connected to the
regulator’s output voltage sense points via a Kelvin−sense
pair. The output voltage sense signal goes through a
compensation network and into the inverting input (FB pin)
of the error amplifier. The non−inverting input of the error
amplifier is connected to the reference input (REFIN pin).
7REFIN
11 FB
10 FBRTN
25 GND
12 COMP
Figure 4. Differential Error Amplifier
Switching Frequency
Switching frequency is programmed by a resistor RFS
applied from the FS pin to ground. The typical frequency
range is from 200 kHz to 800 kHz. The FS pin provides
approximately 2 V out and the source current is mirrored
into the internal ramp generator. The switching frequency in
2−phase operation (PS0 mode) can be estimated by
FSW(kHz) +6603 @RFS(kW)−0.766 (eq. 1)
To reduce output ripple in 1−phase operation, the
switching frequency in PS1 and PS2 modes is set to be
higher than PS0 mode, which can be estimated by
FSW(kHz) +5226 @RFS(kW)−0.665 (eq. 2)
Figure 5 shows a measurement based on a typical
application under condition of Vin = 20 V, Vout = 0.9 V,
Iout = 10 A for PS1 mode operation and Iout = 20 A for PS0
mode operation. It can be also found that the higher RDS(on)
of the low−side MOSFETs the smaller frequency difference
between PS0 and PS1 mode.
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Figure 5. Switching Frequency Programmed by Resistor RFS at FS Pin
Soft Start
The NCP81172 has a soft start function. The output starts
to ramp up following a system reset period after the device
is enabled. The device is able to start up smoothly under an
output pre−biased condition without discharging the output
before ramping up.
REFIN Discharge
An internal switch in REFIN pin starts to short REFIN to
GND just after EN is pulled high and it turns off just before
the beginning of the soft start. The typical on resistance of
the switch is 6.25 W.
Output Discharge in Shut Down
The NCP81172 has an output discharge function when the
device is in shutdown mode. The resistors (2 kW per phase)
from PH node to PGND in both phases are active to
discharge the output capacitors.
Temperature Sense and Thermal Alert
The NCP81172 provides external temperature sense and
thermal alert in the normal operation mode, and disables the
function in the standby mode. The temperature sense and
thermal alert circuit diagram is shown in . An external
voltage divider, consisting of a NTC thermistor R_NTC and
a resistor R_TSNS, is employed to sense temperature and
program alert level. Usually the thermistor is placed close to
a hot spot like a power MOSFET. The NCP81172 monitors
the voltage at TSNS pin and compares the voltage to an
internal 1 V threshold by an internal comparator. Once the
TSNS voltage drops below 1 V, the comparator turns on an
open−drain switch at TALERT# pin and thus indicates a high
temperature alert. The thermal alert can be de−asserted when
TSNS voltage raises back to be higher than 1.05V. In an
exemplary application where a 100 kW (B = 4250 at 25C)
NTC thermistor is applied together with a 5.62 kW resistor,
an low−valid thermal alert signal is asserted when the
temperature of the NTC thermistor reaches 100C and
de−asserted when the temperature drops down to 97C.
Thermal Shutdown
The NCP81172 has a thermal shutdown protection to
protect the device from overheating when the die
temperature exceeds 150C. Once the thermal protection is
triggered, the fault state can be ended by re−applying VCC
and/or EN if the temperature drops down below 125C.
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8VREF
13 TSNS
1.0V
2.0V
14 TALERT #
R_NTC R_TSNSR_TALERT
3.3V
TALERT#
Figure 6. Temperature Sense and Thermal Alert Circuit Diagram
Over Current Protection
The NCP81172 protects converters from over current.
The current through each phase is monitored by voltage
sensing from phase node PHx to power ground PGND. The
sense signal is compared to an internal voltage threshold.
Once over load happens, the inductor current is limited to an
average current per phase, which can be estimated by
ILMT(phase) +
VthOC
RDS(phase)
(eq. 3)
where RDS(phase) is a total on conduction resistance of
low−side MOSFETs per phase. Normally, a continuous over
load event leads to a voltage drop in the output voltage and
possible to eventually trip under voltage protection.
The over−current threshold can be externally
programmed by adding a 1% tolerance resistor between
LG1 pin and GND. The selectable thresholds can be found
in the electrical table. Please note the maximum RC time
constant formed by the resistor and the total input
capacitance of the low−side MOSFETs should be smaller
than 300 ms in order to make sure the detection voltage
settles well.
Under Voltage Protection
There are two under voltage protections implemented in
the NCP81172, which are fast under voltage protection and
slow under voltage protection.
Fast under voltage protection (FUVP) protects converters
in case of an extreme short circuit in output by monitoring
FB voltage. Once FB voltage drops below 0.2 V for more
than 2 ms, the NCP81172 latches off, both the high−side
MOSFETs and the low-side MOSFETs in all phases are
turned off. The fault remains set until the system has either
VCC or EN toggled state. The FUVP function is disabled in
soft start.
Slow under voltage protection (SUVP) of the NCP81172
is based on voltage detection at COMP pin. In normal
operation, COMP level is below 2.5 V. When the output
voltage drops below REFIN voltage for long time and
COMP rises to be over 3 V, an internal UV fault timer will
be triggered. If the fault still exists after 50 ms, the
NCP81172 latches off, both the high-side MOSFETs and the
low−side MOSFETs in all phases are turned off. The fault
remains set until the system has either VCC or EN toggled
state.
Over Voltage Protection
Over voltage protection of the NCP81172 is based on
voltage detection at FB pin. Once FB voltage is over 2 V for
more than 2 ms, all the high−side MOSFETs are turned off
and all the low−side MOSFETs are latched on. The
NCP81172 latches off until the system has either VCC or EN
has toggled state.
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LAYOUT GUIDELINES
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction.
Power Paths: Use wide and short traces for power paths
to reduce parasitic inductance and high−frequency loop
area. It is also good for efficiency improvement.
Power Supply Decoupling: The power MOSFET
bridges should be well decoupled by input capacitors
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission. Place decoupling caps as close as
possible to the controller VCC and VCCP pins.
Output Decoupling: The output capacitors should be as
close as possible to the load like a GPU. If the load is
distributed, the capacitors should also be distributed
and generally placed in greater proportion where the
load is more dynamic.
Switching Nodes: Switching nodes between HS and LS
MOSFETs should be copper pours to carry high current
and dissipate heat, but compact because they are also
noise sources.
Gate Drive: All the gate drive traces such as HGx, LGx,
PHx, and BSTx should be short, straight as possible,
and not too thin. The bootstrap cap and an option
resistor need to be very close and directly connected
between BSTx pin and PHx pin.
Ground: It would be good to have separated ground
planes for PGND and GND and connect the two planes
at one point. PGND plane is an isolation plane between
noisy power traces and all the sensitive control circuits.
Directly connect the exposed pad (GND pin) to GND
ground plane through vias. The analog control circuits
should be surrounded by GND ground plane. GND
ground plane is connected to PGND plane by single
joint with low impedance.
Voltage Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
Current Sense: The NCP81172 senses phase currents by
monitoring voltages from phase nodes PHx to the
common ground PGND pin. PGND ground plane
should be well underneath PHx trances. To get better
current balance between the two phases, try to make a
layout as symmetrical as possible and balance the
current flow in PGND plane for the two phases.
Temperature Sense: A NTC thermistor is placed close
to a hot spot like a power MOSFET, and a filter
capacitor is placed close to TSNS pin of the controller.
To avoid the traces from/to the NTC thermistor to cross
over other sensitive control circuits.
Compensation Network: The compensation network
should be close to the controller. Keep FB trace short to
minimize their capacitance to GND.
PWM VID Circuit: The PWM VID is a high slew−rate
digital signal from GPU to the controller. The trace
routing of it should be done to avoid noise coupling
from the switching node and to avoid coupling to other
sensitive analog circuit as well. The RC network of the
PWM VID circuit needs to be close to the controller. A
10 nF ceramic cap is connected from VREF pin to
GND plane, and another small ceramic cap is connected
from REFIN pin to GND plane.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small−form factor VR with reduced temperature rise.
The exposed pads of the controller and power
MOSFETs must be well soldered on the board.
A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
More vias are welcome to be underneath the exposed
pads and surrounding the power devices to connect the
inner ground layers to reduce thermal resistances.
Use large area copper pour to help thermal conduction
and radiation.
Try distributing multiple heat sources to reduce
temperature rise in hot spots.
NCP81172
http://onsemi.com
14
PACKAGE DIMENSIONS
ÉÉÉ
ÉÉÉ
QFN24, 4x4, 0.5P
CASE 485L
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
SEATING
PLANE
D
B
0.15 C
A
A3
A
E
PIN 1
REFEENCE
2X 0.15 C
2X
0.08 C
0.10 C
C
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D4.00 BSC
D2 2.70 2.90
E4.00 BSC
E2 2.70 2.90
e0.50 BSC
L0.30 0.50
24X
L
D2
b
1
7
13
19
e/2
E2
e
24
0.10 B
0.05
AC
C
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
ÉÉ
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉ
ÇÇ
ÇÇ
A1
A3
TOP VIEW
SIDE VIEW
DETAIL B
BOTTOM VIEW
DETAIL A SOLDERING FOOTPRINT*
DIMENSIONS: MILLIMETERS
2.90
4.30
4.30
0.50
0.55
0.32
24X
24X
PITCH
1
2.90
RECOMMENDED
NOTE 4 A1
24X
NOTE 3
L1 0.05 0.15
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
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does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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