1PS8551 07/31/01
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PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger with 3-State Outputs
Logic Block Diagram
Product Features
PI74AVC+16268 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
True ±24mA Balanced Drive @ 3.3V
IOFF supports partial power-down operation
3.6 I/O Tolerant Inputs and Outputs
All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
Industrial operation: 40°C to +85°C
Available Packages:
 56-pin 240 mil wide plastic TSSOP (A)
 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74AVC+ series of logic circuits are
produced using the Companys advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger
designed for 1.65V to 3.6V VCC operation, is used for applications
in which data must be transferred from a narrow high-speed bus to
a wide, lower frequency bus. It provides synchronous data exchange
between the two ports. Data is stored in internal registers on the low-
to-high transition of the clock (CLK) input when appropriate clock-
enable (CLKEN) inputs are low. The select (SEL) line is synchronous
with CLK and selects 1B or 2B input data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to VCC through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
G1
C1
1D
1
B
1
OEB
CLK
CLKEN1B
SEL
1
1
C1
1D C1 1D
CE
C1
2
B
1
23
6
A1 8
28
56
55
30
27
2
29
CLKEN2B
CLKENA1
CLKENA2
CE
1D
V
V
CE
V
1D
V
CE
C1
1D
CE
C1
1D
VV
C1
V
OEA 1
1 of 12 Channels
C1
1D
V
2PS8551 07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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stupnIstuptuO
1ANEKLC2ANEKLCKLCAB1B2
HHXXB10
)2(
B20
)3(
LL↑LL
)2(
X
LL↑HH
)2(
X
XL↑LXL
XL↑HXH
stupnIstuptuO
KLCAEOBEOA B2,B1
HHZ Z
H LZ evitcA
LH evitcAZ
L L evitcAevitcA
Pin Description Pin Configuration
Notes:
1. H = High Signal Level, L = Low Signal Level, X = Irrelevant,
Z = High Impedance, ↑ = Transition, Low to High
2. Two CLK edges are needed to propagate data
3. Output level before indicated steady state input conditions
were established.
Truth Tables(1)
A to B STORAGE (OEB = L)
B to A STORAGE (OEA = L)
Output Enable
stupnI stuptuO
A
B1NEKLCB2NEKLCKLCLESB1B2
HXXHXX0A
)3(
XHXLXX0A
)3(
LX↑HLX L
LX↑HHX H
XL↑LXL L
XL↑LXH H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
CLKEN2B CLKENA1
1B3 1B4
GND GND
1B2 1B5
1B1 1B6
VCC VCC
A12 1B7
A11 1B8
A10 1B9
GND GND
A9 1B10
A8 1B11
A7 1B12
A6 2B12
A5 2B11
A4 2B10
GND GND
A3 2B9
A2 2B8
A1 2B7
VCC VCC
2B1 2B6
2B2 2B5
2B3 2B4
GND GND
CLKEN1B CLKENA2
OEA OEB
SEL CLK
56-Pin
A, K
emaNniPnoitpircseD
EO)WOLevitcA(tupnIelbanEtuptuO
KLCkcolC
LES)woLevitcA(tceleS
NEKLC)woLevitcA(elbanEkcolC
B2,B1,AstuptuOetatS-3
DNGdnuorG
V
CC
rewoP
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
3PS8551 07/31/01
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Recommended Operating Conditions(1)
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Supply voltage range, VCC .............................. 0.5V to +4.6V
Input voltage range, VI.................................... 0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ....... 0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) .......................... 0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) .................................... 50mA
Output clamp current, IOK (VO <0) ............................... 50mA
Continuous output current, IO..................................... ±50mA
Continuous current through each VCC or GND .......... ±100mA
Package thermal impedance, θJA(3): package A .........64°C/W
package K .................48°C/W
Storage Temperature range, Tstg ..................... 65°C to 150°C
Notes:
1. Input & output negative-voltage ratings may be exceeded if the
input and output curent rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V
maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with
JESD 51.
.niM.xaMstinU
V
CC
egatloVylppuS gnitarepO56.16.3
V
ylnonoitneterataD2.1
V
HI
egatloVtupnIlevel-hgiHV
CC
V2.1=V
CC
V
CC
V59.1otV56.1=x56.0V
CC
V
CC
V7.2otV3.2=7.1
V
CC
V6.3otV3=2
V
LI
egatloVtupnIlevel-woLV
CC
V2.1=DNG
V
CC
V59.1otV56.1=x53.0V
CC
V
CC
V7.2otV3.2=7.0
V
CC
V6.3otV3=8.0
V
I
egatloVtupnI 06.3
V
O
egatloVtuptuO etatSevitcA0V
CC
etatS-306.3
I
HO
tnerructuptuolevel-hgiH V
CC
V59.1otV56.1=6
Am
V
CC
V7.2otV3.2=21
V
CC
V6.3otV3=42
I
LO
tnerructuptuolevel-woL V
CC
V59.1otV56.1=6
V
CC
V7.2otV3.2=21
V
CC
V6.3otV3=42
∆t∆etarllafroesirnoitisnarttupnIvV
CC
V6.3otV56.1=5V/sn
T
A
erutarepmetria-eerfgnitarepO 0458C°
4PS8551 07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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sretemaraPsnoitidnoCtseT
)1(
V
CC
.niM.xaMstinU
V
HO
I
HO
001=µA V6.3otV56.1V
CC
V2.0
V
I
HO
6=m VA
HI
V70.1=V56.12.1
I
HO
21=m VA
HI
V7.1=V3.257.1
I
HO
42=m VA
HI
V2=V30.2
V
LO
I
LO
001=µA V6.3otV56.12.0
I
LO
6=m VA
HI
V75.0=V56.154.0
I
LO
21=m VA
HI
V7.0=V3.255.0
I
LO
42=m VA
HI
V8.0=V38.0
I
I
stupnIlortnoCV
I
V=
CC
DNGroV6.35.2±
Aµ
I
FFO
V
I
Vro
O
V6.3=001±
I
ZO
V
I
V=
CC
DNGroV6.301±
I
CC
V
O
V=
CC
IDNGro
O
0=V6.304
C
I
stupnIlortnoCV
I
V=
CC
DNGroV5.24
Fp
V3.34
stupnIataD V5.26
V3.36
C
O
stuptuOV
O
V=
CC
DNGro V5.28
V3.38
Note:
1. Typical values are measured at TA = 25°C.
DC Electrical Characteristics (Over the Operating Range, TA = 40°C +85°C)
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
5PS8551 07/31/01
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Timing Requirements (Over Operating Range)
sretemaraPnoitpircseD
V
CC
V2.1=
V
CC
V5.1=
V1.0±
V
CC
V8.1=
V51.0±
V
CC
V5.2=
V2.0±
V
CC
V3.3=
V3.0±
stinU.niM.xaM.niM.xaM.niM.xaM.niM.xaM.niM.xaM
f
KCOLC
kcolC
ycneuqerf 051081081zHM
t
W
esluP
,noitarud
hgihKLC
wolro
33 3
sn
t
US
puteS
emit
KLCerofebatadA ↑2.22.20.25.15.1
KLCerofebatadB ↑6.15.15.10.18.0
KLCerofebLES ↑0.28.15.13.11.1
ro1ANEKLC
ANEKLC 2
KLCerofeb ↑2.32.20.28.17.1
ro1BNEKLC
BNEKLC 2
KLCerofeb ↑2.34.20.28.17.1
KLCerofebEO ↑2.35.22.22.20.2
t
H
emitdloHKLCretfaatadA ↑5.05.02.02.01.0
KLCretfaatadB ↑0.10.10.10.10.1
KLCretfaLES ↑4.14.10.10.18.0
ro1ANEKLC
ANEKLC 2
KLCretfa ↑00 2.06.06.0
ro1BNEKLC
EKLC Ν2B
KLCretfa ↑00 1.06.06.0
KLCretfaEO ↑02.02.05.05.0
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
6PS8551 07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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Switching Characteristics (Over Operating Range)
Operating Characteristics, TA= 25°C
sretemaraPsnoitidnoCtseT
VCC V8.1=
V51.0±
VCC V5.2=
V2.0±
VCC V3.3=
V3.0± stinU
lacipyTlacipyTlacipyT
rewoPdpC
noitapissiD
ecnaticapaC
stuptuO
delbanE CL,Fp0=
zHM01=f
065667
Fp
stuptuO
delbasiD 045455
retemaraP
morF
)tupnI(
oT
)tuptuO(V
CC
V2.1=
V
CC
V5.1=
V1.0±
V
CC
V8.1=
V51.0±
V
CC
V5.2=
V2.0±
V
CC
V3.3=
V3.0± stinU
lacipyT.niM.xaM.niM.xaM.niM.xaM.niM.xaM
f
xam
051081081zHM
t
dp
KLCB1.80.50.28.48.10.43.11.3
sn
)B1(A0.95.51.20.57.12.42.14.3
)B2(B0.85.51.20.58.13.43.14.3
)LES(A3.95.65.24.54.23.47.16.3
t
ne
KLCB3.94.68.28.56.24.48.18.3
t
sid
B0.90.70.30.65.28.38.18.3
t
ne
A0.95.61.25.58.12.43.16.3
t
sid
A8.83.63.25.51.25.35.18.3
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
7PS8551 07/31/01
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V and 1.5V ±0.1V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 1. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
8PS8551 07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 2. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
1 kΩ
1 kΩ
0.15V
0.15V
30
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
9PS8551 07/31/01
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ±0.2V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 3. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.15V
–0.15V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
30
10 PS8551 07/31/01
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ±0.3V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO
Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 4. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
tPLH tPHL 0V
Output
VOH
VOL
VCC/2 VCC/2
VCC/2
VCC
VCC/2
Input
tW
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
t
su
t
h
V
CC
/2
V
CC
V
CC
/2
0V
V
CC
0V
Timing
Input V
CC
/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
0.3V
0.3V
30
PI74AVC+16268
12-Bit to 24-Bit Registered Bus
Exchanger w/3-State Outputs
11 PS8551 07/31/01
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Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
56-pin TSSOP (A) Package
56-pin TVSOP (K) Package
.002
.006
SEATING PLANE
.007
.011
.004
.008
1
56
.236
.244
0.50 0.17
0.27 0.05
0.15
0.09
0.20
X.XX
X.XX DENOTES DIMENSIONS
IN MILLIMETERS
.018
.030
0.45
0.75
.047
Max.
1.20
6.0
6.2
.547
.555 13.9
14.1
.319
8.1
.0197
BSC BSC
.047
.031
.041
SEATING
PLANE
.016
BSC
1
56
.169
.177
11.20
11.40
4.30
4.50
1.20
0.40 0.13
0.23
0.80
1.05
X.XX
X.XX DENOTES DIMENSIONS
IN MILLIMETERS
.002
.006
0.05
0.15
.0035
.008
0.09
0.20
.018
.030
0.45
0.75
6.4
.252
BSC
.005
.009
.441
.449
Max.
ataDgniredrOnoitpircseD
A86261+CVA47IP POSSTcitsalpediwlim042,nip-65
K86261+CVA47IP POSVTcitsalpediwlim371,nip-65
Ordering Information