CLC110AJPNOPB - National Semiconductor

CLC111

Ultra-High Slew Rate, Closed-Loop Buffer

General Description

The CLC111 is a high-performance, closed-loop, monolithic buffer

designed for applications requiring very high-frequency signals. The

CLC111's high performance includes an extremely fast 800MHz

small signal bandwidth (0.5Vpp) and an ultra high (3500V/µs) slew rate

while requiring only 10.5mA quiescent current. Signal fidelity is

maintained with low harmonic distortion (-62dBc 2nd and 3rd harmonics

at 20MHz). These performance characteristics are for a demanding

100Ω load.

Featuring a patented closed-loop design, the CLC111 offers nearly

ideal unity-gain (0.996) with very low (1.4Ω) output impedance. The

CLC111 is ideally suited for buffering video signals with its 0.15%/

0.04° differential gain and phase performance at 4.43MHz. Power

sensitive applications will benefit from the CLC111's excellent

performance on reduced or single supply voltages.

Constructed using an advanced, complementary bipolar process and

Comlinear's proven high-performance architectures, the CLC111 is

available in several versions to meet a variety of requirements.

CLC111AJP -40°C to +85°C 8-pin Plastic DIP

CLC111AJE -40°C to +85°C 8-pin Plastic SOIC

CLC111ALC -40°C to +85°C dice

CLC111AMC -55°C to +125°C dice qualified to Method 5008,

MIL-STD-883, Level B

Contact factory for other packages and DESC SMD number.

June 1999

CLC111

Ultra-High Slew Rate, Closed-Loop Buffer

Pinout

DIP & SOIC

Features

■Very wideband (800MHz)

■Ultra-high (3500V/µs) slew rate

■Very low output impedance (1.4Ω)

■Low (-62dBc) 2nd/3rd harmonics @ 20MHz

■60mA output current (±5 supplies)

■Single supply operation (0 to 3V supply min.)

■Evaluation boards and Spice models

Applications

■Video switch buffers

■Test point drivers

■High frequency active filters

■Wideband DC clamping buffer

■High-speed peak detector circuits

Single-Supply Circuit

Typical Application

CLC111

 1999 National Semiconductor Corporation http://www.national.com

Printed in the U.S.A.

PARAMETER CONDITIONS TYP MIN AND MAX RATINGS UNITS SYMBOL

Ambient Temperature CLC111AJ +25°C -40°C +25°C +85°C

FREQUENCY RESPONSE

small signal bandwidth Vout < 0.5Vpp 800 400 400 300 MHz SSBW

Vout < 4.0Vpp 450 250 250 200 MHz LSBW

gain flatness Vout < 0.5Vpp

flatness DC-50MHz 0.02 ±0.1 ±0.1 ±0.2 dB GFL

peaking DC-200MHz 0.1 1.0 0.5 0.5 dB GFPH

rolloff DC-200MHz 0.1 0.8 0.8 1.2 dB GFRH

differential gain 4.43MHz, 150Ω load 0.15 0.4 0.25 0.25 % DG

differential phase 4.43MHz, 150Ω load 0.04 0.08 0.08 0.08 ° DP

TIME DOMAIN RESPONSE

rise and fall time 0.5V step 0.6 0.8 0.8 1.1 n s TR S

4.0V step 1. 0 1. 4 1 .4 1 .7 n s T R L

settling time to ±0.1% 2.0V step 1 6 20 20 20 n s TS

overshoot 4V step 0 8 5 5 % OS1

slew rate 4V step 350 0 27 00 2700 2 300 V/µsec SR

DISTORTION AND NOISE PERFORMANCE

2nd harmonic distortion 2Vpp, 20MHz - 6 2 - 47 -50 - 50 dB c H D 2

3rd harmonic distortion 2Vpp, 20MHz - 6 2 - 55 - 55 - 5 2 dB c H D 3

equivalent output noise

voltage >1MHz 4.0 4.8 4.8 5.3 nV/√Hz VN

current >1MHz 1.6 4.0 3.0 3.0 pA/√Hz ICN

STATIC DC PERFORMANCE

small signal gain no load 0.996 0.994 0.994 0.992 V/V GA1

100Ω load 0.98 0.96 0.97 0.97 V/V GA2

output resistance DC 1.4 3.0 2.0 2.0 ΩRO

*output offset voltage 2 1 7 9 9 mV VIO

average temperature coefficient ±30 ±100 ±50 µV/°C DVIO

*input bias current 5 3 0 1 5 1 5 µAIBN

average temperature coefficient 50 ±187 ±100 nA/°C DIBN

power supply rejection ratio -52 -48 -48 -46 dB PSRR

* supply current no load 10.5 12 12 12 mA ICC

MISCELLANEOUS PERFORMANCE

integral endpoint linearity ±2V, full scale 0.2 1.0 0.5 0.5 % ILIN

input resistance 1 0.3 0.7 1 MΩRIN

input capacitance CERDIP 2.5 3.5 3.5 3.5 pF CIN

Plastic DIP 1.25 2.0 2.0 2.0 pF CIN

output voltage range no load 3.9 3.5 3.6 3.6 V VO

RL=100Ω3.5 +3.1,-2.5 3.2 3.2 V VOL

RL=100Ω, 0°C ±3.1 V VOL

output current 6 0 50,25 50 40 mA IO

0° - 70°C 50,35 50 50 mA IO

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are

determined from tested parameters.

CLC109 Electrical Characteristics (±V(±V

(±V(±V

(±Vcc cc

cc cc

cc = ±5V= ±5V

= ±5V= ±5V

= ±5V,,

, R R

R R

RL L

L L

L = 100= 100

= 100= 100

= 100ΩΩ

ΩΩ

Ω))

))

)

Absolute Maximum Ratings Miscellaneous Ratings

Vcc ±7.0V

Iout output is short circuit protected to

ground, but maximum reliability will be

maintained if Iout does not exceed... 80mA

input voltage ±V cc

maximum junction temperature +150°C

operating temperature range

A J -40°C to +85°C

storage temperature range -65°C to +150°C

lead temperature (soldering 10 sec) +300°C

ESD rating 1000V

CLC111 Electrical Characteristics (±V cc = ± 5V, RL = 100ΩΩ

ΩΩ

Ω unless specified)

Notes:

* A J : 100% tested at +25°C.

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Package Thermal Resistance

Package θJC θJA

Plastic(AJP) 70°C/W 125°C/W

Surface Mount (AJE) 65°C/W 145°C/W

Reliability Information

Transistor count 17

PARAMETERS CONDITIONS VCC = 3V VCC = 5V UNITS

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth Vout < 0.5Vpp 120 300 MHz

Vout < 2.0Vpp 210 MHz

gain flatness Vout < 0.5Vpp

flatness DC to 30MHz 0.5 0 .1 d B

peaking DC to 200MHz 0 0 dB

roll off DC to 60MHz 1.5 0.25 dB

TIME DOMAIN RESPONSE

rise and fall time 0.5V step 3. 9 1.2 ns

2.0V step 1.5 ns

overshoot 1.0V step 3 3 %

slew rate 0.5V step 2 60 4 25 V/µs

DISTORTION AND NOISE RESPONSE

2nd harmonic distortion 0.5Vpp,20MHz -46 dBc

1.0Vpp,20MHz -55 dBc

3rd harmonic distortion 0.5Vpp,20MHz -44 dBc

1.0Vpp,20MHz -64 dBc

STATIC DC PERFORMANCE

small-signal gain AC-coupled 0.96 0.97 V/V

supply current RL= ∞2.0 4.5 mA

MISCELLANEOUS PERFORMANCE

output voltage range RL= ∞1.5 3.4 Vpp

RL=100Ω1.1 2.6 Vpp

Electrical Characteristics (VCC = +3V or VCC = +5V, -VEE = 0V, TA = +25°C, RL = 100ΩΩ

ΩΩ

Ω, unless noted)

Operation

The CLC111 is a low-power, very high-speed unity-gain

buffer. It uses a closed-loop topology which allows for

accuracy not usually found in high-speed open-loop buffers.

A slew enhanced front end allows for low quiescent power

while not sacrificing ac performance.

Single Supply Operation

Although the CLC111 is specified to operate from split ±5V

power supplies, there is no internal ground reference that

prev ents operation from a single voltage power supply. For

single supply operation the input signal should be

biased at a DC value of ½VCC. This can be accomplished

by AC coupling and rebiasing as shown in Figure 1.

The above electrical specifications provide typical perfor-

mance specifications for the CLC111 at 25°C while operat-

ing from a single +3V or a single +5V power supply.

Printed Circuit Layout and Supply Bypassing

As with any high-frequency device, a good PCB layout is

required for optimum performance. This is especially

important for a device as fast as the CLC111.

To minimize capacitive feedthrough, pins 2, 3, 6, and 7

should be connected to the ground plane, as shown in Figure

1. Input and output traces should be laid out as transmission

lines with the appropriate termination resistors very near the

CLC111. On a 0.065 inch epoxy PCB material, a 50Ω

transmission line (commonly called stripline) can be

constructed by using a trace width of 0.1" over a complete

ground plane.

Figure 1 shows recommended power supply bypassing.

The ferrite beads are optional and are recommended only

where additional isolation is needed from high-frequency

(>400MHz) resonances in the power supply.

Parasitic or load capacitance directly on the output of the

CLC111 will introduce additional phase shift in the device.

This phase shift can decrease phase margin and increase

frequency response peaking. A small series resistor before

the capacitance effectively decouples this effect. The graphs

on the following page illustrate the required resistor value and

the resulting performance vs. capacitance.

Precision buffed resistors (PRP8351 series from Precision

Resistive Products), which have low parasitic reactances,

were used to develop the data sheet specifications. Precision

carbon composition resistors or standard spirally-trimmed

RN55D metal film resistors will work, though they will cause

a slight degradation of ac performance due to their reactive

nature at high frequencies.

Evaluation Boards

Evaluation boards are available from National as part

numbers CLC730012 (DIP) and CLC730045 (SOIC). This

board was used in the characterization of the device and

provides optimal performance. Designers are encouraged to

copy these printed circuit board layouts for their applications.

Figure 1: Recommended circuit & evaluation

board schematic

+5V

-5V 0.01µF

0.01µF

6.8µF

ferrite

bead (optional)

ferrite

bead (optional)

2367

out

CLC111

out

is chosen for

desired output impedance.

(CLC111 R

= 1.4Ω)

is chosen

for desired

input impedance.

3http://www.national.com

See "Typical Application" section on front page.

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CLC111

Ultra-High Slew Rate, Closed-Loop Buffer

http://www.national.com 6

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