1. General description
The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for
embedded applications featuring a high level of integration and low power consumption.
The ARM Cortex-M3 is a next generation core that offers system enhancements such as
enhanced debug features and a higher level of support block integration.
The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The
LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU
incorporates a 3- stage pipelin e an d us es a Ha rva rd arc hit ec tu re with separate loca l
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of
flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG
interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP
controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface,
8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface,
four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time
Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.
The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x
ARM7-based microcontroller series.
2. Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
(LPC1768/67/66/65/6 4/63) or of up to 120 MHz (LPC17 69). A Memo ry Protection Unit
(MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash programming memory . Enhanced flash memory accelerator
enables high-speed 120 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
On-chip SRAM includes:
32/16 kB of SRAM on the CPU with local code/dat a bus for high-per formance CPU
access.
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Rev. 9.3 — 8 January 2014 Product data sheet
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Product data sheet Rev. 9.3 — 8 January 2014 2 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose CPU instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, and for
memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays.
Split APB bus allows high throughput with few stalls between the CPU and DMA.
Serial interfaces:
Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on
all parts, see Table 2.)
USB 2.0 full-speed devic e/H ost/ OT G co nt ro ller with de dic ated DMA contr o ller and
on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see
Table 2.)
Four UAR Ts with fractional baud rate genera ti on, inter nal FIFO, and DMA su ppo rt.
One UART has modem control I/O and RS-485/EIA-485 support, and one UART
has IrDA support.
CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.)
SPI controller with synchronous, serial, full duplex communication and
programmable data length.
Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
Three enhanced I2C bus interfaces, one with an open-drain output supporting full
I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard
port pins. Enhancements include multiple address recognition and monitor mode.
I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S-bus interface can be used with th e GPDMA. Th e I2S- bus in te rface
supports 3-wire and 4-wire data transmit and receive as well as master clock
input/output. (Not available on all parts, see Table 2.)
Other periph er als :
70 (100 pin package) General Purpose I/O (GPIO) pins with configurable
pull-up/down resistors. All GPIOs sup port a new , configurab le open-drain operating
mode. The GPIO block is accessed through the AHB multilayer bus for fast access
and located in memory such that it supports Cortex-M3 bit banding and use by the
General Purpose DMA Controller.
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support. (Not available on all parts, see Table 2)
Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
One motor control PWM with support for three-phase motor control.
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Product data sheet Rev. 9.3 — 8 January 2014 3 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Quadrature encoder interface that can monitor one external quadrature encoder.
One standard PWM/timer block with external count input.
RTC with a separate power domain and dedicated RTC oscillator. The RTC block
includes 20 bytes of battery-powered backup registers.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
ARM Cortex-M3 system tick timer, including an external clock input option.
Repetitive inter ru p t timer pr ovides program ma b le an d re pe a tin g ti med inte rr up ts.
Each peripheral ha s its own clock divider for further power savings.
Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire
Debug and Serial Wire Trace Port options.
Emulation trace module enables non-intrusive, high-speed real-time tracing of
instruction execution.
Integrated PMU (Power Management Unit) automatically adjusts internal regulators to
minimize power consumption during Sleep, Deep sleep, Power-down, and Deep
power-down modes.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
Single 3.3 V power supply (2.4 V to 3.6 V).
Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0
and Port 2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NM I) input.
Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, and the USB clock.
The W ake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI).
Brownout detect with separate threshold for interrupt and forced reset.
Power-On Reset (POR).
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a
system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
USB PLL for added flexibility.
Code Read Protection (CRP) with different security levels.
Unique device serial number for identification purposes.
Available as LQFP100 (14 mm 14 mm 1.4 mm) and TFBGA1001 (9 mm 9 mm
0.7 mm) package.
1. LPC1768/65 only.
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Product data sheet Rev. 9.3 — 8 January 2014 4 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
3. Applications
4. Ordering information
4.1 Ordering options
eMetering Alarm systems
Lighting White goods
Industrial networking Motor contro l
Table 1. Ordering information
Type number Package
Name Description Version
LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
Table 2. Ordering options
Type number Flash SRAM in kB Ethernet USB CAN I2SDAC Maximum
CPU
operating
frequency
CPU AHB
SRAM0 AHB
SRAM1 Total
LPC1769FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 120 MHz
LPC1768FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz
LPC1768FET100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz
LPC1767FBD100 512 kB 32 16 16 64 yes no no yes yes 100 MHz
LPC1766FBD100 256 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz
LPC1765FBD100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz
LPC1765FET100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz
LPC1764FBD100 128 kB 16 16 - 32 yes Device only 2 no no 100 MHz
LPC1763FBD100 256 kB 32 16 16 64 no no no yes yes 100 MHz
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Product data sheet Rev. 9.3 — 8 January 2014 5 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
5. Marking
The LPC176x devices typically have the following top-side marking:
LPC176xxxx
xxxxxxx
xxYYWWR[x]
The last/second to last letter in the third line (field ‘R’) will identify the device revision. This
data sheet covers the following revisions of the LPC176x:
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the
device was manufactured during that year.
Table 3. Device revision table
Revision identifier (R) Revision descrip tion
‘-’ Initial device revision
‘A Second device revision
‘B’ Third device revision
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Product data sheet Rev. 9.3 — 8 January 2014 6 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
6. Block diagram
(1) Not available on all parts. See Table 2.
Fig 1. Block diagram
SRAM 32/64 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
FLASH
ACCELERATOR
FLASH
512/256/128 kB
DMA
CONTROLLER
ETHERNET
CONTROLLER
WITH DMA(1)
USB HOST/
DEVICE/OTG
CONTROLLER
WITH DMA(1)
I-code
bus D-code
bus system
bus
AHB TO
APB
BRIDGE 0
HIGH-SPEED
GPIO AHB TO
APB
BRIDGE 1
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTAL1
XTAL2 RESET
clocks and
controls
JTAG
interface
debug
port
USB PHY
SSP0
UART2/3
I2S(1)
I2C2
RI TIMER
TIMER2/3
EXTERNAL INTERRUPTS
SYSTEM CONTROL
MOTOR CONTROL PWM
QUADRATURE ENCODER
SSP1
UART0/1
CAN1/2(1)
I2C0/1
SPI0
TIMER 0/1
WDT
PWM1
12-bit ADC
PIN CONNECT
GPIO INTERRUPT CONTROL
RTC
BACKUP REGISTERS
32 kHz
OSCILLATOR
APB slave group 1
APB slave group 0
DAC(1)
RTC POWER DOMAIN
LPC1769/68/67/
66/65/64/63
master master master
002aad944
slaveslave slave slave
slave ROM
slave
MULTILAYER AHB MATRIX
P0 to
P4
SDA2
SCL2
SCK0
SSEL0
MISO0
MOSI0
SCK1
SSEL1
MISO1
MOSI1 RXD2/3
TXD2/3
PHA, PHB
INDEX
EINT[3:0]
AOUT
MCOA[2:0]
MCOB[2:0]
MCI[2:0]
MCABORT
4 × MAT2
2 × MAT3
2 × CAP2
2 × CAP3
3 × I2SRX
3 × I2STX
TX_MCLK
RX_MCLK
RTCX1
RTCX2
VBAT
PWM1[7:0]
2 × MAT0/1
2 × CAP0/1
RD1/2
TD1/2
SDA0/1
SCL0/1
AD0[7:0]
SCK/SSEL
MOSI/MISO
8 × UART1
RXD0/TXD0
P0, P2
PCAP1[1:0]
RMII pins USB pins
CLKOUT
MPU
= connected to DMA
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Product data sheet Rev. 9.3 — 8 January 2014 7 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
7. Pinning information
7.1 Pinning
Fig 2. Pin configuration LQ FP10 0 packa g e
Fig 3. Pin configuration TFBGA100 package
LPC176xFBD100
50
1
25
75
51
26
76
100
002aad945
002aaf723
LPC1768/65FET100
Transparent top view
J
G
K
H
F
E
D
C
B
A
24681013579
ball A1
index area
Table 4. Pin allocation table TFBGA100
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Row A
1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN
5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/
RD2/CAP2[0]
9 P0[7]/I2STX_CLK/
SCK1/MAT2[1] 10 P0[9]/I2STX_SDA/
MOSI1/MAT2[3] 11 - 12 -
Row B
1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1
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Product data sheet Rev. 9.3 — 8 January 2014 8 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
5 P1[9]/ENET_RXD0 6 P1[17]/
ENET_MDIO 7V
SS 8 P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 -
Row C
1TCK/SWDCLK 2TRST 3 TDI 4 P0[2]/TXD0/AD0[7]
5 P1[8]/ENET_CRS 6 P1[15]/
ENET_REF_CLK 7 P4[28]/RX_MCLK/
MAT2[0]/TXD3 8 P0[8]/I2STX_WS/
MISO1/MAT2[2]
9V
SS 10 VDD(3V3) 11 - 12 -
Row D
1 P0[24]/AD0[1]/
I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/
I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/
AOUT/RXD3 4n.c.
5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/
TD2/CAP2[1] 8 P2[2]/PWM1[3]/
CTS1/TRACEDATA[3]
9 P2[4]/PWM1[5]/
DSR1/TRACEDATA[1] 10 P2[5]/PWM1[6]/
DTR1/TRACEDATA[0] 11 - 12 -
Row E
1V
SSA 2V
DDA 3VREFP 4n.c.
5 P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0] 6 P4[29]/TX_MCLK/
MAT2[1]/RXD3 7 P2[3]/PWM1[4]/
DCD1/TRACEDATA[2] 8 P2[6]/PCAP1[0]/
RI1/TRACECLK
9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 -
Row F
1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/
AD0[5]
5 P1[21]/MCABORT/
PWM1[3]/SSEL0 6 P0[18]/DCD1/
MOSI0/MOSI 7 P2[9]/USB_CONNECT/
RXD2 8 P0[16]/RXD1/
SSEL0/SSEL
9 P0[17]/CTS1/
MISO0/MISO 10 P0[15]/TXD1/
SCK0/SCK 11 - 12 -
Row G
1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D
5 P1[25]/MCOA1/
MAT1[1] 6 P1[29]/MCOB2/
PCAP1[1]/MAT0[1] 7V
SS 8 P0[21]/RI1/RD1
9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 -
Row H
1 P1[30]/VBUS/
AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/
PWM1[2] 4 P1[18]/USB_UP_LED/
PWM1[1]/CAP1[0]
5 P1[24]/MCI2/
PWM1[5]/MOSI0 6V
DD(REG)(3V3) 7 P0[10]/TXD2/
SDA2/MAT3[0] 8P2[11]/EINT1/
I2STX_CLK
9V
DD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 -
Table 4. Pin allocation table TFBGA100 …continued
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
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Product data sheet Rev. 9.3 — 8 January 2014 9 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
7.2 Pin description
Row J
1 P0[28]/SCL0/
USB_SCL 2 P0[27]/SDA0/
USB_SDA 3 P0[29]/USB_D+ 4 P1[19]/MCOA0/
USB_PPWR/
CAP1[1]
5 P1[22]/MCOB0/
USB_PWRD/
MAT1[0]
6V
SS 7 P1[28]/MCOA2/
PCAP1[0]/
MAT0[0]
8 P0[1]/TD1/RXD3/SCL1
9 P2[13]/EINT3/
I2STX_SDA 10 P2[10]/EINT0/NMI 11 - 12 -
Row K
1 P3[26]/STCLK/
MAT0[1]/PWM1[3] 2V
DD(3V3) 3V
SS 4 P1[20]/MCI0/
PWM1[2]/SCK0
5 P1[23]/MCI1/
PWM1[4]/MISO0 6 P1[26]/MCOB1/
PWM1[6]/CAP0[0] 7 P1[27]/CLKOUT
/USB_OVRCR/
CAP0[1]
8 P0[0]/RD1/TXD3/SDA1
9 P0[11]/RXD2/
SCL2/MAT3[1] 10 P2[12]/EINT2/
I2STX_WS 11 - 12 -
Table 4. Pin allocation table TFBGA100 …continued
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Table 5. Pin description
Symbol Pin/ball Type Description
LQFP100
TFBGA100
P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual dire ction controls for each
bit. The operation of port 0 pins depends upon the pin function selected via
the pin connect block. Pins 12, 13, 14, and 31 of this port are not available.
P0[0]/RD1/TXD3/
SDA1 46 K8 [1] I/O P0[0] — General purpose digital input/output pin.
IRD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only).
OTXD3 — Transmitter output for UART3.
I/O SDA1 — I2C1 data input/output. (This is not an I2C-bus compliant
open-drain pin).
P0[1]/TD1/RXD3/
SCL1 47 J8 [1] I/O P0[1] — General purpose digital input/output pin.
OTD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only).
IRXD3 — Receiver input for UART3.
I/O SCL1 — I2C1 clock input/output. (This is not an I2C-bus compliant
open-drain pin).
P0[2]/TXD0/AD0[7] 98 C4 [2] I/O P0[2] — General purpose digital input/o utput pin.
OTXD0 — Transmitter output for UART0.
IAD0[7] — A/D converter 0, input 7.
P0[3]/RXD0/AD0[6] 99 A2 [2] I/O P0[3] — General purpose digital input/output pin.
IRXD0 — Receiver input for UART0.
IAD0[6] — A/D converter 0, input 6.
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NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
81 A8 [1] I/O P0[4] — General purpose digital input/output pin.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
IRD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only).
ICAP2[0] — Capture input for Timer 2, channel 0.
P0[5]/
I2SRX_WS/
TD2/CAP2[1]
80 D7 [1] I/O P0[5] — General purpose digital input/output pin.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification. (LPC1769/68/67/66/65/63 on ly).
OTD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only).
ICAP2[1] — Capture input for Timer 2, channel 1.
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
79 B8 [1] I/O P0[6] — General purpose digital input/output pin.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
I/O SSEL1 — Slave Select for SSP1.
OMAT2[0] — Match output for Timer 2, channel 0.
P0[7]/
I2STX_CLK/
SCK1/MAT2[1]
78 A9 [1] I/O P0[7] — General purpose digital input/output pin.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
I/O SCK1 — Serial Clock for SSP1.
OMAT2[1] — Match output for Timer 2, channel 1.
P0[8]/
I2STX_WS/
MISO1/MAT2[2]
77 C8 [1] I/O P0[8] — General purpose digital input/output pin.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification. (LPC1769/68/67/66/65/63 on ly).
I/O MISO1 — Master In Slave Out for SSP1.
OMAT2[2] — Match output for Timer 2, channel 2.
P0[9]/
I2STX_SDA/
MOSI1/MAT2[3]
76 A10 [1] I/O P0[9] — General purpose digital input/output pin.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
I/O MOSI1 — Master Out Slave In for SSP1.
OMAT2[3] — Match output for Timer 2, channel 3.
P0[10]/TXD2/
SDA2/MAT3[0] 48 H7 [1] I/O P0[10] — General purpose digital input/output pin.
OTXD2 — Transmitter output for UART2.
I/O SDA2 — I2C2 data input/output (this is not an open-drain pin).
OMAT3[0] — Match output for Timer 3, channel 0.
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 11 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P0[11]/RXD2/
SCL2/MAT3[1] 49 K9 [1] I/O P0[11] — General purpose digital input/output pin.
IRXD2 — Receiver input for UART2.
I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin).
OMAT3[1] — Match output for Timer 3, channel 1.
P0[15]/TXD1/
SCK0/SCK 62 F10 [1] I/O P0[15] — General purpose digital input/output pin.
OTXD1 — Transmitter output for UART1.
I/O SCK0 — Serial clock for SSP0.
I/O SCK — Serial clock for SPI.
P0[16]/RXD1/
SSEL0/SSEL 63 F8 [1] I/O P0[16] — General purpose digital input/output pin.
IRXD1 — Receiver input for UART1.
I/O SSEL0 — Slave Select for SSP0.
I/O SSEL — Slave Select for SPI.
P0[17]/CTS1/
MISO0/MISO 61 F9 [1] I/O P0[17] — General purpose digital input/output pin.
ICTS1 — Clear to Send input for UART1.
I/O MISO0 — Master In Slave Out for SSP0.
I/O MISO — Master In Slave Out for SPI.
P0[18]/DCD1/
MOSI0/MOSI 60 F6 [1] I/O P0[18] — General purpose digital input/output pin.
IDCD1 — Data Carrier Detect input for UART1.
I/O MOSI0 — Master Out Slave In for SSP0.
I/O MOSI — Master Out Slave In for SPI.
P0[19]/DSR1/
SDA1 59 G10 [1] I/O P0[19] — General purpose digital input/output pin.
IDSR1 — Data Set Ready input for UART1.
I/O SDA1 — I2C1 data input/output (this is not an I2C-bus compliant
open-drain pin).
P0[20]/DTR1/SCL1 58 G9 [1] I/O P0[20] — General purpose digital input/output pin.
ODTR1 — Data Termi nal Ready output for UART1. Can also be configured
to be an RS-485/EIA-485 output enable signal.
I/O SCL1 — I2C1 clock input/output (this is not an I2C-bus compliant
open-drain pin).
P0[21]/RI1/RD1 57 G8 [1] I/O P0[21] — General purpose digital input/output pin.
IRI1 — Ring Indicator input for UART1.
IRD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only).
P0[22]/RTS1/TD1 56 H10 [1] I/O P0[22] — General purpose digital input/output pin.
ORTS1 — Request to Send output for UART1. Can also be configured to be
an RS-485/EIA-485 output enable signal.
OTD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only).
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 12 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P0[23]/AD0[0]/
I2SRX_CLK/
CAP3[0]
9E5
[2] I/O P0[23] — General purpose digital input/output pin.
IAD0[0] — A/D converter 0, input 0.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
ICAP3[0] — Capture input for Timer 3, channel 0.
P0[24]/AD0[1]/
I2SRX_WS/
CAP3[1]
8D1
[2] I/O P0[24] — General purpose digital input/output pin.
IAD0[1] — A/D converter 0, input 1.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification. (LPC1769/68/67/66/65/63 on ly).
ICAP3[1] — Capture input for Timer 3, channel 1.
P0[25]/AD0[2]/
I2SRX_SDA/
TXD3
7D2
[2] I/O P0[25] — General purpose digital input/output pin.
IAD0[2] — A/D converter 0, input 2.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
OTXD3 — Transmitter output for UART3.
P0[26]/AD0[3]/
AOUT/RXD3 6D3
[3] I/O P0[26] — General purpose digital input/output pin.
IAD0[3] — A/D converter 0, input 3.
OAOUT — DAC output (LPC1769/68/67/6 6/65/63 only).
IRXD3 — Receiver input for UART3.
P0[27]/SDA0/
USB_SDA 25 J2 [4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain.
I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus
compliance).
I/O USB_SDA — USB port I2C serial data (OTG transceiver,
LPC1769/68/66/65 only).
P0[28]/SCL0/
USB_SCL 24 J1 [4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain.
I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus
compliance).
I/O USB_SCL — USB port I2C serial clock (OTG transceiver,
LPC1769/68/66/65 only).
P0[29]/USB_D+ 29 J3 [5] I/O P0[29] — General purpose digital input/output pin.
I/O USB_D+ — USB bidirectio nal D+ line. (LPC1769/68/66/65/64 only).
P0[30]/USB_D30 G4 [5] I/O P0[30] — General purpose digital input/output pin.
I/O USB_DUSB bidirectional D line. (LPC1769/6 8 /66/65/64 only).
P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual dire ction controls for each
bit. The operation of port 1 pins depends upon the pin function selected via
the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not
available.
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 13 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P1[0]/
ENET_TXD0 95 D5 [1] I/O P1[0] — Ge neral purpose digital input/output pin.
OENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only).
P1[1]/
ENET_TXD1 94 B4 [1] I/O P1[1] — General purpose digital input/output pin.
OENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only).
P1[4]/
ENET_TX_EN 93 A4 [1] I/O P1[4] — General purpose digital input/output pin.
OENET_TX_EN — Ethernet transmit data enable. (LPC1769/68/67/66/64
only).
P1[8]/
ENET_CRS 92 C5 [1] I/O P1[8] — General purpose digital input/output pin.
IENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only).
P1[9]/
ENET_RXD0 91 B5 [1] I/O P1[9] — General purpose digital input/output pin.
IENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64 only).
P1[10]/
ENET_RXD1 90 A5 [1] I/O P1[10] — General purpose digital input/output pin.
IENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64 only).
P1[14]/
ENET_RX_ER 89 D6 [1] I/O P1 [14] — General purpose digital input/output pin.
IENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64 only).
P1[15]/
ENET_REF_CLK 88 C6 [1] I/O P1 [15] — General purpose digital input/output pin.
IENET_REF_CLK — Ethernet reference clock. (LPC1769/68/67/66/64
only).
P1[16]/
ENET_MDC 87 A6 [1] I/O P1[16] — General purpose digital input/output pin.
OENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only).
P1[17]/
ENET_MDIO 86 B6 [1] I/O P1[17] — General purpose digital input/output pin.
I/O ENET_MDIO — Ethernet MIIM data input and output.
(LPC1769/68/67/66/64 only).
P1[18]/
USB_UP_LED/
PWM1[1]/
CAP1[0]
32 H4 [1] I/O P1[18] — General purpose digital input/output pin.
OUSB_UP_LED — USB GoodLink LED indicator . It is LOW when the device
is configured (non-control endpoints enabled), or when the host is enabled
and has detected a device on the bus. It is HIGH when the device is not
configured, or when host is enabled and has not detected a device on the
bus, or during global suspend. It transitions between LOW and HIGH
(flashes) when the host is enabl ed and detects activity on the bus.
(LPC1769/68/66/65/64 only).
OPWM1[1] — Pulse Width Modulator 1, channel 1 output.
ICAP1[0] — Capture input for Timer 1, channel 0.
P1[19]/MCOA0/
USB_PPWR/
CAP1[1]
33 J4 [1] I/O P1[19] — General purpose digital input/output pin.
OMCOA0 — Motor control PWM channel 0, output A.
OUSB_PPWRPort Power enable signal for USB port.
(LPC1769/68/66/65 only).
ICAP1[1] — Capture input for Timer 1, channel 1.
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 14 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P1[20]/MCI0/
PWM1[2]/SCK0 34 K4 [1] I/O P1[20] — General purpose digital input/output pin.
IMCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder
Interface PHA input.
OPWM1[2] — Pulse Width Modulator 1, channel 2 output.
I/O SCK0 — Serial clock for SSP0.
P1[21]/MCABORT/
PWM1[3]/
SSEL0
35 F5 [1] I/O P1[21] — General purpose digital input/output pin.
OMCABORTMotor control PWM, LOW-active fast abort.
OPWM1[3] — Pulse Width Modulator 1, channel 3 output.
I/O SSEL0 — Slave Select for SSP0.
P1[22]/MCOB0/
USB_PWRD/
MAT1[0]
36 J5 [1] I/O P1[22] — General purpose digital input/output pin.
OMCOB0 — Motor control PWM channel 0, output B.
IUSB_PWRD — Power Status for USB port (host power switch,
LPC1769/68/66/65 only).
OMAT1[0] — Match output for Timer 1, channel 0.
P1[23]/MCI1/
PWM1[4]/MISO0 37 K5 [1] I/O P1[23] — General purpose digital input/output pin.
IMCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder
Interface PHB input.
OPWM1[4] — Pulse Width Modulator 1, channel 4 output.
I/O MISO0 — Master In Slave Out for SSP0.
P1[24]/MCI2/
PWM1[5]/MOSI0 38 H5 [1] I/O P1[24] — General purpose digital input/output pin.
IMCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder
Interface INDEX input.
OPWM1[5] — Pulse Width Modulator 1, channel 5 output.
I/O MOSI0 — Master Out Slave in for SSP0.
P1[25]/MCOA1/
MAT1[1] 39 G5 [1] I/O P1 [25] — General purpose digital input/output pin.
OMCOA1 — Motor control PWM channel 1, output A.
OMAT1[1] — Match output for Timer 1, channel 1.
P1[26]/MCOB1/
PWM1[6]/CAP0[0] 40 K6 [1] I/O P1[26] — General purpose digital input/output pin.
OMCOB1 — Motor control PWM channel 1, output B.
OPWM1[6] — Pulse Width Modulator 1, channel 6 output.
ICAP0[0] — Capture input for Timer 0, channel 0.
P1[27]/CLKOUT
/USB_OVRCR/
CAP0[1]
43 K7 [1] I/O P1[27] — General purpose digital input/output pin.
OCLKOUT — Clock output pin.
IUSB_OVRCRUSB port Over-Current status. (LPC1769/68/66/65 only).
ICAP0[1] — Capture input for Timer 0, channel 1.
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 15 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P1[28]/MCOA2/
PCAP1[0]/
MAT0[0]
44 J7 [1] I/O P1[28] — General purpose digital input/output pin.
OMCOA2 — Motor control PWM channel 2, output A.
IPCAP1[0] — Capture input for PWM1, channel 0.
OMAT0[0] — Match output for Timer 0, channel 0.
P1[29]/MCOB2/
PCAP1[1]/
MAT0[1]
45 G6 [1] I/O P1[29] — General purpose digital input/output pin.
OMCOB2 — Motor control PWM channel 2, output B.
IPCAP1[1] — Capture input for PWM1, channel 1.
OMAT0[1] — Match output for Timer 0, channel 1.
P1[30]/VBUS/
AD0[4] 21 H1 [2] I/O P1[30] — General purpose digital input/output pin.
IVBUSMonitors the presence of USB bus power. (LPC1769/68/66/65/64
only).
Note: This signal must be HIGH for USB reset to occur.
IAD0[4] — A/D converter 0, input 4.
P1[31]/SCK1/
AD0[5] 20 F4 [2] I/O P1[31] — General purpose digital input/output pin.
I/O SCK1 — Serial Clock for SSP1.
IAD0[5] — A/D converter 0, input 5.
P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual dire ction controls for each
bit. The operation of port 2 pins depends upon the pin function selected via
the pin connect block. Pins 14 through 31 of thi s port are not available.
P2[0]/PWM1[1]/
TXD1 75 B9 [1] I/O P2[0] — General purpose digital input/output pin.
OPWM1[1] — Pulse Width Modulator 1, channel 1 output.
OTXD1 — Transmitter output for UART1.
P2[1]/PWM1[2]/
RXD1 74 B10 [1] I/O P2[1] — General purpose digital input/output pin.
OPWM1[2] — Pulse Width Modulator 1, channel 2 output.
IRXD1 — Receiver input for UART1.
P2[2]/PWM1[3]/
CTS1/
TRACEDATA[3]
73 D8 [1] I/O P2[2] — General purpose digital input/output pin.
OPWM1[3] — Pulse Width Modulator 1, channel 3 output.
ICTS1 — Clear to Send input for UART1.
OTRACEDATA[3] — Trace data, bit 3.
P2[3]/PWM1[4]/
DCD1/
TRACEDATA[2]
70 E7 [1] I/O P2[3] — General purpose digital input/o utput pin.
OPWM1[4] — Pulse Width Modulator 1, channel 4 output.
IDCD1 — Data Carrier Detect input for UART1.
OTRACEDATA[2] — Trace data, bit 2.
P2[4]/PWM1[5]/
DSR1/
TRACEDATA[1]
69 D9 [1] I/O P2[4] — General purpose digital input/output pin.
OPWM1[5] — Pulse Width Modulator 1, channel 5 output.
IDSR1 — Data Set Ready input for UART1.
OTRACEDATA[1] — Trace data, bit 1.
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 16 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P2[5]/PWM1[6]/
DTR1/
TRACEDATA[0]
68 D10 [1] I/O P2[5] — General purpose digital input/output pin.
OPWM1[6] — Pulse Width Modulator 1, channel 6 output.
ODTR1 — Data Termi nal Ready output for UART1. Can also be configured
to be an RS-485/EIA-485 output enable signal.
OTRACEDATA[0] — Trace data, bit 0.
P2[6]/PCAP1[0]/
RI1/TRACECLK 67 E8 [1] I/O P2[6] — General purpose digital input/o utput pin.
IPCAP1[0] — Capture input for PWM1, channel 0.
IRI1 — Ring Indicator input for UART1.
OTRACECLK — Trace Clock.
P2[7]/RD2/
RTS1 66 E9 [1] I/O P2[7] — General purpose digital input/output pin.
IRD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only).
ORTS1 — Request to Send output for UART1. Can also be configured to be
an RS-485/EIA-485 output enable signal.
P2[8]/TD2/
TXD2 65 E10 [1] I/O P2[8] — General purpose digital input/output pin.
OTD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only).
OTXD2 — Transmitter output for UART2.
P2[9]/
USB_CONNECT/
RXD2
64 F7 [1] I/O P2[9] — General purpose digital input/output pin.
OUSB_CONNECT — Signal used to switch an external 1.5 k resistor
under software control. Used with the SoftConnect USB feature.
(LPC1769/68/66/65/64 only).
IRXD2 — Receiver input for UART2.
P2[10]/EINT0/NMI 53 J10 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin
during reset starts the ISP command handler.
IEINT0External interrupt 0 input.
INMI — Non-maskable interrupt input.
P2[11]/EINT1/
I2STX_CLK 52 H8 [6] I/O P2[1 1] General purpose digital input/output pin.
IEINT1External interrupt 1 input.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
P2[12]/EINT2/
I2STX_WS 51 K10 [6] I/O P2[12] — General purpose digital input/output pin.
IEINT2External interrupt 2 input.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification. (LPC1769/68/67/66/65/63 on ly).
P2[13]/EINT3/
I2STX_SDA 50 J9 [6] I/O P2[13] — General purpose digital input/output pin.
IEINT3External interrupt 3 input.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
(LPC1769/68/67/66/65/6 3 only).
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 17 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual dire ction controls for each
bit. The operation of port 3 pins depends upon the pin function selected via
the pin connect block. Pins 0 through 24, and 27 through 31 of this port are
not avail ab l e.
P3[25]/MAT0[0]/
PWM1[2] 27 H3 [1] I/O P3[25] — General purpose digital input/output pin.
OMAT0[0] — Match output for Timer 0, channel 0.
OPWM1[2] — Pulse Width Modulator 1, output 2.
P3[26]/STCLK/
MAT0[1]/PWM1[3] 26 K1 [1] I/O P3[26] — General purpose digital input/output pin.
ISTCLK — System tick timer clock input. The maximum STCLK frequency
is 1/4 of the ARM processor clock frequency CCLK.
OMAT0[1] — Match output for Timer 0, channel 1.
OPWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual dire ction controls for each
bit. The operation of port 4 pins depends upon the pin function selected via
the pin connect block. Pins 0 throug h 27, 30, and 31 of this port are no t
available.
P4[28]/RX_MCLK/
MAT2[0]/TXD3 82 C7 [1] I/O P4 [28] — General purpose digital input/output pin.
IRX_MCLK — I2S receive master clock. (LPC1769/68/67/66/65 only).
OMAT2[0] — Match output for Timer 2, channel 0.
OTXD3 — Transmitter output for UART3.
P4[29]/TX_MCLK/
MAT2[1]/RXD3 85 E6 [1] I/O P4[29] — General purpose digital input/output pin.
ITX_MCLK — I2S transmit master clock. (LPC1769/68/67/66/65 only).
OMAT2[1] — Match output for Timer 2, channel 1.
IRXD3 — Receiver input for UART3.
TDO/SWO 1 A1 [1][7] OTDO — Test Data out for JTAG interface.
OSWO — Serial wire trace output.
TDI 2 C3 [1][8] ITDI — Test Data in for JTAG interface.
TMS/SWDIO 3 B1 [1][8] ITMS — Test Mode Select for JTAG interface.
I/O SWDIO — Serial wire debug data input/output.
TRST 4C2
[1][8] ITRSTTest Reset for JTAG interface.
TCK/SWDCLK 5 C1 [1][7] ITCK — Test Clock for JTAG interface.
ISWDCLK — Serial wire clock.
RTCK 100 B2 [1][7] ORTCK — JTAG interface control signal.
RSTOUT 14 - - O RSTOUTThis is a 3.3 V pin. LOW on this pin indicates the
microcontroller being in Reset state.
RESET 17 F3 [9] IExternal reset input: A LOW-going pulse as short as 50 ns on this pin
resets the device, causing I/O ports and peripherals to t ake on their default
states, and processor execution to begin at address 0. TTL with hysteresis,
5 V tolerant.
XTAL1 22 H2 [10][11] I Input to the oscill ator circuit and internal clock generator circuits.
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9.3 — 8 January 2014 18 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. Wh en configured as the DAC output,
digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide
output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only). This pad is not 5 V tolerant.
[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage
level of 2.3 V to 2.6 V.
[7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled.
XTAL2 23 G3 [10][11] O Output from the oscillator amplifier.
RTCX1 16 F2 [10][11] I Input to the RTC oscillator circuit.
RTCX2 18 G1 [10] O Output fro m the RTC oscillator circuit.
VSS 31,
41,
55,
72,
83,
97
B3,
B7,
C9,
G7,
J6,
K3
[10] Iground: 0 V reference.
VSSA 11 E1 [10] Ianalog gro und: 0 V reference. This should nominally be the same voltage
as VSS, but should be isolated to minimize noise and error.
VDD(3V3) 28,
54,
71,
96
K2,
H9,
C10
, A3
[10] I3.3 V supply voltage: This is the power supply voltage for the I/O ports.
VDD(REG)(3V3) 42,
84 H6,
A7 [10] I3.3 V voltage regulator supply voltage: This is the supply volt age for the
on-chip voltage regulator only.
VDDA 10 E2 [10] Ianalog 3.3 V pad supply voltage: This should be nominally the same
voltage as VDD(3V3) but should be isolated to minimize noise and error . This
voltage is used to power the ADC and DAC. This pin should be tied to 3.3
V if the ADC and DAC are not used.
VREFP 12 E3 [10] IADC posit iv e re ference voltage: This should be nominally the same
voltage as VDDA but should be isolated to minimize noise and error. Level
on this pin is used as a reference for ADC and DAC. This pin should be tied
to 3.3 V if the ADC and DAC are not used.
VREFN 15 F1 I ADC negative reference voltage: This should be nominally the same
voltage as VSS but should be isolated to minimize noise and error . Level on
this pin is used as a reference for ADC and DAC.
VBAT 19 G2 [10][12] IRTC pin power supply: 3.3 V on this pin supplies the power to the RTC
peripheral.
n.c. 13 D4,
E4 - not connected.
Table 5. Pin description …continued
Symbol Pin/ball Type Description
LQFP100
TFBGA100
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32-bit ARM Cortex-M3 microcontroller
[8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor.
[9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hystere sis.
[10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC.
[11] When the system oscillator is not used, connect XTAL1 and XT AL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
[12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating.
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32-bit ARM Cortex-M3 microcontroller
8. Functional description
8.1 Architectural overview
Remark: In the following, the notation LPC17xx refers to all parts:
LPC1769/68/67/66/65/64/63.
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the
system bus and are used similarly to TCM interfaces: one bus dedicated for instruction
fetch (I-code) and one bu s for data access (D-code ). The use of two core buses allo ws for
simultaneous operations if concurrent operations target different devices.
The LPC17xx use a multi-layer AHB matrix to connect the ARM Co rtex-M3 buses and
other bus mast er s to pe riphe r als in a fle xible ma nn e r that op tim i ze s perfo rm a nc e by
allowing peripherals that are on different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
8.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardwa re divid e,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all p arts o f the processing and m emory systems
can operate continuously. Typically, while one instruction is being executed, its successo r
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found on official ARM website.
8.3 On-chip flash program memory
The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash
accelerator maximizes performance for use with the two fast AHB-Lite buses.
8.4 On-chip SRAM
The LPC17xx cont ain a to t al of 64 kB on-chi p static RAM memory. This includes the main
32 kB SRAM, accessible by the CPU and DMA contro ller on a hig her-speed bus, and two
additional 16 kB each SRAM blocks situated on a separate slave port on the AHB
multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three sep arate RAMs
that can be accessed simultaneously.
8.5 Memory Protection Unit (MPU)
The LPC17xx have a Memory Protection Unit (MPU) which can be used to improv e the
reliability of an embedded system by protecting critical data within the user application.
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The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memo ry regio ns, allowing memor y reg ions to b e defined as re ad -onl y
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU support s up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permit te d by th e re gio n settin g , will ca use the Memory Ma na ge m ent Fa u l t
exception to take place.
8.6 Memory map
The LPC17xx incorporates several distinct memory regions, shown in the following
figures. Figure 4 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 perip herals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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32-bit ARM Cortex-M3 microcontroller
(1) Not available on all parts. See Table 2.
Fig 4. LPC17xx memory map
0x5000 0000
0x5000 4000
0x5000 8000
0x5000 C000
0x5020 0000
0x5001 0000
AHB peripherals
Ethernet controller
(1)
USB controller
(1)
reserved
127- 4 reserved
GPDMA controller
0
1
2
3
APB0 peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4002 C000
0x4003 4000
0x4003 0000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 C000
0x4006 0000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WDT
timer 0
timer 1
UART0
UART1
reserved
reserved
SPI
RTC + backup registers
GPIO interrupts
pin connect
SSP1
ADC
CAN AF RAM
(1)
CAN AF registers
(1)
CAN common
(1)
CAN1
(1)
CAN2
(1)
22 - 19 reserved
I2C1
31 - 24 reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
23
reserved
reserved
32 kB local SRAM (LPC1769/8/7/6/5/3)
16 kB local SRAM (LPC1764)
reserved
reserved
private peripheral bus
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x0004 0000
0x0002 0000
0x0008 0000
0x1000 4000
0x1000 0000
0x1000 8000
0x1FFF 0000
0x1FFF 2000
0x2008 0000
0x2007 C000
0x2008 4000
0x2200 0000
0x200A 0000
0x2009 C000
0x2400 0000
0x4000 0000
0x4008 0000
0x4010 0000
0x4200 0000
0x4400 0000
0x5000 0000
0x5020 0000
0xE000 0000
0xE010 0000
0xFFFF FFFF
reserved
reserved
GPIO
reserved
reserved
reserved
reserved
APB0 peripherals
AHB peripherals
APB1 peripherals
AHB SRAM bit-band alias addressing
peripheral bit-band alias addressing
16 kB AHB SRAM1 (LPC1769/8/7/6/5)
16 kB AHB SRAM0
256 kB on-chip flash (LPC1766/65/63)
128 kB on-chip flash (LPC1764)
512 kB on-chip flash (LPC1769/8/7)
PWM1
8 kB boot ROM
0x0000 0000
0x0000 0400 active interrupt vectors+ 256 words
I-code/D-code
memory space
002aad946
APB1 peripherals
0x4008 0000
0x4008 8000
0x4008 C000
0x4009 0000
0x4009 4000
0x4009 8000
0x4009 C000
0x400A 0000
0x400A 4000
0x400A 8000
0x400A C000
0x400B 0000
0x400B 4000
0x400B 8000
0x400B C000
0x400C 0000
0x400F C000
0x4010 0000
SSP0
DAC
(1)
timer 2
timer 3
UART2
UART3
reserved
I2S
(1)
I2C2
1 - 0 reserved
2
3
4
5
6
7
8
9
10
reserved
repetitive interrupt timer
11
12
reserved
motor control PWM
30 - 16 reserved
13
14
15
system control31
QEI
LPC1769/68/67/66/65/64/63
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8.7 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral p art of the Cortex-M3. The tight co upling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
8.7.1 Features
Controls system exceptions and peripheral interrupts
In the LPC17xx, the NVIC supports 33 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt (NMI)
Software interrupt generation
8.7.2 Interrupt sources
Each peripheral devi ce has one interrupt line con nected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both.
8.8 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be conn ected to the appro priate pins prior to being activated and pr ior
to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be con figured as open- drain output s or to have a pull- up, pull-do wn, or
no resistor enabled.
8.9 General purpose DMA controller
The GPDMA is an AMBA AHB compliant periphe ral allowing selected peripherals to have
DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral, and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the USB and Ethernet controllers and the various on-chip SRAM areas. The supported
APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC.
Two match signals for each timer can be used to trigger DMA transfers.
Remark: The Ethernet controller is available on par ts LPC1769/68/67/66/64. The USB
controller is available on p arts LPC1769/68/66/65/64. The I2S-bus interface is available on
parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63.
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8.9.1 Features
Eight DMA channels. Each channel can support an unidirectional transfer.
16 DMA request lines.
Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
Memory-to-memory, memory-to- peripheral, periphe ral-to-memory, and
periphera l-to -p e riphe ra l tra ns fe rs ar e su pp or te d.
Scatter or gather DMA is supported through the use of linked lists. This means tha t
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority.
AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
Internal four-word FIFO per channel.
Supports 8, 16, and 32-bit wid e tra n sactions.
Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
An interrupt to the pr ocessor ca n be gene rate d on a DMA comp letion or when a DMA
error has occurred.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
8.10 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any nu mber of outp uts simultan eously. The value of the
output register may be read back as well as the current state of the port pins.
LPC17xx use accelerated GPIO functions:
GPIO registers ar e accessed throug h the AHB mu ltila ye r bu s so th at th e faste s t
possible I/O timing can be achieved.
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All GPIO registers are byte and half-word addressable.
Entire port value can be written in one instruction.
Support for Cortex-M3 bit banding.
Support for use with the GPDMA controller.
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Additionally, any pin on Po rt 0 and Port 2 (total of 42 pins) providing a digital function can
be programmed to generate an interrupt on a rising edge, a falling edge, or both. The
edge detection is asynchronous, so it may operate when clocks are not present such as
during Power-down mode. Each enabled interrupt can be used to wake up the chip from
Power-down mode.
8.10.1 Features
Bit level set and clear registers allow a single instr uction to set or clear any nu mber of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
8.11 Ethernet
Remark: The Ethernet controller is a vailable on parts LPC1769/68/67/66/64. The
Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120
MHz (LPC1769). See Table 2.
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering an d wa ke-u p on LAN activity. Automatic frame transmission and r eception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus
through the AHB-multilayer matrix to access the various on-chip SRAM blocks for
Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII
(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial
bus.
8.11.1 Features
Ethernet standards support:
Supports 10 M bit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
Fully compliant with IEEE standard 802.3.
Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
Flexible transmit and receive frame options.
Virtual Local Area Network (VLAN) frame support.
Memory management:
Independent transmit and receive buffers memory mapped to shared SRAM.
DMA managers with scatter/gather DMA and arrays of frame descriptors.
Memory traffic optimized by buffering and pre-fetching.
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Enhanced Ethernet features:
Receive filtering.
Multicast and broadcast frame support for both transmit and receive.
Optional automatic Frame Check Sequence (FCS) insertion with Cyclic
Redundancy Check (CRC) for transmit.
Selectable automatic transmit frame padding.
Over-length frame support for both transmit and re ceive allows any length frames.
Promiscuous receive mode.
Automatic collision back-off and frame retransmission.
Includes power management by clock switching.
Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
Physical interface:
Attachment of external PHY chip through standard RMII interface.
PHY register access is available via the MIIM interface.
8.12 USB interface
Remark: The USB controller is available as device/Host/OTG controller on parts
LPC1769/68/66/65 and as device-only controller on part LPC1764.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The USB interface includes a device, Host, and OTG controller with on-chip PHY for
device and Host functions. The OTG switching protocol is supp orted through the use of an
external cont ro ller. Details on typical USB interfacing solutions can be found in
Section 15.1.
8.12.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interf ace engine decodes the USB dat a stream and writes da t a
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the on-chip
SRAM.
8.12.1.1 Features
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
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Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mod e, the part can ente r on e of the re du ced powe r
modes and wake up on USB activity.
Supports DMA transfers wi th all on -c hip SRAM blo cks on all non-contro l endpoints.
Allows dynamic switching between CPU-controlled slave and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
8.12.2 USB host controller
The host controller ena bles full- and low-speed dat a exchange with USB devices attached
to the bus. It consists of a register interface, a serial interface engine, and a DMA
controller. The register interface complies with the OHCI specification.
8.12.2.1 Features
OHCI compliant.
One downstream port.
Supports port power switch in g .
8.12.3 USB OTG controller
USB OTG is a supplement to the USB 2.0 specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionali ty for connecti on to
USB peripherals.
The OTG Controller integrates the host controller, device controller, and a master-only
I2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus
interface controls an external OTG transceiver.
8.12.3.1 Features
Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
8.13 CAN controller and acceptance filters
Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2.
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.
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32-bit ARM Cortex-M3 microcontroller
8.13.1 Features
Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with CAN specification 2.0B, ISO 11898-1.
Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit)
receive identifiers for all CAN buses.
Acceptance Filter can provide FullC AN- style automatic reception for selected
Standard Identifiers.
FullCAN messages can generate interrupts.
8.14 12-bit ADC
The LPC17xx contain a single 12-bit successive approximation ADC with eight channels
and DMA support.
8.14.1 Features
12-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range VREFN to VREFP.
12-bit conver sio n rate : 200 kHz.
Individual channels can be selected for conversion.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or Timer Match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
DMA support.
8.15 10-bit DAC
The DAC allows to generate a variable analog output. The maximum ou tput value of the
DAC is VREFP.
Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2.
8.15.1 Features
10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
Dedicated conversion timer
DMA support
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8.16 UARTs
The LPC17xx each contain four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
8.16.1 Features
Maximum UART data bit rate of 6.25 Mbit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
Support for RS-4 85 /9 -b it/EIA-485 mode (UART1).
UART3 includes an IrDA mode to support infrared communication.
All UARTs have DMA support.
8.17 SPI serial I/O controller
The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to
handle multiple maste rs and slaves co nnected to a given bus. Only a single maste r and a
single slave can communicate on the inte rface during a given data transfer. During a data
transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave
always sends 8 bits to 16 bits of data to the master.
8.17.1 Features
Maximum SPI data bit rate of 12.5 Mbit/s
Compliant with SPI specification
Synchronous, serial, full duplex communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
8.18 SSP serial I/O controller
The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can intera ct with multiple masters and slaves on the
bus. Only a single maste r an d a sin gle slav e can communicate on the bus during a given
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data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of
data flowing from the master to the slave and from the slave to the master. In practice,
often only one of these data flows carries meaningful data.
8.18.1 Features
Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supp or te d by GPDM A
8.19 I2C-bus serial I/O controllers
The LPC17xx each contain three I2C-bus controllers.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus an d ca n be
controlled by more than one bus master connected to it.
8.19.1 Features
I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
I2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mech anism to suspend and
resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
All I2C-bus controllers support multiple address recognition and a bus monitor mode.
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8.20 I2S-bus serial I/O controllers
Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See
Table 2.
The I2S-bus provides a standard commu nication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S-bus connection has one master, which is
always the master, and one slave. The I 2S-bus interface provide s a separate transmit and
receive channel, each of which can operate as either a master or a slave.
8.20.1 Features
The interface has sep arate input/output channels each of which can o perate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
Support for an aud io ma st er clock.
Configurable word select period in master mode (separately for I2S-bus input and
output).
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop and mute options separa tely for I2S-bus input and I2S-bus
output.
8.21 General purpose 32-bit timers/external event counters
The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count
cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts, generate timed DMA requests, or perform other actions at specified
timer values, based on four match registers. Each timer/counter also includes two capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
8.21.1 Features
A 32-bit timer/counter with a programmable 32-bit prescaler.
Counter or timer op er a tion .
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit matc h re gist er s tha t allo w:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
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Up to four external outputs corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
Up to two match registers can be used to generate timed DMA requests.
8.22 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC17xx. The Timer is designed to count
cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when spe cified timer values occur , based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM ou tp u ts require only on e m atc h register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM output s will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both ed ge s co ntr o lled .
Again, the PWMMR0 match register controls the PWM cycle rate. The other match
registers control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repe tition rate is the same for all
PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
8.22.1 Features
One PWM block with Coun ter or Timer operation (may use the peripheral clock or one
of the capture inputs as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
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Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent ge ne ra tio n of
erroneous pulses. Sof tware must ‘release’ new ma tch values before they ca n become
effective.
May be used as a stand ard 32-bit timer /counte r with a progra mmable 32-bit p rescaler
if the PWM mode is not enabled.
8.23 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs ar e provided to automatically sense rotor position and use
that information to ramp sp eed up or down. An abort input is also provided that causes the
PWM to immediately release all motor drive outputs. At the same time, the motor control
PWM is highly configurable for other generalized timing, counting, capture, and compare
applications.
8.24 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental e ncoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two sign als, th e use r can track the p osition, d ire ction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
8.24.1 Features
Tracks encoder position.
Increments/decrements depending on direction.
Programmable for 2 or 4 position counting.
Velocity capture using built-in timer.
Velocity compare function with “less than” interrupt.
Uses 32-bit regis ter s for po sitio n an d ve loc ity.
Three position co mpare registers with interrup ts.
Index counter for revolution counting.
Index compare registe r w ith int er ru p ts.
Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
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Digital filter with programmable delays for encoder input signals.
Can accept decoded signal inputs (clk and direction).
Connected to APB.
8.25 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
8.25.1 Features
32-bit counter running from PCLK. Counter can be free-running or be reset by a
generated interrupt.
32-bit compare value.
32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
8.26 ARM Cortex-M3 system tick timer
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be
clocked from the internal AHB clock or from a device pin.
8.27 Watchdog timer
The purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
8.27.1 Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 232 4) in
multiples of Tcy(WDCLK) 4.
The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC)
oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of
potential timing choices of Watchdog operation under different power reduction
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conditions. It also provides the ability to run the WDT from an entirely internal source
that is not dep endent on an external crystal a nd its associated compon ents and wirin g
for increased reliability.
Includes lock/safe feature.
8.28 RTC and backup registers
The RTC is a set of counte rs for measur ing time when system power is on, and optio nally
when it is off. The RTC on the LPC17xx is designed to have extremely low power
consumption, i.e. less than 1 A. The RTC will typically run from the main chip power
supply, conserving battery power while the rest of the device is powered up. When
operating from a battery, the RTC will continue working down to 2.1 V. Battery power can
be provided from a standard 3 V Lithium button cell.
An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion
of the RTC, moving most of the power consumption out of the time counting function.
The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way
that will provide less than 1 second per day error when operated at a const ant voltage and
temperature. A clock output function (see Section 8.29.4) makes measuring the oscillator
rate easy and accurate.
The RTC contains a small set of backup registers (20 bytes) for holding data while the
main part of the LPC17xx is powered off.
The RTC includes an alarm function that can wake up the LPC17xx from all reduced
power modes with a time resolution of 1 s.
8.28.1 Features
Measures the passage of time to maintain a calendar and clock.
Ultra low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
Periodic interrup t s can be gene rated from in crement s of any fie ld of th e time registe rs.
Backup registe rs (2 0 by te s) po we re d by VBAT.
RTC power supply is isolated from the rest of the chip.
8.29 Clocking and power control
8.29.1 Crystal oscillators
The LPC17xx include three independent oscillators. These are the main oscillator , the IRC
oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose
as required in a particular application. Any of the thr e e clock sources can be cho se n by
software to drive the main PLL and ultimately the CPU.
Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
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See Figure 5 for an overview of the LPC17xx clock ge ne r ation .
8.29.1.1 Internal RC oscillator
The IRC may be used as the clock so urce for th e WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
Upon power-up or an y chip reset, the L PC17xx use the IRC as the clock source. So ftware
may later switch to one of the other available clock sources.
8.29.1.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or withou t using the
PLL. The main oscillator also provides the clock source for the dedicated USB PLL.
The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a highe r fr equen cy, up to the maximum CPU operating fre que ncy, by the main
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to Section 8.29.2 for additional information.
8.29.1.3 RTC oscillator
The RTC oscillator can be used as the clock source for the RTC block, the main PLL,
and/or the CPU.
Fig 5. LPC17xx clocki ng generation block di ag ram
MAIN
OSCILLATOR
INTERNAL
RC
OSCILLATOR
RTC
OSCILLATOR
MAIN PLL
WATCHDOG
TIMER
REAL-TIME
CLOCK
CPU
CLOCK
DIVIDER
PERIPHERAL
CLOCK
GENERATOR
USB BLOCK
ARM
CORTEX-M3
ETHERNET
BLOCK
DMA
GPIO
NVIC
USB
CLOCK
DIVIDER
system
clock
select
(CLKSRCSEL)
USB clock config
(USBCLKCFG)
CPU clock config
(CCLKCFG)
pllclk
CCLK/8
CCLK/6
CCLK/4
CCLK/2
CCLK
pclkWDT
rtclk = 1Hz
usbclk
(48 MHz)
cclk
USB PLL
USB PLL enable
main PLL enable
32 kHz
APB peripherals
LPC17xx
002aad947
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8.29.2 Main PLL (PLL0)
The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and/or the USB block.
The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a
value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range
of output frequencies from the same input frequency.
Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
The PLL0 is turned off and bypasse d following a chip Reset and by enterin g Power -down
mode. PLL0 is enabled by software only. The program must configure and activate the
PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source.
8.29.3 USB PLL (PLL1)
The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB
interface.
The PLL1 receives its clock input from the main oscillator only and provides a fixed
48 MHz clock to the USB block only. The PLL1 is disabled and powere d off on re set. If the
PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main
PLL0.
The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The
input frequency is multiplied up the range of 48 MHz for the USB clock using a Current
Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle.
8.29.4 RTC clock output
The LPC17xx feature a clock output function intended for synchronizing with external
devices and for use during system development to allow checking the internal clocks
CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC
clock output allows tuning the RTC freq uency without probing the pin, which would distort
the results.
8.29.5 Wake-up timer
The LPC17xx begin operation at power-up and when awakened from Power-down mode
by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to
resume quickly. If the main oscillator or the PLL is needed by the application, software will
need to enable these features and wait for them to stabilize before they are used as a
clock source.
When the main oscillator is initially activate d, the wake-up timer allows so ft ware to ensur e
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
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whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the wake-up timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some eve nt caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
sufficie nt amplitude to drive the clock logic. The amount of time d epends on many factors,
including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its
electrical characteristics (if a q uartz cr yst al is used) , as well as any other external cir cuitry
(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
8.29.6 Power control
The LPC17xx support a va riety of power control features. There ar e four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, Peripheral Power Control allows shutting down the clocks to
individual on-chip peripherals, allowing fine tunin g of power consumption by eliminating all
dynamic power use in a ny peripherals that are not require d for the application. Each of the
peripherals has its own clock divider which provides even better power control.
Integrated PMU (Power Management Unit) automatically adjust internal regulators to
minimize power consumption during Sleep, Deep sleep, Power-down, and Deep
power-down modes.
The LPC17xx also implement a separate power domain to allow turning off power to the
bulk of the device while maintaining ope ratio n of the RTC and a small set of regist er s for
storing data during any of the power-down modes.
8.29.6.1 Sleep mode
When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
8.29.6.2 Deep-sleep mode
In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM value s ar e
preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.
The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later .
The RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
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The Deep-sleep mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power
consumptio n to a ve ry low value . Pow er to the flash memory is left on in Deep-sleep
mode, allowing a very quick wake-up.
On wake-up from Deep-sleep mode, the code execution and peripherals activities will
resume after 4 cycles expire if the IRC was used before enterin g Deep- sleep mode. If the
main external oscillator was used, the code execution will resume when 4096 cycles
expire. PLL and clock dividers need to be reconfigured accordingly.
8.29.6.3 Power-down mode
Power-down mode does everything that Deep-sleep mode does, but also turns off the
power to the IRC oscillator and the flash memory. This saves more power but requires
waiting for resumption of flash operation before execution of code or data access in the
flash memory can be accomplished.
On the wake-up of Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. In the meantime, the
flash wake-up timer then coun ts 4 MHz IRC clock cycle s to make the 100 s flash st art-up
time. When it times out, access to the flash will be allowed. Users need to reconfigure the
PLL and clock dividers accordingly.
8.29.6.4 Deep power-down mode
The Deep power-down mode can only be entered from the RTC block. In Deep
power-down mode, power is shut off to the entire chip with the exception of the RTC
module and the RESET pin.
The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm
match event of th e RTC.
8.29.6.5 Wake-up interrupt controller
The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from
any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep,
Power-down, and Deep power-down modes.
The WIC works in connection with the Nested Vectored Interrup t Controller (NVIC). Wh en
the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a
mask of the current interrupt situation to the WIC.This mask includes all of the interru pts
that are both enabled and of sufficient priority to be serviced immediately. With this
information, the WIC simply notices when one of the interrupts has occurred and then it
wakes up the CPU.
The WIC eliminates the need to periodically wake up the CPU and poll the interrupts
resulting in addit ion a l powe r sa vin gs.
8.29.7 Peripheral power control
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
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8.29.8 Power domains
The LPC17xx provide two independent powe r domains that allow the bulk o f the device to
have power removed while maintaining operation of the RTC and the backup Registers.
On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the
VDD(REG)(3V3) pin powers the on-chip voltage reg ulator which in turn pr ovides power to the
CPU and most of the peripherals.
Depending on the LPC17xx application, a design can use two power options to manage
power consum p tion .
The first option assumes that power consumption is not a conce rn and th e design ties the
VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplie s; a 3.3 V supply for the I/O pads (V DD(3V3)) and
a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator
powered independently from the I/O pad ring enables shutting do wn of the I/O pad power
supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore,
there is no power drain from the RTC battery when VDD(REG)(3V3) is available.
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8.30 System control
8.30.1 Reset
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating volt age attains
a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see
description in Section 8.29.5). The wake-up timer ensures that reset remains asserted
until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks
have passed, and the flash controller has completed its initialization. Once reset is
de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD
threshold, the RSTOUT pin goes HIGH.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At th at poin t, all of the pr ocessor
and peripheral registers have been initialized to predetermined values.
Fig 6. Power distribu tio n
REAL-TIME CLOCK
BACKUP REGISTERS
REGULATOR
32 kHz
OSCILLATOR
RTC POWER DOMAIN
MAIN POWER DOMAIN
002aad978
RTCX1
VBAT
V
DD(REG)(3V3)
RTCX2
V
DD(3V3)
V
SS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
ADC POWER DOMAIN
V
DDA
VREFP
VREFN
V
SSA
LPC17xx
ULTRA LOW-POWER
REGULATOR
POWER
SELECTOR
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8.30.2 Brownout detection
The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this
voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Re gister in the
NVIC in order to cause a CPU interrupt; if not, so ftware can monitor the signal by reading
a dedicated status register.
The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when
the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of
the flash as operation of the various elements of the chip would otherwise become
unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at
which point the power-on reset circuitry maintains the overall reset.
Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event
loop to sense the condition.
8.30.3 Code security (Code Read Protection - CRP)
This feature o f the LPC17xx allo ws user to enabl e differ ent levels of security in the system
so that access to the on-chip flash and use of the JTAG and ISP can be restricted . Whe n
needed, CRP is invoked by pr ogramming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables ac ce ss to chip via th e JTAG an d on ly allo ws full flash er ase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
8.30.4 APB interface
The APB peripherals are split into two separate APB buses in order to distribute the bus
bandwidth and thereby reducing stalls caused by contention between the CPU and the
GPDMA controller.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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8.30.5 AHB multilayer matrix
The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code)
and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main
(32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these
memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM
blocks. Additionally, the matrix connects the CPU system bus and all of the DMA
controllers to th e var io us perip h er al fu nc tion s.
8.30.6 External interrupt inputs
The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
8.30.7 Memory mapping control
The Cortex-M3 incorp orates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC17xx is configured for 128 total interrupts.
8.31 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.
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9. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 8.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] See Table 19 for maximum operating voltage.
[4] Including voltage on outputs in 3-state mode.
[5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD(3V3) supply voltage (3.3 V) external rail [2] 0.5 +4.6 V
VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V
VDDA analog 3.3 V pad supply
voltage [2] 0.5 +4.6 V
Vi(VBAT) input voltage on pin VBAT for the RTC [2] 0.5 +4.6 V
Vi(VREFP) input voltage on pin VREFP [2] 0.5 +4.6 V
VIA analog input voltage on ADC related pins [2][3] 0.5 +5.1 V
VIinput voltage 5 V tolerant digital I/O pins;
VDD 2.4 V [2][4] 0.5 +5.5 VI
VDD = 0 V 0.5 +3.6
5 V tolerant open-drain pins
PIO0_27 and PIO0_28 [2][5] 0.5 +5.5
IDD supply current per supply pin - 100 mA
ISS ground current per ground pin - 100 mA
Ilatch I/O latch-up current (0.5VDD(3V3)) < VI <
(1.5VDD(3V3)); Tj < 125 C-100mA
Tstg storage temperature [6] 65 +150 C
Ptot(pack) total power dissipation (per
package) based on package heat
transfer, not device power
consumption
-1.5W
VESD electrostatic discharge voltage human body model; all pins [7] 4000 +4000 V
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10. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
(1)
Tamb = ambient temperature (C)
Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is of ten small and ma ny times can be n egligible. However it can be significant
in some applications.
Table 7. Thermal resistance (15 %)
Symbol Parameter Conditions Max/Min Unit
LQFP100
Rth(j-a) thermal resistance from
junction to ambient JEDEC (4.5 in 4 in); still air 38.01 C/W
Single-layer (4.5 in 3 in); still air 55.09 C/W
Rth(j-c) thermal resistance from
junction to case 9.065 C/W
TFBGA100
Rth(j-a) thermal resistance from
junction to ambient JEDEC (4.5 in 4 in); still air 55.2 C/W
Single-layer (4.5 in 3 in); still air 45.6 C/W
Rth(j-c) thermal resistance from
junction to case 9.5 C/W
TjTamb PDRth j a
+=
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11. Static characteristics
Table 8. Static characteristics
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Supply pins
VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V
VDD(REG)(3V3) regulator supply voltage
(3.3 V) 2.4 3.3 3.6 V
VDDA analog 3.3 V pad supply
voltage [3][4] 2.5 3.3 3.6 V
Vi(VBAT) input voltage on pin
VBAT [5] 2.1 3.3 3.6 V
Vi(VREFP) input voltage on pin
VREFP [3] 2.5 3.3 VDDA V
IDD(REG)(3V3) regulator supply current
(3.3 V) active mode; code
while(1){}
executed from flash; all
peripherals disabled;
PCLK = CCLK8
CCLK = 12 MHz; PLL
disabled [6][7] -7-mA
CCLK = 100 MHz; PLL
enabled [6][7] -42-mA
CCLK = 100 MHz; PLL
enabled (LPC1769) [6][8] -50-mA
CCLK = 120 MHz; PLL
enabled (LPC1769) [6][8] -67-mA
sleep mode [6][9] -2-mA
deep sleep mode [6][10] -240-A
power-down mode [6][10] -31-A
deep power-down mode;
RTC running [11] - 630 - nA
IBAT battery supply current deep power-down mode;
RTC running
VDD(REG)(3V3) present [12] - 530 - nA
VDD(REG)(3V3) not
present [13] -1.1 - A
IDD(IO) I/O supply current deep sleep mode [14][15] -40-nA
power-down mode [14][15] -40-nA
deep power-down mode [14] -10-nA
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IDD(ADC) ADC supply current active mode;
ADC powered
[16][17] -1.95-mA
ADC in Power-down
mode [16][18] -<0.2-A
deep sleep mode [16] -38-nA
power-down mode [16] -38-nA
deep power-down mode [16] -24-nA
II(ADC) ADC input current on pin VREFP
deep sleep mode [19] -100-nA
power-down mode [19] -100-nA
deep power-down
mode [19] -100-nA
Standard port pins, RESET, RTCK
IIL LOW-level input current VI= 0 V; on-chip pull-up
resistor disabled - 0.5 10 nA
IIH HIGH-level input
current VI=V
DD(3V3); on-chip
pull-down resistor
disabled
- 0.5 10 nA
IOZ OFF-state output
current VO=0V; V
O=V
DD(3V3);
on-chip pull-up/down
resistors disabled
- 0.5 10 nA
VIinput voltage pin configured to provide
a digital function [20][21]
[22] 0- 5.0V
VOoutput voltage output active 0 - VDD(3V3) V
VIH HIGH-level input
voltage 0.7VDD(3V3) --V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output
voltage IOH =4 mA VDD(3V3)
0.4 --V
VOL LOW-level output
voltage IOL =4 mA --0.4V
IOH HIGH-level output
current VOH =V
DD(3V3) 0.4 V 4--mA
IOL LOW-level output
current VOL =0.4V 4--mA
IOHS HIGH-level short-circuit
output current VOH =0V [23] --45 mA
IOLS LOW-level short-circuit
output current VOL =V
DD(3V3) [23] --50mA
Ipd pull-down current VI=5V 10 50 150 A
Ipu pull-up current VI=0V 15 50 85 A
VDD(3V3) <V
I<5V 000A
Table 8. Static characteristics …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design.
[3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.
[4] VDDA for DAC specs are from 2.7 V to 3.6 V.
I2C-bus pins (P0[27] and P0[28])
VIH HIGH-level input
voltage 0.7VDD(3V3) --V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage - 0.05
VDD(3V3)
-V
VOL LOW-level output
voltage IOLS =3 mA --0.4V
ILI input leakage current VI=V
DD(3V3) [24] -24A
VI=5V - 10 22 A
Oscillator pins
Vi(XTAL1) input voltage on pin
XTAL1 0.5 1.8 1.95 V
Vo(XTAL2) output voltage on pin
XTAL2 0.5 1.8 1.95 V
Vi(RTCX1) input voltage on pin
RTCX1 0.5 - 3.6 V
Vo(RTCX2) output voltage on pin
RTCX2 0.5 - 3.6 V
USB pins (LPC1769/68/66/65/64 only)
IOZ OFF-state output
current 0V<V
I<3.3V [2] --10 A
VBUS bus supply voltage [2] --5.25V
VDI differential input
sensitivity voltage (D+) (D)[2] 0.2--V
VCM differential common
mode voltage range includes VDI range [2] 0.8 - 2.5 V
Vth(rs)se single-ended recei v er
switching threshold
voltage
[2] 0.8 - 2.0 V
VOL LOW-level output
voltage for
low-/full-speed
RL of 1.5 k to 3.6 V [2] --0.18V
VOH HIGH-level output
voltage (driven) for
low-/full-speed
RL of 15 k to GND [2] 2.8 - 3.5 V
Ctrans transceiver capacitance pin to GND [2] --20pF
ZDRV driver output
impedance for driver
which is not high-speed
capable
with 33 series resistor;
steady state drive [2][25] 36 - 44.1
Table 8. Static characteristics …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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[5] The RTC typically fails when Vi(VBAT) drops below 1.6 V.
[6] VDD(REG)(3V3) = 3.3 V; Tamb =25C for all power consumption measurements.
[7] Applies to LPC1768/67/66/65/64/63.
[8] Applies to LPC1769 only.
[9] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = CCLK8.
[10] BOD disabled.
[11] On pin VDD(REG)(3V3). IBAT = 530 nA. VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb =25C.
[12] On pin VBAT; IDD(REG)(3V3) = 630 nA; VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb =25C.
[13] On pin VBAT; VBAT = 3.0 V; Tamb =25C.
[14] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb =25C.
[15] TCK/SWDCLK pin needs to be externally pulled LOW.
[16] On pin VDDA; VDDA =3.3V; T
amb =25C. The ADC is powered if the PDN bit in the AD0CR register is set to 1 and in Power-down mode
of the PDN bit is set to 0.
[17] The ADC is powered if the PDN bit in the AD0CR register is set to 1. See LPC17xx user manual UM10360_1.
[18] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360_1.
[19] Vi(VREFP) = 3.3 V; Tamb =25C.
[20] Including voltage on outputs in 3-state mode.
[21] VDD(3V3) supply voltages must be present.
[22] 3-state outputs go into 3-state mode in Deep power-down mode.
[23] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[24] To VSS.
[25] Includes external resistors of 33 1 % on D+ and D.
11.1 Power consumption
Conditions: BOD disabled.
Fig 7. Deep-sleep mode: typical regulator supply current IDD(Reg)(3V3) versus
temperature
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Conditions: BOD disabled.
Fig 8. Pow e r-down mode: Typical regulator supply current IDD(Reg)(3V3) versus
temperature
Conditions: VDD(REG)(3V3) floating; RTC running.
Fig 9. Deep power-down mode: Typical battery supply current IBAT versus temperature
002aag119
1.0
1.4
1.8
0.6
temperature (°C)
-40 853510 60-15
IBAT)
(μA)
Vi(VBAT) = 3.6 V
3.3 V
3.0 V
2.4 V
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Conditions: VBAT = 3.0 V; VDD(REG)(3V3) = 3.0 V; RTC running.
Fig 10. De ep power-down mode: Typical regulator supply cu rrent IDD(REG)(3V3) and battery
supply current IBAT versus temperature
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11.2 Peripheral power consumption
The supply current p er peripheral is measured as the differ ence in supply current between
the peripheral block enabled and the peripheral block disabled in the PCONP register. All
other blocks are disabled and no code is executed. Measured on a typical sample at
Tamb =25C. The peripheral clock PCLK = CCLK/4.
[1] The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current
measured separately.
Table 9. Power consumption for individual analog and digital blocks
Peripheral Conditions Typical supply current in mA;
CCLK = Notes
12 MHz 48 MHz 100 MHz
Timer 0.03 0.11 0.23 Average cur rent per timer
UART 0.07 0.26 0.53 Average current per UART
PWM 0.05 0.20 0.41
Motor control
PWM 0.05 0.21 0.42
I2C 0.02 0.08 0.16 Average current per I2C
SPI 0.02 0.06 0.13
SSP1 0.04 0.16 0.32
ADC PCLK = 12 MHz for CCLK = 12 MHz
and 48 MHz; PCLK = 12.5 MHz for
CCLK = 100 MHz
2.12 2.09 2.07
CAN PCLK = CCLK/6 0.13 0.49 1.00 Average current per CAN
CAN0, CAN1,
acceptance filter PCLK = CCLK/6 0.22 0.85 1.73 Both CAN blocks and
acceptance filter[1]
DMA PCLK = CCLK 1.33 5.10 10.36
QEI 0.05 0.20 0.41
GPIO 0.33 1.27 2.58
I2S 0.09 0.34 0.70
USB and PLL1 0.94 1.32 1.94
Ethernet Ethernet block enabled in the PC ONP
register; Ethernet not connected. 0.49 1.87 3.79
Ethernet
connected Ethernet initialized, conn ected to
network, and running web server
example.
- - 5.19
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11.3 Electrical pin characteristics
Conditions: VDD(REG)(3V3) =V
DD(3V3) = 3.3 V; standard port pins.
Fig 11. Typical HIGH-level output vo ltage VOH versus HIGH-level output source current
IOH
Conditions: VDD(REG)(3V3) =V
DD(3V3) = 3.3 V; standard port pins.
Fig 12. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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Conditions: VDD(REG)(3V3) =V
DD(3V3) = 3.3 V; standard port pins.
Fig 13. Typical pull-up current Ipu versus input voltage VI
Conditions: VDD(REG)(3V3) =V
DD(3V3) = 3.3 V; standard port pins.
Fig 14. Typical pull-down current Ipd versus input voltage VI
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12. Dynamic characteristics
12.1 Flash memory
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
12.2 External clock
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
Table 10. Flash characteristics
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Nendu endurance [1] 10000 100000 - cycles
tret retention time powered 10 - - years
unpowered 20 - - years
ter erase time sector or multiple
consecutive sectors 95 100 105 ms
tprog programming time [2] 0.95 1 1.05 ms
Table 11. Dynamic characteristic: external clock
Tamb =
40
C to +85
C; VDD(3V3) over specified ranges.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc oscillator frequency 1 - 25 MHz
Tcy(clk) clock cycle time 40 - 1000 ns
tCHCX clock HIGH time Tcy(clk) 0.4 - - ns
tCLCX clock LOW time Tcy(clk) 0.4 - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns
Fig 15. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
tCHCL tCLCX tCHCX
Tcy(clk)
tCLCH
002aaa907
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12.3 Internal oscillators
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
12.4 I/O pins
[1] Applies to standard I/O pins.
Table 12. Dynamic characteristic: in ternal oscillators
Tamb =
40
C to +85
C; 2.7 V
VDD(REG)(3V3)
3.6 V.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz
fi(RTC) R TC input frequency - - 32.768 - kHz
Conditions: Frequency values are typical values. 4 MHz 1 % accuracy is guaranteed for
2.7 V VDD(REG)(3V3) 3.6 V and Tamb =40 Cto+85C. Variations between parts may cause
the IRC to fall outside the 4 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 16. Internal RC oscillator frequency versus temperature
002aaf107
temperature (°C)
-40 853510 60-15
4.024
4.032
4.020
4.028
4.036
fosc(RC)
(MHz)
4.016
VDD(REG)(3V3) = 3.6 V
3.3 V
3.0 V
2.7 V
2.4 V
Table 13. Dynamic characteristic: I/O pins[1]
Tamb =
40
C to +85
C; VDD(3V3) over specified ranges.
Symbol Parameter Conditions Min Typ Max Unit
trrise time pin configured as output 3.0 - 5.0 ns
tffall time pin configured as output 2.5 - 5.0 ns
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32-bit ARM Cortex-M3 microcontroller
12.5 I2C-bus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[7] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for S tandard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see the I2C-bus specification UM10204). This
maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a S tandard-mode I2C-bus system but the requirement tSU;DAT =
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Table 14. Dynamic characteristic: I2C-bus pins[1]
Tamb =
40
C to +85
C.[2]
Symbol Parameter Conditions Min Max Unit
fSCL SCL clock
frequency Standard-mode 0 100 kHz
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tffall time [3][4][5][6] of both SDA and
SCL signals
Standard-mode
- 300 ns
Fast-mode 20 + 0.1 Cb300 ns
Fast-mode Plus - 120 ns
tLOW LOW period of
the SCL clock Standard-mode 4.7 - s
Fast-mode 1.3 - s
Fast-mode Plus 0.5 - s
tHIGH HIGH period of
the SCL clock Standard-mode 4.0 - s
Fast-mode 0.6 - s
Fast-mode Plus 0.26 - s
tHD;DAT data hold time [3][7][8] Standard-mode 0 - s
Fast-mode 0 - s
Fast-mode Plus 0 - s
tSU;DAT dat a set-up
time
[9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns
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NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
12.6 I2S-bus interface
Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See
Table 2.
[1] CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK4; I2S cl ock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK
signal in the I2S-bus specification.
Fig 17. I2C-bus pins clock timing
002aaf425
tf
70 %
30 %
SDA
tf
70 %
30 %
S
70 %
30 %
70 %
30 %
tHD;DAT
SCL
1 / fSCL
70 %
30 %
70 %
30 %
tVD;DAT
tHIGH
tLOW
tSU;DAT
Table 15. Dynamic characteristics: I2S-bus interface pins
Tamb =
40
C to +85
C.
Symbol Parameter Conditions Min Typ Max Unit
common to input and output
trrise time [1] --35ns
tffall time [1] --35ns
tWH pulse width HIGH on pins I2STX_CLK and
I2SRX_CLK [1] 0.495 Tcy(clk) -- -
tWL pulse width LOW on pins I2STX_CLK and
I2SRX_CLK [1] - - 0.505 Tcy(clk) ns
output
tv(Q) data output valid time on pin I2STX_SDA [1] --30ns
on pin I2STX_WS [1] --30ns
input
tsu(D) data input set-up time on pin I2SRX_SDA [1] 3.5 - - ns
th(D) data input hold time on pin I2SRX_SDA [1] 4.0 - - ns
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32-bit ARM Cortex-M3 microcontroller
Fig 18. I2S-bus timing (output)
Fig 19. I2S-bus timing (input)
002aad992
I2STX_CLK
I2STX_SDA
I2STX_WS
T
cy(clk)
t
f
t
r
t
WH
t
WL
t
v(Q)
t
v(Q)
002aae159
Tcy(clk) tftr
tWH
tsu(D) th(D)
tsu(D) tsu(D)
tWL
I2SRX_CLK
I2SRX_SDA
I2SRX_WS
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32-bit ARM Cortex-M3 microcontroller
12.7 SSP interface
[1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz.
Table 16. Dynamic characteristic: SSP interface
Tamb =25
C; VDD(3V3) over specified ranges.
Symbol Parameter Conditions Min Typ Max Unit
SSP interface
tsu(SPI_MISO) SPI_MISO set-up time measured in SPI Master mode;
see Figure 20 [1] 30 - ns
Fig 20. MISO line set-up time in SSP Master mode
tsu(SPI_MISO)
SCK
shifting edges
MOSI
MISO
002aad326
sampling edges
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32-bit ARM Cortex-M3 microcontroller
12.8 USB interface
Remark: The USB controller is available as a device/Host/OTG controller on parts
LPC1769/68/66/65 and as device-only controller on part LPC1764.
[1] Characterized but not implemented as production test. Guaranteed by design.
Table 17. Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 k
on D+ to VDD(3V3); 3.0 V
VDD(3V3)
3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
trrise time 10 % to 90 % 8.5 - 13.8 ns
tffall time 10 % to 90 % 7.7 - 13.7 ns
tFRFM differential rise and fall time
matching tr/t
f--109%
VCRS output signal crossover voltage 1.3 - 2.0 V
tFEOPT source SE0 interval of EOP see Figure 21 160 - 175 ns
tFDEOP source jitter for differential transition
to SE0 transition see Figure 21 2-+5ns
tJR1 receiver jitter to next transition 18.5 - +18.5 ns
tJR2 receiver jitter for paired transitions 10 % to 90 % 9-+9ns
tEOPR1 EOP width at receiver must reject as
EOP; see
Figure 21
[1] 40 --ns
tEOPR2 EOP width at receiver must accept as
EOP; see
Figure 21
[1] 82 --ns
Fig 21. Differential data-to-EOP transition skew and EOP width
002aab561
TPERIOD
differential
data lines
crossover point
source EOP width: tFEOPT
receiver EOP width: tEOPR1, tEOPR2
crossover point
extended
differential data to
SE0/EOP skew
n × TPERIOD + tFDEOP
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32-bit ARM Cortex-M3 microcontroller
12.9 SPI
[1] TSPICYC = (Tcy(PCLK) n) 0.5 %, n is the SPI clock divider value (n 8); PCLK is derived from the
processor clock CCLK.
[2] Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %)
edge of the data signal (MOSI or MISO).
Table 18. Dynamic characteristics of SPI pins
Tamb =
40
C to +85
C.
Symbol Parameter Min Typ Max Unit
Tcy(PCLK) PCLK cycle time 10 - - ns
TSPICYC SPI cycle time [1] 79.6 - - ns
tSPICLKH SPICLK HIGH time 0.485 TSPICYC -- ns
tSPICLKL SPICLK LOW time - 0.515 TSPICYC ns
SPI master
tSPIDSU SPI data set-up time [2] 0--ns
tSPIDH SPI data hold time [2] 2 Tcy(PCLK) 5 - - ns
tSPIQV SPI data output valid time [2] 2 Tcy(PCLK) + 30 - - ns
tSPIOH SPI output data hold time [2] 2 Tcy(PCLK) + 5 - - ns
SPI slave
tSPIDSU SPI data set-up time [2] 0--ns
tSPIDH SPI data hold time [2] 2 Tcy(PCLK) + 5 - - ns
tSPIQV SPI data output valid time [2] 2 Tcy(PCLK) + 35 - - ns
tSPIOH SPI output data hold time [2] 2 Tcy(PCLK) + 15 - - ns
Fig 22. SPI master timing (CPHA = 1)
SCK (CPOL = 0)
MOSI
MISO
002aad986
TSPICYC tSPICLKH tSPICLKL
tSPIDSU tSPIDH
tSPIQV
D ATA V ALID D ATA V ALID
tSPIOH
SCK (CPOL = 1)
D ATA V ALID D ATA V ALID
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32-bit ARM Cortex-M3 microcontroller
Fig 23. SPI master timing (CPHA = 0)
Fig 24. SPI slave timing (CPHA = 1)
SCK (CPOL = 0)
MOSI
MISO
002aad987
TSPICYC tSPICLKH tSPICLKL
tSPIDSU tSPIDH
D ATA V ALID D ATA V ALID
tSPIOH
SCK (CPOL = 1)
D ATA V ALID D ATA V ALID
tSPIQV
SCK (CPOL = 0)
MOSI
MISO
002aad988
TSPICYC tSPICLKH tSPICLKL
tSPIDSU tSPIDH
tSPIQV
D ATA V ALID D ATA V ALID
tSPIOH
SCK (CPOL = 1)
D ATA V ALID D ATA V ALID
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13. ADC electrical characteristics
[1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 26.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 26.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 26.
[6] ADCOFFS value (bits 7:4) = 2 in the ADTRM register. See LPC17xx user manual UM10360.
[7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 26.
[8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 26.
[9] See Figure 27.
[10] The conversion frequency corresponds to the number of samples per second.
Fig 25. SPI slave timing (CPHA = 0)
SCK (CPOL = 0)
MOSI
MISO
002aad989
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPIQV
D ATA V ALID D ATA V ALID
t
SPIOH
SCK (CPOL = 1)
D ATA V ALID D ATA V ALID
Table 19. ADC characteristics (full resolution)
VDDA = 2.5 V to 3.6 V; Tamb =
40
C to +85
C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.[1]
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input vol tage 0 - VDDA V
Cia analog input capacitance - - 15 pF
EDdifferential linearity error [2][3] --1LSB
EL(adj) integral non-linearity [4] --3LSB
EOoffset error [5][6] --2LSB
EGgain error [7] --0.5%
ETabsolute er ror [8] --4LSB
Rvsi voltage source interface
resistance [9] --7.5k
fclk(ADC) ADC clock frequency - - 13 MHz
fc(ADC) ADC conversion frequency [10] --200kHz
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[1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 26.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 26.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 26.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 26.
[7] The conversion frequency corresponds to the number of samples per second.
Table 20. ADC characteristics (lower re solution)
Tamb =
40
C to +85
C unless otherwise specified; 12-bit A DC used as 10-bit resolution ADC.[1]
Symbol Parameter Conditions Min Typ Max Unit
EDdifferential linearity error [2][3] -1- LSB
EL(adj) integral non-linearity [4] -1.5 - LSB
EOoffset error [5] -2- LSB
EGgain error [6] -2- LSB
fclk(ADC) ADC clock frequency 3.0 V VDDA 3.6 V - - 33 MHz
2.7 V VDDA < 3.0 V - - 25 MHz
fc(ADC) ADC conversion frequency 3 V VDDA 3.6 V [7] -- 500 kHz
2.7 V VDDA < 3.0 V [7] -- 400 kHz
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(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 26. 12-bit ADC characteristics
002aad948
4095
4094
4093
4092
4091
(2)
(1)
40964090 4091 4092 4093 4094 4095
7123456
7
6
5
4
3
2
1
0
4090
(5)
(4)
(3)
1 LSB
(ideal)
code
out
VREFP VREFN
4096
offset
error
EO
gain
error
EG
offset error
EO
VIA (LSBideal)
1 LSB =
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14. DAC electrical characteristics
Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2.
The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are
process-dependent (see Table 21).
Parasitic resistance and capacitance from the pad are not included in this figure.
Fig 27. ADC interface to pins AD0[n]
Table 21. ADC interface components
Component Range Description
Ri1 2 k to 5.2 kSwitch-on resistance for channel selection switch. Varies with
temperature, input voltage, and process.
Ri2 100 to 600 Switch-on resistance for the comparator input switch. Varies
with temperature, input voltage, and process.
C1 750 fF Parasitic capacitance from the ADC block level.
C2 65 fF Parasitic capacitance from the ADC block level.
C3 2.2 pF Sampling capacitor.
LPC17xx
AD0[n]
750 fF 65 fF Cia
2.2 pF
Rvsi
Ri2
100 Ω - 600 Ω
Ri1
2 kΩ - 5.2 kΩ
VSS VEXT
002aaf197
ADC
COMPARATOR
BLOCK C1
C3
C2
Table 22. DAC electrical characteristics
VDDA = 2.7 V to 3.6 V; Tamb =
40
C to +85
C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
EDdifferential linearity error - 1-LSB
EL(adj) integral non-linearity - 1.5 - LSB
EOoffset error - 0.6 - %
EGgain error - 0.6 - %
CLload capacitance - 200 - pF
RLload resistance 1 - - k
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32-bit ARM Cortex-M3 microcontroller
15. Application information
15.1 Suggested USB interface solutions
Remark: The USB controller is available as a device/Host/OTG controller on parts
LPC1769/68/66/65 and as device-only controller on part LPC1764.
If the LPC1769/68/67/66/65/64/63 VDD is always greater than 0 V while VBUS = 5 V, the
VBUS pin can be connected directly to the VBUS pin on the USB connector.
This applies to bus powered devices where the USB cable supplies the system power . For
systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions
must be taken to reduce the voltage to below 3.6 V.
The maximum allowable voltage on the VBUS pin is 3.6 V. One method is to use a voltage
divider to connect the VBUS pin to the VBUS on the USB connector.
The voltage divider ratio should be such that the VBUS pin will be greater than 0.7VDD to
indicate a logic HIGH while below th e 3. 6 V allow ab le ma xim u m vo ltage.
Use the following operating conditions:
VBUSmax = 5.25 V
VDD = 3.6 V
The voltage divider would need to provide a reduction of 3.6 V/5.25 V or ~0.686 V.
Fig 28. USB interface on a bus-powe red device
LPC17xx
VDD(3V3)
R1
1.5 kΩ
R2
USB_UP_LED
002aad940
USB-B
connector
USB_D+
USB_D
VBUS
VSS
RS = 33 Ω
RS = 33 Ω
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Fig 29. USB interface on a bus-powe red device where VBUS = 5 V, VDD not present
LPC17xx
VDD
R1
1.5 kΩ
R2
R3
USB-B
connector
USB_D+
USB_D-
USB_VBUS
VSS
RS = 33 Ω
RS = 33 Ω
aaa-008962
R2
USB_UP_LED
Fig 30. USB interface with soft-connect
LPC17xx
USB-B
connector
USB_D+
USB_CONNECT
SoftConnect switch
USB_D
V
BUS
V
SS
V
DD(3V3)
R1
1.5 kΩ
RS = 33 Ω
002aad939
RS = 33 Ω
USB_UP_LED
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32-bit ARM Cortex-M3 microcontroller
Fig 31. USB OTG port configuration
USB_D+
USB_D
USB_SDA
USB_SCL
RSTOUT
LPC17xx
Mini-AB
connector
33 Ω
33 Ω
V
DD
V
DD
002aad941
EINTn
RESET_N
ADR/PSW
SPEED
SUSPEND
OE_N/INT_N
SCL
SDA
INT_N
VBUS
ID
DP
DM
ISP1302
V
SS
USB_UP_LED
V
DD
Fig 32. USB host port configuration
USB_UP_LED
USB_D+
USB_D
USB_PWRD
15 kΩ15 kΩ
LPC17xx USB-A
connector
33 Ω
33 Ω
002aad942
VDD
USB_OVRCR
USB_PPWR
LM3526-L
ENA
IN
5 V
FLAGA
OUTA
VDD
D+
D
VBUS
VSS
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15.2 Crystal oscillator XTAL input and component selection
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuate s the input volt age by a facto r Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF
(Figure 34), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 35 and in
Table 23 and Table 24. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 35 represent s the p arallel p ackage cap acitance and sho uld
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
Fig 33. USB device port configuration
LPC17xx
USB-B
connector
33 Ω
33 Ω
002aad943
USB_UP_LED
USB_CONNECT
VDD
VDD
D+
D
USB_D+
USB_D
VBUS VBUS
VSS
Fig 34. Slave mode operation of the on-chip oscillator
LPC1xxx
XTAL1
Ci
100 pF Cg
002aae835
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32-bit ARM Cortex-M3 microcontroller
15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load cap acitors C x1, Cx2, and Cx3 in case o f
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
Fig 35. Oscillator modes and models: oscillation mode of op eration and external crystal
model used for CX1/CX2 evaluation
Table 23. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1/CX2
1 MHz to 5 M Hz 10 pF < 300 18 pF, 18 pF
20 pF < 300 39 pF, 39 pF
30 pF < 300 57 pF, 57 pF
5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 200 39 pF, 39 pF
30 pF < 100 57 pF, 57 pF
10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 60 39 pF, 39 pF
15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF
Table 24. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): high frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF
20 pF < 100 39 pF, 39 pF
20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 80 39 pF, 39 pF
002aaf424
LPC1xxx
XTALIN XTALOUT
CX2
CX1
XTAL
=CLCP
RS
L
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order to keep the no ise couple d in via th e PCB as sm all as po ss ible . A lso parasitic s
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
15.4 Standard I/O pin configuration
Figure 36 shows the possible pin modes for standard I/O pins with analog input function:
Digital output driver: Open -dra i n mod e en ab le d/ disa b led
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Digital input: Repeater mode enabled/disabled
Analog input
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
Fig 36. Standard I/O pin configuration with analog input
PIN
VDD VDD
ESD
VSS
ESD
strong
pull-up
strong
pull-down
VDD
weak
pull-up
weak
pull-down
open-drain enable
output enable
repeater mode
enable
pull-up enable
pull-down enable
data output
data input
analog input
select analog input
002aaf272
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
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15.5 Reset pin configuration
Fig 37. Reset pin configuration
VSS
reset
002aaf274
VDD
VDD
VDD
Rpu ESD
ESD
20 ns RC
GLITCH FILTER PIN
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15.6 ElectroMagnetic Compatibility (EMC)
Radiated emission measurements according to the IEC61967-2 standard using the
TEM-cell method are shown for part LPC1768.
[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.
Table 25. ElectroMagnetic Compatibility (EMC) for part LPC1768 (TEM-cell method)
VDD = 3.3 V; Tamb = 25
C.
Parameter Frequency ba nd System clock = Unit
12 MHz 24 MHz 48 MHz 72 MHz 100 MHz
Input clock: IRC (4 MHz)
maximum
peak level 150 kHz to 30 MHz 76477dBV
30 MHz to 150 MHz + 1 +5 +11 +16 +9 dBV
150 MHz to 1 GHz 2 +4 +11 +12 +19 dBV
IEC level[1] - OONML -
Input clock: crystal oscillator (12 MHz)
maximum
peak level 150 kHz to 30 MHz 54478dBV
30 MHz to 150 MHz 1+5+10+15+7dBV
150 MHz to 1 GHz 1 +6 +11 +10 +16 dBV
IEC level[1] - OONMM-
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16. Package outline
Fig 38. Package outline SOT407-1 (LQFP100)
UNIT A
max. A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.15
0.05 1.45
1.35 0.25 0.27
0.17 0.20
0.09 14.1
13.9 0.5 16.25
15.75 1.15
0.85 7
0
o
o
0.08 0.080.21
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT407-1 136E20 MS-026 00-02-01
03-02-20
D(1) (1)(1)
14.1
13.9
HD
16.25
15.75
E
Z
1.15
0.85
D
bp
e
θ
EA1
A
Lp
detail X
L
(A )
3
B
25
c
D
H
bp
E
HA2
vMB
D
ZD
A
ZE
e
vMA
X
1
100
7675 5150
26
y
pin 1 index
wM
wM
0 5 10 mm
scale
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
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Product data sheet Rev. 9.3 — 8 January 2014 77 of 86
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Fig 39. Package outline SOT926-1 (TFBGA100)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT926-1 - - - - - - - - -
SOT926-1
05-12-09
05-12-22
UNIT A
max
mm 1.2 0.4
0.3 0.8
0.65 0.5
0.4 9.1
8.9 9.1
8.9
A1
DIMENSIONS (mm are the original dimensions)
TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm
A2b D E e2
7.2
e
0.8
e1
7.2
v
0.15
w
0.05
y
0.08
y1
0.1
0 2.5 5 mm
scale
b
e2
e1
e
e
1/2 e
1/2 e
AC B
vMCwM
ball A1
index area
A
B
C
D
E
F
H
K
G
J
24681013579
ball A1
index area
B A
E
D
C
y
C
y1
X
detail X
A
A1
A2
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17. Soldering
Fig 40. Reflow soldering for the LQFP100 package
SOT407-1
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP100 package
Ax
Bx
Gx
Gy
Hy
Hx
AyBy
P1P2
D2 (8×) D1
(0.125)
Ax Ay Bx By D1 D2 Gx Gy Hx HyP1 P2 C
sot407-1
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
17.300 17.300 14.300 14.3000.500 0.560 0.2801.500 0.400 14.500 14.500 17.550 17.550
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Product data sheet Rev. 9.3 — 8 January 2014 79 of 86
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Fig 41. Reflow soldering of the T FBGA10 0 package
DIMENSIONS in mm
PSLSPSRHxHy
Hx
Hy
SOT926-1
solder land plus solder paste
occupied area
Footprint information for reflow soldering of TFBGA100 package
solder land
solder paste deposit
solder resist
P
P
SL
SP
SR
Generic footprint pattern
Refer to the package outline drawing for actual layout
detail X
see detail X
sot926-1_fr
0.80 0.330 0.400 0.480 9.400 9.400
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18. Abbreviations
Table 26. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
BOD BrownOut Detection
CAN Controller Area Networ k
DAC Digital-to-Analog Converter
DMA Direct Memory Access
EOP End Of Packet
GPIO General Purpose Input/Output
IRC Internal RC
IrDA Infrared Data Association
JTAG Joint Test Action Group
MAC Media Access Control
MIIM Media Independent Interface Management
OHCI Open Host Controller Inte rface
OTG On-The-Go
PHY Physical Layer
PLL Phase-Locked Loop
PWM Pulse Width Modulator
RIT Repetitive Interrupt Timer
RMII Reduced Media Independent Interface
SE0 Single Ended Zero
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
TCM Tightly Coupled Memory
TTL Transistor- Transistor Logic
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
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19. Revision history
Table 27. Revision history
Document ID Release
date Data sheet status Change
notice Supersedes
LPC1769_68_67_66_65_64_63 v.9.3 20140108 Product data sheet - LPC1769_68_67_66_65_64 v.9.2
Modifications: Table 7 “Thermal resistanc e (±15 %): Added TFBGA100.
LPC1769_68_67_66_65_64_63 v.9.2 20131021 Product data sheet - LPC1769_68_67_66_65_64 v.9.1
Modifications: Table 8 “Static characteristics ”:
Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the
ADC and DAC are not used.”
Added Table note 4 “VDDA for DAC specs are from 2.7 V to 3.6 V.”
VDDA/VREFP spec changed from 2.7 V to 2.5 V.
Table 19 “ADC characteristics (full resolution)”:
Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the
ADC and DAC are not used.”
VDDA changed from 2.7 V to 2.5 V.
Table 20 “ADC characteristics (lower resolution)”: Added Table note 1 “VDDA
and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used .”
LPC1769_68_67_66_65_64_63 v.9.1 20130916 Product data sheet - LPC1769_68_ 67_66_65_64 v.9
Modifications: Added Table 7 “Thermal resistance”.
Table 6 “Limiting values”:
Updated min/max values for VDD(3V3) and VDD(REG)(3V3).
Updated conditions for VI.
Updated table notes.
Table 8 “Static characteristics”: Added Table note 15 “TCK/SWDCLK pin needs
to be externally pulled LOW.”
Updated Section 15.1 “Suggested USB interface solutions”.
Added Section 5 “Marking”.
Changed title of Figure 31 from “USB interface on a self-powered device” to
“USB interface with soft-connect”.
LPC1769_68_67_66_65_64_63 v.9 20120810 Product data sheet - LPC1769_68_ 67_66_65_64 v.8
Modifications: Remove table note “The peak current is limited to 25 times the corresponding
maximum current.” from Table 5 “Limiting values”.
Change VDD(3V3) to VDD(REG)(3V3) in Section 11.3 “Internal oscillators”.
Glitch filter constant changed to 10 ns in Table note 6 in Table 4.
Description of RESET function updated in Table 4.
Pull-up value added for GPIO pins in Table 4.
Pin configuration diagram for LQFP100 package corrected (Figure 2).
LPC1769_68_67_66_65_64_63 v.8 20111114 Product data sheet - LPC1769_68_67_66_65_64 v.7
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Product data sheet Rev. 9.3 — 8 January 2014 82 of 86
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Modifications: Pin description of USB_UP_LED pin updated in Table 4.
Ri1 and Ri2 labels in Figure 27 updated.
Part LPC1765FET100 added .
Table note 10 updated in Table 4.
Table note 1 updated in Table 12.
Pin description of STCLK pin updated in Table 4.
Electromagnetic compatibility data added in Section 14.6.
Section 16 added.
LPC1769_68_67_66_65_64_63 v.7 20110405 Product data sheet - LPC1769_68_67_66_65_64 v. 6
Modifications: Pin description of pins P0[29] and P0[30] update d in Table note 5 of Table 4.
Pins are not 5 V tolerant.
Typical value for Parameter Nendu added in Table 9.
Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD(3V3) in
Table 7.
Condition 3.0 V VDD(3V3) 3.6 V added in Table 16.
Typical values for parameters IDD(REG)(3V3) and IBAT with condi tion Deep
power-down mode corrected in Table 7 and Table note 9, Table note 10, and
Table note 11 updated.
For Deep power-down mode, F igure 9 updated and Figure 10 added.
LPC1769_68_67_66_65_64_63 v.6 20100825 Product data sheet - LPC1769_68_ 67_66_65_64 v.5
Modifications: Part LPC1768TFBGA added.
Section 7.30.2; BOD level corrected.
Added Section 10.2.
LPC1769_68_67_66_65_64_63 v.5 20100716 Product data sheet - LPC1769_68_ 67_66_65_64 v.4
LPC1769_68_67_66_65_64 v.4 20100201 Prod uct data sheet - LPC1768_67_66_65_64 v.3
LPC1768_67_66_65_64 v.3 20091119 Product data sheet - LPC1768_66_65_64 v.2
LPC1768_66_65_64 v.2 20090211 Objective data sheet - LPC1768_66_65_64 v.1
LPC1768_66_65_64 v.1 20090115 Objective data sheet - -
Table 27. Revision history …continued
Document ID Release
date Data sheet status Change
notice Supersedes
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20. Legal information
20.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s docume nt was publish ed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
20.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Te rms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly ob jects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specificatio ns, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specificat ions.
20.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet Rev. 9.3 — 8 January 2014 85 of 86
continued >>
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
22. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4
4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4
5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 Functional description . . . . . . . . . . . . . . . . . . 20
8.1 Architectural overview . . . . . . . . . . . . . . . . . . 20
8.2 ARM Cortex-M3 processor. . . . . . . . . . . . . . . 20
8.3 On-chip flash program memory . . . . . . . . . . . 20
8.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 20
8.5 Memory Protection Unit (MPU). . . . . . . . . . . . 20
8.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.7 Nested Vectored Interrupt Controller (NVIC) . 23
8.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 23
8.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 23
8.9 General purpose DMA controller . . . . . . . . . . 23
8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.10 Fast general purpose parallel I/O . . . . . . . . . . 24
8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 26
8.12.1 USB device controller. . . . . . . . . . . . . . . . . . . 26
8.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.12.2 USB host controller . . . . . . . . . . . . . . . . . . . . 27
8.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 27
8.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.13 CAN controller and acceptance filters . . . . . . 27
8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 29
8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 29
8.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.19 I2C-bus serial I/O controllers . . . . . . . . . . . . . 30
8.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 31
8.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.21 General purpose 32-bit timers/external event
counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 32
8.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 33
8.24 Quadrature Encoder Interface (QEI) . . . . . . . 33
8.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 34
8.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.26 ARM Cortex-M3 system tick timer . . . . . . . . . 34
8.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 34
8.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.28 RTC and backup registers. . . . . . . . . . . . . . . 35
8.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.29 Clocking and power control . . . . . . . . . . . . . . 35
8.29.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 35
8.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 36
8.29.1.2 Main oscilla tor . . . . . . . . . . . . . . . . . . . . . . . . 36
8.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 36
8.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 37
8.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 37
8.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 37
8.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 37
8.29.6 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 38
8.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 38
8.29.6.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 39
8.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 39
8.29.6.5 Wake-up interrupt controller . . . . . . . . . . . . . 39
8.29.7 Peripheral power control . . . . . . . . . . . . . . . . 39
8.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 40
8.30 System control. . . . . . . . . . . . . . . . . . . . . . . . 41
8.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 42
8.30.3 Code security (Code Read Protection - CRP) 42
8.30.4 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 42
8.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 43
8.30.6 External interrupt inputs. . . . . . . . . . . . . . . . . 43
8.30.7 Memory mapping control . . . . . . . . . . . . . . . . 43
8.31 Emulation and debugging . . . . . . . . . . . . . . . 43
9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 44
10 Thermal characteristics . . . . . . . . . . . . . . . . . 45
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2014. Al l rights rese rved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 January 2014
Document identifier: LPC1769_68_67_66_65_64_63
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 46
11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 49
11.2 Peripheral power consumption. . . . . . . . . . . . 52
11.3 Electrical pin characteristics. . . . . . . . . . . . . . 53
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 55
12.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 55
12.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.3 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 56
12.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.6 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 58
12.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 61
12.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13 ADC electrical characteristics . . . . . . . . . . . . 64
14 DAC electrical characteristics . . . . . . . . . . . . 67
15 Application information. . . . . . . . . . . . . . . . . . 68
15.1 Suggested USB interface solutions . . . . . . . . 68
15.2 Crystal oscillator XTAL input and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15.3 XTAL and RTCX Printed Circuit Board (PCB)
layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 72
15.4 Standard I/O pin configuration . . . . . . . . . . . . 73
15.5 Reset pin configuration. . . . . . . . . . . . . . . . . . 74
15.6 ElectroMagnetic Compatibility (EMC). . . . . . . 75
16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 76
17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 80
19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 81
20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 83
20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 83
20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
20.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 83
20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
21 Contact information. . . . . . . . . . . . . . . . . . . . . 84
22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85