1
Features
•One-time Programmable (OTP) Feature
•Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
•Internally Organized 16,384 x 8
•2-wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
•Write Protect Pin for Hardware and Software Data Protection
•64-byte Page Write Mode (Partial Page Writes Allowed)
•Self-timed Write Cycle (5 ms typical)
•High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
•Automotive Grade and Extended Temperature Devices Available
•8-lead JEDEC PDIP, 8-lead JEDEC SOIC and 8-lead EIAJ SOIC Packages
Description
The AT24CS128 provides 131,072 bits of serial electrically-erasable and programma-
ble read only memory (EEPROM) organized as 16,384 words of 8 bits each. The
device’s cascadable feature allows up to 4 devices to share a common 2-wire bus. The
device also features a one-time programmable 2048-bit array, which once enabled,
becomes read-only and cannot be overwritten. If not enabled, the OTP section will
function as part of the normal memory array. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The device is available in space-saving 8-lead JEDEC PDIP, 8-lead
JEDEC SOIC and 8-lead EIAJ SOIC packages. In addition, the entire family is avail-
able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
Rev. 1152G–SEEPR–10/05
2-wire Serial
EEPROMs
with Permanent
Software Write
Protect
128K (16,384 x 8)
AT24CS128(1)
Note: 1. This device is not rec-
ommended for new
designs.
Table 1. Pin Configurations
Pin Name Function
A0 - A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
Pin SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
2AT24CS128
1152G–SEEPR–10/05
Figure 1. Block Diagram
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A1 and A0 pins are device address inputs
that are hardwired or left not connected for hardware compatibility with AT24C32. When the
pins are hardwired, as many as four 128K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section). When the pins
are not hardwired, the default A1 and A0 are zero. The A2 device address input is a “don’t
care” input.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write oper-
ations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
A2
3
AT24CS128
1152G–SEEPR–10/05
unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write
operation creates a software write protect function.
Memory Organization AT24CS128, 128K SERIAL EEPROM: The 128K is internally organized as 256 pages
of 64-bytes each. Random word addressing requires a 14-bit data word address.
Note: This parameter is characterized and is not 100% tested.
Note: VIL min and VIH max are reference only and are not tested.
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 3.6 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA
ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA
ISB1 Standby Current
(1.8V option)
VCC = 1.8V VIN = VCC or VSS
1.0 µA
VCC = 3.6V 3.0
ISB2 Standby Current
(2.7V option)
VCC = 2.7V VIN = VCC or VSS
2.0 µA
VCC = 5.5V 5.0
ISB3 Standby Current
(5.0V option) VCC = 4.5 - 5.5V VIN = VCC or VSS 5.0 µA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
ILO Output Leakage
Current VOUT = VCC or VSS 0.05 3.0 µA
VIL Input Low Level(Note:) -0.6 VCC x 0.3 V
VIH Input High Level(Note:) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC3 = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
4AT24CS128
1152G–SEEPR–10/05
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5VCC
Table 4. AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
Symbol Parameter
1.8-volt 2.7-volt 5.0-volt
UnitsMin Max Min Max Min Max
fSCL Clock Frequency, SCL 100 400 1000 kHz
tLOW Clock Pulse Width Low 4.7 1.3 0.4 µs
tHIGH Clock Pulse Width High 4.0 0.6 0.4 µs
tAA Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs
tBUF Time the bus must be free before a new
transmission can start(1) 4.7 1.3 0.5 µs
tHD.STA Start Hold Time 4.0 0.6 0.25 µs
tSU.STA Start Set-up Time 4.7 0.6 0.25 µs
tHD.DAT Data In Hold Time 0 0 0 µs
tSU.DAT Data In Set-up Time 200 100 100 ns
tRInputs Rise Time(1) 1.0 0.3 0.3 µs
tFInputs Fall Time(1) 300 300 100 ns
tSU.STO Stop Set-up Time 4.7 0.6 0.25 µs
tDH Data Out Hold Time 100 50 50 ns
tWR Write Cycle Time 20 10 10 ms
Endurance(1) 5.0V, 25°C, Page Mode 100K 100K 100K Write
Cycles
5
AT24CS128
1152G–SEEPR–10/05
Device
Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Figure 4).
Data changes during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Figure 5).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (refer to
Figure 5).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24CS128 features a low-power standby mode which is enabled: a)
upon power-up and b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in
each cycle while SCL is high and then (c) create a start condition as SDA is high.
6AT24CS128
1152G–SEEPR–10/05
Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
twr(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
7
AT24CS128
1152G–SEEPR–10/05
Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
8AT24CS128
1152G–SEEPR–10/05
Device
Addressing
The 128K EEPROM requires an 8-bit device address word following a start condition to enable
the chip for a read or write operation (refer to Figure 7). The device address word consists of a
mandatory one, zero sequence for the first five most significant bits as shown. This is common
to all 2-wire EEPROM devices.
The 128K uses the two device address bits A1, A0 to allow as many as four devices on the
same bus. These bits must compare to their corresponding hardwired input pins. The A1 and
A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins
are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24CS128 has a hardware data protection scheme that allows the
user to write protect the whole memory when the WP pin is at VCC.
Write
Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during
this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 8).
PAGE WRITE: The 128K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter-
minate the page write sequence with a stop condition (refer to Figure 9).
The data word address lower 6 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.
9
AT24CS128
1152G–SEEPR–10/05
OTP Description/
Operation
The OTP feature provides the user with a 2048-bit (256 x 8) security section, which once
programmed and enabled, becomes read-only and data cannot be changed or overwrit-
ten. The OTP section is located in the upper 2K section of the memory array in the
AT24CS128. If not enabled, the OTP section will function as part of the normal memory
array.
To enable the OTP section:
1. Inputs must be connected:
A2 = Don’t Care, A1 and A0 = VCC or GND
2. Initiate the programming sequence:
START 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx STOP
Once enabled, previously written data cannot be changed. The status of the OTP sec-
tion can only be confirmed by initiating a programming sequence to the OTP section and
verifying by a read command. The use of the write protect (WP) feature can be utilized
with or without enabling the OTP function.
Read Operations Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 10).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 11).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi-
tion (refer to Figure 12).
10 AT24CS128
1152G–SEEPR–10/05
Figure 7. Device Address
Figure 8. Byte Write
Figure 9. Page Write
(* = DON’T CARE bit)
(† = DON’T CARE bit for the 128K)
11
AT24CS128
1152G–SEEPR–10/05
Figure 10. Current Address Read
Figure 11. Random Read
(* = DON’T CARE bit)
(† = DON’T CARE bit for the 128K)
Figure 12. Sequential Read
12 AT24CS128
1152G–SEEPR–10/05
Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
AT24CS128 Ordering Information
Ordering Code Package Operation Range
AT24CS128-10PI-2.7
AT24CS128N-10SI-2.7
AT24CS128W-10SI-2.7
8P3
8S1
8S2
Industrial
(-40°C to 85°C)
AT24CS128-10PI-1.8
AT24CS128N-10SI-1.8
AT24CS128W-10SI-1.8
8P3
8S1
8S2
Industrial
(-40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
Options
-2.7 Low-voltage (2.7V to 5.5V)
-1.8 Low-voltage (1.8V to 3.6V)
13
AT24CS128
1152G–SEEPR–10/05
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Top View
Side View
End View
14 AT24CS128
1152G–SEEPR–10/05
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
3/17/05
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
θ 0˚ – 8˚
Ø
Ø
E
E
1
1
N
N
TOP VIEW
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
SIDE VIEW
15
AT24CS128
1152G–SEEPR–10/05
8S2 – EIAJ
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
Printed on recycled paper.
1152G–SEEPR–10/05
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