SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
FEATURES
DSimultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
DSignal-to-Noise and Distortion Ratio:
68 dB at fI = 2 MHz
DDifferential Nonlinearity Error: ±1 LSB
DIntegral Nonlinearity Error: ±1.5 LSB
DAuto-Scan Mode for 2, 3, or 4 Inputs
D3-V or 5-V Digital Interface Compatible
DLow Power: 216 mW Max at 5 V
DPower Down: 1 mW Max
D5-V Analog Single Supply Operation
DInternal Voltage References ...50 PPM/°C
and ±5% Accuracy
DGlueless DSP Interface
DParallel µC/DSP Interface
APPLICATIONS
DRadar Applications
DCommunications
DControl Applications
DHigh-Speed DSP Front-End
DAutomotive Applications
DESCRIPTION
The THS1207 is a CMOS, low-power, 12-bit, 6 MSPS
analog-to-digital converter (ADC). The speed,
resolution, bandwidth, and single-supply operation are
suited for applications in radar, imaging, high-speed
acquisition, and communications. A multistage
pipelined architecture with output error correction logic
provides for no missing codes over the full operating
temperature range. Internal control registers are used
to program the ADC into the desired mode. The
THS1207 consists of four analog inputs, which are
sampled simultaneously. These inputs can be selected
individually and configured to single-ended or
differential-inputs. Internal reference voltages for the
ADC (1.5 V and 3.5 V) are provided. An external
reference can also be chosen to suit the dc accuracy
and temperature drift requirements of the application.
The THS1207C is characterized for operation from 0°C
to 70°C, the THS1207I is characterized for operation
from –40°C to 85°C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D0
D1
D2
D3
D4
D5
BVDD
BGND
D6
D7
D8
D9
D10/RA0
D11/RA1
CONV_CLK
SYNC
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
DA PACKAGE
(TOP VIEW)
ORDERING INFORMATIONPACKAGED DEVICE
TATSSOP
(DA)
0°C to 70°C THS1207CDA
–40°C to 85°C THS1207IDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002, Texas Instruments Incorporated
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
DGND to DVDD –0.3 V to 6.5 V
Supply voltage range BGND to BVDD –0.3 V to 6.5 V
Su ly
voltage
range
AGND to AVDD –0.3 V to 6.5 V
Analog input voltage range AGND –0.3 V to AVDD + 1.5 V
Reference input voltage –0.3 V + AGND to AVDD + 0.3 V
Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V
Operating virtual junction temperature range, TJ–40°C to 150°C
Operating free air temperature range T
THS1207C 0°C to 70°C
Operating free-air temperature range, TATHS1207I –40°C to 85°C
Storage temperature range, Tstg –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , an d
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
POWER SUPPLY MIN NOM MAX UNIT
AVDD 4.75 5 5.25
Supply voltage DVDD 4.75 5 5.25 V
yg
BVDD 3 5.25
ANALOG AND REFERENCE INPUTS MIN NOM MAX UNIT
Analog input voltage in single-ended configuration VREFM VREFP V
Common-mode input voltage VCM in differential configuration 1 2.5 4 V
External reference voltage,VREFP (optional) 3.5 AVDD–1.2 V
External reference voltage, VREFM (optional) 1.4 1.5 V
Input voltage dif ference, REFP – REFM 2 V
DIGITAL INPUTS MIN NOM MAX UNIT
High level input voltage V
BVDD = 3.3 V 2 V
High-level input voltage, VIH BVDD = 5.25 V 2.6 V
Low level input voltage V
BVDD = 3.3 V 0.6 V
Low-level input voltage, VIL BVDD = 5.25 V 0.6 V
Input CONV_CLK frequency DVDD = 4.75 V to 5.25 V 0.1 6 MHz
CONV_CLK pulse duration, clock high, tw(CONV_CLKH) DVDD = 4.75 V to 5.25 V 80 83 5000 ns
CONV_CLK pulse duration, clock low, tw(CONV_CLKL) DVDD = 4.75 V to 5.25 V 80 83 5000 ns
Operating free air temperature T
THS1207CDA 0 70
°C
Operating free-air temperature, TATHS1207IDA –40 85 °C
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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3
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, A VDD = DVDD = 5 V, BVDD = 3.3 V, VREWF = internal (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital inputs
IIH High-level input current DVDD = digital inputs –50 50 µA
IIL Low-level input current Digital input = 0 V –50 50 µA
CiInput capacitance 5 pF
Digital outputs
VOH High-level output voltage IOH = –50 µA
BV 3 3 V 5 V
BVDD–0.5 V
VOL Low-level output voltage IOL = 50 µABVDD = 3.3 V, 5 V 0.4 V
IOZ High-impedance-state output current CS1 = DGND, CS0 = DVDD –10 10 µA
COOutput capacitance 5 pF
CLLoad capacitance at databus D0 – D11 30 pF
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, A VDD = DVDD = 5 V, BVDD = 3.3 V, fs = 6 MSPS, VREF = internal (unless otherwise noted)
DC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
Accuracy
Integral nonlinearity, INL ±1.5 LSB
Differential nonlinearity, DNL ±1 LSB
Offset error
After calibration in single-ended mode 20 LSB
Offset error After calibration in differential mode –20 20 LSB
Gain error –20 20 LSB
Analog input
Input capacitance 15 pF
Input leakage current VAIN = VREFM to VREFP ±10 µA
Internal voltage reference
Accuracy, VREFP 3.3 3.5 3.7 V
Accuracy, VREFM 1.4 1.5 1.6 V
Temperature coefficient 50 PPM/°C
Reference noise 100 µV
Accuracy, REFOUT 2.475 2.5 2.525 V
Power supply
IDDA Analog supply current AVDD = DVDD = 5 V, BVDD =3.3 V 36 40 mA
IDDD Digital supply current AVDD = DVDD = 5 V, BVDD = 3.3 V 0.5 3 mA
IDDB Buffer supply current AVDD = DVDD = 5 V, BVDD = 3.3 V 1.5 4 mA
Power dissipation AVDD = DVDD = 5 V, BVDD = 3.3 V 186 216 mW
Power dissipation in power down with conversion
clock inactive AVDD = DVDD = 5 V, BVDD = 3.3 V 0.25 mW
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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4
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 6 MSPS, fI = 2 MHz at –1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SINAD
Signal to noise ratio + distortion
Differential mode 63 63
dB
SINAD Signal-to-noise ratio + distortion Single-ended mode 62 64 dB
SNR
Signal to noise ratio
Differential mode 64 69
dB
SNR Signal-to-noise ratio Single-ended mode 64 68 dB
THD
Total harmonic distortion
Differential mode –70 –67
dB
THD Total harmonic distortion Single-ended mode –68 –64 dB
ENOB
Effective number of bits
Differential mode 10.17 10.5
Bits
ENOB Effective number of bits Single-ended mode 10 10.3 Bits
SFDR
S
p
urious free dynamic range
Differential mode 67 71
dB
SFDR Spurious free dynamic range Single-ended mode 65 69 dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
dif ferential configuration.
Full scale sinewave 3dB
96
MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, –3 dB 54 MHz
Small-signal bandwidth with a source impedance of 150 Ω in
dif ferential configuration.
100 mV
pp
sinewave 3dB
96
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, –3 dB 54 MHz
TIMING REQUIREMENTS
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpipe Latency 5 CONV
CLK
tsu(CONV_CLKL-READL) Setup time, CONV_CLK low before CS valid 10 ns
tsu(READH-CONV_CLKL) Setup time, CS invalid to CONV_CLK low 20 ns
td(CONV_CLKL-SYNCL) Delay time, CONV_CLK low to SYNC low 10 ns
td(CONV_CLKL-SYNCH) Delay time, CONV_CLK low to SYNC high 10 ns
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
AINP 32 I Analog input, single-ended or positive input of differential channel A
AINM 31 I Analog input, single-ended or negative input of differential channel A
BINP 30 I Analog input, single-ended or positive input of differential channel B
BINM 29 I Analog input, single-ended or negative input of differential channel B
AVDD 23 I Analog supply voltage
AGND 24 I Analog ground
BVDD 7 I Digital supply voltage for buffer
BGND 8 I Digital ground for buffer
CONV_CLK 15 I Digital input. This input is the conversion clock input.
CS0 22 I Chip select input (active low)
CS1 21 I Chip select input (active high)
DGND 17 I Digital ground. Ground reference for digital circuitry.
DVDD 18 I Digital supply voltage
D0 – D9 1–6,
9–12 I/O/Z Digital input, output; D0 = LSB
D10/RA0 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is
required for writing to the control register 0 and control register 1. See Table 7.
D11/RA1 14 I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register.
This is required for writing to control register 0 and control register 1. See Table 7.
REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the
reference output REFOUT.
REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.
An external reference voltage at this input can be applied. This option can be programmed through control
register 0. See Table 8.
REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.
An external reference voltage at this input can be applied. This option can be programmed through control
register 0. See Table 8.
REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output
requires a capacitor of 10 µF to AGND for filtering and stability.
RD(1) 19 I The R D input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active
low as a data read select from the processor. See timing section.
SYNC 16 O Synchronization output. This signal indicates in a multichannel operation that data of channel A is brought to the
digital output and can therefore be used for synchronization.
WR (R/W)(1) 20 I This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only
input W R , which is active low and used as data write select from the processor. In this case, the RD input is used
as a read input from the processor. See timing section.
(1) The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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6
FUNCTIONAL BLOCK DIAGRAM
Logic and Control
12 Bit
Pipeline
ADC
S/H
S/H
S/H
S/H
Single
Ended
and/or
Differential
MUX
+
–
VREFM
1.5 V
3.5 V
1.225 V
REF
12
Buffers
2.5 V
Control
Register
AVDD DVDD
AGND DGND
REFOUT
BVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10/RA0
D11/RA1
BGND
REFP
REFM
AINP
AINM
BINP
BINM
CONV_CLK
CS0
CS1
RD
WR (R/W)
REFIN
VREFP
SYNC
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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7
TYPICAL CHARACTERISTICS
Figure 1
40
45
50
55
60
65
70
75
80
01234567
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 2
40
45
50
55
60
65
70
01234567
SIGNAL-TO-NOISE AND DIST ORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs – Sampling Frequency – MHz
SINAD – Signal-to-Noise and Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 3
40
45
50
55
60
65
70
75
80
85
90
01234567
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs – Sampling Frequency – MHz
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 4
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs – Sampling Frequency – MHz
SNR – Signal-to-Noise – dB
40
45
50
55
60
65
70
01234567
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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8
TYPICAL CHARACTERISTICS
Figure 5
40
45
50
55
60
65
70
75
80
85
01234567
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 6
40
45
50
55
60
65
70
75
80
01234567
SIGNAL-TO-NOISE AND DIST ORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs – Sampling Frequency – MHz
SINAD – Signal-to-Noise and Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 7
40
45
50
55
60
65
70
75
80
85
90
95
100
01234567
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs – Sampling Frequency – MHz
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 8
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs – Sampling Frequency – MHz
SNR – Signal-to-Noise – dB
40
45
50
55
60
65
70
75
80
01234567
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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9
TYPICAL CHARACTERISTICS
Figure 9
40
45
50
55
60
65
70
75
80
85
0.0 0.5 1.0 1.5 2.0 2.5 3.0
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 10
40
45
50
55
60
65
70
75
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0
SIGNAL-TO-NOISE AND DIST ORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
SINAD – Signal-to-Noise and Distortion – dB
fi – Input Frequency – MHz
Figure 11
40
45
50
55
60
65
70
75
80
85
90
95
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
Figure 12
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (SINGLE-ENDED)
SNR – Signal-to-Noise – dB
40
45
50
55
60
65
70
75
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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10
TYPICAL CHARACTERISTICS
Figure 13
20
30
40
50
60
70
80
90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 14
20
30
40
50
60
70
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SIGNAL-TO-NOISE AND DIST ORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
SINAD – Signal-to-Noise and Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
Figure 15
20
30
40
50
60
70
80
90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (DIFFERENTIAL)
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
20
30
40
50
60
70
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Figure 16
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
SNR – Signal-to-Noise – dB
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11
TYPICAL CHARACTERISTICS
Figure 17
6
7
8
9
10
11
12
01234567
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz Figure 18
6
7
8
9
10
11
12
01234567
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz
Figure 19
6
7
8
9
10
11
12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz Figure 20
6
7
8
9
10
11
12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
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12
TYPICAL CHARACTERISTICS
Figure 21
–30
–25
–20
–15
–10
–5
0
5
0 102030405060708090100110120
G – Gain – dB
GAIN
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
Figure 22
–140
–120
–100
–80
–60
–40
–20
0
20
0 500000 1000000 1500000 2000000 2500000 3000000 3500000
Magnitude – dB
f – Frequency – Hz
FAST FOURIER TRANSFORM (4096 POINTS) (SINGLE-ENDED)
vs
FREQUENCY
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
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TYPICAL CHARACTERISTICS
–140
–120
–100
–80
–60
–40
–20
0
20
0 500000 1000000 1500000 2000000 2500000 3000000 3500000
Figure 23
Magnitude – dB
f – Frequency – Hz
FAST FOURIER TRANSFORM (4096 POINTS) (DIFFERENTIAL)
vs
FREQUENCY
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
Figure 24
–1.0
–0.8
–0.6
–0.4
–0.2
–0.0
0.2
0.4
0.6
0.8
1.0
0 500 1000 1500 2000 2500 3000 3500 4000
DNL – Differential Nonlinearity – LSB
ADC Code
DIFFERENTIAL NONLINEARITY
vs
ADC CODE
AVDD = 5 V
DVDD = BVDD = 3 V
fs = 8 MSPS
Figure 25
–1.0
–0.8
–0.6
–0.4
–0.2
–0.0
0.2
0.4
0.6
0.8
1.0
0 500 1000 1500 2000 2500 3000 3500 4000
INL – Integral Nonlinearity – LSB
ADC Code
INTEGRAL NONLINEARITY
vs
ADC CODE
AVDD = 5 V
DVDD = BVDD = 3 V
fs = 8 MSPS
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14
DETAILED DESCRIPTION
Reference Voltage
The THS1207 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP
and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS1207 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
Converter
The THS1207 uses a 12-bit pipelined multistaged architecture, which achieves a high sample rate with low
power consumption. The THS1207 distributes the conversion over several smaller ADC sub-blocks, refining
the conversion with progressively higher accuracy as the device passes the results from stage to stage. This
distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.
A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input
sample while the second through the eighth stages operate on the seven preceding samples.
Conversion Clock
An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal. The conversion values are available
at the output with a latency of 5 clock cycles.
SYNC
In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK
after a SYNC reset. This is due to the latency of the pipeline architecture of the THS1207.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels.
Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate
CHANNEL CONFIGURATION NUMBER OF
CHANNELS MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel 16 MSPS
2 single-ended channels 23 MSPS
3 single-ended channels 32 MSPS
4 single-ended channels 41.5 MSPS
1 differential channel 16 MSPS
2 dif ferential channels 23 MSPS
1 single-ended and 1 differential channel 23 MSPS
2 single-ended and 1 differential channels 32 MSPS
The maximum conversion rate in the continuous conversion mode per channel, is given by:
fc +6 MSPS
# channels
Conversion
During conversion the ADC operates with a free running external clock applied to the input CONV_CLK. With
every falling edge of the CONV_CLK signal a new converted value is available to the databus with the
corresponding read signal. The THS1207 allows up to four analog input to be selected. The inputs can be
configured as two differential channels, four single-ended channels or a combination of differential and
single-ended.
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15
To provide the system with channel information, the THS1207 utilizes an active low SYNC signal. When
operated i n a multichannel configuration, the SYNC signal is active low when data from channel one is available
to the databus. When operated in single-channel mode (single-ended or differential operation) the SYNC signal
is disabled.
Figure 26 shows the timing of the conversion when one analog input channel is selected. The maximum
throughput rate is 6 MSPS in this mode. There is a certain timing relationship required for the read signal with
respect to the conversion clock. This can be seen in Figure 26 and in the read and SYNC timing table. A more
detailed description of the timing is given in the timing section and signal description of the THS1207.
Sample N
Channel 1 Sample N+2
Channel 1 Sample N+3
Channel 1
Sample N+1
Channel 1 Sample N+4
Channel 1 Sample N+5
Channel 1 Sample N+6
Channel 1
Data N–1
Channel 1 Data N
Channel 1 Data N+1
Channel 1 Data N+2
Channel 1
Data N–4
Channel 1 Data N–3
Channel 1 Data N–2
Channel 1
AIN
CONV_CLK
READ†
†READ i s the logical combination from CS0, CS1 and RD
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
Figure 26. Conversion Timing in 1-Channel Operation
Figure 27 shows the conversion timing when 2 analog input channels are selected. The maximum throughput
rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The signal SYNC is active low when data of channel one is available
to the databus. The data of channel one is followed by the data of channel two before channel one is again
available and the SYNC signal is active low.
Sample N
Channel 1, 2 Sample N+1
Channel 1, 2 Sample N+2
Channel 1, 2 Sample N+3
Channel 1, 2
Data N–1
Channel 2 Data N
Channel 1 Data N
Channel 2 Data N+1
Channel 1
Data N–2
Channel 1 Data N–2
Channel 2 Data N–1
Channel 1
AIN
CONV_CLK
READ†
†READ i s the logical combination from CS0, CS1 and RD
SYNC
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL) td(CONV_CLKL-SYNCH)
Figure 27. Conversion Timing in 2-Channel Operation
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16
Figure 28 shows the conversion timing when 3 analog input channels are selected. The maximum throughput
rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The signal SYNC is always active low if data of channel one is
available to the databus. The data of channel one is followed by the data of channel two and data of channel
three before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3 Sample N+1
Channel 1, 2, 3 Sample N+2
Channel 1, 2, 3
Data N–1
Channel 3 Data N
Channel 1 Data N
Channel 2 Data N
Channel 3
Data N–2
Channel 3 Data N–1
Channel 1 Data N–1
Channel 2
AIN
CONV_CLK
READ†
†READ i s the logical combination from CS0, CS1 and RD
SYNC
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL) td(CONV_CLKL-SYNCH)
Figure 28. Conversion Timing in 3-Channel Operation
Figure 29 shows the timing of the conversion mode where 4 analog input channels are selected. The maximum
throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the databus. The signal SYNC is active low when data of channel one
is available to the databus. The data of channel one is followed by the data of channel two, data of channel three
and data of channel 4 before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3, 4 Sample N+1
Channel 1, 2, 3, 4
Data N–1
Channel 4 Data N
Channel 1 Data N
Channel 2 Data N
Channel 3
Data N–1
Channel 1 Data N–1
Channel 2 Data N–1
Channel 3
AIN
CONV_CLK
READ†
†READ i s the logical combination from CS0, CS1 and RD
SYNC
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-SYNCH)
tsu(CONV_CLKL-SYNCL)
Figure 29. Timing of Continuous Conversion Mode (4-channel operation)
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17
DIGITAL OUTPUT DATA FORMAT
The digital output data format of the THS1207 can either be in binary format or in twos complement format. The
following tables list the digital outputs for the analog input voltages.
Table 2. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINAR Y OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = VREFP FFFh
AIN = (VREFP + VREFM)/2 800h
AIN = VREFM 000h
Table 3. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = VREFP 7FFh
AIN = (VREFP + VREFM)/2 000h
AIN = VREFM 800h
Table 4. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF FFFh
Vin = 0 800h
Vin = –VREF 000h
Table 5. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF 7FFh
Vin = 0 000h
Vin = –VREF 800h
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18
ADC CONTROL REGISTER
The THS1207 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the
desired mode. The bit definitions of both control registers are shown in Table 6.
Table 6. Bit Definitions of Control Register CR0 and CR1
REG BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RESERVED VREF
CR1 RBACK OFFSET BIN/2’s R/W RESERVED RESERVED RESERVED RESERVED SRST RESET
Writing to Control Register 0 and Control Register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper data bits D10
and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0
to D9 contain the desired control register value. Table 7 shows the addressing of each control register.
Table 7. Control Register Addressing
D0 – D9 D10/RA0 D11/RA1 Addressed Control Register
Desired register value 0 0 Control register 0
Desired register value 1 0 Control register 1
Desired register value 0 1 Reserved for future
Desired register value 1 1 Reserved for future
Start
Use Default
Values?
Yes
W rite 0x401 to
THS1207
(Set Reset Bit in CR1)
No
W rite 0x401 to
THS1207
(Set Reset Bit in CR1)
Clear RESET By
W riting 0x400 to CR1
W rite the User
Configuration to CR0
W rite the User
Configuration to CR1
(Must Exclude RESET)
Continue
Clear RESET By
W riting 0x400 to
CR1
Figure 30. THS1207 Configuration Flow
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19
Control Register 0 (see Table 7)
BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RESERVED VREF
Table 8. Control Register 0 Bit Functions
BITS RESET
VALUE NAME FUNCTION
0 0 VREF Vref select:
Bit 0 = 0 → The internal reference is used
Bit 0 = 1 → The external reference voltage is used for the ADC
1 0 RESERVED RESERVED
2 0 PD Power down.
Bit 2 = 0 → The ADC is active
Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down.
3, 4 0,0 CHSEL0,
CHSEL1 Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 9.
5,6 1,0 DIFF0, DIFF1 Number of differential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 9.
7 0 SCAN Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 9.
8,9 0,0 TEST0,
TEST1 Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC in its bits.
Refer to Table 10 for selection of the three different test voltages.
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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20
ANALOG INPUT CHANNEL SELECTION
The analog input channels of the THS1207 can be selected via bits 3 to 7 of control register 0. One channel
(single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection
between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than o ne
input channel is selected. Table 9 shows the possible selections.
Table 9. Analog Input Channel Configurations
BIT 7
SCAN BIT 6
DIFF1 BIT 5
DIFF0 BIT 4
CHSEL1 BIT 3
CHSEL0 DESCRIPTION OF THE SELECTED INPUTS
0 0 0 0 0 Analog input AINP (single ended)
0 0 0 0 1 Analog input AINM (single ended)
0 0 0 1 0 Analog input BINP (single ended)
0 0 0 1 1 Analog input BINM (single ended)
0 0 1 0 0 Dif ferential channel (AINP–AINM)
0 0 1 0 1 Dif ferential channel (BINP–BINM)
1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, …
1 0 0 1 0 Autoscan three single ended channels: AINP, AINM, BINP, AINP, …
1 0 0 1 1 Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …
1 0 1 0 1 Autoscan one differential channel and one single ended channel AINP, (BINP–BINM),
AINP, (BINP–BINM), …
1 0 1 1 0 Autoscan one differential channel and two single ended channel AINP, AINM, (BINP–
BINM), AINP, …
1 1 0 0 1 Autoscan two differential channels (AINP–AINM), (BINP–BINM), (AINP–AINM), …
0 0 1 1 0 Reserved
0 0 1 1 1 Reserved
1 0 0 0 0 Reserved
1 0 1 0 0 Reserved
1 0 1 1 1 Reserved
1 1 0 0 0 Reserved
1 1 0 1 0 Reserved
1 1 0 1 1 Reserved
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Reserved
1 1 1 1 1 Reserved
Test Mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 10.
Table 10. Test Mode
BIT 9
TEST1 BIT 8
TEST0 OUTPUT RESULT
0 0 Normal mode
0 1 VREFP
1 0 ((VREFM)+(VREFP))/2
1 1 VREFM
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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21
Control Register 1 (see Table 7)
BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 1 RBACK OFFSET BIN/2s R/W RESERVED RESERVED RESERVED RESERVED SRST RESET
Table 11. Control Register 1 Bit Functions
BITS RESET
VALUE NAME FUNCTION
0 0 RESET Reset
W riting a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
To bring the device out of reset, a 0 has to be written into this bit.
1 0 SRST Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the
configuration cycle.
2, 3 0,0 RESERVED Always write 0
4 1 RESERVED Always write 0
5 1 RESERVED Always write 0
6 0 R/W R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to
1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with
R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR
becomes a write input.
7 0 BIN/2s Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5.
8 0 OFFSET Offset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-
sion. The conversion result is stored in an offset register and subtracted from all conversions in order to
reduce the of fset error.
9 0 RBACK Debug mode
Bit 9 = 0 → normal conversion mode
Bit 9 = 1 → enable debug mode
When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0
and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0.
The second read after bit 9 is set to 1 contains the value of control register 1. To bring the device back into normal
conversion mode, this bit has to be set back to 0 by writing again to control register 1.
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22
TIMING AND SIGNAL DESCRIPTION OF THE THS1207
The reading from the THS1207 and writing to the THS1207 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS1207 takes place by an internal RDint signal, which is generated from the logical
combination o f the external signals CS0, CS1 and RD (see Figure 6). This signal is then used to strobe out the
words and to enable the output buffers. The last external signal (either CS0, CS1 or RD ) to become valid makes
RDint active while the write input (WR) is inactive. The first of those external signals switching to an inactive
state deactivates RDint again.
Writing t o the THS1207 takes place by an internal WRint signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and
1. The last external signal (either CS0, CS1 or WR) to become valid switches WRint active while the read input
(RD) is inactive. The first of those external signals going to its inactive state deactivates WRint again.
Read Enable
W rite Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 31. Logical Combination of CS0, CS1, RD, and WR
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23
Read Timing (using RD, RD-controlled)
Figure 32 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input
RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external
signal of CS0, CS1, and RD which becomes valid.
ÓÓÓÓ
ÓÓÓÓ
ÔÔÔ
ÔÔÔ
90%90%
90%
10%
tw(RD)
tsu(CS) th(CS)
tath
td(CSDAV)
CS0
CS1
WR
RD
D(0–9)
DATA_AV
10%
Figure 32. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD-controlled)
PARAMETER MIN TYP MAX UNIT
tsu(CS) Setup time, RD low to last CS valid 0 ns
taAccess time, last CS valid to data valid 0 10 ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive 12 ns
thHold time, first CS invalid to data invalid 0 5 ns
th(CS) Hold time, RD change to first CS invalid 5 ns
tw(RD)Pulse duration, RD active 10 ns
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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24
Write Timing (using WR, WR-controlled)
Figure 33 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The
input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last
external signal of CS0, CS1, and WR which becomes valid.
90%90%
10%
tsu th
D(0–9)
DATA_AV
10%
ÓÓÓÓÓ
ÓÓÓÓÓ
ÔÔÔÔ
ÔÔÔÔ
tw(WR)
tsu(CS) th(CS)
CS0
CS1
WR
RD
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
Figure 33. Write Timing Diagram Using WR (WR-controlled)
Write Timing Parameter Using WR (WR-controlled)
PARAMETER MIN TYP MAX UNIT
tsu(CS) Setup time, CS stable to last WR valid 0 ns
tsu Setup time, data valid to first WR invalid 5 ns
thHold time, WR invalid to data invalid 2 ns
th(CS) Hold time, WR invalid to CS change 5 ns
tw(WR)Pulse duration, WR active 10 ns
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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25
Read Timing (using R/W, CS0-controlled)
Figure 34 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data
must be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 34.
tsu(CONV_CLKL–CS0L)
tsu(CS0H–CONV_CLKL)
tath
10% 10%
90%
90%
90% 90%
90%
10% 10%
ÓÓÓ
ÓÓÓ
ÔÔÔ
ÔÔÔ
CONV_CLK
CS0
CS1
R/W
RD
D(O–11)
tw(CS)
tsu(R/W)th(R/W)
Figure 34. Read Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)
PARAMETER MIN TYP MAX UNIT
tsu(CONV_CLKL-CSOL) Setup time, CONV_CLK low before CS valid 10 ns
tsu(CSOH-CONV_CLKL) Setup time, CS invalid to CONV_CLK low 20 ns
tsu(R/W)Setup time, R/W high to last CS valid 0 ns
taAccess time, last CS valid to data valid 0 10 ns
thHold time, first CS invalid to data invalid 0 5 ns
th(R/W)Hold time, first external CS invalid to R/W change 5 ns
tw(CS) Pulse duration, CS active 10 ns
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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26
Write Timing Diagram (using R/W, CS0-controlled)
Figure 35 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because C S 0 is the last external signal of CS0, CS1, and R/W which becomes valid. The writing to the THS1207
can be performed irrespective of the conversion clock signal CONV_CLK.
ÓÓÓ
ÓÓÓ
ÔÔÔ
ÔÔÔ
90%
90% 90%
10%
tw(CS)
tsu(R/W)th(R/W)
CS0
CS1
R/W
RD
D(0–11)
10%
tsu th
10% 10%
Figure 35. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (CS0-controlled)
PARAMETER MIN TYP MAX UNIT
tsu(R/W)Setup time, R/W stable to last CS valid 0 ns
tsu Setup time, data valid to first CS invalid 5 ns
thHold time, first CS invalid to data invalid 2 ns
th(R/W)Hold time, first CS invalid to R/W change 5 ns
tw(CS) Pulse duration, CS active 10 ns
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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27
ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE
The THS1207 features four analog input channels. These can be configured for either single-ended or
differential operation. Figure 36 shows a simplified model, where a single-ended configuration for channel AINP
is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference
voltages). The analog input voltage range is between VREFM to VREFP. This means that VREFM defines the
minimum voltage, and VREFP defines the maximum voltage, which can be applied to the ADC. The internal
reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V (see also section
reference voltage). The resulting analog input voltage swing of 2 V can be expressed by:
VREFM vAINP vVREFP
12-Bit
ADC
VREFP
VREFM
AINP
Figure 36. Single-Ended Input Stage
A differential operation is desired in many applications due to a better signal-to-noise ration. Figure 37 shows
a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The
differential operation mode provides in terms of performance benefits over single-ended mode and is therefore
recommended for best performance. The THS1207 offers 2 differential analog inputs and in the single-ended
mode 4 analog inputs. If the analog input architecture is differential, common mode noise and common mode
voltages can be rejected. Additional details for both modes are given below.
12-Bit
ADC
VREFP
VREFM
AINP
ΣVADC
AINM
+
–
Figure 37. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the
input of the ADC is the difference between the input AINP and AINM. The voltage VADC can be calculated as
follows:
VADC +ABS(AINP–AINM)
The advantage to single-ended operation is that the common-mode voltage
VCM +AINM )AINP
2
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND vAINM, AINP vAVDD
1VvVCM v4V
(1)
(2)
(3)
(4)
(5)
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28
SINGLE-ENDED MODE OF OPERATION
The THS1207 can be configured for single-ended operation using dc or ac-coupling. In either case, the input
of the THS1207 must be driven from an operational amplifier that does not degrade the ADC performance.
Because the THS1207 operates from a single supply 5 V, it is necessary to level-shift ground-based bipolar
signals to comply with its input requirements. This can be achieved with dc and ac-coupling.
DC-COUPLING
An operational amplifier can be configured to shift the signal level according to the analog input voltage range
of the THS1207. The analog input voltage range of the THS1207 is between 1.5 V and 3.5 V. An operational
amplifier can be used as shown in Figure 38.
Figure 38 shows an example where the analog input signal in the range between –1 V up to 1 V. This signal
is shifted by an operational amplifier to the analog input range of the THS1207 (1.5 V to 3.5 V). The operational
amplifier is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the
noninverting input is derived from the 2.5-V output reference REFOUT of the THS1207 by using a resistor
divider. Therefore, the operational amplifier output voltage is centered at 2.5 V. The 10 µF tantalum capacitor
is required for bypassing REFOUT. REFIN of the THS1207 must be connected directly to REFOUT in
single-ended mode. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.
_
+
5 V
R1
R1RS
3.5 V
2.5 V
1.5 V THS1207
AINP
REFOUT
R2
R2
1.25 V
1 V
0 V
–1 V REFIN
+
C
10 µF
Figure 38. Level-Shift for DC-Coupled Input
DIFFERENTIAL MODE OF OPERATION
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion
to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best
performance is achieved in differential mode.
THS1207
AINP
AINM
REFOUT
C
C
R
R
200 Ω
49.9 Ω
Mini Circuits
T4–1
+
10 µF
Figure 39. Transformer Coupled Input
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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29
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference b e t ween first and last code transitions and the ideal difference between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number Of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N+(SINAD*1.76)
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS1207CDA ACTIVE TSSOP DA 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS1207CDAG4 ACTIVE TSSOP DA 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS1207IDA ACTIVE TSSOP DA 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS1207IDAG4 ACTIVE TSSOP DA 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
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