ADS823 ADS826 (R) ADS 826 ADS 823 For most current data sheet and other product information, visit www.burr-brown.com 10-Bit, 60MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM +3V/+5V LOGIC I/O COMPATIBLE (ADS826) POWER DOWN: 20mW 28-LEAD SSOP PACKAGE FEATURES HIGH SNR: 60dB HIGH SFDR: 74dBFS LOW POWER: 265mW INTERNAL/EXTERNAL REFERENCE OPTION SINGLE-ENDED OR DIFFERENTIAL ANALOG INPUT PROGRAMMABLE INPUT RANGE LOW DNL: 0.25LSB SINGLE +5V SUPPLY OPERATION APPLICATIONS DESCRIPTION The ADS823 and ADS826 employ digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Their low distortion and high SNR give the extra margin needed for medical imaging, communications, video, and test instrumentation. The ADS823 and ADS826 offer power dissipation of 265mW and also provide a power down mode, thus reducing power dissipation to only 20mW. The ADS823 and ADS826 are pipeline, CMOS analog-todigital converters that operate from a single +5V power supply. These converters provide excellent performance with a singleended input and can be operated with a differential input for added spurious performance. These high-performance converters include a 10-bit quantizer, high-bandwidth track-and-hold, and a high-accuracy internal reference. They also allow for disabling the internal reference and utilizing external references. This external reference option provides excellent gain and offset matching when used in multi-channel applications or in applications where full-scale range adjustment is required. ADS823 ADS826 IN IN T/H The ADS823 and ADS826 are specified at a maximum sampling frequency of 60MHz and a single-ended input range of 1.5V to 3.5V. The ADS823 and ADS826 are available in a 28-lead SSOP package and are pin-compatible with the 10-bit, 40MHz ADS822 and ADS825, and the 10-bit, 70MHz ADS824. CLK +VS VIN MEDICAL IMAGING COMMUNICATIONS CCD IMAGING VIDEO DIGITIZING TEST EQUIPMENT VDRV Timing Circuitry 10-Bit Pipelined A/D Core Error Correction Logic 3-State Outputs D0 * * * D9 Internal Reference CM Optional External Reference Int/Ext PD OE International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 Twx: 910-952-1111 * Internet: http://www.burr-brown.com/ * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (c) 1997 Burr-Brown Corporation PDS-1386E Printed in U.S.A. October, 1999 SPECIFICATIONS At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. ADS826E(1) ADS823E MIN RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Standard Single-Ended Input Range Optional Single-Ended Input Range Common-Mode Voltage Optional Differential Input Range Analog Input Bias Current Input Impedance Track-Mode Input Bandwidth Ambient Air 2Vp-p 1Vp-p 1.5 2 2Vp-p 2 DIGITAL INPUTS Logic Family Convert Command High Level Input Current(6) (VIN = 5V) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance MAX MIN MAX UNITS 10 Guaranteed Bits -40 to +85 -40 to +85 C 3.5 3 3 10k 60M 1.0 Guaranteed 2.0 V V V V A M || pF MHz Samples/s Clk Cyc LSB LSB LSBs 5 0.25 0.25 Guaranteed 0.5 1 1.25 || 5 300 -3dBFS Input TYP 10 Guaranteed 2.5 CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes Integral Nonlinearity Error, f = 1MHz Spurious Free Dynamic Range(2) f = 1MHz f = 10MHz Two-Tone Intermodulation Distortion(4) f = 9.5MHz and 9.9MHz (-7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz f = 10MHz Signal-to-(Noise + Distortion) (SINAD) f = 1MHz f = 10MHz Effective Number of Bits(5), f = 1MHz Output Noise Aperture Delay Time Aperture Jitter Overvoltage Recovery Time(5) Full-Scale Step Acquisition Time TYP 73 73 dBFS(3) dBFS dBc 59 59 dB dB 58 58 dB dB Bits LSBs rms ns ps rms ns ns CMOS-Compatible Rising Edge of Convert Clock +100 +10 +3.5 +1.0 5 TTL, +3V/+5V CMOS-Compatible Rising Edge of Convert Clock +2.0 +0.8 A A V V pF CMOS Straight Offset Binary +0.1 +4.9 +0.1 +2.8 2 40 2 10 5 CMOS Straight Offset Binary V V V V ns ns pF 1.0 16 3.0 1.5 66 1.0 23 70 10 10 3.5 1.5 1.6 2.5 0.29 % FS ppm/C % FS % FS ppm/C % FS ppm/C dB mV mV V V k 67 74 74 65 64 Referred to Full-Scale Sinewave 57 60 60 56 Referred to Full-Scale Sinewave 56 Input Grounded Start Conversion DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50A to 1.6mA) High Output Voltage, (IOH = 50A to 0.5mA) Low Output Voltage, (IOL = 50A to 1.6mA) High Output Voltage, (IOH = 50A to 0.5mA) 3-State Enable Time 3-State Disable Time Output Capacitance VDRV = 5V VDRV = 3V OE = H to L OE = L to H ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (referred to -FS) At 25C Zero Error Drift (referred to -FS) Midscale Offset Error At 25C Gain Error(7) At 25C Gain Error Drift(7) Gain Error(8) At 25C Gain Error Drift(8) Power Supply Rejection of Gain VS = 5% REFT Tolerance Deviation From Ideal 3.5V REFB Tolerance Deviation From Ideal 1.5V External REFT Voltage Range External REFB Voltage Range Reference Input Resistance REFT to REFB 50 REFB + 0.8 1.25 (R) ADS823, ADS826 2 59 59 9.5 0.2 3 1.2 2 5 55 1.5 25 25 VS - 1.25 REFT - 0.8 SPECIFICATIONS (Cont.) At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. ADS826E(1) ADS823E PARAMETER POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Power Down Thermal Resistance, JA 28-Lead SSOP CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Operating Operating External Reference External Reference Internal Reference Internal Reference Operating +4.75 +5.0 55 275 265 295 285 20 +5.25 V mA mW mW mW mW mW 335 350 89 C/W Indicates the same specifications as the ADS823E. NOTES: (1) ADS826 accepts a +3V clock input. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to Full Scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD - 1.76)/6.02. (6) A 50k pull-down resistor is inserted internally on OE pin. (7) Includes internal reference. (8) Excludes internal reference. PIN DESCRIPTIONS PIN CONFIGURATION Top View SSOP GND 1 28 VDRV Bit 1 (MSB) 2 27 +VS Bit 2 3 26 GND Bit 3 4 25 IN Bit 4 5 24 IN Bit 5 6 23 CM Bit 6 7 22 REFT Bit 7 8 21 ByT Bit 8 9 20 ByB Bit 9 10 19 REFB Bit 10 (LSB) 11 18 INT/EXT OE 12 17 RSEL PD 13 16 GND CLK 14 15 +VS ADS823 ADS826 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 GND Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 OE 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PD CLK +VS GND RSEL INT/EXT REFB ByB ByT REFT CM IN IN GND +VS VDRV DESCRIPTION Ground Data Bit 1 (D9) (MSB) Data Bit 2 (D8) Data Bit 3 (D7) Data Bit 4 (D6) Data Bit 5 (D5) Data Bit 6 (D4) Data Bit 7 (D3) Data Bit 8 (D2) Data Bit 9 (D1) Data Bit 10 (D0) (LSB) Output Enable. HI: High Impedance State. LO: Normal Operation (Internal Pull-down Resistor) Power Down: HI = Power Down; LO = Normal Convert Clock Input +5V Supply Ground Input Range Select: HI = 2V; LO = 1V Reference Select: HI = External; LO = Internal Bottom Reference Bottom Ladder Bypass Top Ladder Bypass Top Reference Common-Mode Voltage Output Complementary Input (-) Analog Input (+) Ground +5V Supply Output Logic Driver Supply Voltage The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) 3 ADS823, ADS826 TIMING DIAGRAM N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+7 N+6 tH Clock 5 Clock Cycles t2 Data Out N-5 N-4 N-3 N-2 N-1 N Data Invalid SYMBOL tCONV tL tH tD t1 t2 N+1 N+2 t1 DESCRIPTION MIN Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 16.6 7.9 7.9 TYP MAX UNITS 100s ns ns ns ns ns ns 8.3 8.3 3 3.9 12 PACKAGE /ORDERING INFORMATION PRODUCT ADS823E " ADS826E " PACKAGE PACKAGE DRAWING NUMBER SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER (1) TRANSPORT MEDIA SSOP-28 " SSOP-28 " 324 " 324 " -40C to +85C " -40C to +85C " ADS823E " ADS826E " ADS823E ADS823E/1K ADS826E ADS826E/1K Rails Tape and Reel Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of ADS823E/1K" will get a single 1000-piece Tape and Reel. ELECTROSTATIC DISCHARGE SENSITIVITY DEMO BOARD ORDERING INFORMATION PRODUCT DEMO BOARD ADS823E DEM-ADS823E This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ............................................................. -0.3V to (+VS + 0.3V) Logic Input ............................................................... -0.3V to (+VS + 0.3V) Case Temperature ......................................................................... +100C Junction Temperature .................................................................... +150C Storage Temperature ..................................................................... +150C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. (R) ADS823, ADS826 4 TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 1MHz SNR = 60dBFS SFDR = 77dBFS -20 Magnitude (dB) Magnitude (dB) -20 -40 -60 -40 -60 -80 -80 -100 -100 0 7.5 15 22.5 0 30 7.5 22.5 Frequency (MHz) SPECTRAL PERFORMANCE (Single-Ended, 1Vp-p) SPECTRAL PERFORMANCE (Differential Input, 2Vp-p) 30 0 fIN = 10MHz SNR = 56.6dBFS SFDR = 74dBFS fIN = 10MHz SNR = 60dBFS SFDR = 73dBFS -20 Magnitude (dB) -20 -40 -60 -40 -60 -80 -80 -100 -100 0 7.5 15 22.5 0 30 7.5 15 22.5 30 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE (Differential Input, 2Vp-p) SPECTRAL PERFORMANCE 0 0 fIN = 20MHz SNR = 60.4dBFS SFDR = 72dBFS fIN = 20MHz SNR = 58.7dBFS SFDR = 70dBFS -20 Magnitude (dB) -20 Magnitude (dB) 15 Frequency (MHz) 0 Magnitude (dB) fIN = 10MHz SNR = 60dBFS SFDR = 76dBFS -40 -60 -80 -40 -60 -80 -100 -100 0 7.5 15 22.5 30 0 Frequency (MHz) 7.5 15 22.5 30 Frequency (MHz) (R) 5 ADS823, ADS826 TYPICAL PERFORMANCE CURVES (Cont.) At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. UNDERSAMPLING (Differential Input, 2Vp-p) TWO-TONE INTERMODULATION DISTORTION 0 0 fIN = 41MHz fS = 56MHz SNR = 59.8dBFS SFDR = 78dBFS -20 Magnitude (dB) Magnitude (dB) -20 f1 = 9.5MHz at -7dBFS f2 = 9.9MHz at -7dBFS IMD(3) = -64.4dBc -40 -60 -40 -60 -80 -80 -100 -100 0 7 14 21 28 0 7.50 Frequency (MHz) 15 22.50 DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 1.0 1.0 fIN = 10MHz fIN = 20MHz 0.5 0.5 DLE (LSB) DLE (LSB) 30 Frequency (MHz) 0 -0.5 0 -0.5 -1.0 -1.0 0 256 512 768 1024 0 256 512 Output Code 768 1024 Output Code SWEPT POWER SFDR INTEGRAL LINEARITY ERROR 100 2.0 fIN = 1MHz fIN = 10MHz 80 SFDR (dB) ILE (LSB) 1.0 0 -1.0 dBFS 60 dBc 40 20 0 -2.0 0 256 512 768 -60 1024 (R) ADS823, ADS826 -50 -40 -30 -20 Input Amplitude (dBFS) Output Code 6 -10 0 TYPICAL PERFORMANCE CURVES (Cont.) At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. DYNAMIC PERFORMANCE vs INPUT FREQUENCY DYNAMIC PERFORMANCE vs TEMPERATURE 80 80 SFDR SFDR, SNR (dBFS) SFDR, SNR (dBFS) 75 70 SNR 60 SFDR (fIN = 10MHz) 70 SFDR (fIN = 20MHz) 65 SNR (fIN = 10MHz) 60 SNR (fIN = 20MHz) 50 55 0.1 1 10 -50 100 -25 0 25 50 75 Frequency (MHz) Temperature (C) SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 65 100 .40 60 DLE (LSB) SINAD (dBFS) fIN = 1MHz fIN = 10MHz fIN = 20MHz 55 .30 fIN = 20MHz fIN = 1MHz .20 fIN = 10MHz 50 -50 -25 0 25 50 75 .10 100 -50 -25 0 Temperature (C) 25 50 75 100 Temperature (C) OUTPUT NOISE HISTOGRAM (DC Input) POWER DISSIPATION vs TEMPERATURE 800k 290 VDRV = +5V Counts Power (mW) 600k 280 400k 270 200k 0 260 -50 -25 0 25 50 75 N-2 100 N-1 N N+1 N+2 Code Temperature (C) (R) 7 ADS823, ADS826 APPLICATION INFORMATION The selection for the optimum interface configuration will depend on the individual application requirements and system structure. For example, communications applications often process a band of frequencies that does not include DC, whereas in imaging applications, the previously restored DC level must be maintained correctly up to the A/D converter. Features on the ADS823 and ADS826 like the input range select (RSEL pin) or the option for an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the ADS823 and ADS826 should be configured such that the application objectives are met while observing the headroom requirements of the driving amplifier in order to yield the best overall performance. THEORY OF OPERATION The ADS823 and ADS826 are high-speed CMOS analog-todigital converters which employ a pipelined converter architecture consisting of 9 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 10-bit level. The output data becomes valid on the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of 5 clock cycles. The analog input of the ADS823 and the ADS826 is a differential track-and-hold, see Figure 1. The differential topology along with tightly matched capacitors produce a high level of AC-performance while sampling at very high rates. INPUT CONFIGURATIONS AC-Coupled, Single-Supply Interface Figure 2 shows the typical circuit for an AC-coupled analog input configuration of the ADS823 and ADS826 while all components are powered from a single +5V supply. The ADS823 and ADS826 allows its analog inputs to be driven either single-ended or differentially. The typical configuration for the ADS823 and the ADS826 is for the singleended mode in which the input track-and-hold performs a single-ended to differential conversion of the analog input signal. With the RSEL pin connected High, the full-scale input range is set to 2Vp-p. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3.5V and +1.5V, respectively. Two resistors ( 2x 1.62k) are used to create a common-mode voltage (VCM) of approximately +2.5V to bias the inputs of the driving amplifier A1. Using the OPA680 on a single +5V supply, its ideal common-mode point is at +2.5V, which coincides with the recommended common-mode input level for the ADS823 and ADS826, thus obviating the need of a coupling capacitor between the amplifier and the converter. Even though the OPA680 has an AC gain of +2, the DC gain is only +1 due to the blocking capacitor at resistor RG. Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level (+VS/2). The following application discussion focuses on the singleended configuration. Typically, its implementation is easier to achieve and the rated specifications for the ADS823 and ADS826 are characterized using the single-ended mode of operation. DRIVING THE ANALOG INPUT The ADS823 and ADS826 achieve excellent AC performance either in the single-ended or differential mode of operation. Op Amp Bias 1 VCM 1 CH 2 CI IN 1 2 The addition of a small series resistor (RS) between the output of the op amp and the input of the ADS823 and ADS826 will be beneficial in almost all interface configurations. This will de-couple the op amp's output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100. Furthermore, the series resistor in combination with the 10pF capacitor establishes a passive low-pass filter limiting the bandwidth for the wideband noise, thus helping improve the SNR performance. OUT 1 OUT IN 1 AC-Coupled, Dual Supply Interface The circuit provided in Figure 3 shows typical connections for the analog input in case the selected amplifier operates on dual supplies. This might be necessary to take full advantage of very low distortion operational amplifiers, like the OPA642. The advantage is that the driving amplifier can be operated with a ground referenced bipolar signal swing. This will keep the distortion performance at its lowest since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. By capacitively coupling the single-ended signal to the input of the ADS823 and ADS826, their common-mode requirements can easily be satisfied with two resistors connected between the top and bottom reference. CI 2 CH 1 1 Input Clock (50%) Op Amp Bias VCM Internal Non-overlapping Clock 1 2 1 FIGURE 1. Simplified Circuit of Input Track and Hold with Timing Diagram. (R) ADS823, ADS826 8 1.62k +5V VCM +2.5V 1.62k +5V 0.1F 50 REFB +1.5V RS 50 VIN REFT +3.5V RSEL +VS IN OPA680 10pF +VIN 0V ADS823 ADS826 RF 402 -VIN CM IN RG 402 0.1F INT/EXT 0.1F GND FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived from the Internal Top (REFT) and Bottom Reference (REFB). +5V 1.62k +5V RS 24.9 VIN REFT +3.5V 0.1F RSEL +VS IN OPA642 100pF ADS823 ADS826 -5V RF 402 1.62k CM IN 0.1F RG 402 REFB +1.5V INT/EXT GND FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS823 and ADS826 for a 2Vp-p Full Scale Input Range. For applications requiring the driving amplifier to provide a signal amplification, with a gain 5, consider using decompensated voltage-feedback op amps, like the OPA643, or current-feedback op amps like the OPA681 and OPA658. ately biased using the +2.5V common-mode voltage available at the CM pin. One half of amplifier A1 buffers the REFB pin and drives the voltage divider R1, R2. Due to the op amp's noise gain of +2V/V, assuming RF = RIN, the common-mode voltage (VCM) has to be re-scaled to +1.25V. This results in the correct DC level of +2.5V for the signal input (IN). Any DC voltage differences between the IN and IN inputs of the ADS823 and ADS826 effectively produce an offset, which can be corrected for by adjusting the resistor values of the divider, R1 and R2. The selection criteria for a suitable op amp should include the supply voltage, input bias current, output voltage swing, distortion, and noise specification. Note that in this example the overall signal phase is inverted. To re-establish the original signal polarity, it is always possible to interchange the IN and IN connections. DC-Coupled with Level Shift Several applications may require that the bandwidth of the signal path includes DC, in which case the signal has to be DC-coupled to the A/D converter. In order to accomplish this, the interface circuit has to provide a DC level shift to the analog input signal. The circuit shown in Figure 4 employs a dual op amp, A1, to drive the input of the ADS823 and ADS826, and level shift the signal to be compatible with the selected input range. With the RSEL pin tied to the supply and the INT/EXT pin to ground, the ADS823 and ADS826 are configured for a 2Vp-p input range and uses the internal references. The complementary input (IN) may be appropri- (R) 9 ADS823, ADS826 +5V RF 499 RIN 499 VIN 1/2 OPA2681 +VS RSEL RS 50 IN 2Vp-p 10pF ADS823 ADS826 NOTE: RF = RIN, G = -1 CM (+2.5V) IN +5V 0.1F REFB (+1.5V) REFT (+3.5V) INT/EXT 50 R2 200 0.1F 1/2 OPA2681 VCM = +1.25V 0.1F R1 1k RF 1k FIGURE 4. DC-Coupled Interface Circuit with Level-Shifting, Dual Current-Feedback Amplifier OPA2681. SINGLE-ENDED TO DIFFERENTIAL CONFIGURATION (Transformer Coupled) If the application requires a signal conversion from a singleended source to feed the ADS823 and ADS826 differentially, a RF transformer might be a good solution. The selected transformer must have a center tap in order to apply the common-mode DC voltage necessary to bias the converter inputs. AC grounding the center tap will generate the differential signal swing across the secondary winding. Consider a step-up transformer to take advantage of a signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to an improved distortion performance. circuit. The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. The resistor across the secondary side (RT) should be calculated using the equation RT = n2 * RG to match the source impedance (RG) for good power transfer and VSWR. REFERENCE OPERATION Figure 6 depicts the simplified model of the internal reference circuit. The internal blocks are the bandgap voltage reference, the drivers for the top and bottom reference, and RSEL The differential input configuration may provide a noticeable advantage of achieving good SFDR performance over a wide range of input frequencies. In this mode, both inputs of the ADS823 and ADS826 see matched impedances, and the differential signal swing can be reduced to half of the swing required for single-ended drive. Figure 5 shows the schematic for the suggested transformer-coupled interface ADS823 ADS826 50k +VS INT/EXT 50k Bandgap Reference and Logic VREF +1 RG 0.1F 1:n +1 22 VIN IN 47pF 400 ADS823 ADS826 RT 22 IN REFT CM 400 ByT 400 CM 400 ByB REFB RSEL INT/EXT 47pF +5V + 10F 0.1F Bypass Capacitors: 0.1F || 2.2F each FIGURE 6. Equivalent Reference Circuit with Recommended Reference Bypassing. FIGURE 5. Transformer Coupled Input. (R) ADS823, ADS826 10 The common-mode voltage available at the CM pin may be used as a bias voltage to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this node, which is not buffered and has a high impedance. An alternative way of generating a common-mode voltage is given in Figure 7. Here, two external precision resistors (tolerance 1% or better) are located between the top and bottom reference pins. The commonmode voltage, VCM, will appear at the midpoint. the resistive reference ladder. The bandgap reference circuit includes logic functions that allow to set the analog input swing of the ADS823 and ADS826 to either a 1Vp-p or 2Vp-p full-scale range simply by tying the RSEL pin to a Low or High potential, respectively. While operating the ADS823 and ADS826 in the external reference mode, the buffer amplifiers for the REFT and REFB are disconnected from the reference ladder. As shown, the ADS823 and ADS826 have internal 50k pull-up resistors at the range select pin (RSEL) and reference select pin (INT/EXT). Leaving those pins open configures the ADS823 for a 2Vp-p input range and external reference operation. Setting the ADS823 up for internal reference mode requires bringing the INT/EXT pin Low. EXTERNAL REFERENCE OPERATION For even more design flexibility, the internal reference can be disabled and an external reference voltage be used. The utilization of an external reference may be considered for applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the converter's full-scale range. Especially in multichannel applications, the use of a common external reference has the benefit of obtaining better matching of the full-scale range between converters. The reference buffers can be utilized to supply up to 1mA (sink and source) to external circuitry. The resistor ladders of the ADS823 and ADS826 are divided into several segments and have two additional nodes, ByT and ByB, which are brought out for external bypassing only (Figure 6). To ensure proper operation with any reference configurations, it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum. All bypassing capacitors should be located as close to their respective pins as possible. ADS823 ADS826 REFT +3.5V R1 1.6k 0.1F The external references can vary as long as the value of the external top reference REFTEXT stays within the range of (VS - 1.25V) and (REFB + 0.8V), and the external bottom reference REFBEXT stays within 1.25V and (REFT - 0.8V), see Figure 8. DIGITAL INPUTS AND OUTPUTS Clock Input Requirements Clock jitter is critical to the SNR performance of high-speed, high-resolution A/D converters. Clock jitter leads to aperture jitter (tA), which adds noise to the signal being converted. The ADS823 and ADS826 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total REFB +1.5V R2 1.6k 0.1F VCM +2.5V FIGURE 7. Alternative Circuit to Generate CM Voltage. +5V B A - Short for 1Vp-p Input Range B - Short for 2Vp-p Input Range (Default) +VS VIN A RSEL INT/EXT GND IN ADS823 ADS826 VCM +2.5VDC IN REFT External Top Reference REFT = REFB +0.8V to +3.75V ByT GND 4 x 0.1F || 2.2F ByB REFB External Bottom Reference REFB = REFT -0.8V to +1.25V FIGURE 8. Configuration Example for External Reference Operation. 11 (R) ADS823, ADS826 It is recommended to keep the capacitive loading on the data lines as low as possible ( 15pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS823 and ADS826 and affect performance. If necessary, external buffers or latches close to the converter's output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS823 and ADS826 from any digital noise activities on the bus coupling back high frequency noise. SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. Jitter SNR = 20 log 1 rms signal to rms noise 2 IN t A where: IN is input signal frequency tA is rms clock jitter Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. To estimate the typical performance deviation for clock duty cycles in the range of 50% 7.5%, refer to Figure 9. The clock input of the ADS826 can be driven with either 3V or 5V logic levels. Using low-voltage logic (3V) may lead to improved AC performance of the converters. Digital Output Driver (VDRV) The ADS823 and ADS826 feature a dedicated supply pin for the output logic drivers, VDRV, which is not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V, the ADS823 and ADS826 produce corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS823 and ADS826 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the ACperformance of the converter. In some applications, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. 80 SFDR 75 SINGLE-ENDED INPUT (IN = CMV) (dBFS) 70 +FS -1LSB (IN = REFT) +1/2 Full Scale Bipolar Zero (IN = VCM) -1/2 Full Scale -FS (IN = REFB) 65 SNR 60 50 55 52.5 50 47.5 45 42.5 Clock Duty Cycle (tH/tL x 100%) DIFFERENTIAL INPUT FIGURE 9. ADS823 and ADS826 Duty Cycle Sensitivity. +FS -1LSB (IN = +3V, IN = +2V) +1/2 Full Scale Bipolar Zero (IN = IN = VCM) -1/2 Full Scale -FS (IN = +2V, IN = +3V) Digital Outputs The output data format of the ADS823 and ADS826 is in positive Straight Offset Binary code (see Tables I and II). This format can easily be converted into the Two's Binary Complement code by inverting the MSB. STRAIGHT OFFSET BINARY (SOB) 1111111111 1100000000 1000000000 0100000000 0000000000 TABLE II. Coding Table for Differential Input Configuration and 2Vp-p Full-Scale Range. (R) ADS823, ADS826 1111111111 1100000000 1000000000 0100000000 0000000000 TABLE I. Coding Table for Single-Ended Input Configuration with IN tied to the Common-Mode Voltage (VCM). 55 57.5 STRAIGHT OFFSET BINARY (SOB) 12 bypassed. Figure 10 shows the recommended decoupling scheme for the ADS823 and ADS826. In most cases 0.1F ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. In addition, a larger bipolar capacitor (1F to 22F) should be placed on the PC board in proximity of the converter circuit. GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS823 and ADS826 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable performance. All ground connections on the ADS823 and ADS826 are internally joined together, obviating the design of split ground planes. The ground pins (1, 16, 26) should directly connect to an analog ground plane which covers the PC board area around the converter. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. Due to the high sampling rate, the ADS823 and ADS826 generate high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. This requires that all supply and reference pins are sufficiently ADS823 ADS826 +VS 27 GND 26 +VS 15 0.1F VDRV 28 GND 16 0.1F 0.1F 10F + +5V +3/+5V FIGURE 10. Recommended Bypassing for the Supply Pins. (R) 13 ADS823, ADS826