1
FEATURES
D OR PW PACKAGE...TS12A44513
(TOP VIEW)
1 14
213
312
411
510
69
NO1
COM1
NC2
COM2
IN2
IN3
GND 78
V+
IN1
IN4
NC4
COM4
COM3
NO3
D OR PW PACKAGE...TS12A44514
(TOP VIEW)
1 14
213
312
411
510
69
NO1
COM1
NO2
COM2
IN2
IN3
GND 78
V+
IN1
IN4
NO4
COM4
COM3
NO3
D OR PW PACKAGE...TS12A44515
(TOP VIEW)
1 14
213
312
411
510
69
NC1
COM1
NC2
COM2
IN2
IN3
GND 78
V+
IN1
IN4
NC4
COM4
COM3
NC3
DESCRIPTION/ORDERING INFORMATION
TS12A44513 , , TS12A44514 , , TS12A44515
www.ti.com
............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
LOW ON-STATE RESISTANCEQUAD SPST CMOS ANALOG SWITCHES
•2-V to 12-V Single-Supply Operation •Specified Low OFF-Leakage Currents:•Specified ON-State Resistance: – 1 nA at 25 ° C– 15 ΩMax With 12-V Supply – 10 nA at 85 ° C– 20 ΩMax With 5-V Supply •Specified Low ON-Leakage Currents:– 50 ΩMax With 3.3-V Supply – 1 nA at 25 ° C•R
DSON
Matching – 10 nA at 85 ° C– 2.5 Ω(Max) at 12 V •Low Charge Injection: 11.5 pC (12-V Supply)– 3 Ω(Max) at 5 V •Fast Switching Speed:t
ON
= 80 ns, t
OFF
= 50 ns (12-V Supply)– 3.5 Ω(Max) at 3.3 V
•Break-Before-Make Operation (t
ON
> t
OFF
)•TTL/CMOS-Logic Compatible With 5-V Supply•Available in TSSOP-14 Package, SOIC-14
The TS12A44513/TS12A44514/TS12A44515 are quad single pole/single throw (SPST), low-voltage / wide range,single-supply CMOS analog switches, with very low switch ON-state resistance. The TS12A44513 has twoswitches normally closed (NC) and two switches normally open (NO), the TS12A44514 switches are normallyopen (NO), the TS12A44515 switches are normally closed (NC).
These CMOS switches can operate continuously with a single supply between 2 V and 12 V. Each switch canhandle rail-to-rail analog signals. The OFF-leakage current maximum is only 1 nA at 25 ° C or 10 nA at 85 ° C.
All digital inputs have 0.8-V to 2.4-V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a 5-Vsupply.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MINIMUM AND MAXIMUM RATINGS
(1) (2)
THERMAL IMPEDANCE
TS12A44513 , , TS12A44514 , , TS12A44515
SCDS247 – OCTOBER 2008 .............................................................................................................................................................................................
www.ti.com
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Reel of 2500 TS12A44513DR TS12A44513SOIC – D Reel of 2500 TS12A44514DR TS12A44514Reel of 2500 TS12A44515DR TS12A44515– 40 ° C to 85 ° C
Reel of 2000 TS12A44513PWR YD4513TSSOP – PW Reel of 2000 TS12A44514PWR YD4514Reel of 2000 TS12A44515PWR YD4515
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
voltages referenced to GND
MIN MAX UNIT
V
+
Supply voltage range – 0.3 13 VV
NC
V
NO
Analog voltage range
(3)
– 0.3 V
+
+ 0.3 VV
COM
I
NC
I
NO
Analog Current range -20 20 mAI
COM
Continuous current into any terminal ± 20 mAPeak current, NO or COM (pulsed at 1 ms, 10% duty cycle) ± 30 mAESD per method 3015.7 2000 VT
A
Operating temperature range – 40 85 ° CD package 1.15Mounted on JEDEC 4-layer board (JESDP
D
Power dissipation W51-7), No airflow, T
A
= 25 ° C, T
J
= 125 ° C
PW package 0.88T
stg
Storage temperature range – 65 150 ° CLead temperature (soldering, 10 s) 300 ° C
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum(3) Voltages exceeding V
+
or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum currentrating.
UNIT
D package 133Mounted on JEDEC 1-layer board (JESD 51-3),No airflow
PW package 167Thermal impedance,θ
JA
° C/Wjunction to free air
D package 86Mounted on JEDEC 4-layer board (JESD 51-7),No airflow
PW package 112
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ELECTRICAL CHARACTERISTICS FOR 5-V SUPPLY
(1)
TS12A44513 , , TS12A44514 , , TS12A44515
www.ti.com
............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
V
+
= 4.5 V to 5.5 V, V
INH
= 2.4 V, V
INL
= 0.8 V, T
A
= – 40 ° C to 85 ° C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS T
A
MIN TYP
(2)
MAX UNIT
Analog Switch
Analog signal range V
COM
, V
NO
, V
NC
0 V
+
V25 ° C 12 20V
+
= 4.5 V, V
COM
= 3.5 V,ON-state resistance r
on
ΩI
COM
= 1 mA
Full 3025 ° C 1 3ON-state resistance V
COM
= 1 V, 2 V, 3 V,r
on(flat)
Ωflatness I
COM
= 1 mA
Full 4ON-state resistance 25 ° C 3V
+
= 4.5 V, I
COM
= 5 mA,matching between Δr
on
ΩV
NO
or V
NC
= 3 V
T
MIN
to T
MAX
4channels
(3)
25 ° C 1NO, NC I
NO(OFF),
V
+
= 5.5 V, V
COM
= 1 V,
nAOFF leakage current
(4)
I
NC(OFF)
V
NO
or V
NC
= 4.5 V
Full 1025 ° C 1COM V
+
= 5.5 V, V
COM
= 1 V,I
COM(OFF)
nAOFF leakage current
(4)
V
NO
or V
NC
= 4.5 V
Full 1025 ° C 1COM V
+
= 5.5 V, V
COM
= 4.5 V,I
COM(ON)
nAON leakage current
(4)
V
NO
or V
NC
= 4.5 V
Full 10
Digital Control Input (IN)
Input logic high V
IH
Full 2.4 V
+
VInput logic low V
IL
Full 0 0.8 VInput leakage current I
IH
, I
IL
V
IN
= V
+
, 0 V Full 0.01 µA
Dynamic
25 ° C 45 100Turn-on time t
ON
see Figure 6 nsFull 12525 ° C 35 50Turn-off time t
OFF
see Figure 6 nsFull 70C
L
= 1 nF, V
NO
= 0 V,Charge injection
(5)
Q
C
25 ° C – 1.5 pCR
S
= 0 Ω, See Figure 5NO, NC C
NO(OFF)
,
f = 1 MHz, See Figure 8 25 ° C 8 pFOFF capacitance C
NC(OFF)
COM
C
COM(OFF)
f = 1 MHz, See Figure 8 25 ° C 8 pFOFF capacitance
COM
C
COM(ON)
f = 1 MHz, See Figure 8 25 ° C 19 pFON capacitance
Digital input capacitance C
I
V
IN
= V
+
, 0 V 25 ° C 2 pFR
L
= 50 Ω, C
L
= 15 pF,Bandwidth BW 25 ° C 530 MHzV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,OFF isolation O
ISO
25 ° C – 94 dBV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,Total harmonic distortion THD 25 ° C 0.09 %V
NO
= 1 V
RMS
, f = 100 kHz
Supply
25 ° C 0.05V
+
supply current I
+
V
IN
= 0 V or V
+
µAFull 0.1
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.(2) Typical values are at T
A
= 25 ° C.(3) Δr
ON
= r
ON(MAX)
– r
ON(MIN)(4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25 ° C.(5) Specified by design, not production tested
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ELECTRICAL CHARACTERISTICS FOR 12-V SUPPLY
(1)
TS12A44513 , , TS12A44514 , , TS12A44515
SCDS247 – OCTOBER 2008 .............................................................................................................................................................................................
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V
+
= 11.4 V to 12.6 V, V
INH
= 5 V, V
INL
= 0.8 V, T
A
= – 40 ° C to 85 ° C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS T
A
MIN TYP
(2)
MAX UNIT
Analog Switch
Analog signal range V
COM
, V
NO
, V
NC
0 V
+
V25 ° C 6.5 10V
+
= 11.4 V, V
COM
= 10 V,ON-state resistance r
on
ΩI
COM
= 1 mA
Full 15V
+
= 11.4 V, 25 ° C 1.5 3ON-state resistance
r
on(flat)
V
COM
= 2 V, 5 V, 10 V, Ωflatness
Full 4I
COM
= 1 mAON-state resistance 25 ° C 2.5V
+
= 11.4 V, I
COM
= 5 mA,matching between Δr
on
ΩV
NO
or V
NC
= 10 V
T
MIN
to T
MAX
3channels
(3)
25 ° C 1NO, NC I
NO(OFF),
V
+
= 12.6 V, V
COM
= 1 V,
nAOFF leakage current
(4)
I
NC(OFF)
V
NO
or V
NC
= 10 V
Full 1025 ° C 1COM V
+
= 12.6 V, V
COM
= 1 V,I
COM(OFF)
nAOFF leakage current
(4)
V
NO
or V
NC
= 10 V
Full 1025 ° C 1COM V
+
= 12.6 V, V
COM
= 10 V,I
COM(ON)
nAON leakage current
(4)
V
NO
or V
NC
= 10 V
Full 10
Digital Control Input (IN)
Input logic high V
IH
Full 5 V
+
VInput logic low V
IL
Full 0 0.8 VInput leakage current I
IH
, I
IL
V
IN
= V
+
, 0 V Full 0.001 µA
Dynamic
25 ° C 25 75Turn-on time t
ON
See Figure 6 nsFull 8025 ° C 20 45Turn-off time t
OFF
See Figure 6 nsFull 50C
L
= 1 nF, V
NO
= 0 V,Charge injection
(5)
Q
C
25 ° C – 10.5 pCR
S
= 0 Ω, See Figure 5NO, NC C
NO(OFF)
,
f = 1 MHz, See Figure 8 25 ° C 8 pFOFF capacitance C
NC(OFF)
COM
C
COM(OFF)
f = 1 MHz, See Figure 8 25 ° C 8 pFOFF capacitance
COM
C
COM(ON)
f = 1 MHz, See Figure 8 25 ° C 21.5 pFON capacitance
Digital input capacitance C
I
V
IN
= V
+
, 0 V 25 ° C 2 pFR
L
= 50 Ω, C
L
= 15 pF,Bandwidth BW 25 ° C 530 MHzV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,OFF isolation O
ISO
25 ° C – 95 dBV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,Total harmonic distortion THD 25 ° C 0.07 %V
NO
= 1 V
RMS
, f = 100 kHz
Supply
25 ° C 0.05V
+
supply current I
+
V
IN
= 0 V or V
+
µAFull 0.2
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.(2) Typical values are at T
A
= 25 ° C.(3) Δr
ON
= r
ON(MAX)
– r
ON(MIN)(4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25 ° C.(5) Specified by design, not production tested
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ELECTRICAL CHARACTERISTICS FOR 3-V SUPPLY
(1)
TS12A44513 , , TS12A44514 , , TS12A44515
www.ti.com
............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
V
+
= 3 V to 3.6 V, T
A
= – 40 ° C to 85 ° C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS T
A
MIN TYP
(2)
MAX UNIT
Analog Switch
Analog signal range V
COM
, V
NO
, V
NC
0 V
+
V25 ° C 20 40V
+
= 3 V, V
COM
= 1.5 V,ON-state resistance r
on
ΩI
NO
= 1 mA,
Full 50V
+
= 3 V, 25 ° C 1 3ON-state resistance
r
on(flat)
V
COM
= 1 V, 1.5 V, 2 V, Ωflatness
Full 4I
COM
= 1 mAON-state resistance 25 ° C 3.5V
+
= 2.7 V, I
COM
= 5 mA,matching between Δr
on
ΩV
NO
or V
NC
= 1.5 V
T
MIN
to T
MAX
4.5channels
(3)
25 ° C 1NO, NC I
NO(OFF),
V
+
= 3.6 V, V
COM
= 1 V,
nAOFF leakage current
(4)
I
NC(OFF)
V
NO
or V
NC
= 3 V
Full 1025 ° C 1COM V
+
= 3.6 V, V
COM
= 1 V,I
COM(OFF)
nAOFF leakage current
(4)
V
NO
or V
NC
= 3 V
Full 1025 ° C 1COM V
+
= 3.6 V, V
COM
= 3 V,I
COM(ON)
nAON leakage current
(4)
V
NO
or V
NC
= 3 V
Full 10
Digital Control Input (IN)
Input logic high V
IH
Full 2.4 V
+
VInput logic low V
IL
Full 0 0.8 VInput leakage current I
IH
, I
IL
V
IN
= V
+
, 0 V Full 0.01 µA
Dynamic
25 ° C 70 120Turn-on time
(5)
t
ON
See Figure 6 nsFull 17525 ° C 50 80Turn-off time
(5)
t
OFF
See Figure 6 nsFull 120Charge injection
(5)
Q
C
C
L
= 1 nF, See Figure 5 25 ° C – 0.5 pCNO, NC C
NO(OFF)
,
f = 1 MHz, See Figure 8 25 ° C 8 pFOFF capacitance C
NC(OFF)
COM
C
COM(OFF)
f = 1 MHz, See Figure 8 25 ° C 8 pFOFF capacitance
COM
C
COM(ON)
f = 1 MHz, See Figure 8 25 ° C 17 pFON capacitance
Digital input capacitance C
I
V
IN
= V
+
, 0 V 25 ° C 2 pFR
L
= 50 Ω, C
L
= 15 pF,Bandwidth BW 25 ° C 510 MHzV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,OFF isolation O
ISO
25 ° C – 94 dBV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,Total harmonic distortion THD 25 ° C 0.27 %V
NO
= 1 V
RMS
, f = 100 kHz
Supply
25 ° C 0.03V
+
supply current I
+
V
IN
= 0 V or V
+
µAFull 0.05
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.(2) Typical values are at T
A
= 25 ° C.(3) Δr
ON
= r
ON(MAX)
– r
ON(MIN)(4) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25 ° C.(5) Specified by design, not production tested
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TYPICAL PERFORMANCE
0
5
10
15
20
25
0 1 2 3 4 5 6 7 8 9 10 11 12
Analog Signal, V (V)
COM
ON-State Resistance, r ( )
ON Ω
V = 3 V
+
V = 4.5 V
+
V = 11.4 V
+
0
5
10
15
20
25
30
01234
Analog Signal, V (V)
COM
ON-State Resistance, r ( )
ON Ω
T = 25°C
A
T = 85°C
A
T = –40°C
A
0
5
10
15
20
25
0 1 2 3 4 5 6 7 8 9 10 11 12
Analog Signal, V (V)
COM
ON-State Resistance, r ( )
ON Ω
T = 25°C
A
T = 85°C
A
T = –40°C
A
0
5
10
15
20
25
0 1 2 3 4 5
Analog Signal, V (V)
COM
ON-State Resistance, r ( )
ON Ω
VDD = 5.5 V
T = –40°C
A
T = 25°C
A
T = 85°C
A
TS12A44513 , , TS12A44514 , , TS12A44515
SCDS247 – OCTOBER 2008 .............................................................................................................................................................................................
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Figure 1. r
ON
vs V
COM
(T
A
= 25 ° C) Figure 2. r
ON
vs V
COM
(V
+
= 3 V)
Figure 3. r
ON
vs V
COM
(V
+
= 4.5 V) Figure 4. r
ON
vs V
COM
(V
+
= 11.4 V)
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............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
PIN DESCRIPTION
(1)
PIN NO.
TS12A44513 TS12A44514 TS12A44515 NAME DESCRIPTION
TSSOP-14
2, 4, 9, 10 2, 4, 9, 10 2, 4, 9, 10 COM Common14 14 14 V
+
Power supply5, 6, 12, 13 5, 6, 12, 13 5, 6, 12, 13 IN Digital control to connect COM to NO or NC7 7 7 GND Digital ground1, 8 1, 3, 8, 11 – NO Normally open3, 11 – 1, 3, 8, 11 NC Normally closed
(1) NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in bothdirections.
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APPLICATION INFORMATION
Power-Supply Considerations
Logic-Level Thresholds
High-Frequency Performance
Test Circuits/Timing Diagrams
TS12A44514
GND
IN
NO
COM
50 Ω
∆VOUT isthemeasuredvoltagedueto charge
transfer errorQwhenthechannelturnsoff.
Q= VOUT xCL
VIN VOUT
VNO or VNC =0 V
CL
1000 pF
VIN
VOUT ∆VOUT
V+
V+V+
0 V
TS12A44515
TS12A44514
TS12A44513
TS12A44515
TS12A44513 , , TS12A44514 , , TS12A44515
SCDS247 – OCTOBER 2008 .............................................................................................................................................................................................
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The TS12A44513/TS12A44514/TS12A44515 construction is typical of most CMOS analog switches, except thatthey have only two supply pins: V
+
and GND. V
+
and GND drive the internal CMOS switches and set their analogvoltage limits. Reverse ESD-protection diodes connected in series are internally connected between eachanalog-signal pin and both V
+
and GND. If an analog signal exceeds V
+
or GND, one of the diodes will beforward biased, but the other will be reverse biased preventing current flow.
Virtually all the analog leakage current comes from the ESD diodes to V
+
or GND. Although the ESD diodes on agiven signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each isbiased by either V
+
or GND and the analog signal. This means their leakages will vary as the signal varies. Thedifference in the two diode leakages to the V
+
and GND pins constitutes the analog-signal-path leakage current.All analog leakage current flows between each pin and one of the supply terminals, not to the other switchterminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity.
There is no connection between the analog-signal paths and V
+
or GND.
V
+
and GND also power the internal logic and logic-level translators. The logic-level translators convert the logiclevels to switched V
+
and GND signals to drive the analog signal gates.
The logic-level thresholds are CMOS/TTL compatible when V
+
is 5 V. As V
+
is raised, the level thresholdincreases slightly. When V
+
reaches 12 V, the level threshold is about 3 V – above the TTL-specified high-levelminimum of 2.8 V, but still compatible with CMOS outputs.
CAUTION:
Do not connect the TS12A44513/TS12A44514/MAS4515 V
+
to 3 V and thenconnect the logic-level pins to logic-level signals that operate from 5-V supply.Output levels can exceed 3 V and violate the absolute maximum ratings,damaging the part and/or external circuits.
In 50- Ωsystems, signal response is reasonably flat up to 250 MHz (see Typical Operating Characteristics).Above 20 MHz, the on response has several minor peaks that are highly layout dependent. The problem is not inturning the switch on; it is turning it off. The OFF-state switch acts like a capacitor and passes higher frequencieswith less attenuation. At 10 MHz, OFF isolation is about – 45 dB in 50- Ωsystems, decreasing (approximately 20dB per decade) as frequency increases. Higher circuit impedances also make OFF isolation decrease. OFFisolation is about 3 dB above that of a bare IC socket, and is due entirely to capacitive coupling.
Figure 5. Charge Injection
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50%
tOFF
tON
V
IN
0 V
GND
IN
NO
COM
50 Ω
TS12A44514
TS12A44513
300 Ω35pF
90% 90%
0 V
50%
tON
tOFF
V
IN
0 V
GND
IN
NC
COM
50 Ω300 Ω35pF
90% 90%
0 V
TS12A44515
TS12A44513
VNOPEAK
VNOPEAK
VNO
VOUT
VIN
VNO
VOUT
VIN
V+
V+
V+
V+
V+
V+
VOUT
VOUT
Measurementsarestandardizedagainstshortatsocket
terminals. OFFisolationismeasuredbetweenCOMandOFF
terminals oneachswitch. ONlossismeasuredbetween COM
and ONterminalsoneachswitch. Signaldirectionthrough
switch isreversed; worstvaluesarerecorded.
V
OUT
GND
IN
NO
COM
V
IN
TS12A44513/14/15
OFFIsolation=20log VOUT
VIN
ONLoss=20log V
OUT
V
IN
50 Ω
50 Ω50 Ω
50 Ω
MEAS REF
10nF
V+
V+
V+
GND
IN
NO
COM
1-MHz
As
Required Analyzer
Capacitance
or
NC
TS12A44513/14/15
V+
V+
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............................................................................................................................................................................................. SCDS247 – OCTOBER 2008
Figure 6. Switching Times
Figure 7. OFF Isolation and ON Loss
Figure 8. NO, NC, and COM Capacitance
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TS12A44513DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44513DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44513PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44513PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44514DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44514DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44514PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44514PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44515DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44515DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44515PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A44515PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2008
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TS12A44513DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TS12A44513PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TS12A44514DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TS12A44514PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TS12A44515DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TS12A44515PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS12A44513DR SOIC D 14 2500 367.0 367.0 38.0
TS12A44513PWR TSSOP PW 14 2000 367.0 367.0 35.0
TS12A44514DR SOIC D 14 2500 367.0 367.0 38.0
TS12A44514PWR TSSOP PW 14 2000 367.0 367.0 35.0
TS12A44515DR SOIC D 14 2500 367.0 367.0 38.0
TS12A44515PWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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