Dual PLL Precision Synthesizer AD9578 Data Sheet FEATURES GENERAL DESCRIPTION Any output frequency precision synthesis 11.8 MHz to 919 MHz Better than 0.1 ppb frequency resolution Ultralow rms jitter (12 kHz to 20 MHz) <300 fs rms using integer synthesis <405 fs rms using fractional synthesis Dual reference inputs support LVPECL, LVDS, 1.8 V LVCMOS, or fundamental mode AT cut crystals from 22 MHz to 54 MHz or reference clocks from 20 MHz to 60 MHz Numerical (NCO) frequency control Dynamically pullable output frequency enables FPGAbased PLLs (HDL available) Fast serial peripheral interface (SPI) bus write speeds up to 100 MHz On-the-fly frequency changes Dual PLL in compact 7 mm x 7 mm package Replaces multiple large clock ICs, PLLs, fanout buffers, crystal oscillators (XOs), and voltage controlled crystal oscillators (VCXOs) Mix and match output buffers In-circuit programmable LVPECL/LVDS/HCSL/LVCMOS Independent buffer (VDDOx) drives multiple technologies Enhanced power supply noise rejection The AD9578 is a programmable synthesizer intended for jitter attenuation and asynchronous clocking applications in high performance telecommunications, networking, data storage, serializer/deserializer (SERDES), and physical layer (PHY) applications. The device incorporates two low jitter PLLs that provide any frequency with precision better than 0.1 ppb, each with two separate output dividers, for a total of four programmable outputs, delivering maximum flexibility and jitter performance. Each output is independently programmable to provide frequencies of up to 919 MHz with <410 fs typical rms jitter (12 kHz to 20 MHz) utilizing compact, low cost fundamental mode crystals (XTALs) that enable a robust supply chain. Using integer frequency synthesis, the AD9578 is capable of achieving rms jitter as low as 290 fs. The AD9578 is packaged with a factory programmed default power-on configuration. After power-on, all settings including output frequency are reconfigurable through a fast SPI. The AD9578 architecture permits it to be used as a numerically controlled oscillator (NCO). This allows the user to dynamically change the frequency using the fast SPI bus. FPGAs and other devices can take advantage of this function to implement digital PLLs with configurable loop bandwidths for jitter attenuation applications, precision disciplined clocks that lock to tight stability references, or digitally controlled precision timing applications, such as network timing and IEEE 1588 applications. The SPI bus can operate up to 50 MHz, enabling fast FPGA loops while multiple devices share the same bus. The AD9578 can also be used in multirate precision applications, such as broadcast video or OTN. HDL FPGA code for digital PLL applications is available from Analog Devices, Inc. APPLICATIONS FPGA-based jitter attenuators and low jitter PLLs Precision disciplined clocks and clock synthesizers Multirate clock synthesizers Optical: OTN/SDH/SONET Broadcast video: 3G SDI, HD SDI, SDI Networking and storage: Ethernet/SAS/Fibre Channel Wireless infrastructure: OBSAI/CPRI Industrial: IEEE 1588 Numerically controlled oscillators (NCOs) SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM AD9578 XO4 REF2 REF INPUT MUX XO3 OPTIONAL XO2 FRACTIONAL PLL1 FRACTIONAL PLL2 REF1 XO1 POWER SUPPLIES OUTPUT ENABLE LOGIC DIVIDER DIVIDER DIVIDER DIVIDER REFOUT, REFOUT OUT1, OUT1 OUT2, OUT2 OUT3, OUT3 OUT4, OUT4 SPI AND OTP PROGRAMMABLE LOGIC CONTROL NOTES 1. IF SUPPLYING A SINGLE-ENDED 1.8V CMOS SIGNAL, CONNECT THE SIGNAL TO EITHER XO2 OR XO4. 11356-001 OPTIONAL Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9578 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Overview ............................................................................. 25 Applications...............................................................................1 Crystal Oscillator Gain ........................................................ 25 General Description ..................................................................1 Crystal Load Capacitors....................................................... 25 Simplified Functional Block Diagram........................................1 PLLs ........................................................................................ 26 Revision History ........................................................................3 Overview ............................................................................. 26 Specifications.............................................................................4 PLL Modes of Operation ..................................................... 26 Supply Voltage and Current (2.5 V Operation)......................4 VCO .................................................................................... 27 Supply Voltage and Current (3.3 V Operation)......................4 Charge Pump....................................................................... 27 Power Dissipation ..................................................................4 Output Dividers................................................................... 27 Logic Inputs (CS, PD1, OEREF, OE1, OE2, OE3, OE4) .........5 Loss of Lock Indicator ......................................................... 27 Reference Inputs (XO1, XO2, XO3, XO4)..............................5 Resets................................................................................... 27 Distribution Clock Outputs (Including REFOUT/REFOUT) 6 Example Values for 49.152 MHz crystal .............................. 28 Serial Port ..............................................................................9 SPI Programming .................................................................... 29 Digital PLL...........................................................................10 Overview ............................................................................. 29 Digital Functions Timing.....................................................10 SPI Description.................................................................... 29 Jitter Generation Using 49.152 MHz Crystal........................10 OTP Programming .............................................................. 30 Jitter Generation Using 25 MHz Square wave......................11 Register Map ........................................................................... 32 Absolute Maximum Ratings ....................................................12 Register Map Bit Descriptions................................................. 34 ESD Caution ........................................................................12 Chip and Manufacturer ID (Register 0, Address 0x00)........ 34 Pin Configuration and Function Descriptions.........................13 Product ID, Chip ID, and User Programing Space (Register 1, Address 0x01) ...................................................................... 34 Typical Performance Characteristics .......................................15 Test Setup and Configuration Circuits.....................................18 Input/Output Termination Recommendations........................19 Getting Started.........................................................................20 Chip Power Monitor and Startup.........................................20 External Pin Readback and Override (Register 2, Address 0x02).................................................................................... 34 REFOUT/OUTPUT Divider Enable (Register 3, Address 0x03).................................................................................... 36 Device Register Programming Using a Register Setup File ..20 XTAL1 and Output Buffer Configuration (Register 4, Address 0x04) ...................................................................... 37 OTP Programming ..............................................................20 Output Driver Configuration (Register 5, Address 0x05).... 38 Theory of Operation................................................................21 PLL1 Configuration (Register 6, Address 0x06) .................. 38 Overview..............................................................................21 PLL1 Configuration (Register 7, Address 0x07) .................. 39 PLL and Output Driver Control ..............................................22 PLL2 Configuration (Register 8, Address 0x08) .................. 40 Overview..............................................................................22 PLL2 Configuration (Register 9, Address 0x09) .................. 40 PLL Enable/Disable..............................................................22 XTAL2 Configuration (Register 10, Address 0x0A)............. 42 Output Driver Format..........................................................23 Reserved (Register 11, Address 0x0B).................................. 42 Output Configuration Example ...........................................23 PLL1 KVCO Band (Register 12, Address 0x0C)...................... 42 Reference Input........................................................................24 Reserved (Register 13, Address 0x0D)................................. 42 Overview..............................................................................24 PLL2 KVCO Band (Register 14, Address 0x0E) ...................... 43 Reference Input....................................................................24 PLL Lock Detect (Register 15, Address 0x0F)...................... 43 Crystal Oscillator Amplifier Enable .....................................24 Outline Dimensions ................................................................ 44 REFOUT/REFOUT Source Selection...................................24 Ordering Guide ................................................................... 44 Crystal Oscillator Inputs..........................................................25 Rev. B | Page 2 of 44 Data Sheet AD9578 REVISION HISTORY 1/2017--Rev. A to Rev. B Change to Table 31 ..........................................................................32 10/2016--Rev. 0 to Rev. A Changes to Figure 3.........................................................................13 Changes to Table 29 ........................................................................28 Added Exposed Pad Notation to Outline Dimensions ..............44 10/2014--Revision 0: Initial Version Rev. B | Page 3 of 44 AD9578 Data Sheet SPECIFICATIONS SUPPLY VOLTAGE AND CURRENT (2.5 V OPERATION) VDD = 2.5 V 5%, TA = -25C to +85C. Table 1. Parameter SUPPLY VOLTAGE SUPPLY CURRENT Symbol VDD I DD Min 2.375 229 337 Typ 2.50 247 365 Max 2.625 265 388 Unit V mA mA Test Conditions/Comments Using typical configuration in Table 3 Using all blocks running configuration in Table 3 SUPPLY VOLTAGE AND CURRENT (3.3 V OPERATION) VDD = 3.3 V 10%, TA = -25C to +85C. Table 2. Parameter SUPPLY VOLTAGE SUPPLY CURRENT Symbol VDD VPROG Min 2.97 5.25 I DD Typ 3.30 5.5 Max 3.63 VDD + 2.5 Unit V V 252 373 268 397 mA mA Test Conditions/Comments CS pin only; used only for one time programmable (OTP) programming; perform OTP programming only with VDD = 3.3 V Using typical configuration in Table 3 Using all blocks running configuration in Table 3 POWER DISSIPATION VDD = 2.5 V 5%, TA = -25C to +85C. Maximum power is at VDD = 2.625 V and is usually 11% higher than typical. Table 3. Parameter POWER DISSIPATION Typical Configuration Min Typ Max Unit Test Conditions/Comments 618 696 mW All Blocks Running 913 1018 mW Full Power-Down 67 75 mW XTAL: 25 MHz REFOUT driver: disabled PLL1: one LVPECL driver at 644.53125 MHz PLL2: one single-ended LVCMOS driver (with 80 pF load) at 100 MHz XTAL: 49.152 MHz XTAL on both XTAL inputs REFOUT driver: LVPECL mode, 49.152 MHz PLL1: two LVPECL drivers at 693.812 MHz PLL2: two LVPECL drivers at 693.812 MHz PD1 pin grounded; Register 0x02 = 0x015555 to disable remainder of chip Starting with typical configuration; change in power due to the indicated operation Incremental Power Dissipation Crystal Reference On/Off PLL On/Off 25 259 mW mW Output Distribution Driver On/Off HCSL (at 644.53 MHz) LVDS (at 644.53 MHz) LVPECL (at 644.53 MHz) 3.3 V LVCMOS (at 25 MHz) 75 43 107 75 mW mW mW mW Rev. B | Page 4 of 44 PLL1 or PLL2 on/off, including output drivers or channel dividers Each output of a differential pair has 50 to ground 100 across differential pair 50 to VDD - 2 V A single 3.3 V LVCMOS output with an 80 pF load Data Sheet AD9578 LOGIC INPUTS (CS , PD1, OEREF, OE1, OE2, OE3, OE4) Table 4. Parameter Min LOGIC INPUTS (CS in OTP FUNCTION) Input Voltage (VPROG ) Typ Max Unit Test Conditions/Comments Specifications apply to the CS pin while in OTP programming mode 5.25 Input Current Time to OTP Program LOGIC INPUTS (PD1 ,OEREF, OE1, OE2, OE3, OE4, CS ) Input Voltage High (VIH ) Low (VIL) Input Current (I INH , I INL) Input Capacitance (CIN ) 5.5 VDD + 2.5 V 20 25 mA s 800 2.2 38 3 See VPROG definition in Table 1; OTP programming must be done with VDD = 3.3 V Current consumed during OTP programming Time required per bit programmed Numbers are valid for VDD = 2.5 V and 3.3 V V V A pF 0.8 60 REFERENCE INPUTS (XO1, XO2, XO3, XO4) Table 5. Parameter REFERENCE INPUT DRIVEN BY CRYSTAL RESONATOR Crystal Resonator Frequency Range Crystal Motional Resistance REFERENCE INPUT DRIVEN BY A DIFFERENTIAL CLOCK Input Frequency Range Input Slew Rate Differential Input Voltage Sensitivity REFERENCE INPUT DRIVEN BY A SINGLE-ENDED CLOCK Input Frequency Range Input Slew Rate Single-Ended Input (XO2, XO4 Pins Only) Input Voltage High (VIH ) Low (VIL) Min Max Unit Test Conditions/Comments 60 MHz Fundamental mode, AT cut crystal 100 20 133 250 60 MHz V/s mV p-p 20 67 60 MHz V/s Guaranteed by design This input is a source follower and must be either dc-coupled 1.8 V LVCMOS on the XO2 or XO4 pin, or ac-coupled Assumes ac-coupled LVDS (494 mV p-p across the differential pair) Minimum limit imposed for jitter performance Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding of complementary input The XO2 pin (for PLL1) and XO4 pin (for PLL2) input accepts dccoupled 1.8 V LVCMOS DC-coupled Minimum limit imposed for jitter performance 20 Typ V 1.48 0.98 V Rev. B | Page 5 of 44 AD9578 Data Sheet DISTRIBUTION CLOCK OUTPUTS (INCLUDING REFOUT/REFOUT) Table 6. Parameter Min Typ Max Unit 919 MHz 130 142 183 203 ps ps 50 43 46 52 47 50 54 51 54 % % % Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 49 45 51 700 51 49 57 850 53 51 63 1000 % % % mV Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz Voltage across pins at minimum output frequency; if a differential probe is used, peak-to-peak voltage (VPP) is 2x this value 1.81 1.91 2.01 V 3.3 V LVPECL MODE Output Frequency Rise Time (20% to 80%) Fall Time (80% to 20%) Duty Cycle, OUTPUT1 and OUTPUT4 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Duty Cycle, OUTPUT2 and OUTPUT3 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Differential Output Voltage Swing Common-Mode Output Voltage 11.8 2.5 V LVPECL MODE Output Frequency Rise Time (20% to 80%) Fall Time (80% to 20%) Duty Cycle, OUTPUT1 and OUTPUT4 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Duty Cycle, OUTPUT2 and OUTPUT3 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Differential Output Voltage Swing Common-Mode Output Voltage 3.3 V HCSL MODE Output Frequency Rise Time (20% to 80%) Fall Time (80% to 20%) Duty Cycle, OUTPUT1 and OUTPUT4 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Duty Cycle, OUTPUT2 and OUTPUT3 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Output High Voltage Output Low Voltage Output Voltage Swing (VSWING ) Absolute Crossing Point (VOX) Short-Circuit Output Current 11.8 Test Conditions/Comments VDD = 3.3V ; 50 to VDD - 2 V termination at output pins REFOUT/REFOUT limited to 60 MHz VDD = 2.5 V; 50 to VDD - 2 V termination at output pins REFOUT/REFOUT limited to 60 MHz 919 MHz 137 148 186 209 ps ps 50 49 46 52 51 50 54 54 54 % % % Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 43 44 51 700 48 48 57 850 51 52 63 1000 % % % mV Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz Voltage across pins at minimum output frequency; if a differential probe is used, VPP is 2x this value 1.05 1.15 1.25 V 919 MHz 180 186 266 286 ps ps 51 48 49 52 51 52 54 54 56 % % % Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 50 48 53 624 -50 624 53 51 59 750 0 750 54 53 67 850 +50 850 % % % mV mV mV Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 295 360 14 400 17 mV mA 11.8 Rev. B | Page 6 of 44 50 to ground termination at output pins REFOUT/REFOUT limited to 60 MHz Voltage across pins at minimum output frequency; when a differential probe is used, VPP is 2x this value Data Sheet AD9578 Parameter 2.5 V HCSL MODE Output Frequency Rise Time (20% to 80%) OUTPUT1, OUTPUT2, OUTPUT3 OUTPUT4 Fall Time (80% to 20%) OUTPUT1, OUTPUT2, OUTPUT3 OUTPUT4 Duty Cycle, OUTPUT1 and OUTPUT4 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Duty Cycle, OUTPUT2 and OUTPUT3 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Output High Voltage Output Low Voltage Output Voltage Swing (VSWING ) Min Absolute Crossing Point (VOX) Short-Circuit Output Current LVDS MODE (VDD = 3.3 V and 2.5 V) Output Frequency Rise Time (20% to 80%) Fall Time (80% to 20%) OUTPUT1 and OUTPUT4 Duty Cycle 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 OUTPUT2 and OUTPUT3 Duty Cycle 111.8 fOUT 357 MHz 357 < fOUT 919 MHz Output Divider = 4.5 Differential Output Voltage Swing Balanced, VOD Typ Max Unit 919 MHz Test Conditions/Comments 50 to ground termination at output pins REFOUT/REFOUT limited to 60 MHz 199 243 275 370 ps ps Output divider settings other than 4.5 Output divider settings other than 4.5 191 226 287 329 ps ps Output divider settings other than 4.5 Output divider settings other than 4.5 50 47 39 52 50 52 54 53 55 % % % Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 50 48 45 624 -50 624 52 50 59 750 0 750 54 53 65 850 50 850 % % % mV mV mV Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 295 360 14 400 17 mV mA 173 177 919 215 223 MHz ps ps 50 46 49 52 50 52 54 54 55 % % % Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 50 46 51 52 50 59 54 53 66 % % % Output divider settings other than 4.5 Output divider settings other than 4.5 Measured at 765 MHz 454 mV 50 mV Voltage across pins at minimum output frequency; if a differential probe is used, VPP is 2x this value Absolute difference between voltage swing of true pin and complementary pin 1.375 50 V mV 24 mA 250 MHz 1.3 1.2 1.9 1.7 ns ns 1.3 1.5 2 2.4 ns ns 11.8 11.8 247 Unbalanced, VOD Offset Voltage Common Mode, VOS Common-Mode Difference, VOS Short-Circuit Output Current LVCMOS MODE (VDD = 3.3 V and 2.5 V) Output Frequency Rise Time (20% to 80%) 330 Pull-Down Resistor 3.3 k Pull-Down Resistor Fall Time (20% to 80%) 330 Pull-Down Resistor 3.3 k Pull-Down Resistor 1.08 1.26 16 11.8 Voltage across pins at minimum output frequency; if a differential probe is used, VPP is 2x this value 100 termination across the output pair REFOUT/REFOUT limited to 54 MHz Voltage difference between pins at minimum output frequency REFOUT limited to 60 MHz Capacitor load (CLOAD ) = 10 pF CLOAD = 10 pF Rev. B | Page 7 of 44 AD9578 Data Sheet Parameter Duty Cycle (20% to 80%) 330 Pull-Down Resistor 3.3 k Pull-Down Resistor Output Voltage High (VOH ) VDD = 3.3 V VDD = 2.5 V Output Voltage Low (VOL) VDD = 3.3 V VDD = 2.5 V OUTPUT TIMING SKEW LVPECL Between OUTPUT1 Drivers Between OUTPUT3 Drivers LVDS Between OUTPUT1 Drivers Between OUTPUT3 Drivers HCSL Between OUTPUT1 Drivers Between OUTPUT3 Drivers LVCMOS Between OUTPUT1 Drivers Between OUTPUT3 Drivers Min Typ Max 43 44 52 53 62 63 Unit ns % % Test Conditions/Comments CLOAD = 10 pF At minimum output frequency; outputs terminated 50 to VDD /2 3.0 1.9 3.1 2.0 3.35 2.1 V V At minimum output frequency; outputs terminated 50 to VDD /2 0.22 0.2 0.32 0.3 0.42 0.4 V V OUTPUT2 lags OUTPUT1; OUTPUT3 lags OUTPUT4 and OUTPUT2 90 ps and OUTPUT4 102 ps and OUTPUT2 94 ps and OUTPUT4 100 ps and OUTPUT2 48 ps and OUTPUT4 59 ps and OUTPUT2 64 ps and OUTPUT4 59 ps Rev. B | Page 8 of 44 LVPECL mode on both drivers; rising edge only; any divide value LVPECL mode on both drivers; rising edge only; any divide value LVDS mode on both drivers; rising edge only; any divide value LVDS mode on both drivers; rising edge only; any divide value HCSL mode on both drivers; rising edge only; any divide value HCSL mode on both drivers; rising edge only; any divide value LVCMOS mode on both drivers; rising edge only; any divide value LVCMOS mode on both drivers; rising edge only; any divide value Data Sheet AD9578 SERIAL PORT Table 7. Parameter Min CS Input Voltage Logic 1 Logic 0 Input Current Logic 1 Logic 0 Input Capacitance SCK Input Voltage Logic 1 Logic 0 Input Current Logic 1 Logic 0 Input Capacitance SDI Input Voltage Logic 1 Logic 0 Input Current Logic 1 Logic 0 Input Capacitance SDO/LOL Output Logic 1 Voltage Output Logic 0 Voltage TIMING SCK Clock Rate, 1/t CLK Typ Max Unit 1.2 44 V V A 88 2 A pF 2.2 Test Conditions/Comments See Table 4 for using CS while in OTP programming mode Internal 30 k pull-down resistor 2.2 0.8 1.2 200 1 2 A A pF 2.2 1.2 1 1 2 0.4 V V 1 mA load current 1 mA load current See Figure 2 50 MHz SDO/LOL pin maximum speed may be limited by excess capacitance on the receiver connected to the SDO/LOL pin 100 65 0 MHz ns ns ns ns ns ns ns 65 ns 2 2 1.5 2 8 CS Minimum Pulse Width High V V A A pF VDD - 0.6 Write Only Pulse Width High, t HIGH Pulse Width Low, t LOW SDI to SCK Setup, t DS SCK to SDI Hold, t DH SCK to Valid SDO, t DV CS to SCK Setup, t S CS to SCK Hold, t C V V SDO function of SDO/LOL pin (see Figure 33) CS is normally held low during a complete SPI transaction Timing Diagram tDS tS tHIGH tDH CS DON'T CARE SDIO DON'T CARE tC DON'T CARE OP[3] OP[2] OP[1] OP[0] ADDR[3] ADDR[2] ADDR[1] ADDR[0] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] Figure 2. Serial Port Timing Diagram Rev. B | Page 9 of 44 DON'T CARE 11356-131 SCK tCLK tLOW AD9578 Data Sheet DIGITAL PLL Table 8. Parameter FREQUENCY STEP SIZE Min 0.1 Typ Max Unit ppb Test Conditions/Comments DIGITAL FUNCTIONS TIMING Table 9. Parameter OTP PROGRAMMING TIME, PER BIT Min 0.8 POWER-ON RESET TIME 4 Typ 1 Max 2 Unit ms Test Conditions/Comments See Table 4 for using CS while in OTP programming mode (the AD9578 has 444 bits; therefore, the total programming time is <1 sec) ms Do not access serial port during power-on reset. JITTER GENERATION USING 49.152 MHZ CRYSTAL Both PLLs are generating the same output frequency and use a 49.152 MHz crystal for the input reference. The loop bandwidth is set to the default value of 300 kHz. Where multiple driver types are listed, there is no significant difference between driver types. Table 10. Parameter JITTER GENERATION LVPECL, HCSL, LVDS Driver fOUT = 622.08 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz fOUT = 693.48 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz fOUT = 174.703 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz fOUT = 161.1328 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz LVPECL, HCSL, LVDS, LVCMOS Driver fOUT = 156.25 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 1.875 MHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Min Typ Max Unit 320 370 fs rms fs rms 403 408 fs rms fs rms 403 410 fs rms fs rms 361 363 fs rms fs rms 350 77 352 fs rms fs rms fs rms Rev. B | Page 10 of 44 Test Conditions/Comments Fractional mode on, fREF = 49.152 MHz XTAL Data Sheet AD9578 JITTER GENERATION USING 25 MHZ SQUARE WAVE Both PLLs are generating the same output frequency and use a 25 MHz square wave for the input reference. The loop bandwidth is set to the default value of 300 kHz. Where multiple driver types are listed, there is no significant difference between driver types. Fractional mode turned on, unless otherwise stated. Table 11. Parameter JITTER GENERATION LVPECL, HCSL, LVDS Driver fOUT = 622.08 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz fOUT = 693.48 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz fOUT = 174.703 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz fOUT = 161.1328 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 20 kHz to 80 MHz LVPECL, HCSL, LVDS, LVCMOS Driver fOUT = 156.25 MHz Bandwidth: 12 kHz to 20 MHz Bandwidth: 1.875 MHz to 20 MHz Bandwidth: 20 kHz to 80 MHz Min Typ Max Unit 515 516 fs rms fs rms 504 505 fs rms fs rms 517 523 fs rms fs rms 527 530 fs rms fs rms 290 61 292 fs rms fs rms fs rms Test Conditions/Comments fREF = 25 MHz square wave Integer mode operation Rev. B | Page 11 of 44 AD9578 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 12. Parameter Supply Voltage (VDD ) Inputs (VIN ) (Except for CS Pin) Rating 4.6 V -0.50 V to VDD + 0.5 V CS Pin Outputs (VOUT) Operating Temperature Range (TA) Industrial Storage Temperature Range (TS) VDD + 2.5 V -0.50 V to VDD + 0.5 V -25C to +85C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION -65C to +150C Rev. B | Page 12 of 44 Data Sheet AD9578 48 47 46 45 44 43 42 41 40 39 38 37 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9578 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 11356-002 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 Figure 3. Pin Configuration Table 13. Pin Function Descriptions Pin No. 1 2 Mnemonic VSSO1 OUT1 Type Negative power Output 3 OUT1 Output 4 VDDO1 5, 12, 25, 31, 37, 48 6 VDDA VDDO2 7 OUT2 Supply, positive power Supply, positive power Supply, positive power Output 8 OUT2 Output 9 10, 36 11 VSSO2 VSS OEREF Negative power Negative power Input 13 FILTER1+ Filter 14 15 FILTER1- OE1 Filter Input 16 OE2 Input 17 18 SDO/LOL CS Output Input 19 SCK Input Description Return Path Ground for Clock Output 1. Clock Output 1 Derived from PLL1. Supports frequencies up to the device maximum. OUT1 is a selectable 1 pin. When used in LVCMOS mode, OUT1 is the active pin. Active Low Clock Output 1 Derived from PLL1. Supports frequencies up to the device maximum. OUT1 is a selectable 1 pin. OUT1 is not used in LVCMOS mode; it is high-Z in LVCMOS mode. Power Supply for Clock Output 1. 2.5 V or 3.3 V Analog Power Supply. Power Supply for Clock Output 2. Clock Output 2 Derived from PLL1. Supports frequencies up to the device maximum. OUT2 is a selectable 1 pin. When used in LVCMOS mode, OUT2 is the active pin. Active Low Clock Output 2 Derived from PLL1. Supports frequencies up to the device maximum. OUT1 is a selectable 1 pin. OUT2 is not used in LVCMOS mode; it is high-Z in LVCMOS mode. Return Path Ground for Clock Output 2. Device Ground. Output Enable for REFOUT and REFOUT Pins, LVCMOS. Active high. This pin has an internal 75 k pull-down resistor. Phase-Locked Loop 1 (PLL1) Filter Node, Positive Side. Connect a 220 nF capacitor between this pin and Pin 14. PLL1 Filter Node, Negative Side. Connect a 220 nF capacitor between this pin and Pin 13. Output Enable 1 for Clock Output 1, LVCMOS. Places OUT1 and OUT1 in a high-Z state. Active high. This pin has an internal 75 k pull-up resistor. Output Enable 2 for Clock Output 2, LVCMOS. Places OUT2 and OUT2 in a high-Z state. Active high. This pin has an internal 75 k pull-up resistor. Serial Data Output for SPI Control/Loss of Lock, LVCMOS. Chip Select for SPI Control, LVCMOS. Active low. When this pin is set to 5 V, OTP programming is enabled (see Table 4 and the OTP Programming section). This pin has an internal 75 k pull-up resistor. Serial Clock Input for SPI Control, LVCMOS. Rev. B | Page 13 of 44 AD9578 Data Sheet Pin No. 20 21 Mnemonic SDI OE3 Type Input Input 22 OE4 Input 23 24 26 27 28 FILTER2- FILTER2+ PD1 VSSO3 OUT3 Filter Filter Input Negative power Output 29 OUT3 Output 30 VDDO3 32 VDDO4 33 OUT4 Supply, positive power Supply, positive power Output 34 OUT4 Output 35 38 VSSO4 XO2 Negative power Input 39 XO1 Input 40, 41, 42 43 NIC REFOUT Output 44 REFOUT Output 45 XO4 Input 46 XO3 Input 47 VDD Supply, positive power EPAD 1 Description Serial Data Input for SPI Control, LVCMOS. Output Enable 3 for Clock Output 3, LVCMOS. Places OUT3 and OUT3 in a high-Z state. Active high is the default but active low is programmable. This pin has an internal 75 k pull-up resistor. Output Enable 4 for Clock Output 4, LVCMOS. Places OUT4 and OUT4 in a high-Z state. Active high is the default but active low is programmable. This pin has an internal 75 k pull-up resistor. PLL2 Filter Node, Negative Side. Connect a 220 nF capacitor between this pin and Pin 24. PLL2 Filter Node, Positive Side. Connect a 220 nF capacitor between this pin and Pin 23. Active Low Power-Down for PLL1, LVCMOS. This pin has an internal 75 k pull-up resistor. Return Path Ground for Clock Output 3. Active Low Clock Output 3 Derived from PLL2. Supports frequencies up to the device maximum. OUT3 is a selectable 1 pin. OUT3 is not used in LVCMOS mode; it is high-Z in LVCMOS mode. Clock Output 3 Derived from PLL2. Supports frequencies up to the device maximum. OUT3 is a selectable 1 pin. When used in LVCMOS mode, OUT3 is the active pin. Power Supply for Clock Output 3. Power Supply for Clock Output 4. Clock Output 4 Derived from PLL2. Supports frequencies up to the device maximum. OUT4 is not used in LVCMOS mode and is high-Z. OUT4 is a selectable 1 pin. Clock Output 4 Derived from PLL2. Supports frequencies up to the device maximum. OUT4 is a selectable 1 pin. When used in LVCMOS mode, OUT4 is the active pin. Return Path Ground for Clock Output 4. Reference Input 1. Connect a crystal across this pin and XO1. Alternatively, the user can connect a 1.8 V LVCMOS clock to this pin only, or connect a differential, ac-coupled LVDS or LVPECL signal across this pin and the XO1 pin. This pin can be a crystal or reference input. Complementary Reference Input 1. Connect a crystal across this pin and XO2. Alternatively, the user can connect a differential, ac-coupled LVDS or LVPECL signal to this pin and the XO2 pin. This pin can be a crystal or reference input. No Internal Connection. Leave these pins unconnected. Active Low Reference Clock Output. This pin provides a copy of the reference input or crystal input frequency. REFOUT is a selectable 1 pin. Reference Clock Output. This pin provides a copy of the reference input or crystal input frequency. REFOUT is a selectable 1 pin. Reference Input 2. Connect a crystal across this pin and XO3. Alternatively, connect a 1.8 V LVCMOS clock to this pin only, or connect a differential, ac-coupled LVDS or LVPECL signal across this pin and the XO3 pin. This pin can be a crystal or reference input. Complementary Reference Input 2. Connect a crystal across this pin and XO4. Alternatively, connect a differential, ac-coupled LVDS or LVPECL signal to this pin and the XO4 pin. 2.5 V or 3.3 V Power Supply for Device Core. This pin can be a crystal or reference input. Exposed Pad. The exposed pad on the bottom of the package must be connected to ground for proper operation. Selectable pins are factory programmed to a default power-up configuration. The user can override the default programming to support LVCMOS, LVDS, LVPECL, or HCSL mode after power-up using the SPI. Rev. B | Page 14 of 44 Data Sheet AD9578 TYPICAL PERFORMANCE CHARACTERISTICS fR is the input reference clock frequency; fOUT is the output clock frequency; VDD at nominal supply voltage (3.3 V). 25 MHz square wave input is a dc-coupled 3.3 V LVCMOS signal with 0.8 ns (20% to 80%) rise time. -70 INTEGRATED RMS JITTER (12kHz TO 20MHz): 290fs PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -116 1kHz -125 10kHz -132 100kHz -133 1MHz -142 10MHz -163 FLOOR -164 -130 -140 -110 -120 -130 -140 -150 -150 -160 -160 -170 100 1k 10k 1M 100k 10M 100M FREQUENCY (Hz) -170 100 -110 -130 -140 -100 -110 -120 -130 -140 -150 -150 -160 -160 100k 1M 10M 100M FREQUENCY (Hz) -170 100 11356-004 10k 100M PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -104 1kHz -122 10kHz -127 100kHz -129 1MHz -140 10MHz -161 FLOOR -163 -90 -120 1k 10M INTEGRATED RMS JITTER (12kHz TO 20MHz): 361fs -80 PHASE NOISE (dBc/Hz) -100 -170 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 5. Absolute Phase Noise (Output Driver = LVCMOS), fR = 25 MHz Square Wave, fOUT = 161.1328125 MHz on Both PLLs Figure 8. Absolute Phase Noise (Output Driver = 3.3.V LVCMOS), fR = 49.152 MHz Crystal, fOUT = 161.1328125 MHz on Both PLLs -70 -70 INTEGRATED RMS JITTER (12kHz TO 20MHz): 517fs -80 -110 -120 -130 -140 -100 -110 -120 -130 -140 -150 -150 -160 -160 -170 100 1k 10k 100k 1M 10M PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -105 1kHz -121 10kHz -127 100kHz -126 1MHz -141 10MHz -163 FLOOR -165 -90 PHASE NOISE (dBc/Hz) -100 INTEGRATED RMS JITTER (12kHz TO 20MHz): 403fs -80 PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -114 1kHz -123 10kHz -128 100kHz -125 1MHz -137 10MHz -162 FLOOR -163 -90 PHASE NOISE (dBc/Hz) -70 100M FREQUENCY (Hz) 11356-005 PHASE NOISE (dBc/Hz) -90 1M Figure 7. Absolute Phase Noise (Output Driver = LVDS), fR = 49.152 MHz Crystal, fOUT = 156.25 MHz on Both PLLs INTEGRATED RMS JITTER (12kHz TO 20MHz): 527fs PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -113 1kHz -123 10kHz -127 100kHz -122 1MHz -144 10MHz -163 FLOOR -163 -80 100k 10k FREQUENCY (Hz) Figure 4. Absolute Phase Noise (Output Driver = LVDS), fR = 25 MHz Square Wave, fOUT = 156.25 MHz on Both PLLs -70 1k Figure 6. Absolute Phase Noise (Output Driver = LVPECL), fR = 25 MHz Square Wave, fOUT = 174.703 MHz on Both PLLs -170 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 9. Absolute Phase Noise (Output Driver = LVPECL), fR = 49.152 MHz Crystal, fOUT = 174.703 MHz on Both PLLs Rev. B | Page 15 of 44 11356-007 -110 -120 -100 11356-008 -100 PHASE NOISE (dBc/Hz): LEVEL OFFSET -116 100Hz -121 1kHz -129 10kHz -130 100kHz -141 1MHz -162 10MHz -164 FLOOR -90 11356-003 PHASE NOISE (dBc/Hz) -90 INTEGRATED RMS JITTER (12kHz TO 20MHz): 350fs -80 PHASE NOISE (dBc/Hz) -80 11356-006 -70 AD9578 Data Sheet -70 -110 -120 -130 -130 -140 -150 10k 1M 100k 10M 100M -160 100 11356-009 1k -110 -120 -130 -140 -90 -100 -110 -120 -130 -150 -170 100 -160 100 10k 1M 100k 10M 100M FREQUENCY (Hz) -80 -80 -90 -90 PHASE NOISE (dBc/Hz) -70 -100 -110 -120 INTEGRATED RMS JITTER (12kHz TO 20MHz): 506fs PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -101 1kHz -110 10kHz -114 100kHz -110 1MHz -108 10MHz -154 FLOOR -160 10k 10M 100M INTEGRATED RMS JITTER (12kHz TO 20MHz): 361fs PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -93 -107 1kHz -114 10kHz 100kHz -116 1MHz -122 -152 10MHz FLOOR -159 -100 -110 -120 -130 -140 -150 -160 100k 1M FREQUENCY (Hz) 10M 100M 11356-011 1k 1M 100k Figure 14. Absolute Phase Noise (Output Driver = LVPECL), fR = 49.152 MHz Crystal, fOUT = 693.482991 MHz on Both PLLs -70 -170 100 10k FREQUENCY (Hz) Figure 11. Absolute Phase Noise (Output Driver = LVPECL), fR = 25 MHz Square Wave, fOUT = 693.482991 MHz on Both PLLs -160 1k Figure 12. Absolute Phase Noise (Output Driver = LVPECL), fR = 25 MHz Square Wave on XO1/XO2 Pins, fOUT = 919 MHz on Both PLLs Rev. B | Page 16 of 44 -170 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 15. Absolute Phase Noise (Output Driver = LVPECL), fR = 49.152 MHz Crystal, fOUT = 919 MHz on Both PLLs 11356-014 1k 11356-010 -160 11356-013 -140 -150 -150 100M PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -93 -110 1kHz -116 10kHz -118 100kHz -125 1MHz -153 10MHz -155 FLOOR -80 PHASE NOISE (dBc/Hz) -100 10M INTEGRATED RMS JITTER (12kHz TO 20MHz): 392fs -70 PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -101 1kHz -111 10kHz -114 100kHz -110 1MHz -127 10MHz -153 FLOOR -154 -90 1M 100k Figure 13. Absolute Phase Noise (Output Driver = LVPECL), fR = 49.152 MHz Crystal, fOUT = 622.08 MHz on Both PLLs INTEGRATED RMS JITTER (12kHz TO 20MHz): 504fs -80 -140 10k -60 -70 -130 1k FREQUENCY (Hz) Figure 10. Absolute Phase Noise (Output Driver = LVPECL), fR = 25 MHz 3.3 V LVCMOS Square Wave, fOUT = 622.08 MHz on Both PLLs PHASE NOISE (dBc/Hz) -110 -120 -150 FREQUENCY (Hz) PHASE NOISE (dBc/Hz) -90 -100 -140 -160 100 PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -95 1kHz -110 10kHz -116 100kHz -118 1MHz -132 10MHz -155 FLOOR -158 -80 PHASE NOISE (dBc/Hz) -90 -100 INTEGRATED RMS JITTER (12kHz TO 20MHz): 327fs -70 PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -102 1kHz -112 10kHz -115 100kHz -110 1MHz -128 10MHz -155 FLOOR -159 -80 PHASE NOISE (dBc/Hz) -60 INTEGRATED RMS JITTER (12kHz TO 20MHz): 515fs 11356-012 -60 Data Sheet AD9578 4.0 -60 INTEGRATED RMS JITTER (12kHz TO 5MHz): 5.8ps -70 -90 -100 -110 3.0 AMPLITUDE (V) -80 PHASE NOISE (dBc/Hz) 3.5 PHASE NOISE (dBc/Hz): OFFSET LEVEL 100Hz -100 -110 1kHz -118 10kHz -127 100kHz -130 1MHz -131 10MHz -131 FLOOR -120 2.5 2.0 1.5 1.0 -130 0.5 -140 0 -0.5 1k 10k 1M 100k 10M 100M FREQUENCY (Hz) 0 11356-015 -160 100 0.3 0.3 DIFFERENTIAL AMPLITUDE (V) 4 5 6 7 8 9 10 11 12 0.2 0.1 0 -0.1 -0.2 0.2 0.1 0 -0.1 -0.2 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (ns) -0.4 11356-023 -1.5 0 0.2 0.4 0.6 1.0 0.8 1.2 1.4 1.6 1.8 2.0 2.2 TIME (ns) Figure 17. Output Waveform, LVDS (400 MHz) 11356-040 -0.3 Figure 20. Output Waveform, LVDS (900 MHz) 1.0 1.2 0.8 1.0 DIFFERENTIAL AMPLITUDE (V) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 TIME (ns) 3.0 11356-024 -1.0 -1.2 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 TIME (ns) Figure 21. Output Waveform, LVPECL (400 MHz) Figure 18. Output Waveform, HCSL (400 MHz) Rev. B | Page 17 of 44 3.0 11356-041 DIFFERENTIAL AMPLITUDE (V) 0.4 -0.3 DIFFERENTIAL AMPLITUDE (V) 3 Figure 19. Output Waveform, 3.3 V CMOS (100 MHz) 0.4 -1.0 -2.0 2 TIME (ns) Figure 16. Phase Noise of 25 MHz, 3.3 V LVCMOS Input Clock Used -0.4 -2.0 1 11356-025 2pF LOAD 10pF LOAD -150 AD9578 Data Sheet TEST SETUP AND CONFIGURATION CIRCUITS OSCILLOSCOPE OSCILLOSCOPE 50 50 OSCILLOSCOPE VDD POWER VDD = 2.0V VDDOx OUTx OUTx OSCILLOSCOPE VDD POWER VDD = 3.3V 50 VDDOx OUTx OUTx AD9578 AD9578 VSS VSS VSS VDD 11356-030 VSS POWER = -1.3V LEAVE VDD FIXED AT 2.0V AND ADJUST VSS. 11356-032 VDD 50 ADJUST VDD. Figure 22. LVPECL Test Circuit Figure 24. LVDS Test Circuit OSCILLOSCOPE 50 OSCILLOSCOPE OPEN VDDOx OUTx OUTx AD9578 VDDOx OUTx OUTx VSS VDD OSCILLOSCOPE VDD POWER VDD = 3.3V 50 50 AD9578 VSS VSS VDD ADJUST VSS AND VDD TOGETHER. 11356-031 VSS POWER = -1.65V VSS Figure 23. LVCMOS Test Circuit 11356-033 VDD POWER VDD = 1.65V Figure 25. HCSL Test Circuit Rev. B | Page 18 of 44 Data Sheet AD9578 INPUT/OUTPUT TERMINATION RECOMMENDATIONS See Figure 26 to Figure 30 for recommendations on how to connect the outputs. VDD VDD VDD R1 33 (OPTIONAL) Z0 = 50 50 Z0 = 50 HCSL RECEIVER 50 LVPECL NOTES 1. THE 50 PULL-DOWN RESISTORS CAN BE PLACED IMMEDIATELY AFTER 33 SERIES RESISTORS, AND DOING SO ALLOWS THE USER TO PLACE MULTIPLE HIGH IMPEDANCE LOADS AT THE DESTINATION. FOR DRIVING A SINGLE LOAD, THE 50 PULL-DOWN RESISTORS CAN BE PLACED NEAR THE DRIVER OR NEAR THE DESTINATION. EITHER IMPLEMENTATION IS FINE. Z0 = 50 R1 130 R2 82 2.5V R2 R2 11356-026 VDD 3.3V 240 82 Figure 26. Thevenin Equivalent DC-Coupled LVPECL Termination Figure 29. DC-Coupled HCSL VDD VDD Z0 = 50 AD9578 LVPECL MODE 100 VDD = 2.5V OR 3.3V (SAME AS AD9578) VDD = 2.5V OR 3.3V LVPECL RECEIVER AD9578 33 Z0 = 50 CMOS (HIGH-Z) 200 11356-027 200 11356-029 Z0 = 50 Figure 27. AC-Coupled LVPECL Termination VDD Figure 30. DC-Coupled LVCMOS Termination VDD Z0 = 50 100 Z0 = 50 LVDS RECEIVER 11356-028 AD9578 LVDS Figure 28. AC-Coupled LVDS Rev. B | Page 19 of 44 11356-128 LVPECL Z0 = 50 AD9578 HCSL VDD R1 VDD 33 (OPTIONAL) AD9578 Data Sheet GETTING STARTED CHIP POWER MONITOR AND STARTUP The AD9578 monitors the voltage on the power supplies at power-up. When power supplies are greater than 2.1 V 0.1 V, the device generates an internal reset pulse, at which time, the AD9578 loads the values programmed in OTP memory. Do not use the SPI until 4 ms after power-up to ensure that all registers are correctly loaded from the OTP memory and that all internal voltages are stable. It is possible for the user to overwrite any value stored in the OTP memory if the security bits in Register 0x00 were not set at the time the OTP programming occurred. Take care not to overwrite the factory programmed calibrations (Register 11 through Register 14). When programming the device through the serial port, write unused or reserved bits to their default values as listed in the register map. DEVICE REGISTER PROGRAMMING USING A REGISTER SETUP FILE The evaluation software contains a programming wizard and a convenient graphical user interface that assists the user in determining the optimal configuration for the device. It generates a register setup file with a .STP extension that is easily readable using a text editor. These registers can be loaded directly into the AD9578. OTP PROGRAMMING The AD9578 has 444 bits of OTP memory. OTP stores the nonvolatile default configuration used on power-up. The default configuration is determined and programmed by the user. Use the SPI to overwrite these bits and change the operation of the AD9578 after power-up. The SPI Programming section describes how the bits affect the device operation and how to use the SPI to modify them. Rev. B | Page 20 of 44 Data Sheet AD9578 THEORY OF OPERATION PD1 FILTER1+ AD9578 FILTER1- OE1 REFSEL1 FRACTIONAL PLL1 OUT1 DIVIDER /4 TO /259 OUT2 DIVIDER /4 TO /259 XO3 OUT1 OE2 (3053MHz TO 3677MHz) OPTIONAL OUT1 REFERENCE MUX SELECT OUT2 OUT2 OEREF REF2 REFOUT XO4 REFOUT OE3 REFSEL2 OPTIONAL OUT3 FRACTIONAL PLL2 REF1 OE4 (3053MHz TO 3677MHz) OUT4 DIVIDER /4 TO /259 XO2 SPI AND OTP PROGRAMMABLE LOGIC CONTROL CS OUT3 SCK SDI FILTER2+ SDO/ LOL FILTER2- NOTES 1. IF SUPPLYING A SINGLE-ENDED 1.8V CMOS SIGNAL, CONNECT THE SIGNAL TO EITHER XO2 OR XO4. OUT4 OUT4 11356-034 XO1 OUT3 DIVIDER /4 TO /259 Figure 31. Detailed Block Diagram OVERVIEW The AD9578 is a dual synthesizer with four programmable outputs. Two PLLs, with either a crystal or external reference input frequency, produce up to four unique output frequencies. Output format standards on each output include LVCMOS, LVDS, LVPECL, and HCSL. The input crystal is a low cost fundamental mode type, and the AD9578 provides programmable gain and load capacitors. Alternatively, an input reference clock can be used for either or both PLLs. The crystal or external reference frequency is available on the REFOUT/REFOUT pins. The PLLs operate independently but may share the input reference, if desired. Three modes of operation can be selected: integer mode, fractional mode, and rational mode. The integer mode provides the lowest noise and behaves like a conventional PLL with whole number dividers. The fractional mode allows the feedback divider to have an 8-bit integer part and a 28-bit fractional part, resulting in a frequency resolution of 0.1 ppb or better. Rotary traveling wave oscillator (RTWO)-based VCOs operate at rates from 3053 MHz to 3677 MHz. Rational mode is similar to fractional mode, but allows the user to specify the feedback divider in terms of one integer divided by another. There are two output dividers on each VCO, with a range of 4 to 259. To prevent an output frequency gap between 750.8 MHz and 777.25 MHz, a special divide by 4.5 mode is also included. Any output frequency between 11.8 MHz and 919 MHz can be produced with a frequency error of 0.1 ppb or better. Additional features include loss of lock indicators, smooth change of output frequency for small frequency steps, and SPI control. The AD9578 can be configured through the SPI, factory programmed, user programmed, or any combination thereof. The AD9578 ships with a default power-up configuration programmed into OTP memory. All settings can be reprogrammed after power-up using the SPI. At offset frequencies below the PLL bandwidth (which is typically 300 kHz), the PLL tracks and multiplies the reference phase noise. The crystal input offers a very low phase noise reference, ensuring that the output phase noise near the carrier is low. When selecting the reference input signal, ensure that the phase noise of the reference input is low enough to meet the system noise requirements. Rev. B | Page 21 of 44 AD9578 Data Sheet PLL AND OUTPUT DRIVER CONTROL Table 14. Register 2 Bits Bits [23:16] Bit 7 Bit 6 Bit 5 Unused Bit 4 [15:8] OUTPUT4 Override OE4 pin OUTPUT3 Override OE3 pin [7:0] REFSEL2 REFSEL2 enable (set to 1 to enable REFSEL2) REFSEL1 REFSEL1 enable (set to 1 to enable REFSEL1) Bit 3 MR (master reset) OUTPUT2 PLL2 Bit 2 MR enable (set to 1 to enable MR) Override OE2 pin PLL2 enable (set to 1 to enable PLL2) Bit 1 REFOUT OUTPUT1 PLL1 Bit 0 REFOUT enable (override OEREF pin) Override OE1 pin PLL1 enable (override PD1 pin) Table 15. Register 4 Bits Bits [15:8] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 XTAL frequency trim XTAL Capacitance Value[2:0] OUTPUT4 Mode[1:0] OUTPUT3 Mode[1:0] Bit 3 Bit 2 Unused OUTPUT2 Mode[1:0] Bit 1 Bit 0 XTAL Gain[2:0] OUTPUT1 Mode[1:0] OVERVIEW Reading the Hardware OEx Pin States The AD9578 has five output drivers: OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4, and REFOUT. Each output can be individually configured as LVCMOS, LVDS, LVPECL, or HCSL. By default, the AD9578 OEx pins determine which outputs are enabled. If the corresponding override OEx pin bits are not set in Register 2, the user can read the states of these pins by reading Register 2. Note that the OE1, OE2, OE3, and OE4 pins have 75 k pull-up resistors. Each output has an output enable pin (OEx). Pin control of the outputs is enabled when the corresponding override OEx pin bit in Register 2 is low. When configured this way, the OUTPUTx bit is read only and indicates the status of the OEx pin. When the override OEx pin (where x = 1 to 4) bit is high, the OUTPUTx bit in Register 2 turns OUTPUTx on and off. See Table 14 for the contents of Register 2. The AD9578 ships with the default start-up output enable and output format functionality selected by the user. After powerup, the user can override the default programming through the SPI. PLL ENABLE/DISABLE Each output is enabled only if the associated PLL is powered up. Bits[3:0] in Register 2 control this function. There are two ways to power up/down PLL1. If the PLLx enable bit is 0, the user can power down PLL1 by pulling the PD1 pin low. If the PLLx enable bit is high, PLL1 is powered up/down using the PLL1 bit (Bit 1). PLL2 is under software control only. Therefore, always set Bit 2 to 1. The PLL2 bit (Bit 3) powers up/down PLL2. Disabling Hardware OEx Pin Control To disable the hardware pin control, the associated override OEx pin bit can be set in Register 2 (see Table 14). The override OEx pin bits are OTP, allowing the device to power up with any output forced on, forced off, or controlled by the OEx pin. In Register 2, when the override OEx pin bit is set to 1, the corresponding OEx pin is ignored, and the OUTPUTx bit enables or disables an input or output. To enable an output, both the override OEx pin bit and the OUTPUTx bit in Register 2 must be set to 1. Glitch-Free Output Enable When an output changes from disabled to enabled, there is an approximate 2 s delay before switching begins. During this delay, the outputs settle to the appropriate dc differential levels according to the configured mode. After this initial delay, the outputs begin toggling without glitches or runt pulses. Output Disable Sequence When an output changes from enabled to disabled, it stops switching at the appropriate dc levels according to the configured mode. After it has stopped switching, the biases are disabled and the output is set to high impedance. Rev. B | Page 22 of 44 Data Sheet AD9578 OUTPUT DRIVER FORMAT series termination resistor is recommended (see Figure 30). Place a series termination 33 resistor within 7 mm of the AD9578. A 50 transmission line configured this way is impedance matched. However, differential output modes are preferred over single-ended modes to preserve the high performance of the AD9578 and to reduce noise pickup and generation. The default power-up output mode is factory programmed to single-ended LVCMOS. The user can override the defaults using the serial port, and the drivers can be programmed simultaneously. Table 16. Output Driver Modes 1 OUTPUTx Mode[1:0] 00 01 10 11 1 Output Mode LVCMOS LVDS LVPECL HCSL OUTPUT CONFIGURATION EXAMPLE Table 17 and Table 18 show how Register 2 and Register 4, respectively, are used to configure the AD9578 inputs and outputs. PLL1 and PLL2 are enabled so that the output drivers connected to them are also enabled. To disable any output through the SPI, the corresponding override OEx pin bit and OUTPUTx bit must be set to 1 and 0, respectively. This prevents any condition of the external OEx pin from affecting the state of the output driver. In OTP programming, setting the override bit to 1 disables the output pin permanently. The OE1 and OE2 pins are ignored, OUTPUT1 is enabled and in LVCMOS mode, and OUTPUT2 is disabled. The OE3 and OE4 pins determine the state of OUTPUT3 and OUTPUT4, respectively. The REFOUT driver is disabled, OUTPUT3 is LVDS, and OUTPUT4 is LVPECL. Note that all of the output modes are differential except LVCMOS mode. When LVCMOS is selected, the positive output pin is LVCMOS, and the negative (complementary) output pin is high impedance. The LVCMOS output driver mode can be used for output frequencies 250 MHz, and a The X in Table 17 and Table 18 indicates that the register bit is not related to output driver configuration. Table 17. Example of Output Driver Configuration Using Register 2 Bits [23:16] Bit 7 Bit 6 [15:8] OUTPUT4 = X REFSEL2 = X Override OE4 pin = 0 REFSEL2 enable = X [7:0] Bit 5 Unused = XXXX OUTPUT3 = X REFSEL1 = X Bit 4 Override OE3 pin = 0 REFSEL1 enable = X Bit 3 MR (master reset) = 0 OUTPUT2 = 0 PLL2 = 1 Bit 2 MR enable =1 Override OE2 pin = 1 PLL2 enable =1 Bit 1 REFOUT = 0 OUTPUT1 =1 PLL1 = 1 Bit 0 REFOUT enable (override OEREF pin) = 1 Override OE1 pin = 1 PLL enable (override PD1 pin) = 1 Table 18. Example of Output Driver Configuration Using Register 4 Bits [15:8] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 XTAL1 frequency trim = X XTAL1 Capacitance Value[2:0] = XXX OUTPUT4 Mode[1:0] = 10 OUTPUT3 Mode[1:0] = 01 Rev. B | Page 23 of 44 Bit 3 Bit 2 Bit 1 Bit 0 Unused = X XTAL1 Gain[2:0] = XXX OUTPUT2 Mode[1:0] = XX OUTPUT1 Mode[1:0] = 00 AD9578 Data Sheet REFERENCE INPUT Table 19. Register 2 Bits Bits [23:16] Bit 7 Bit 6 Bit 5 Unused Bit 4 [15:8] OUTPUT4 Override OE4 pin OUTPUT3 Override OE3 pin [7:0] REFSEL2 REFSEL2 enable (set to 1 to enable REFSEL2 bit) REFSEL1 REFSEL1 enable (set to 1 to enable REFSEL1 bit) Bit 3 MR (master reset) OUTPUT2 PLL2 Bit 2 MR enable (set to 1 to enable MR bit) Override OE2 pin PLL2 enable (set to 1 to enable PLL2 bit) Bit 1 REFOUT Bit 0 REFOUT enable (override OEREF pin) Override OE1 pin OUTPUT1 PLL1 enable (override PD1 pin) (set to 1 to enable PLL1 bit) PLL1 Table 20. Register 3 Bits Bits [31:24] Bit 7 Bit 6 REFOUT mode[1:0] [23:16] [15:8] Bit 5 Unused Bit 4 Enable activity detect (set to 1) Unused Unused [7:0] LVCMOS Edge Trim[2:0] Bit 3 Reference mux select Enable OUTPUT4 divider Enable OUTPUT4 4.5 mode Bit 1 Enable OUTPUT3 divider Enable OUTPUT3 4.5 mode Enable OUTPUT2 divider Enable OUTPUT2 4.5 mode Exponent[3:0] Two reference inputs are available for the PLLs. The user can connect either a crystal or an input clock to the XO1/XO2 pins or the XO3/XO4 pins. The allowable reference input logic types are 1.8 V LVCMOS, ac-coupled LVDS, and ac-coupled LVPECL. The crystal oscillators accept standard crystals from 22 MHz to 54 MHz. Either reference can be used by either PLL through the internal selectors. Likewise, either reference can be buffered to the REFOUT driver, which supports LVCMOS, LVDS, LVPECL, or HCSL format. OTP fuses are available to automatically load the user settings loaded each time the chip powers up or resets. Register 2 contains the reference input control bits, Bits[7:4], and is shown in Table 19. Register 3 contains the configuration bits for the input reference buffer, and reference output, shown in Table 20. See the PLL and Output Driver Control section for information about the control of the reference output buffer. REFERENCE INPUT Table 21. PLL1 Reference Selection Register 2 REFSEL1 Enable 0 1 1 X = don't care. REFSEL1 X1 0 1 Register 3 Enable XTAL1 X1 X1 X1 Bit 0 Unused Enable OUTPUT1 divider Enable OUTPUT1 4.5 mode Mantissa[3:0] OVERVIEW 1 Bit 2 Enable XTAL1 PLLx Reference Reference 1 (XO1, XO2) Reference 1 (XO1, XO2) Reference 2 (XO3, XO4) Table 22. PLL2 Reference Selection Register 2 REFSEL2 Enable 0 1 1 1 REFSEL2 X1 0 1 Register 10 Enable XTAL2 X1 X1 X1 PLLx Reference Reference 1 (XO1, XO2) Reference 1 (XO1, XO2) Reference 2 (XO3, XO4) X = don't care. CRYSTAL OSCILLATOR AMPLIFIER ENABLE The crystal oscillator amplifier is automatically enabled when either the PLLx or REFOUT bit in Register 2 uses the crystal oscillator for either Reference 1 or Reference 2. Otherwise, the crystal oscillator amplifier is disabled if neither the PLLx nor REFOUT bit selects that input. However, this setting can be overridden with the enable XTAL1 bit in Register 3 and enable XTAL2 bit in Register 10. Setting these bits forces the corresponding crystal oscillator on. These bits are useful to allow a crystal to power up and stabilize before it is needed. However, these bits are usually set to 0 under normal operation. REFOUT/REFOUT SOURCE SELECTION The REFOUT/REFOUT pins can be used to buffer the crystal oscillator signal. Like the other outputs, it can be set to LVPECL, LVDS, HCSL, or LVCMOS format (see the PLL and Output Driver Control section for more information). Rev. B | Page 24 of 44 Data Sheet AD9578 CRYSTAL OSCILLATOR INPUTS Table 23. Register 4 Bits Bit Range [15:8] [7:0] Bit 7 Bit 6 Bit 5 Bit 4 XTAL1 frequency trim XTAL1 Capacitance Value[2:0] OUTPUT4 Mode[1:0] OUTPUT3 Mode[1:0] Bit 3 Bit 2 Unused OUTPUT2 Mode[1:0] Bit 1 Bit 0 XTAL1 Gain[2:0] OUTPUT1 Mode[1:0] Table 24. Register 10 Bits Bit Range Bit 7 [15:8] [7:0] XTAL2 frequency trim Bit 6 Bit 5 Bit 4 Bit 3 XTAL2 Capacitance Value[2:0] Sync Step[3:0] Bit 2 Bit 1 Bit 0 XTAL2 Gain[2:0] XTAL2 Enable Sync DIVN[3:0] OVERVIEW CRYSTAL OSCILLATOR GAIN The quartz crystal inputs, XO1/XO2 and XO3/XO4, accept standard 8 pF to 12 pF AT cut crystals from 22 MHz to 54 MHz. These inputs have programmable gain and programmable on-chip load capacitors so that a wide range of crystals can be used. Set the XTALx frequency trim bit in Register 4 and Register 10 if the crystal frequency is 33 MHz or lower. The recommended values for the bits in Register 4 and Register 10 are given in Table 25. In general, use the highest frequency crystal for lowest phase noise. If integer modes of PLL operation are possible, select the crystal such that the overall frequency multiplication is an integer value for lowest noise. XTAL Enable Setting the enable XTAL1 bit in Register 3 (for the crystal connected to the XO1/XO2 pins), or enable XTAL2 in Register 10 (for the crystal connected to the XO3/XO4 pins), and the REFSELx bit in Register 2 enables the second crystal oscillator. The second crystal oscillator (OSC2) is on Pin 45 and Pin 46, XO4 and XO3, respectively. OSC2 is useful if the crystal frequency on the first crystal oscillator (OSC1) results in an integer boundary spur; OSC2 can be set to a different frequency that does not cause an integer boundary. OSC2 is automatically enabled if it is selected and is disabled otherwise. Table 25. XTALx Gain[2:0] Values Crystal Frequency (MHz) 22 27 33 34 39 44 49 54 ESR = 25 0 1 2 1 2 3 4 5 XTALx Gain[2:0] ESR = ESR = 35 45 1 3 2 4 3 5 2 3 3 4 4 5 5 6 6 7 XTALx Frequency Trim Bit 1 1 1 0 0 0 0 0 CRYSTAL LOAD CAPACITORS The AD9578 has internal crystal load capacitors that are used as the load capacitance for an external crystal. XTALx Capacitance Value[2:0], Bits[14:12] in Register 4 (for the crystal connected to the XO1/XO2 pins) or Register 10 (for the crystal connected to the XO3/XO4 pins), set the on-chip load capacitance, as shown in Table 36. Rev. B | Page 25 of 44 AD9578 Data Sheet PLLs OVERVIEW Rational Mode The two PLLs in the AD9578 operate independently. Each PLL consists of an input reference frequency (which can be shared), a phase/frequency detector, loop filter, RTWO-based VCO, complex feedback divider and phase selector, and two output dividers. The feedback divider can operate in two distinct modes: integer and fractional. Rational mode allows the user to express the feedback divider as a ratio of rational numbers. Rational mode is enabled by setting the rational mode bit (Bit 2 in Register 7 (for PLL1) or Register 9 (for PLL2)) to 1. Using the AD9578 evaluation software is the easiest way to configure the AD9578. See the PLL Modes of Operation section for more information on the various register settings. S[1:0] S=0 S=1 S=2 S=3 In the PLL Modes of Operation section, the possible feedback divider settings is expressed in Q notation, QN.M, where N (the integer part) is eight bits and M (the fractional part) is 28 bits. The S[1:0] value represents the amount of phase interpolation used to represent a portion of the fractional part of the divider value. When S[1:0] = 3, there is no phase interpolation. When S[1:0] = 0, there is phase interpolation in 1/8 increments. PLL MODES OF OPERATION The PLLs on the AD9578 have three modes of operation: integer, fractional, and rational. In this section, PLLx refers to either PLL1 (whose settings are in Register 6 and Register 7) or PLL2 (whose settings are Register 8 and Register 9). The feedback divider has two parts: an 8-bit integer part and a 28-bit fractional part. The fractional part is modulated by a multistage noise shaping (MASH) modulator. The order of the MASH modulator is set in PLLx MASH[2:0] in Register 7 and Register 9, Bits[31:29]. Set the value of MASH[2:0] to 0 for integer mode, and 1 to 4 for fractional mode. Setting PLLx MASH[2:0] = 2 usually provides the lowest jitter for settings of PLLx Fractional Feedback Divider[27:0] greater than 2% from an integer. The value of S[1:0] is as follows: S[1:0] = 0, 1, and 2 results in eight, four, and two phases, respectively. Typically, a value of 0 for S[1:0] is best. Fractional Mode The fractional mode allows the feedback divider to take on a value of the Q notation, QN.M, where N (the integer part) is eight bits and M (the fractional part) is 28 bits. The VCO frequency divided by the feedback divider must always equal the reference frequency. FRAC fVCO = f IN x INT + 28 2 where: INT is PLLx Integer Feedback Divider[7:0] in Register 6 (for PLL1) or Register 8 (for PLL2). FRAC is PLLx Fractional Feedback Divider[27:0] in Register 6 (for PLL1) or Register 8 (for PLL2) Table 26. Rational Mode Feedback Divider Calculation 1 Feedback Divider (FBDIV)1 FBDIV = A + (1/8)(B + C/D) FBDIV = A + (1/4)(B + C/D) FBDIV = A + (1/2)(B + C/D) FBDIV = A + C/D PLLx Fractional Feedback Divider[27:25] B = 0, 1, ... , 7 (Bits[27:25]) B = 0, 1, 2, 3 (Bits[27:26]) B = 0, 1 (Bit 27) B ignored (Bits[27:25] = 000b) A is PLLx Integer Feedback Divider[7:0], C is PLLx Fractional Feedback Divider[24:9], D is PLLx Modulus Value[15:0]. Integer Mode Integer mode provides the lowest possible phase noise and behaves like a traditional integer PLL in which the feedback divisor is an integer. Integer mode is a special case of rational mode in which the rational mode bit is zero, and the C and D terms in Table 26 are 0. Integer mode is set when the following conditions are met: * * * * * PLLx MASH[2:0] = 000b PLLx Fractional Feedback Divider[24:0] = 0x000 If PLLx S[1:0] = 3 (no phase interpolation), PLLx Fractional Feedback Divider[27:25] must be zero. If PLLx S[1:0] = 2 (phase interpolation of 1/2 or 0) PLLx Fractional Feedback Divider[26:25] must be zero. If PLLx S[1:0] = 1, (phase interpolation of 1/4, 1/2, 3/4, or 0) PLLx Fractional Feedback Divider[25] must be zero. When programming integer mode with S[1:0] = 0, the AD9578 is in integer mode (with better noise performance), even though the feedback divider has a fraction (for example, 1/8, 2/8, 3/8). When using this mode, the user must reset the feedback divider by writing a 1 to Bit 14 of Register 7 (for PLL1) or Register 9 (for PLL2). NCO Functionality Fractional mode allows operation as a precision NCO, which offers the capability of digitally pulling the output frequency using precise numerical control. A digital alternative to analog VCXOs that pull the crystal using varactors, NCO functionality enables completely digitally controlled PLLs that trim the output frequency through the fast SPI bus. Precise numerical control enables PLL applications to be implemented digitally within FPGAs and other digital ICs. Writing the AD9578 registers using an SPI bus that runs at 100 MHz allows the AD9578 output frequency to be updated frequently. The continuous trimming range of the output is greater than 1000 ppm, resulting Rev. B | Page 26 of 44 Data Sheet AD9578 in better tracking range than is possible with analog VCXObased PLLs. The output frequencies change smoothly with no sudden phase step when the change to the feedback divider is small (for example, a change in phase or a few parts per million in frequency.) The change in the feedback divider is instantaneous, but the PLL response causes the PLL to change its frequency gradually. Thus, any changes small enough not to cause lock disturbance are smooth and continuous. VCO The VCO has 28 frequency bands. PLLx Frequency Select[4:0] in Register 7 (for PLL1) or Register 9 (for PLL2) selects the VCO band according to Table 27. Using the AD9578 evaluation software is the easiest way to ensure that these bits are set correctly. Table 27. VCO Frequencies and KVCO Band Settings PLLx Frequency Select[4:0]1 Dec Binary 0 00000 1 00001 2 00010 3 00011 4 00100 5 00101 6 00110 7 00111 8 01000 9 01001 10 01010 11 01011 12 01100 13 01101 14 01110 15 01111 16 10000 17 10001 18 10010 19 10011 20 10100 21 10101 22 10110 23 10111 24 11000 25 11001 26 11010 27 11011 1 VCO Min (MHz) 3642 3615 3583 3556 3532 3509 3486 3463 3440 3416 3391 3375 3360 3345 3307 3290 3268 3249 3228 3209 3189 3171 3154 3135 3119 3100 3084 3053 VCO Nom (MHz) 3654 3623 3597 3568 3542 3518 3496 3473 3450 3426 3402 3382 3366 3350 3322 3298 3278 3256 3237 3217 3198 3179 3161 3143 3126 3108 3091 3072 VCO Max (MHz) 3677 3642 3615 3583 3556 3532 3509 3486 3463 3440 3416 3391 3375 3360 3345 3307 3290 3268 3249 3228 3209 3189 3171 3154 3135 3119 3100 3084 PLLx KVCO Band 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PLLx Frequency Select[4:0] is in Register 0x07 for PLL1 and Register 0x09 for PLL2. 2 The PLLx K VCO band bits are in Register 0x0C for PLL1 and Register 0x0E for PLL2. The PLLx KVCO band bit (Bit 31 in Register 0x0C for PLL1 and Bit 31 in Register 0x0E for PLL2) must be set to 1 for PLLx Frequency Select[4:0] values between 14 and 27, and must be 0 for Frequency Select[4:0] values between 0 and 13. The reserved bits in Register 11, Register 12, Register 13, and Register 14 are factory calibrated values, and must not be changed. CHARGE PUMP The PLL charge pump current is programmed in Register 7 and Register 9, Bits[20:16], the CUR[4:0] value. CUR[4:0] can optimize the PLL bandwidth for minimum integrated phase noise. For crystals of approximately 50 MHz, CUR[4:0] values near 15 often produce the lowest noise. The AD9578 evaluation software generates these values for the user. See Table 29 for a variety of output frequencies and settings for PLLx MASH[2:0], S[1:0], and CUR[4:0] when using a 49.152 MHz crystal. OUTPUT DIVIDERS The output divider divides the RTWO frequency down to the required output frequency. There is one divider per output, and the divide ratios are located in Register 5 (see Table 28). Table 28. Output Divider Locations in Register 5 Bits [31:24] [23:16] [15:8] [7:0] Bits[7:0] OUTPUT4 OUTPUT3 OUTPUT2 OUTPUT1 Divider[7:0] Divider[7:0] Divider[7:0] Divider[7:0] The output divider has a range of 4 to 259. Writing 0x04 to Address 0xFF to the output divider results in a divide ratio that is the same as the value stored in the register. Writing 0x00 to Address 0x03 to the output divider results in a divide ratio of 256 to 259, respectively. For the special case of frequencies between 750 MHz and 778 MHz, which cannot be accessed with divide by 4 or divide by 5, a divide by 4.5 is provided. To divide by 4.5, set the enable OUTPUTx 4.5 mode bit in Register 3, Bits[11:8]. When the OUTPUTx 4.5 mode bit is set, the associated output divider ignores the value in Register 5 and divides by 4.5. LOSS OF LOCK INDICATOR The lock status of a PLL can be monitored via the PLLx lock detect bit in Register 0x0F, Bit 21 (for PLL1) or Bit 23 (for PLL2). A value of 1 indicates lock and is the normal condition. A value of 0 indicates out of lock, or the absence of an input reference. If the user programs Bit 0 of Register 6 (PLL1) and/or Register 8 (PLL2) to 1, the SDO/LOL pin changes function to the logical AND of the PLL1 and PLL2 loss of lock (LOL) function. RESETS If the PLLx MASH (Bits[31:29] in Register 7 for PLL1 or Register 9 for PLL2) is changed, issue a reset by toggling the reset feedback divider bit in Register 7 or Register 9, Bit 14. Rev. B | Page 27 of 44 AD9578 Data Sheet EXAMPLE VALUES FOR 49.152 MHZ CRYSTAL Table 29 shows the output frequency settings when using a 49.152 MHz crystal, TXC Part Number 8Z49100001, 2.5 mm x 2.0 mm, 49.152 MHz, 30 ppm, CL = 9 pF, maximum ESR = 50 . Table 29. Register Settings for Various Output Frequencies with a 49.152 MHz Crystal Output Frequency (MHz) 125.000000 155.520000 156.250000 159.375000 161.132813 164.355469 166.628571 167.331646 168.040678 172.642299 173.370748 174.105369 174.153733 174.703084 176.095145 176.838163 212.500000 425.000000 622.080000 625.000000 637.500000 644.531250 657.421875 666.514286 669.326582 672.162712 690.569196 693.482991 696.421478 696.614931 698.812335 704.380580 707.352650 PLLx Feedback Divider 71.207682292 69.609375 66.757202148 68.092346191 72.121620402 70.220232117 74.581473023 68.087421061 71.79472327 73.760747864 74.071974854 74.385838806 70.863335368 71.086866862 71.653297933 64.760069458 69.173177083 69.173177083 63.281250000 63.57828776 64.849853516 65.565109253 66.876411438 67.801339315 68.087420858 68.375926921 70.248331299 70.544737854 63.759290588 70.863335266 71.086866760 71.653297933 64.760069275 OUTPUTx Divider[7:0] 28 22 21 21 22 21 22 20 21 21 21 21 20 20 20 18 16 8 5 5 5 5 5 5 5 5 5 5 4.5 5 5 5 4.5 Frequency Select[4:0] 6 9 16 13 4 8 0 13 5 1 1 0 7 6 5 21 10 10 25 24 21 19 16 14 13 12 8 7 24 7 6 5 21 PLLx KVCO Band 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 Rev. B | Page 28 of 44 PLLx MASH[2:0] 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 3 2 2 2 2 2 2 S[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUR[4:0] 17 16 16 16 16 19 19 19 15 19 22 19 19 16 15 15 14 14 16 14 13 12 7 15 19 9 15 12 16 19 18 15 15 VCO Frequency (MHz) 3500 3421.44 3281.25 3346.875 3544.92189 3451.46485 3665.82856 3346.63292 3528.85424 3625.48828 3640.78571 3656.21275 3483.07466 3494.06168 3521.9029 3183.08693 3400 3400 3110.4 3125 3187.5 3222.65625 3287.10938 3332.57143 3346.63291 3360.81356 3452.84598 3467.41495 3133.89665 3483.07465 3494.06167 3521.9029 3183.08693 Data Sheet AD9578 SPI PROGRAMMING SCK is the clock input to the SPI. SDI is the data input to the SPI. Data must be valid on the rising edge of SCK. SDO is the data output from the SPI. OVERVIEW The AD9578 SPI bus transfers data in byte multiples. All transfers are most significant byte and most significant bit first. On the falling edge of CS, the SPI controller expects to see a series of eight SCK clock pulses and eight bits of data on SDI, valid through the rising edge of the clock. As shown in Figure 32, the first four bits are the operation code (opcode), and the last four bits are the register to be addressed. Table 30 contains the AD9578 opcodes that are used by the interface. At power-up, the AD9578 loads the values programmed in OTP memory. Thereafter, the SPI can be used to overwrite any value. Write 0 to unused or reserved bits, and do not overwrite factory programmed calibrations in Register 11 through Register 14. Note that throughout this data sheet, the multifunction SDO/LOL pin is referred to either by the entire pin name or by a single function of the pin, for example, SDO, when only that function is relevant. The default state on startup and when CS = high is Opcode 0 (OP[3:0] = 0000), or no operation. Opcode 2, the read opcode (OP[3:0] = 0010), is followed by one or more series of eight SCK pulses. Data from the register addressed by ADDR[3:0] appear on SDO most significant bit (MSB) first. The number of eight-pulse cycles is determined by the type of register defined at ADDR[3:0]. Opcode 1, the write opcode (OP[3:0] = 0001), is followed by one or more series of eight SCK pulses, with data to be written to the addressed register placed on SDI and valid at the rising edge of SCK. The new values take effect immediately after a write operation on the falling edge of the last SCK pulse. SPI DESCRIPTION The SPI is in reset on power-up. All fuse values are loaded into the SPI and those become the default configuration for the device. The SPI is inaccessible for the duration of the fuse reset cycle. Setting the CS pin high disables the SPI controller and resets it to its idle state. SDO is high impedance when CS is high. Setting CS to 0 enables the SPI controller (awaiting the control/address byte). In this mode, the controller responds to events on SCK. CS SCK OP[3] SDO OP[2] OP[1] OP[0] ADDR[3] ADDR[2] ADDR[1] ADDR[0] 11356-035 SDI SDO IS LOW DURING THE COMMAND AND ADDRESS INPUT CYCLES. Figure 32. Control and Address Byte Format READ (OPCODE 2) CYCLE: CS CS MUST BE HELD LOW THROUGH THE ENTIRE OPERATION ...REPEAT AS NECESSARY SCK SDO DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] tDV 11356-036 ANY DATA ON SDI ARE IGNORED SDI Figure 33. Opcode 2, Read Cycle WRITE (OPCODE 1) CYCLE: CS CS MUST BE HELD LOW THROUGH THE ENTIRE OPERATION ...REPEAT AS NECESSARY SCK SDO DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] SDO IS LOW DURING THE COMMAND AND ADDRESS INPUT CYCLES. Figure 34. Opcode 1, Write Cycle Rev. B | Page 29 of 44 11356-037 SDI AD9578 Data Sheet The precise timing of the OTP programming sequence is ensured by on-board circuitry, and is 800 s minimum per register. While either the OTP program or the fuse reset commands are executing, the SDO/LOL pin goes high, and it returns to zero at the end of the fuse reset or OTP program cycle. The host controlling the AD9578 must monitor the state of the SDO/LOL pin to determine when it may continue SPI communication. SPI communication from the host is ignored during OTP programming. Table 30. Opcode x Settings OP[3:0] ADDR[3:0] Operation/Command Opcode 0 Opcode 1 0000 0001 No operation Write data Opcode 2 0010 Opcode 3 Opcode 4 0011 0100 Ignored Register to be written Register to be read Ignored 0000 Opcode Opcode Opcode Opcode 0100 0100 0100 0101 5 6 7 8 Read data 0001 1110 1111 Register to be queried Do not use Fuse reset (reloads OTP programmed values) OTP program OTP program enable OTP program disable Query register length Registers labeled read only have no associated fuses. The Register Map Bit Descriptions section has details about which registers are read only. Security[15:0] are per register security bits. Setting the security bit for a register disables writing to that register so that values in the register can no longer be changed with SPI write commands. By disabling writing, OTP programing is also disabled. All OTP programing, including the security bits, can be performed at the same time. The new configuration settings for read/program bits, such as the security bits, is not applied until a fuse reset cycle or power cycle to the chip. That is, writing a 1 to Security[15:0] does not change the security setting, but writing a 1 to Security[15:0] followed by the OTP program and fuse reset commands does. Note that OTP programming the Security0 bit prevents further writing to Security[15:0] and, therefore, prevents any other security bits from being set in the future. Other than the security bit settings, there is no limitation to the number of times that the OTP program command can be executed. This allows an incremental approach in which certain registers are factory calibrated, preprogrammed, and optionally secured to prevent further modification. OTP PROGRAMMING The AD9578 has OTP registers so that a desired configuration can be programmed as the power-on default. All OTP programmable registers (except for those set at the factory) are initially set to the default values in the register map. The desired start-up configuration is programmed into the OTP bits by sending the OTP program command after the registers are set to their desired values. Note that the AD9578 must be powered at VDD = 3.3 V to perform OTP programming because the CS pin must never be more than 2.5 V above VDD. The CS pin has two functions: serial port chip select and OTP programming enable. To access the SPI normally, use the CS pin at normal digital LVCMOS levels (between 0 V and VDD.) To program the OTP, follow the OTP program procedure: Enable OTP programming by setting the CS pin to 5.5 V. Configure the SPI registers to the desired configuration. Send the OTP program enable command, Opcode 6. Send the OTP program command, Opcode 5. Send the OTP program disable command, Opcode 7. Set the CS pin back to 0 V. Send the fuse reset command, Opcode 4, to load the new register values. This final step is a verification of the OTP programming procedure. TRIP POINT AT 1.6V 5.0 CS 3.3 0 Changing the OTP default for a single register is difficult because the OTP programming sequence is not random access. To blow the fuse of a single bit, it is necessary to first send a fuse reset command to ensure that all registers contain default values. Then, change a single register bit and send the OTP program command, Opcode 5 (see Table 30). INTERNAL SIGNAL VOLTAGE (V) INTERNAL SIGNAL VOLTAGE (V) 1. 2. 3. 4. 5. 6. 7. VPROG 5.0 3.3 TRIP POINT AT 4.1V 0 0 3.3 5.0 0 VOLTAGE ON PIN (V) Figure 35. CS Pin Function Rev. B | Page 30 of 44 3.3 5.0 VOLTAGE ON PIN (V) 11356-039 Name Data Sheet AD9578 SPI Configuration The AD9578 can be programmed after power-up through the SPI. This section describes how to set a specific configuration in the SPI registers. 1. 2. 3. Prepare default values. The AD9578 evaluation software is an ideal way to determine the optimal default values of the AD9578 registers. Note that Register 0 and Register 1 are read only and cannot be changed. Enable all subsystems. This normally includes the per PLL values found in Register 0x06 (for PLL1) and Register 0x08 (for PLL2). They are the feedback divider PU (Bit 1), VCO PU (Bit 2), and ENPFD (Bit 3), as well as the enable activity detect bit, which is a global bit (Register 0x03, Bit 28). The enable XTAL1 (in Register 3) and enable XTAL2 (in Register 10) bits are normally set to 0 because the crystals 4. 5. Rev. B | Page 31 of 44 are enabled as necessary. Setting these to 1 forces the corresponding input on permanently. The following bits are internal resets, and cannot be OTP programmed. These bits are in three groups (global, PLL1, and PLL2) and must be 0 for normal device operation. The internal reset global bits are in Register 15. The PLL1 bits are in Register 7, Bits[11:15]. The PLL2 bits are in Register 9, Bits[11:15]. For each output to be used (OUTPUT1 through OUTPUT4 and REFOUT), select the mode according to Table 16, as well as the corresponding enable bits in Register 2 and Register 3. AD9578 Data Sheet REGISTER MAP The shaded cells in Table 31 indicate bit(s) that can be OTP programmed. See the OTP Programming section for more information. Table 31. Addr Name Register 0 0x00 Chip and manufacturer ID Register 1 0x01 Product ID, chip ID and user programming space Register 2 0x02 External pin readback and override Register 3 0x03 Reference buffer and divider, interpolated value increment Register 4 0x04 XTAL1 and output buffer configuration Register 5 0x05 Output driver configuration Register 6 0x06 PLL1 configuration Bits D7 D6 [31:24] [23:16] [15:8] [7:0] D5 REFSEL2 Override OE4 pin REFSEL2 enable (set to 1) REFOUT Mode[1:0] MR (master reset) OUTPUT3 REFSEL1 Unused [23:16] Unused [15:8] Unused [7:0] Exponent[3:0] [7:0] Manufacturer ID[10:8] Override OE3 pin REFSEL1 enable (set to 1) OUTPUT2 Enable activity detect Reference mux select Enable OUTPUT4 divider Enable OUTPUT4 4.5 mode XTAL1 XTAL1 Capacitance Value[2:0] frequency trim OUTPUT4 Mode[1:0] OUTPUT3 Mode[1:0] PLL2 MR enable (set to 1 to enable MR) Override OE2 pin PLL2 enable (set to 1) REFOUT OUTPUT1 PLL1 Enable XTAL1 Unused REFOUT enable (override OEREF pin) Override OE1 pin PLL1 enable (override PD1 pin) Unused Enable Enable OUTPUT3 OUTPUT2 divider divider Enable Enable OUTPUT3 OUTPUT2 4.5 mode 4.5 mode Mantissa[3:0] Enable OUTPUT1 divider Enable OUTPUT1 4.5 mode XTAL1 Gain[2:0] OUTPUT2 Mode[1:0] OUTPUT1 Mode[1:0] OUTPUT4 Divider[7:0] OUTPUT3 Divider[7:0] OUTPUT2 Divider[7:0] OUTPUT1 Divider[7:0] Rev. B | Page 32 of 44 ENPFD 0x03 0x10 0x00 0x00 0x00 0x00 0x00 0x10 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 PLL1 Integer Feedback Divider[7:0] PLL1 Fractional Feedback Divider[27:20] PLL1 Fractional Feedback Divider[19:12] PLL1 Fractional Feedback Divider[11:6] PLL1 Fractional Feedback Divider[3:0]; PLL1 Modulus Value[3:0] Default 0x7A 0x08 0x00 0x00 0x00 0x00 Product Revision[3:0] Unused [7:0] [39:32] [31:24] [23:16] [15:8] D0 User ID[31:24] User ID[23:16] User ID[15:8] User ID[7:0] OUTPUT4 [31:24] [23:16] [15:8] [7:0] D1 Product ID[7:0] [15:8] [7:0] D2 Unused Manufacturer ID[7:0] Security[15:8] Security[7:0] Chip ID[7:4] [23:16] [15:8] D3 Chip ID[3:0] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0] [31:24] D4 VCO PU PLL1 Fractional Feedback Divider[5:4]; PLL1 Modulus Value[5:4] Feedback PLL1 lock IRQ divider PU 0x00 0x00 0x00 0x00 0x0E Data Sheet Addr Name Register 7 0x07 PLL1 configuration AD9578 Bits D7 [39:32] [31:24] [23:16] PLL1 Dither[2:0] PLL1 MASH[2:0] Power-on S[1:0] override PLL1 Reset OUTPUT1_2 phase feedback reset advance divider [15:8] D6 D5 D4 [7:0] Register 8 0x08 PLL2 configuration [39:32] [31:24] [23:16] [15:8] [7:0] Register 9 0x09 PLL2 configuration [39:32] [31:24] [23:16] [15:8] [15:8] Force reset PLL1 Rational phase mode retard PLL1 Modulus Value[13:6] PLL2 Fractional Feedback Divider[3:0], PLL2 Modulus Value[3:0] PLL2 Dither[2:0] PLL2 MASH[2:0] Power-on S[1:0] override PLL2 Reset OUTPUT3_4 phase feedback reset advance divider XTAL2 frequency trim ENPFD Register 12 0x0C PLL1 KVCO band Register 13 0x0D Reserved Register 14 0x0E PLL2 KVCO band [31:24] 0x00 0x00 PLL2 Fractional Feedback Divider[5:4], PLL2 Modulus Value[5:4] Feedback PLL2 lock IRQ divider PU (SDO changes to IRQ) PLL2 Rational phase mode retard PLL2 Modulus Value[13:6] 0x00 0x00 0x00 0x00 0x0E 0x00 0x00 0x00 PLL2 Modulus Value[15:14] 0x00 0x00 XTAL2 Gain[2:0] Enable XTAL2 0x00 Reserved 0x00 configured; do not change) configured; do not change) configured; do not change) configured; do not change) Varies Varies Varies Varies Reserved Reserved (factory configured; do not change) Varies [23:16] [15:8] [7:0] Reserved (factory configured; do not change) Reserved (factory configured; do not change) Reserved (factory configured; do not change) Varies Varies Varies [31:24] [23:16] [15:8] [7:0] Reserved (factory Reserved (factory Reserved (factory Reserved (factory Varies Varies Varies Varies [31:24] PLL2 KVCO band [23:16] [15:8] [7:0] configured; do not change) configured; do not change) configured; do not change) configured; do not change) Reserved [23:16] [15:8] [7:0] Register 15 0x0F PLL lock detect (read only) VCO PU Default 0x00 0x00 0x00 PLL1 Modulus Value[15:14] Force reset Reserved (factory Reserved (factory Reserved (factory Reserved (factory PLL1 KVCO band D0 Dither Scale[4:0] PLL2 Frequency Select[4:0] CUR[4:0] XTAL2 Capacitance Value[2:0] [31:24] [23:16] [15:8] [7:0] D1 Dither Scale[4:0] PLL1 Frequency Select[4:0] CUR[4:0] [7:0] Register 11 0x0B Reserved D2 PLL2 Integer Feedback Divider[7:0] PLL2 Fractional Feedback Divider[27:20] PLL2 Fractional Feedback Divider[19:12] PLL2 Fractional Feedback Divider[11:6] [7:0] Register 10 0x0A XTAL2 configuration D3 Reserved (factory configured; do not change) Reserved (factory configured; do not change) Reserved (factory configured; do not change) Reserved (factory configured; do not change) PLL2 lock detect Reserved PLL1 lock detect Reserved Unused Unused Rev. B | Page 33 of 44 Revision Subcode[1:0] Varies Varies Reserved Varies 0x00 0x00 AD9578 Data Sheet REGISTER MAP BIT DESCRIPTIONS CHIP AND MANUFACTURER ID (REGISTER 0, ADDRESS 0x00) Table 32. Chip and Manufacturer ID Bits 31:28 Bit Name Chip ID[3:0] Description This register has no effect on device operation. The customer can use it for tracking different versions of device programming or identifying a chip on a printed circuit board. Including the four bits in Register 0x01, there are a total of eight bits for this function, and these values can be OTP programmed. 27 26:16 Unused Manufacturer ID[10:0] Security[15:0] Default = 0b. Manufacturer ID. These bits identify this chip as an Analog Devices IC and have no effect on device operation. 15:0 During the process of OTP programming, these bits control whether a given register becomes read only during future operation. There is one bit for each register. If the security bit for a given register is 1 during an OTP programming sequence, the corresponding register becomes read only, and the user can make no additional modifications to that register through the serial port. PRODUCT ID, CHIP ID, AND USER PROGRAMING SPACE (REGISTER 1, ADDRESS 0x01) Table 33. Product ID, Chip ID, and User Programing Space Bits 47:40 39:36 Bit Name Product ID[7:0] Chip ID[7:4] 35:32 Product Revision[3:0] 31:0 User ID[31:0] Description Product ID. This register has no effect on device operation. The customer can use it for tracking different versions of device programming or identifying a chip on a printed circuit board. Including the four bits in Register 0x00, there are a total of eight bits for this function, and these values can be OTP programmed. This read only register contains the AD9578 silicon revision information. Additional OTP programmable bits to program up to 32 bits of user assigned information. EXTERNAL PIN READBACK AND OVERRIDE (REGISTER 2, ADDRESS 0x02) Table 34. External Pin Readback and Override Bits 23:20 19 Bit Name Unused MR (master reset) 18 MR enable 17 REFOUT 16 REFOUT enable (override OEREF pin) Description Default = 0x0. This bit resets the chip. This bit is not self clearing. 1: the AD9578 is held in reset. MR enable (Bit 18 in this register) must be 1 for this bit to take effect. 0 (default): normal operation. This bit enables the MR (master reset) bit (Bit 19 in this register). 1: master reset is enabled. 0 (default): master reset (Bit 19 of this register) is disabled. This bit enables/disables the REFOUT driver. If REFOUT enable (Bit 16 in this register) = 1, this bit enables the REFOUT driver, as follows: 1: the REFOUT driver is enabled. 0 (default): the REFOUT driver is disabled. If REFOUT enable (Bit 16 in this register) = 0, this is a read only register, as follows: 1: the OEREF pin is high and the REFOUT driver is enabled. 0 (default): the OEREF pin is low and the REFOUT driver is disabled. This bit enables REFOUT (Bit 17 in this register). 1: the REFOUT bit controls the on/off state of the REFOUT driver. 0 (default): the OEREF pin controls the on/off state of the REFOUT driver. Rev. B | Page 34 of 44 Data Sheet Bits 15 Bit Name OUTPUT4 14 Override OE4 pin 13 OUTPUT3 12 Override OE3 pin 11 OUTPUT2 10 Override OE2 pin 9 OUTPUT1 8 Override OE1 pin 7 REFSEL2 6 REFSEL2 enable 5 REFSEL1 AD9578 Description This bit enables/disables the OUTPUT4 driver. Note that the user must enable PLL2 for the OUTPUT4 driver to be enabled. If override OE4 pin (Bit 14 in this register) = 1, this bit enables the OUTPUT4 driver, as follows: 1: the OUTPUT4 driver is enabled. 0 (default): the OUTPUT4 driver is disabled. If override OE4 pin (Bit 14 in this register) = 0, this is a read only register, as follows: 1: the OE4 pin is high and the OUTPUT4 driver is enabled. 0 (default): the OE4 pin is low and the OUTPUT4 driver is disabled. This bit enables the OUTPUT4 bit (Bit 15 in this register). 1: the OUTPUT4 bit controls the on/off state of the OUTPUT4 driver. 0 (default): the OE4 pin controls the on/off state of the OUTPUT4 driver. This bit enables/disables the OUTPUT3 driver. Note that the user must enable PLL2 for the OUTPUT3 driver to be enabled. If override OE3 pin (Bit 12 in this register) = 1, this bit enables the OUTPUT3 driver, as follows: 1: the OUTPUT3 driver is enabled. 0 (default): the OUTPUT3 driver is disabled. If override OE3 pin (Bit 12 in this register) = 0, this is a read only register, as follows: 1: the OE3 pin is high and the OUTPUT3 driver is enabled. 0 (default): the OE3 pin is low and the OUTPUT3 driver is disabled. This bit enables the OUTPUT3 bit (Bit 13 in this register). 1: the OUTPUT3 bit controls the on/off state of the OUTPUT3 driver. 0 (default): the OE3 pin controls the on/off state of the OUTPUT3 driver. This bit enables/disables the OUTPUT2 driver. Note that the user must enable PLL2 for the OUTPUT2 driver to be enabled. If override OE2 pin (Bit 10 in this register) = 1, this bit enables the OUTPUT2 driver, as follows: 1: the OUTPUT2 driver is enabled. 0 (default): the OUTPUT2 driver is disabled. If override OE2 pin (Bit 10 in this register) = 0, this is a read only register, as follows: 1: the OE2 pin is high and the OUTPUT2 driver is enabled. 0 (default): the OE2 pin is low and the OUTPUT2 driver is disabled. This bit enables the OUTPUT2 bit (Bit 11 in this register). 1: the OUTPUT2 bit controls the on/off state of the OUTPUT2 driver. 0 (default): the OE2 pin controls the on/off state of the OUTPUT2 driver. This bit enables/disables the OUTPUT1 driver. Note that the user must enable PLL2 for the OUTPUT1 driver to be enabled. If override OE1 pin (Bit 8 in this register) = 1, this bit enables the OUTPUT1 driver, as follows: 1: the OUTPUT1 driver is enabled. 0 (default): the OUTPUT1 driver is disabled. If override OE1 pin (Bit 8 in this register) = 0, this is a read only register, as follows: 1: the OE1 pin is high and OUTPUT1 is enabled. 0 (default): the OE1 pin is low and the OUTPUT1 driver is disabled. This bit enables the OUTPUT1 bit (Bit 9 in this register). 1: the OUTPUT1 bit controls the on/off state of the OUTPUT1 driver. 0 (default): the OE1 pin controls the on/off state of the OUTPUT1 driver. This bit controls which input is used by PLL2, provided that REFSEL2 enable (Bit 6 of this register) is 1. 1: PLL2 uses Reference 2 (which corresponds to the XO3/XO4 pins). 0: (default) PLL2 uses Reference 1 (which corresponds to the XO1/XO2 pins). This bit enables the REFSEL2 bit, and must be set to 1 for Bit 7 to function. 1: the REFSEL1 bit is enabled. 0 (default): the REFSEL1 bit is disabled. PLL2 uses Reference 1. This bit controls which input is used by PLL1, provided that REFSEL1 enable (Bit 4 of this register) is 1. 1: PLL1 uses Reference 2 (which corresponds to the XO3/XO4 pins). 0 (default): PLL1 uses Reference 1 (which corresponds to the XO1/XO2 pins). Rev. B | Page 35 of 44 AD9578 Data Sheet Bits 4 Bit Name REFSEL1 enable Description This bit enables the REFSEL1 bit, and must be set to 1 for Bit 5 to function. 1: the REFSEL1 bit is enabled. 0 (default): the REFSEL1 bit is disabled. PLL1 uses Reference 1. This bit enables/disables PLL2 when PLL2 enable (Bit 2 of this register) is 1. 1: PLL2 is enabled. 0 (default): PLL2 is disabled. This bit enables the PLL2 bit, and must be set to 1 for Bit 3 to function. 1: the PLL2 bit is enabled. 0 (default): the PLL2 bit is disabled. PLL2 is powered down. 3 PLL2 2 PLL2 enable 1 PLL1 This bit enables/disables PLL1. If PLL1 enable (Bit 0 in this register) = 1, this bit enables PLL1, as follows: 1: PLL1 is enabled. 0 (default): PLL1 is disabled. If PLL1 enable (Bit 0 in this register) = 0, this is a read only register, as follows: 1: the PD1 pin is high and PLL1 is enabled. 0 (default): the PD1 pin is low and PLL1 is disabled. 0 PLL1 enable (override PD1 pin) This bit enables the PLL1 bit (Bit 1 in this register). 1: the PLL1 bit controls the on/off state of PLL1. 0 (default): the PD1 pin controls the on/off state of PLL1. In this case, the PLL1 bit is read only and its value is the same as the state of the PD1 pin. REFOUT/OUTPUT DIVIDER ENABLE (REGISTER 3, ADDRESS 0x03) Table 35. Reference Buffer and Divider, Interpolated Value Increment Bits 31:30 Bit Name REFOUT Mode[1:0] 29 28 Unused Enable activity detect 27 Reference mux select 26 Enable XTAL1 25:20 19 Unused Enable OUTPUT4 divider Enable OUTPUT3 divider Enable OUTPUT2 divider 18 17 Description These bits set the mode of the REFOUT driver. 00 (default): 3.3 V LVCMOS (normal output only; complementary output is high-Z). 01: LVDS. 10: 3.3 V LVPECL. 11: HCSL. Set to 0. This bit enables the activity detectors. Always set this bit to 1 for normal operation. The activity detectors determine when an active clock signal is passing through a circuit inside of the chip. 1 (default): spot activity detector enabled. 0: spot activity detector disabled. (Do not use.) This bit controls which input is buffered to the REFOUT driver. 1: REFOUT uses Reference 2 (which corresponds to the XO3/XO4 pins). 0: (default) REFOUT uses Reference 1 (which corresponds to the XO1/XO2 pins). Set to 0 for normal operation. This bit enables the crystal oscillator connected to the XO1 and XO2 pins when this bit is set to 1. Note that the crystal oscillator is automatically enabled when Reference Input 1 is selected. Setting this bit to 1 keeps the oscillator enabled at all times, avoiding the crystal start-up delay when switching between crystal and reference inputs. Set to 0. This bit enables the OUTPUT4 divider. Set this bit whenever the corresponding output buffer is enabled. This bit enables the OUTPUT3 divider. Set this bit whenever the corresponding output buffer is enabled. This bit enables the OUTPUT2 divider. Set this bit whenever the corresponding output buffer is enabled. Rev. B | Page 36 of 44 Data Sheet AD9578 Bits 16 Bit Name Enable OUTPUT1 divider Description This bit enables the OUTPUT1 divider. Set this bit whenever the corresponding output buffer is enabled. 15:12 11:8 Unused Enable OUTPUTx 4.5 mode 7:4 Exponent[3:0] 3:0 Mantissa[3:0] Set to 0. For the special case of frequencies between 750 MHz and 778 MHz, which cannot be accessed with divide by 4 or divide by 5, a divide by 4.5 is provided. To divide by 4.5, set the enable OUTPUTx 4.5 mode bit (where x is an integer from 1 to 4). When the OUTPUTx 4.5 mode bit is set, the associated output divider ignores the OUTPUTx Divider[7:0] value in Register 5 and divides by 4.5. If a new value is presented to the fractional-N divider, the change is interpolated in steps equal in size to the value of mantissa << exponent, that is, the value of the Mantissa[3:0] bits shifted up by the exponent bits. If Mantissa[3:0] is 0, the new value takes effect immediately. Allowable values are 0d to 15d for Exponent[3:0], with 1d having the smallest step size and the most gradual change in the fractional feedback divider. If a new value is presented to the fractional-N divider, the change is interpolated in steps equal in size to the value of mantissa << exponent, that is, the value of the mantissa bits shifted up by the exponent bits. If Mantissa[3:0] is 0, the new value takes effect immediately. Allowable values are 0d to 15d for Mantissa[3:0] with 1d having the smallest step size and the most gradual change in the fractional feedback divider. XTAL1 AND OUTPUT BUFFER CONFIGURATION (REGISTER 4, ADDRESS 0x04) Table 36. XTAL1 and Output Buffer Configuration Bits 15 14:12 Bit Name XTAL1 frequency trim XTAL1 Capacitance Value[2:0] 11 10:8 Unused XTAL1 Gain[2:0] 7:6 OUTPUT4 Mode[1:0] 5:4 OUTPUT3 Mode[1:0] 3:2 OUTPUT2 Mode[1:0] Description This is an additional gain trim bit for the crystal oscillator. Setting XTAL frequency trim = 1 is recommended for optimal performance with crystal frequencies 33 MHz. See Table 25. These register bits control the amount of internal load capacitance on the XO1 and XO2 pins. The correct setting can be determined using the following equation: 2 x (CLOAD - CSTRAY) where CLOAD is the specified load capacitance of the crystal used, and CSTRAY is the stray capacitance (usually 2 pF to 5 pF) on the circuit board. XTAL1 Capacitance C LOAD of Crystal Recommended Internal Capacitance on XO1/XO2 Pins Value[2:0] (pF) (Assuming 3 pF Stray Capacitance) (pF) 000 8 10 001 9 12 010 10 14 011 11 16 100 12 18 101 13 20 110 14 22 111 15 24 These are gain trim bits for the crystal oscillator. Optimal performance is achieved when the gain is programmed according to the ESR of the crystal. See Table 25. These bits set the mode of OUTPUT4. 00 (default): 3.3 V LVCMOS (normal output only; complementary output is high-Z). 01: LVDS. 10: 3.3 V LVPECL. 11: HCSL. These bits set the mode of OUTPUT3. 00 (default): 3.3 V LVCMOS (normal output only; complementary output is high-Z). 01: LVDS. 10: 3.3 V LVPECL. 11: HCSL. These bits set the mode of OUTPUT2. 00 (default): 3.3 V LVCMOS (normal output only; complementary output is high-Z). 01: LVDS. 10: 3.3 V LVPECL. 11: HCSL. Rev. B | Page 37 of 44 AD9578 Bits 1:0 Bit Name OUTPUT1 Mode[1:0] Data Sheet Description These bits set the mode of OUTPUT1. 00 (default): 3.3 V LVCMOS (normal output only; complementary output is high-Z). 01: LVDS. 10: 3.3 V LVPECL. 11: HCSL. OUTPUT DRIVER CONFIGURATION (REGISTER 5, ADDRESS 0x05) Table 37. Output Driver Configuration Bits 31:24 Bit Name OUTPUT4 Divider[7:0] 23:16 OUTPUT3 Divider[7:0] 15:8 OUTPUT2 Divider[7:0] 7:0 OUTPUT1 Divider[7:0] Description The value of the OUTPUT4 divider. As an 8-bit decimal value, n, the VCO frequency is divided by n, where n = 4 to 255, and divided by 256 + n, where n = 0 to 3. The value of the OUTPUT3 divider. As an 8-bit decimal value, n, the VCO frequency is divided by n, where n = 4 to 255, and divided by 256 + n, where n = 0 to 3. The value of the OUTPUT2 divider. As an 8-bit decimal value, n, the VCO frequency is divided by n, where n = 4 to 255, and divided by 256 + n, where n = 0 to 3. The value of the OUTPUT1 divider. As an 8-bit decimal value, n, the VCO frequency is divided by n, where n = 4 to 255, and divided by 256 + n, where n = 0 to 3. PLL1 CONFIGURATION (REGISTER 6, ADDRESS 0x06) Table 38. PLL1 Configuration Bits 39:32 31:10 Bit Name PLL1 Integer Feedback Divider[7:0] PLL1 Fractional Feedback Divider[27:6] 9:4 PLL1 Fractional Feedback Divider[5:0], PLL1 Modulus Value[5:0] 3 ENPFD 2 VCO PU 1 Feedback divider PU 0 PLL1 lock IRQ Description PLL1 integer feedback divider. This is a fixed point value that contains the integer portion of the feedback divider. The smallest allowable value of the PLL1 feedback divider is 23. PLL1 fractional feedback divider, Bits[27:6]. If PLL1 is in fractional mode, all 28 bits in the PLL1 fractional feedback divider are used. If PLL1 is in integer mode, the first three bits in this register can be used either for phase interpolation or for MASH modulation, according to the value of S[1:0]. In fractional mode, at full phase interpolation, the fractional portion of the PLL1 feedback divider is 28 bits, for a resolution of 1/(2 28 ), or 3.7 x 10 -9 , or approximately 4 ppb. In fractional mode, this register contains Bits[5:0] of the PLL1 fractional feedback divider. In rational mode, this register contains Bits[5:0] of the PLL1 modulus value. This register is not used in integer mode; do not set the bits in this register to 0 in integer mode. This bit controls the power supplies to the charge pump and phase frequency detector. Keep this bit set to 1, the default setting. These subsystems are automatically disabled whenever the corresponding PLL is powered down via the PD1 pin. This bit controls the power supplies to the VCO. Keep this bit set to 1, the default setting. This subsystem is automatically disabled whenever the corresponding PLL is powered down via the PD1 pin. This bit controls the power supplies to the feedback divider. Keep this bit set to 1, the default setting. This subsystem is automatically disabled whenever the corresponding PLL is powered down via the PD1 pin. This bit sets the function of the SDO/LOL pin. 0 (default): the SDO/LOL pin function is serial data output (SDO). 1: the SDO/LOL pin function is IRQ, which is used as a loss of lock (LOL) indicator. Rev. B | Page 38 of 44 Data Sheet AD9578 PLL1 CONFIGURATION (REGISTER 7, ADDRESS 0x07) Table 39. PLL1 Configuration Bits 39:37 Bit Name PLL1 Dither[2:0] 36:32 Dither Scale[4:0] 31:29 PLL1 MASH[2:0] 28:24 PLL1 Frequency Select[4:0] 23 22:21 Power-on override S[1:0] 20:16 CUR[4:0] 15 PLL1 phase advance 14 Reset feedback divider OUTPUT1_2 reset 13 Description Order of dither generation. When PLL1 Dither[2:0] is 0, there is no dithering. All nonzero values create dither of the value stored in PLL1 Dither[2:0]. Dither is a noise shaped random value that is added to the divider fractional value at each calculation of the modulation, which helps to disperse harmonic spurs resulting from short modulation sequences. The time average value of dither is always zero, so that the use of dither does not change the divider value. The use of dither is highly dependent upon the choice of value for Dither Scale[4:0]. For normal operation, always set PLL1 Dither[2:0] to zero when PLL1 MASH[2:0] is zero. The largest usable value of PLL1 Dither[2:0] is 5. Typically, the value of PLL1 Dither[2:0] is set equal to the value of PLL1 MASH[2:0]. Dither scale. The dither scale, in bits. The dither value is a signed value of one to five bits in length, depending on the value chosen for PLL1 Dither[2:0]. To be effective, this value must be scaled up until the amount of dither is equal to 1/2 LSB of the divider value. The proper dither scale value for the dither is therefore equal to the number of zeros following the last bit set to 1 in the feedback divider value. Because the dither is a signed value, Dither Scale[4:0] must always be larger than the PLL1 Dither[2:0] setting. The order of MASH modulation. When PLL1 MASH[2:0] = 0, there is no modulation. Any fractional value given to the feedback divider that is at a finer resolution than the phase interpolation, S[1:0], results in an inaccurate output frequency. For all nonzero values of PLL1 MASH[2:0], modulation is used unless the feedback divider does not require modulation to be represented exactly (for example, if the feedback divider is an integer number). Modulation means that the feedback divider alternates between floor(PLL1 Fractional Feedback Divider[27:0]) and ceiling(PLL1 Fractional Feedback Divider[27:0]) according to a pattern whose time averaged value is PLL1 Fractional Feedback Divider[27:0]. When PLL1 MASH[2:0] = 1, first-order modulation is used. First-order modulation typically has large noise spurs due to the short length of the modulation patterns. Noise decreases as a function of PLL1 MASH[2:0], although for values of PLL1 MASH[2:0] greater than 2, this effect may not be measurable. The largest usable value of PLL1 MASH[2:0] is 4. This 5-bit value sets the frequency range of the VCO. Smaller values correspond to higher frequency. The evaluation software sets the optimal value; therefore, the user does not normally need to change this register. Table 27 contains the frequency ranges for each register setting. Note that the PLL1 KVCO band bit in Register 0x0C must be set to 1 for Frequency Select[4:0] = 14 through 27 (decimal). When set to 1, this bit, one for each PLL, disables the simultaneous synchronization pulses sent to PLL1 and PLL2 during the power-up cycle. Otherwise, both PLL outputs are synchronized at startup. The order of phase interpolation. When S[1:0] = 0, a fractional divider is interpolated among eight phases; therefore, values down to 1/8 can be represented exactly, without modulation. When S[1:0] = 1, the value is interpolated among four phases. When S[1:0] = 2, the value is interpolated between two phases, and when S[1:0] = 3, there is no phase interpolation. For example, the feedback divider of 64.5 can be represented either by PLL1 MASH[2:0] = 0, S[1:0] = 2; or by PLL1 MASH[2:0] = 1, S[1:0] = 3. In both cases, the output frequency is the same. However, the phase noise characteristics of the two representations differ. The use of phase interpolation allows up to three bits greater precision in the feedback divider. A consequence of reducing the phase interpolation is the loss of bits at the end of PLL1 Fractional Feedback Divider[27:0]. For example, when S[1:0] = 2, the last bit of PLL1 Fractional Feedback Divider[27:0] is ignored. Each PLL has a current trim for the charge pump, with the current given by the equation (3.125 x (1 + CUR)) A, for a minimum current of 3.125 A at CUR[4:0] = 0, and a maximum current of 100 A at CUR[4:0] = 31. This bit, one for each PLL, is an active control that shifts the output of the VCO forward one of eight phases (1/8 cycle). This phase shift happens regardless of the S[1:0] setting for the PLL. The phase advance is edge triggered; therefore, no further phase advancement occurs until this bit is set back to 0 and raised again. This feature can be used to precisely align the phases of the two PLLs. This bit resets the feedback divider. Set and clear this bit if the order of the MASH is changed or if the feedback divider in Register 6 is changed. This bit resets the OUTPUT1 and OUTPUT2 output driver. This bit is normally set to 0, although it can be set and cleared to reset the OUTPUT1 and OUTPUT2 output drivers. 12 11 Force reset PLL1 phase retard This active signal forces a reset cycle that generates synchronization pulses for the outputs of each PLL. This bit is similar to the advance bit but shifts the output of the VCO backward one of eight phases. 10 Rational mode This bit sets the rational mode, the use of which is described in detail in the PLLs section. In rational mode, the feedback divider fractional part is a ratio of integers, with the numerator encoded in PLL1 Fractional Feedback Divider[24:9] in Register 6and the denominator encoded in PLL1 Modulus Value[15:6] of this register. Rev. B | Page 39 of 44 AD9578 Bits 9:0 Bit Name PLL1 Modulus Value[15:6] Data Sheet Description The first 10 bits of the 16-bit modulus value. When the 16-bit binary value is 0, the PLL1 Fractional Feedback Divider[27:0] value is interpreted as a 28-bit fixed point value. When PLL1 Modulus Value[15:0] is nonzero, and the rational mode bit is set, the feedback divider ratio is calculated by a complicated expression (see Table 26). In the simplest case, S[1:0] is set to 3 (no phase interpolation), and the feedback divider expression is PLL1 Fractional Feedback Divider[24:9] + (PLL1 Feedback Divider[24:9]/modulus), generating a feedback divider that is an exact ratio of integers. Note that having a numerator that is larger than the denominator is an invalid configuration. Also, note that the lower six bits of the modulus value are shared with the lowest six bits of PLL1 Feedback Divider[27:0], which are not otherwise used in rational mode. PLL2 CONFIGURATION (REGISTER 8, ADDRESS 0x08) Table 40. PLL2 Configuration Bits 39:32 31:10 Bit Name PLL2 Integer Feedback Divider[7:0] PLL2 Fractional Feedback Divider[27:6] 9:4 PLL2 Fractional Feedback Divider[5:0], PLL2 Modulus Value[5:0] 3 ENPFD 2 VCO PU 1 Feedback divider PU 0 PLL2 lock IRQ (SDO changes to IRQ) Description PLL2 integer feedback divider. This is a fixed point value that contains the integer portion of the feedback divider. The smallest allowable value of the PLL1 feedback divider is 23. PLL2 fractional feedback divider, Bits[27:6]. If PLL2 is in fractional mode, all 28 bits in the PLL2 fractional feedback divider are used. If PLL1 is in integer mode, the first three bits in this register can be used either for phase interpolation or for MASH modulation, according to the value of S[1:0]. In fractional mode at full phase interpolation, the fractional part of the PLL1 feedback divider is 28 bits, for a resolution of 1/(228 ), or 3.7 x 10 -9 , or approximately 4 ppb. In fractional mode, this register contains Bits[5:0] of the PLL2 fractional feedback divider. In rational mode, this register contains Bits[5:0] of the PLL2 modulus value. This register is not used in integer mode; do not set the bits in this register to 0 in integer mode. This bit controls the power supplies to the charge pump and phase frequency detector. Keep this bit set to 1, the default setting. These subsystems are automatically disabled whenever the corresponding PLL is powered down via the PD1 pin. This bit controls the power supplies to the VCO. Keep this bit set to 1, the default setting. This subsystem is automatically disabled whenever the corresponding PLL is powered down via the PD1 pin. This bit controls the power supplies to the feedback divider. Keep this bit set to 1, the default setting. This subsystem is automatically disabled whenever the corresponding PLL is powered down via the PD1 pin. This bit sets the function of the SDO/LOL pin. 0 (default): the SDO/LOL pin function is serial data output (SDO). 1: the SDO/LOL pin function is IRQ, which is used as a loss of lock (LOL) indicator. PLL2 CONFIGURATION (REGISTER 9, ADDRESS 0x09) Table 41. PLL2 Configuration Bits 39:37 Bit Name PLL2 Dither[2:0] 36:32 Dither Scale[4:0] Description Order of dither generation. When PLL2 Dither[2:0] is 0, there is no dithering. All nonzero values create dither of the value stored in PLL2 Dither[2:0]. Dither is a noise shaped random value that is added to the divider fractional value at each calculation of the modulation, which helps to disperse harmonic spurs resulting from short modulation sequences. The time average value of dither is always zero, so that the use of dither does not change the divider value. The use of dither is highly dependent upon the choice of value for Dither Scale[4:0]. For normal operation, always set PLL2 Dither[2:0] to zero when PLL2 MASH[2:0] is zero. The largest usable value of PLL2 Dither[2:0] is 5. Typically, the value of PLL2 Dither[2:0] is set equal to the value of PLL2 MASH[2:0]. Dither scale. The dither scale, in bits. The dither value is a signed value of one to five bits in length, depending on the value chosen for PLL2 Dither[2:0]. To be effective, this value must be scaled up until the amount of dither is equal to 1/2 LSB of the divider value. The proper dither scale value for the dither is therefore equal to the number of zeros following the last bit set to 1 in the feedback divider value. Because the dither is a signed value, Dither Scale[4:0] must always be larger than the PLL2 Dither[2:0] setting. Rev. B | Page 40 of 44 Data Sheet Bits 31:29 Bit Name PLL2 MASH[2:0] 28:24 PLL2 Frequency Select[4:0] 23 22:21 Power-on override S[1:0] 20:16 CUR[4:0] 15 PLL2 phase advance 14 Reset feedback divider OUTPUT3_4 reset 13 AD9578 Description The order of MASH modulation. When PLL2 MASH[2:0] = 0, there is no modulation. Any fractional value given to the feedback divider that is at a finer resolution than the phase interpolation, S[1:0], results in an inaccurate output frequency. For all nonzero values of PLL2 MASH[2:0], modulation is used unless the feedback divider does not require modulation to be represented exactly (for example, if the feedback divider is an integer number). Modulation means that the feedback divider alternates between floor(PLL2 Fractional Feedback Divider[27:0]) and ceiling(PLL2 Fractional Feedback Divider[27:0]) according to a pattern whose time averaged value is PLL2 Fractional Feedback Divider[27:0]. When PLL2 MASH[2:0] = 1, first-order modulation is used. First-order modulation typically has large noise spurs due to the short length of the modulation patterns. Noise decreases as a function of PLL2 MASH[2:0], although for values of PLL2 MASH[2:0] greater than 2, this effect may not be measurable. The largest usable value of PLL2 MASH[2:0] is 4. This 5-bit value sets the frequency range of the VCO. Smaller values correspond to higher frequency. The evaluation software sets the optimal value; therefore, the user does not normally need to change this register. Table 27 contains the frequency ranges for each register setting. Note that the PLL2 KVCO band bit in Register 0x0E must be set to 1 for PPL2 Frequency Select[4:0] = 14 through 27 (decimal). When set to 1, this bit, one for each PLL, disables the simultaneous synchronization pulses sent to PLL1 and PLL2 during the power-up cycle. Otherwise, both PLL outputs are synchronized at startup. The order of phase interpolation. When S[1:0] = 0, a fractional divider is interpolated among eight phases; therefore, values down to 1/8 can be represented exactly, without modulation. When S[1:0] = 1, the value is interpolated among four phases. When S[1:0] = 2, the value is interpolated between two phases, and when S[1:0] = 3, there is no phase interpolation. For example, the feedback divider of 64.5 can be represented either by PLL2 MASH[2:0] = 0, S[1:0] = 2; or by PLL2 MASH[2:0] = 1, S[1:0] = 3. In both cases, the output frequency is the same. However, the phase noise characteristics of the two representations differ. The use of phase interpolation allows up to three bits greater precision in the feedback divider. A consequence of reducing the phase interpolation is the loss of bits at the end of PLL2 Fractional Feedback Divider[27:0]. For example, when S[1:0] = 2, the last bit of PLL2 Fractional Feedback Divider[27:0] is ignored. Each PLL has a current trim for the charge pump, with the current given by the equation (3.125 x (1 + CUR)) A, for a minimum current of 3.125 A at CUR[4:0] = 0, and a maximum current of 100 A at CUR[4:0] = 31. This bit, one for each PLL, is an active control that shifts the output of the VCO forward one of eight phases (1/8 cycle). This phase shift happens regardless of the S[1:0] setting for the PLL. The phase advance is edge triggered; therefore, no further phase advancement occurs until this bit is set back to 0 and raised again. This feature can be used to precisely align the phases of the two PLLs. This bit resets the feedback divider. Set and clear this bit if the order of the MASH is changed or if the feedback divider in Register 8 is changed. This bit resets the OUTPUT3 and OUTPUT4 output driver. This bit is normally set to 0, although it can be set and cleared to reset the OUTPUT3 and OUTPUT4 output drivers. 12 11 Force reset PLL2 phase retard This active signal forces a reset cycle that generates synchronization pulses for the outputs of each PLL. This bit is similar to the advance bit but shifts the output of the VCO backward one of eight phases. 10 Rational mode 9:0 PLL2 Modulus Value[15:6] This bit sets the rational mode, the use of which is described in detail in the PLLs section. In rational mode, the feedback divider fractional part is a ratio of integers, with the numerator encoded in PLL2 Fractional Feedback Divider[24:9] in Register 8and the denominator encoded in PLL2 Modulus Value[15:6] of this register. The first 10 bits of the 16-bit modulus value. When the 16-bit binary value is 0, the PLL1 Fractional Feedback Divider[27:0] value is interpreted as a 28-bit fixed point value. When PLL1 Modulus Value[15:0] is nonzero, and the rational mode bit is set, the feedback divider ratio is calculated by a complicated expression (see Table 26). In the simplest case, S[1:0] is set to 3 (no phase interpolation), and the feedback divider expression is PLL1 Fractional Feedback Divider[24:9] + (PLL1 Feedback Divider[24:9]/modulus), generating a feedback divider that is an exact ratio of integers. Note that having a numerator that is larger than the denominator is an invalid configuration. Also, note that the lower six bits of the modulus value are shared with the lowest six bits of PLL1 Feedback Divider[27:0], which are not otherwise used in rational mode. Rev. B | Page 41 of 44 AD9578 Data Sheet XTAL2 CONFIGURATION (REGISTER 10, ADDRESS 0x0A) Table 42. XTAL2 Configuration Bits 15 Bit Name XTAL2 frequency trim 14:12 XTAL1 Capacitance Value[2:0] 14:12 XTAL2 Capacitance Value[2:0] 11:9 XTAL2 Gain[2:0] 8 Enable XTAL2 7:0 Reserved Description This is an additional gain trim bit for the second crystal oscillator. XTAL2 frequency trim = 1 is recommended for optimal performance with crystal frequencies 33 MHz. See Table 25. These register bits control the amount of internal load capacitance on the XO3 and XO4 pins. The correct setting can be determined using the following equation: 2 x (CLOAD - CSTRAY) where CLOAD is the specified load capacitance of the crystal used, and CSTRAY is the stray capacitance (usually 2 pF to 5 pF) on the circuit board. XTAL2 Capacitance C LOAD of Crystal Recommended Internal Capacitance on XO3/XO4 Pins Value[2:0] (pF) (Assuming 3 pF Stray Capacitance) (pF) 000 8 10 001 9 12 010 10 14 011 11 16 100 12 18 101 13 20 110 14 22 111 15 24 These register bits are identical to the ones in Register 3, except that they apply to XTAL2, which is connected to the XO3 and XO4 pins. These are gain trim bits for the second crystal oscillator. Optimal performance is achieved when the gain is programmed according to the ESR of the crystal. See Table 25. Setting the enable XTAL2 bit and the REFSELx bit allows the second crystal oscillator to be used as the PLLx reference. Reserved. Set to 0. RESERVED (REGISTER 11, ADDRESS 0x0B) Table 43. Reserved Bits 31:0 Bit Name Reserved Description Factory configured; do not change. PLL1 KVCO BAND (REGISTER 12, ADDRESS 0x0C) Table 44. PLL1 KVCO Band Bits 31 Bit Name PLL1 KVCO band 30:0 Reserved Description KVCO band for PLL1. When changing the PLL1 KVCO band bit, it is best to first read the entire register and then write the same values for other bits in this register. 0 (default): set to 0 if PLL1 Frequency Select[4:0] (Register 7, Bits[28:24]) is between 0 and 13. 1: set to 1 if PLL1 Frequency Select[4:0] (Register 7, Bits[28:24]) is between 14 and 27. Factory configured; do not change. Default: varies. RESERVED (REGISTER 13, ADDRESS 0x0D) Table 45. Reserved Bits 31:0 Bit Name Reserved Description Factory configured; do not change. Rev. B | Page 42 of 44 Data Sheet AD9578 PLL2 KVCO BAND (REGISTER 14, ADDRESS 0x0E) Table 46. PLL2 KVCO Band Bits 31 Bit Name PLL2 KVCO band 30:0 Reserved Description KVCO band for PLL2. When changing the PLL2 KVCO band bit, it is best to first read the entire register and then write the same values for other bits in this register. 0 (default): set to 0 if PLL2 Frequency Select[4:0] (Register 9, Bits[28:24]) is between 0 and 13. 1: set to 1 if PLL2 Frequency Select[4:0] (Register 9, Bits[28:24]) is between 14 and 27. Factory configured; do not change. Default: varies. PLL LOCK DETECT (REGISTER 15, ADDRESS 0x0F) Table 47. PLL Lock Detect (Read Only) Bits 23 Bit Name PLL2 lock detect 22 21 Reserved PLL1 lock detect 20:19 18:17 Reserved Revision Subcode[1:0] Reserved Unused 6 15:0 Description PLL2 lock detect. 0: PLL2 is not locked, possibly indicating the absence of an input reference, or that the PLL is misconfigured. 1: PLL2 is locked. PLL1 lock detect. 0: PLL1 is not locked, possibly indicating the absence of an input reference, or that the PLL is misconfigured. 1: PLL1 is locked. Set to 00b. This 2-bit value gives the mask variant of the AD9578. Default: 01b Default: 0x00 Set to 0. Rev. B | Page 43 of 44 AD9578 Data Sheet OUTLINE DIMENSIONS 7.10 7.00 SQ 6.90 0.30 0.25 0.18 37 36 48 1 0.50 BSC 5.70 5.60 SQ 5.50 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-004452 SEATING PLANE 0.50 0.40 0.30 24 PIN 1 INDICATOR 13 BOTTOM VIEW 0.20 MIN 5.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4. 02-29-2016-A PIN 1 INDICATOR Figure 36. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Very Thin Quad (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9578BCPZ AD9578BCPZ-REEL7 AD9578/PCBZ 1 Temperature Range -25C to +85C -25C to +85C -25C to +85C Package Description 48-Lead LFCSP_VQ Tube 48-Lead LFCSP_VQ Tape and Reel Evaluation Board Z = RoHS Compliant Part. (c)2014-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11356-0-1/17(B) Rev. B | Page 44 of 44 Package Option CP-48-13 CP-48-13 CP-48-13