1/17
¡ Semiconductor MSM514400D/DL
DESCRIPTION
The MSM514400D/DL is a 1,048,576-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM514400D/DL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
single-layer metal CMOS process. The MSM514400D/DL is available in a 26/20-pin plastic SOJ, 20-
pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514400DL (the low-power version) is specially
designed for lower-power applications.
FEATURES
• 1,048,576-word ¥ 4-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input : TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
• Fast page mode, read modify write capability
•CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options:
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514400D/DL-xxSJ)
20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514400D/DL-xxZS)
26/20-pin 300 mil plastic TSOP
(TSOPII26/20-P-300-1.27-K)
(Product : MSM514400D/DL-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
¡ Semiconductor
MSM514400D/DL
1,048,576-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM514400D/DL-70 70 ns 130 ns
90 ns
440 mW
550 mW 5.5 mW/
Family Access Time (Max.) Cycle Time
(Min.) Standby (Max.)
Power Dissipation
MSM514400D/DL-50
t
RAC
50 ns
35 ns
t
AA
25 ns
20 ns
t
CAC
13 ns
20 ns
t
OEA
13 ns
MSM514400D/DL-60 60 ns 110 ns 495 mW
30 ns 15 ns 15 ns
Operating (Max.)
1.1 mW (L-version)
E2G0023-17-41
This version: Jan. 1998
Previous version: May 1997
2/17
¡ Semiconductor MSM514400D/DL
PIN CONFIGURATION (TOP VIEW)
Pin Name Function
A0 - A9 Address Input
RAS Row Address Strobe
CAS Column Address Strobe
DQ1 - DQ4 Data Input/Data Output
OE Output Enable
WE Write Enable
V
CC
Power Supply (5 V)
V
SS
Ground (0 V)
3
4
5
9
10
11
12
13
WE
RAS
A9
A0
A1
A2
A3
V
CC
24
23
22
18
17
16
15
14
DQ3
CAS
OE
A8
A7
A6
A5
A4
2
DQ2 25 DQ4
1
DQ1 26 V
SS
3
5
7
11
13
15
17
19
DQ3
V
SS
DQ2
A0
A2
V
CC
A5
A7
4
6
8
12
14
16
18
20
DQ4
DQ1
WE
A1
A3
A4
A6
A8
1
OE 2CAS
9RAS
26/20-Pin Plastic SOJ
3
4
5
9
10
11
12
13
WE
RAS
A9
A0
A1
A2
A3
V
CC
24
23
22
18
17
16
15
14
DQ3
CAS
OE
A8
A7
A6
A5
A4
2
DQ2 25 DQ4
1
DQ1 26 V
SS
10 A9
20-Pin Plastic ZIP 26/20-Pin Plastic TSOP
(K Type)
3/17
¡ Semiconductor MSM514400D/DL
BLOCK DIAGRAM
Timing
Generator
RAS
CAS
Timing
Generator
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
A0 - A9
V
CC
V
SS
On Chip
V
BB
Generator
Row
De-
coders
Word
Drivers
Memory
Cells
Refresh
Control Clock
Sense
Amplifiers
Column
Decoders
Write
Clock
Generator
I/O
Selector
Output
Buffers
WE
OE
4
DQ1 - DQ4
4
44
4
4
Input
Buffers
4
10
10
10
10
4/17
¡ Semiconductor MSM514400D/DL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Recommended Operating Conditions
Capacitance
*: Ta = 25°C
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
T
Symbol
I
OS
P
D
*
T
opr
T
stg
–1.0 to 7.0
50
1
0 to 70
–55 to 150
Rating
mA
W
°C
°C
Parameter
V
Unit
Power Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
Symbol
V
SS
V
IH
V
IL
5.0
0
—
—
Typ.Parameter
4.5
0
2.4
–1.0
Min.
5.5
0
6.5
0.8
Max.
(Ta = 0°C to 70°C)
V
Unit
V
V
V
Input Capacitance (A0 - A9)
Input Capacitance (RAS, CAS, WE, OE)
Output Capacitance (DQ1 - DQ4)
C
IN1
Symbol
C
IN2
C
I/O
6
7
7
Max.
pF
Unit
pF
pF
Parameter
(V
CC
= 5 V ±10%, Ta = 25°C, f = 1 MHz)
—
—
—
Typ.
5/17
¡ Semiconductor MSM514400D/DL
DC Characteristics
Parameter
Symbol
Condition
MSM514400
D/DL-50
MSM514400
D/DL-60
MSM514400
D/DL-70
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
IOH = –5.0 mAOutput High Voltage
IOL = 4.2 mAOutput Low Voltage
0 V £ VI £ 6.5 V;
All other pins notInput Leakage Current
under test = 0 V
DQ disable
Output Leakage Current 0 V £ VO £ 5.5 V
RAS, CAS cycling,
Average Power
tRC = Min.
Supply Current
(Operating)
RAS, CAS = VIH
Power Supply RAS, CAS
Current (Standby)
RAS cycling,Average Power
CAS = VIH,Supply Current
tRC = Min.(RAS-only Refresh)
RAS = VIH,
Power Supply CAS = VIL,
Current (Standby) DQ = enable
Average Power
CAS before RAS
Supply Current
(CAS before RAS Refresh)
RAS = VIL,Average Power
CAS cycling,Supply Current
tPC = Min.(Fast Page Mode)
tRC = 125 ms,
Average Power
VOH
VOL
ILI
ILO
ICC1
ICC2
ICC3
ICC5
ICC6
ICC7
ICC10 CAS before RAS,
Supply Current
tRAS £ 1 ms
(Battery Backup)
≥ VCC –0.2 V
Min.
2.4
0
–10
–10
—
—
—
—
—
—
—
—
—
Max.
VCC
0.4
10
10
100
2
1
100
5
100
80
300
200
Min.
2.4
0
–10
–10
—
—
—
—
—
—
—
—
—
Max.
VCC
0.4
10
10
90
2
1
90
5
90
70
300
200
Min.
2.4
0
–10
–10
—
—
—
—
—
—
—
—
—
Max.
VCC
0.4
10
10
80
2
1
80
5
80
60
300
200
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
1, 2
1
1, 2
1
1, 2
1, 3
1, 4,
5
1, 5
RAS cycling,
Notes : 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
4. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.
5. L-version.
6/17
¡ Semiconductor MSM514400D/DL
AC Characteristics (1/2)
Parameter
Random Read or Write Cycle Time
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
MSM514400
D/DL-60
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from OE
Output Low Impedance Time from CAS
Transition Time
Refresh Period
Refresh Period (L-version)
RAS Precharge Time
RAS Pulse Width (Fast Page Mode)
RAS Hold Time
CAS Precharge Time (Fast Page Mode)
CAS Pulse Width
RAS Pulse Width
CAS Hold Time
CAS to RAS Precharge Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from RAS
Column Address to RAS Lead Time
Access Time from CAS Precharge
OE to Data Output Buffer Turn-off Delay Time
RAS Hold Time referenced to OE
Note
4, 5, 6
4, 5
4, 6
4
7
3
5
6
4
7
4
RAS Hold Time from CAS Precharge
CAS to Data Output Buffer Turn-off Delay Time
Symbol
t
RC
t
RWC
t
PC
t
PRWC
t
RAC
t
CAC
t
AA
t
OEA
t
CLZ
t
OFF
t
T
t
REF
t
REF
t
RP
t
RAS
t
RASP
t
RSH
t
CP
t
CAS
t
CSH
t
CRP
t
RCD
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
AR
t
RAL
t
CPA
t
OEZ
t
ROH
t
RHCP
Min.
110
150
40
80
—
—
—
—
0
0
3
—
—
40
60
60
15
10
15
60
5
20
15
0
10
0
15
50
30
—
0
15
35
Max.
—
—
—
—
60
15
30
15
—
15
50
16
128
—
10,000
100,000
—
—
10,000
—
—
45
30
—
—
—
—
—
—
35
15
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
130
180
45
95
—
—
—
—
0
0
3
—
—
50
70
70
20
10
20
70
5
20
15
0
10
0
15
55
35
—
0
20
40
Max.
—
—
—
—
70
20
35
20
—
20
50
16
128
—
10,000
100,000
—
—
10,000
—
—
50
35
—
—
—
—
—
—
40
20
—
—
Max.
—
—
—
—
50
13
25
13
—
13
50
16
128
—
10,000
100,000
—
—
10,000
—
—
37
25
—
—
—
—
—
—
30
13
—
—
Min.
90
131
35
76
—
—
—
—
0
0
3
—
—
30
50
50
13
10
13
50
5
20
15
0
10
0
10
45
25
—
0
10
30
MSM514400
D/DL-70
MSM514400
D/DL-50
7/17
¡ Semiconductor MSM514400D/DL
AC Characteristics (2/2)
Symbol
Parameter
Read Command Set-up Time tRCS
Read Command Hold Time tRCH
MSM514400
D/DL-60
Read Command Hold Time referenced to RAS
Write Command Set-up Time
Write Command Hold Time
Write Command Hold Time from RAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Set-up Time
tRRH
tWCS
tWCH
tWCR
tWP
tRWL
tCWL
tDS
Data-in Hold Time tDH
Data-in Hold Time from RAS tDHR
CAS to WE Delay Time tCWD
Column Address to WE Delay Time tAWD
RAS to WE Delay Time
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)
RAS to CAS Hold Time (CAS before RAS)
WE to RAS Precharge Time (CAS before RAS)
WE Hold Time from RAS (CAS before RAS)
RAS to WE Set-up Time (Test Mode)
RAS to WE Hold Time (Test Mode)
tRWD
tRPC
tCSR
tCHR
tWRP
tWRH
tWTS
tWTH
OE Command Hold Time tOEH
OE to Data-in Delay Time tOED
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
CAS Precharge WE Delay Time tCPWD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
0
0
0
0
10
45
10
15
15
0
15
50
35
50
80
10
5
10
10
10
10
10
15
15
55
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
0
0
0
0
10
50
10
20
20
0
15
55
45
60
95
10
5
10
10
10
10
10
20
20
65
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
0
0
0
0
10
40
10
13
13
0
10
45
36
48
73
10
5
10
10
10
10
10
13
13
53
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSM514400
D/DL-70
MSM514400
D/DL-50 Note
8
8
9
9
9
9
9
10
10
8/17
¡ Semiconductor MSM514400D/DL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ t CWD (Min.) , tRWD ≥ t RWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not
used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
9/17
¡ Semiconductor MSM514400D/DL
,
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
OH
V
OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,,
,
t
RC
t
RAS
t
RP
t
AR
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
Row Column
t
RCS
t
RRH
t
RCH
t
AA
t
ROH
t
OEA
t
CAC
t
RAC
t
OEZ
t
OFF
Open
t
CLZ
Valid Data-out
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
IH
V
IL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,,,,
t
RC
t
RAS
t
RP
t
AR
t
CRP
t
RCD
t
CSH
t
RSH
t
CRP
t
CAS
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
Row Column
t
WCS
t
WCH
t
WCR
t
DHR
t
DS
t
DH
Valid Data-in
t
WP
t
RAL
Open
t
CWL
t
RWL
TIMING WAVEFORM
Read Cycle
Write Cycle (Early Write)
E2G0094-17-41G
10/17
¡ Semiconductor MSM514400D/DL
Read Modify Write Cycle
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
I/OH
V
I/OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,
,,
t
RWC
t
RAS
t
RP
t
AR
t
CRP
t
CSH
t
RCD
t
CRP
t
RSH
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
Row Column
t
CWD
t
CWL
t
RWD
t
RWL
t
WP
t
AA
t
AWD
t
OEA
t
OED
t
CAC
t
RAC
t
OEZ
t
DS
t
DH
t
CLZ
Valid
Data-out
Valid
Data-in
t
RAD
t
RCS
t
OEH
11/17
¡ Semiconductor MSM514400D/DL
Fast Page Mode Read Cycle
Fast Page Mode Write Cycle (Early Write)
"H" or "L"
RAS
CAS
VIH
VIL
–
–
VIH
VIL
–
–
DQ VIH
VIL
–
–
Address VIL
–
–
WE VIH
VIL
–
–
,
,
,
tRASP tRP
tAR
tCRP tRCD
tCAS
tCP tCAS
tRSH
tCRP
tCAS
tASR tRAH tCAH
tCSH tASC tCAH tASC tCAH
tRAL
Row Column Column Column
tRAD
tWCS tWCH
tWP
tWCS tWCH
tWP
tWCS tWCH
tWP
tDS tDH tDS tDH tDS tDH
Valid Data-in Valid
Data-in
Valid
Data-in
tDHR
Note: OE = "H" or "L"
VIH
tASC
tPC tRHCP
tCP
tCWL tCWL tRWL
tCWL
tWCR
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
OH
V
OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,
,
,
,
,
,
t
RASP
t
RP
t
AR
t
CRP
t
RCD
t
PC
t
RSH
t
CRP
t
CAS
t
CAS
t
CP
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
CSH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
Row Column Column Column
t
RCS
t
RCH
t
RCS
t
RCS
t
RCH
t
AA
t
OEA
t
AA
t
AA
t
RRH
t
OEA
t
OEA
t
CAC
t
RAC
t
OFF
t
OEZ
t
CAC
t
CLZ
t
OFF
t
OEZ
t
CAC
t
CLZ
t
OEZ
t
OFF
t
CLZ
Valid
Data-out
Valid
Data-out
Valid
Data-out
t
RHCP
t
CP
t
RCH
t
CPA
t
CPA
12/17
¡ Semiconductor MSM514400D/DL
Fast Page Mode Read Modify Write Cycle
t
WP
RAS
CAS
Address
OE
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
DQ V
I/OH
V
I/OL
–
–
,
,
,
,
,
,
,
t
RASP
t
AR
t
RP
t
CSH
t
PRWC
t
RSH
t
RCD
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
CRP
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
t
RAL
Row Column Column Column
t
RWD
t
RCS
t
CWD
t
CWL
t
CWD
t
CWL
t
CWD
t
RWL
t
CWL
t
AWD
t
AWD
t
AWD
t
OEA
t
WP
t
OEA
t
WP
t
OEA
t
AA
t
OED
t
CAC
t
DS
t
DH
t
CAC
t
AA
t
RAC
t
DS
t
DH
t
CPA
t
OED
t
CAC
t
AA
t
DS
t
DH
t
CLZ
t
CLZ
t
CLZ
Out In Out OutIn In
t
ROH
t
OEZ
t
OEZ
t
CPA
t
OED
t
RCS
t
RCS
t
CPWD
t
CPWD
"H" or "L"
t
OEZ
RAS-Only Refresh Cycle
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
Address V
IH
V
IL
–
–
,
t
RC
t
RAS
t
RP
t
CRP
t
RPC
t
ASR
t
RAH
Row
"H" or "L"
DQ V
OH
V
OL
–
–
Note: WE, OE = "H" or "L"
Open
t
OFF
13/17
¡ Semiconductor MSM514400D/DL
RAS
CAS
VIH
VIL
–
–
VIH
VIL
–
–
Column
Row
DQ VOH
VOL
–
–
WE VIH
VIL
–
–
OE VIH
VIL
–
–
Address VIH
VIL
–
–
,,
,
tRC tRC
tRAS tRP tRAS tRP
tAR
tCRP tRCD tRSH tCHR
tRAD
tASR
tASC
tRAH tCAH
tRCS tRAL tRRH
tAA
tROH
tOEA
tCAC
tCLZ
tRAC
tOFF
tOEZ
Valid Data-out
,
"H" or "L"
CAS before RAS Refresh Cycle
Hidden Refresh Read Cycle
PQRS
\]^
KLM
V
IH
V
IL
RAS
t
RP
–
–
CAS V
IH
V
IL
–
–
V
IH
V
IL
WE
V
V
t
RC
t
RAS
t
RPC
t
CHR
t
RP
t
RPC
t
CP
t
CSR
t
WRP
t
WRH
t
OFF
t
WRP
Open
–
–
OL
OH
–
–
DQ
Note: OE, Address = "H" or "L"
"H" or "L"
14/17
¡ Semiconductor MSM514400D/DL
Hidden Refresh Write Cycle
Test Mode Initiate Cycle
t
ASR
Row Column
V
IH
V
IL
RAS
Address
WE
CAS V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
–
–
–
–
–
–
–
–
t
CRP
t
RC
t
ASC
t
RP
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
RAH
t
RAL
DQ V
IH
V
IL
–
–
t
WCS
t
CHR
t
RAS
t
WRH
t
WRP
t
RC
t
RP
t
AR
OE V
IH
V
IL
–
–
t
DHR
,,,,
t
DS
,
t
WP
t
WCH
t
DH
Valid Data-in
"H" or "L"
V
IH
V
IL
RAS
CAS V
IH
V
IL
–
–
–
–
t
RAS
V
OH
V
OL
–
–
V
IH
V
IL
–
–
Open
t
RC
t
WTH
,
t
RPC
t
WTS
t
CP
t
CSR
t
CHR
t
OFF
Note: OE, Address = "H" or "L"
t
RP
WE
DQ
"H" or "L"
15/17
¡ Semiconductor MSM514400D/DL
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
SOJ26/20-P-300-1.27
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Mirror finish
16/17
¡ Semiconductor MSM514400D/DL
(Unit : mm)
ZIP20-P-400-1.27
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.50 TYP.
Mirror finish
17/17
¡ Semiconductor MSM514400D/DL
(Unit : mm)
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
TSOPII26/20-P-300-1.27-K
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.38 TYP.
Mirror finish
