K20P144M120SF3
K20 Sub-Family
Supports the following:
MK20FX512VLQ12,
MK20FN1M0VLQ12,
MK20FX512VMD12,
MK20FN1M0VMD12
Key features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 120 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Memories and memory interfaces
– Up to 1024 KB program flash memory on non-
FlexMemory devices
– Up to 512 KB program flash memory on
FlexMemory devices
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– NAND flash controller interface
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to
128 request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per
chip
• Human-machine interface
– Low-power hardware touch sensor interface
(TSI)
– General-purpose input/output
• Analog modules
– Four 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Four analog comparators (CMP) containing a 6-
bit DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Two 8-channel motor control/general purpose/
PWM timers
– Two 2-channel quadrature decoder/general
purpose timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
Freescale Semiconductor Document Number K20P144M120SF3
Data Sheet: Technical Data Rev 5, 10/2013
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012–2013 Freescale Semiconductor, Inc.
• Communication interfaces
– USB high-/full-/low-speed On-the-Go controller with ULPI interface
– USB high-/full-/low-speed On-the-Go controller with on-chip high speed transceiver
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– USB Device Charger detect
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital host controller (SDHC)
– Two I2S modules
K20 Sub-Family, Rev5, 10/2013.
2 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................5
1.1 Determining valid orderable parts......................................5
2 Part identification......................................................................5
2.1 Description.........................................................................5
2.2 Format...............................................................................5
2.3 Fields.................................................................................5
2.4 Example............................................................................6
3Terminology and guidelines......................................................6
3.1 Definition: Operating requirement......................................6
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................7
3.4 Definition: Rating...............................................................7
3.5 Result of exceeding a rating..............................................8
3.6 Relationship between ratings and operating
requirements......................................................................8
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................9
3.9 Typical value conditions....................................................10
4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................11
4.3 ESD handling ratings.........................................................11
4.4 Voltage and current operating ratings...............................11
5 General.....................................................................................12
5.1 AC electrical characteristics..............................................12
5.2 Nonswitching electrical specifications...............................12
5.2.1 Voltage and current operating requirements......12
5.2.2 LVD and POR operating requirements...............13
5.2.3 Voltage and current operating behaviors............14
5.2.4 Power mode transition operating behaviors.......16
5.2.5 Power consumption operating behaviors............17
5.2.6 EMC radiated emissions operating behaviors....20
5.2.7 Designing with radiated emissions in mind.........20
5.2.8 Capacitance attributes........................................21
5.3 Switching specifications.....................................................21
5.3.1 Device clock specifications.................................21
5.3.2 General switching specifications.........................21
5.4 Thermal specifications.......................................................23
5.4.1 Thermal operating requirements.........................23
5.4.2 Thermal attributes...............................................24
5.5 Power sequencing.............................................................24
6 Peripheral operating requirements and behaviors....................25
6.1 Core modules....................................................................25
6.1.1 Debug trace timing specifications.......................25
6.1.2 JTAG electricals..................................................26
6.2 System modules................................................................29
6.3 Clock modules...................................................................29
6.3.1 MCG specifications.............................................29
6.3.2 Oscillator electrical specifications.......................31
6.3.3 32 kHz oscillator electrical characteristics..........33
6.4 Memories and memory interfaces.....................................34
6.4.1 Flash (FTFE) electrical specifications.................34
6.4.2 EzPort switching specifications...........................38
6.4.3 NFC specifications..............................................39
6.4.4 Flexbus switching specifications.........................42
6.5 Security and integrity modules..........................................45
6.6 Analog...............................................................................45
6.6.1 ADC electrical specifications..............................45
6.6.2 CMP and 6-bit DAC electrical specifications......53
6.6.3 12-bit DAC electrical characteristics...................55
6.6.4 Voltage reference electrical specifications..........58
6.7 Timers................................................................................59
6.8 Communication interfaces.................................................59
6.8.1 USB electrical specifications...............................59
6.8.2 USB DCD electrical specifications......................60
6.8.3 USB VREG electrical specifications...................60
6.8.4 ULPI timing specifications...................................61
6.8.5 CAN switching specifications..............................62
6.8.6 DSPI switching specifications (limited voltage
range).................................................................62
6.8.7 DSPI switching specifications (full voltage
range).................................................................64
6.8.8 Inter-Integrated Circuit Interface (I2C) timing.....65
6.8.9 UART switching specifications............................66
6.8.10 SDHC specifications...........................................67
6.8.11 I2S/SAI switching specifications.........................68
6.9 Human-machine interfaces (HMI)......................................74
6.9.1 TSI electrical specifications................................74
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7 Dimensions...............................................................................75
7.1 Obtaining package dimensions.........................................75
8 Pinout........................................................................................76
8.1 Pins with active pull control after reset..............................76
8.2 K20 Signal Multiplexing and Pin Assignments..................76
8.3 K61 Signal Multiplexing and Pin Assignments..................82
8.4 K20 pinouts.......................................................................88
9 Revision History........................................................................90
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4 Freescale Semiconductor, Inc.
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK20 and MK20
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
K## Kinetis family • K20
A Key attribute • F = Cortex-M4 w/ DSP and FPU
M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory
FFF Program flash memory size • 512 = 512 KB
• 1M0 = 1 MB
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Ordering parts
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 5
Field Description Values
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC Maximum CPU frequency (MHz) • 12 = 120 MHz
N Packaging type • R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK20FN1M0VLQ12
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
Terminology and guidelines
K20 Sub-Family, Rev5, 10/2013.
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3.2.1 Example
This is an example of an operating behavior:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/
pulldown current
10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
Terminology and guidelines
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 7
3.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
3.6 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
Terminology and guidelines
K20 Sub-Family, Rev5, 10/2013.
8 Freescale Semiconductor, Inc.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
Terminology and guidelines
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 9
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Ratings
K20 Sub-Family, Rev5, 10/2013.
10 Freescale Semiconductor, Inc.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit
VDD Digital supply voltage1–0.3 3.8 V
IDD Digital supply current — 300 mA
VDIO Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2–0.3 5.5 V
VAIO Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
–0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB1_DP USB1_DP input voltage –0.3 3.63 V
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VUSB1_DM USB1_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. It applies for all port pins.
Ratings
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Freescale Semiconductor, Inc. 11
2. It covers digital pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
Table continues on the next page...
General
K20 Sub-Family, Rev5, 10/2013.
12 Freescale Semiconductor, Inc.
Table 1. Voltage and current operating requirements (continued)
Symbol Description Min. Max. Unit Notes
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage (digital pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage (digital pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis (digital pins) 0.06 × VDD — V
IICDIO Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V -5 — mA
IICAIO Analog2, EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC
injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
-5
—
—
+5
mA
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
-25
—
—
+25
mA
VODPU Open drain pullup voltage level VDD VDD V4
VRAM VDD voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
2. Open drain outputs must be pulled to VDD.
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
Table continues on the next page...
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K20 Sub-Family, Rev5, 10/2013.
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Table 2. LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±80 — mV
VLVDL Falling low-voltage detect threshold — low range
(LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period
factory trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
VOH Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT Output high current total for all ports — — 100 mA
IOHT_io60 Output high current total for fast digital ports — — 100 mA
VOL Output low voltage — high drive strength
—
—
0.5
V
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K20 Sub-Family, Rev5, 10/2013.
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Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
— — 0.5 V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1 mA
—
—
—
—
0.5
0.5
V
V
IOLT Output low current total for all ports — — 100 mA
IOLT_io60 Output low current total for fast digital ports — — 100 mA
IINA Input leakage current, analog pins and digital
pins configured as analog inputs
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
—
—
—
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
1,
IIND Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
• All digital pins
• VIN = VDD
• All digital pins except PTD7
• PTD7
—
—
—
0.002
0.002
0.004
0.5
0.5
1
μA
μA
μA
2,
IIND Input leakage current, digital pins
• VIL < VIN < VDD
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
18
12
8
3
26
19
13
6
μA
μA
μA
μA
2, 3,
IIND Input leakage current, digital pins
• VDD < VIN < 5.5 V
—
1
50
μA
2, 3
ZIND Input impedance examples, digital pins
• VDD = 3.6 V
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
2, 5
RPU Internal pullup resistors 20 — 50 kΩ 6
RPD Internal pulldown resistors 20 — 50 kΩ 7
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
General
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 15
2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
3. Internal pull-up/pull-down resistors disabled.
4. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. See
Figure 1.
5. Measured at VDD supply voltage = VDD min and Vinput = VSS
6. Measured at VDD supply voltage = VDD min and Vinput = VDD
Figure 2. 5 V Tolerant Input IIND Parameter
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
—
—
300
1.7 V / (VDD
slew rate)
μs
1
• VLLS1 → RUN — 160 μs
• VLLS2 → RUN — 114 μs
• VLLS3 → RUN — 114 μs
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Table 5. Power mode transition operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
• LLS → RUN — 5.0 μs
• VLPS → RUN — 5 μs
• STOP → RUN — 4.8 μs
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
51.1
51.7
160
162
mA
mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
75.2
75.9
175
177
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 35.7 60 mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
— 19.6 44 mA
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
1.3
3.0
7.5
3.8
27
42
mA
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 1.4 32 mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 2.2 38 mA
IDD_VLPW Very-low-power wait mode current at 3.0 V — 0.926 22 mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.25
0.85
2.4
1.3
7.6
12.54
mA
mA
mA
Table continues on the next page...
General
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 17
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.25
0.85
2.4
1.3
7.6
12.54
mA
mA
mA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
5.6
30.1
120.8
20
137
246
μA
μA
μA
6
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
3.2
11.8
51.2
14
40
60
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
2.8
8.7
39.3
12
29
43
μA
μA
μA
IDD_VBAT Average current when CPU is not accessing RTC
registers at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
—
—
0.91
1.5
4.3
1.1
1.85
4.3
μA
μA
μA
7
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
4. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. For
devices with 32 KB of RAM, power consumption is reduced by 3 μA.
7. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode is greater than 100 MHz frequencies.
General
K20 Sub-Family, Rev5, 10/2013.
18 Freescale Semiconductor, Inc.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
General
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 19
Figure 4. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol Description Frequency
band (MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 21 dBμV , ,
VRE2 Radiated emissions voltage, band 2 50–150 24 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 29 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 28 dBμV
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
General
K20 Sub-Family, Rev5, 10/2013.
20 Freescale Semiconductor, Inc.
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
CIN_D_io60 Input capacitance: fast digital pins — 9 pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock — 120 MHz
fSYS_USBFS System and core clock when Full Speed USB in
operation
20 — MHz
fSYS_USBHS System and core clock when High Speed USB in
operation
60 — MHz
fBUS Bus clock — 60 MHz
FB_CLK FlexBus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
FB_CLK FlexBus clock — 4 MHz
fFLASH Flash clock — 0.5 MHz
fLPTMR LPTMR clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
General
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 21
5.3.2 General switching specifications
These general purpose specifications apply to all pins configured for:
• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16 — ns 3
External reset pulse width (digital glitch filter disabled) 100 — ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
14
8
36
24
ns
ns
ns
ns
4
Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
14
8
36
24
ns
ns
ns
ns
5
tio50 Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
7
3
28
14
ns
ns
ns
ns
—
—
—
—
tio50 Port rise and fall time (low drive strength)
• Slew disabled
—
18
ns
—
—
Table continues on the next page...
General
K20 Sub-Family, Rev5, 10/2013.
22 Freescale Semiconductor, Inc.
Table 10. General switching specifications (continued)
Symbol Description Min. Max. Unit Notes
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
9
48
24
ns
ns
ns
—
—
tio60 Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
6
3
28
14
ns
ns
ns
ns
6
—
—
—
—
tio60 Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
18
6
48
24
ns
ns
ns
ns
7
—
—
—
—
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
6. 25 pF load
7. 15 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C
General
K20 Sub-Family, Rev5, 10/2013.
Freescale Semiconductor, Inc. 23
5.4.2 Thermal attributes
Board type Symbol Description 144 LQFP 144 MAPBGA Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient (natural
convection)
45 50 °C/W
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient (natural
convection)
36 30 °C/W 1
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
36 41 °C/W 1
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
30 27 °C/W 1
— RθJB Thermal
resistance,
junction to
board
24 17 °C/W
— RθJC Thermal
resistance,
junction to case
9 10 °C/W
—ΨJT Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
2 2 °C/W
5.5 Power sequencing
Voltage supplies must be sequenced in the proper order to avoid damaging internal
diodes. There is no limit on how long after one supply powers up before the next supply
must power up. Note that VDD and VDD_INT can use the same power source.
The power-up sequence is:
1. VDD
General
K20 Sub-Family, Rev5, 10/2013.
24 Freescale Semiconductor, Inc.