© 2009 Microchip Technology Inc. DS22121B-page 1
MCP23009/MCP23S09
Features
• 8-bit remote bidirectional I/O port:
- I/O pins default to input
• Open-drain outputs:
-5.5V tolerant
- 25 mA sink capable (per pin)
- 200 mA total
• High-speed I2C™ interface: (MCP23009)
- 100 kHz
- 400 kHz
-3.4MHz
• High-speed SPI interface: (MCP23S09)
-10MHz
• Single hardware addre ss pin: (MCP23009)
- Voltage input to allow up to eight devices on
the bus
• Configurable interrupt output pin s :
- Config urable as active-high, active-lo w or
open-drain
• Configurable interrupt source:
- Interrupt-on-change from configured defaults
or pin change
• Polarity inversion register to configure the polarity
of the input port data
• External reset input
• Low standby current:
- 1 µA (-40°C ≤ TA ≤ +85°C)
- 6 µA (+85°C ≤ TA ≤ +125°C)
• Operating voltage:
- 1.8V to 5.5V
Packages
16-pin QFN (3x3 [mm])
18-pin PDI P (300 mil)
18-pin SOIC (300 mil)
20-pin SSOP
Block Diagram
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
I2C
Control
GPIO
SCL
SDA
RESET
INT
8
Configuration/
8
Control
Registers
SPI
SI
SO
SCK
CS MCP23S09
ADDR
Serializer/
Deserializer
Multi-bit
Decode
MCP23009
8-Bit I/O Expander with Open-Drain Outputs
MCP23009/MCP23S09
DS22121B-page 2 © 2009 Microchip Technology Inc.
Package Types:
Package Types:
MCP23009
PDIP/SOIC QFN
VSS18 NC17 NC16 GP715 GP614 GP513 GP412
GP210
VDD 1
N/C 2
SCL 3
SDA 4
ADDR 5
RESET 6
INT 7
GP0 8GP311
GP1 9
GP6 15
GP7 16
VSS 1
VDD
2
NC
3
SCL 4
SDA 5
ADDR 6
RESET 7
GP312 GP211 GP110 GP09
INT 8
GP5 14
GP4 13
EP
17
VSS
20 NC
19 NC
18 GP7
17 GP6
16 GP5
15 GP4
14 GP3
13 GP2
12 NC
11
VDD 1
NC 2
SCL 3
SDA 4
ADDR 5
RESET 6
INT 7
GP0 8
GP1 9
NC 10
SSOP
* Includes Exposed Thermal Pad (EP); see Table 1-1 and.Table 1-2
MCP23S09
PDIP/SOIC QFN *
VSS18
NC17
GP716
GP615
GP514
GP413
GP312
GP110
VDD 1
NC 2
CS3
SCK 4
SI 5
SO 6
RESET 7
INT 8GP211
GP0 9
GP6 15
GP7 16
VSS 1
SCK 2
VDD 3
CS 4
SI 5
SO 6
RESET 7
GP312 GP211 GP110 GP09
INT 8
GP5 14
GP4 13
EP
17
* Includes Exposed Thermal Pad (EP); see Table 1-1 and.Table 1-2
© 2009 Microchip Technology Inc. DS22121B-page 3
MCP23009/MCP23S09
1.0 DEVICE OVERVIEW
The MCP23X09 device provides 8-bit, general purpose
parallel I/O expansion for I2C bus or SPI applications.
The two devices differ only in the serial interface.
• MCP23009 - I2C interface
• MCP23S09 - SPI interface
The MCP23X09 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
input or output register. The polarity of the input port
register can be inverted with the polarity inversion
register . All registers can be read by the system master .
The interrupt output can be configured to activate
under two conditions (mutually exclusive):
1. When any input state differs from its
corresponding input port register state. This is
used to indicate to the system master that an
input state has changed.
2. When an input state differs from a
pre-configured register value (DEFVAL
register).
The Interrupt Capture register captures port values at
the time of the interrupt, thereby saving the condition
that caused the interrupt.
The Power-on Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pin is used to determine the
device address.
MCP23009/MCP23S09
DS22121B-page 4 © 2009 Microchip Technology Inc.
1.1 Pin Descriptions
TABLE 1-1: I2C PINOUT DESCRIPTION (MCP23009)
Pin
Name
18LD
PDIP/
SOIC
16LD
QFN 20LD
SSOP Pin
Type Standard Functio n
VDD 131PPower
VSS 18 1 20 P Ground
SCL 3 4 3 I Serial clock input
SDA 4 5 4 I/O Serial data I/O
ADDR 5 6 5 I Hardware address pin allows up to 8 slave devices on the bus
RESET 6 7 6 I Hardware reset
INT 7 8 7 O Interrupt output for port. Can be configured as active high, active low,
or open-drain.
GP0 8 9 8 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
GP1 9 10 9 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
GP2 10 1 1 12 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
GP3 1 1 12 13 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
GP4 12 13 14 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
GP5 13 14 15 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
GP6 14 15 16 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
GP7 15 16 17 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can
be enabled for interrupt on change, and/or internal pull-up resistor.
NC 2, 16,
17 22,10,
11,19,1
8
Not connected
EP — 17 Exposed Thermal Pad (EP). Do not electrically connect. Can connect
to VSS.
© 2009 Microchip Technology Inc. DS22121B-page 5
MCP23009/MCP23S09
TABLE 1-2: SPI PINOUT DESCRIPTION (MCP23S09)
Pin
Name
18LD
PDIP/
SOIC
16LD
QFN Pin
Type Standard Function
VDD 1 3 P Power (high current capable)
VSS 18 1 P Ground (high current capable)
CS 34IChip select
SCK 4 2 I Serial clock input
SI 5 5 I Serial data input
SO 6 6 O Serial data out
RESET 7 7 I Hardware reset (must be externally biased)
INT 8 8 O Interrupt output for port. Can be configured as active high, active low, or open-drain.
GP0 9 9 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GP1 10 10 I/O Bidirectional I/O Pin (5.5 volt tolera nt inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GP2 11 11 I/O Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GP3 12 12 I/O Bidirectional I/O Pin (5.5 volt tolera nt inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GP4 13 13 I/O Bidirectional I/O Pin (5.5 volt tolera nt inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GP5 14 14 I/O Bidirectional I/O Pin (5.5 volt tolera nt inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GP6 15 15 I/O Bidirectional I/O Pin (5.5 volt tolera nt inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
GP7 16 16 I/O Bidirectional I/O Pin (5.5 volt tolera nt inputs; open-drain outputs). Can be enabled
for interrupt on change, and/or internal pull-up resistor.
NC 2, 17 — Not connected
EP — 17 — Exposed Thermal Pad (EP). Do not electrically connect, Can connect to VSS.
MCP23009/MCP23S09
DS22121B-page 6 © 2009 Microchip Technology Inc.
1.2 Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in the
electrical specification section.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
1.3 Serial Interface
This block handles the functionality of the I2C
(MCP23009) or SPI (MCP23S09) interface protocol.
The MCP23X09 contains eleven (11) individual
registers which can be addressed through the Serial
Interface block (Table 1-3).
TABLE 1-3: REGISTER ADDRESSES
1.3.1 BYTE MODE AND SEQUENTIAL
MODE
The MCP23X09 has the ability to operate in “Byte
Mode” or “Sequential Mode” (IOCON.SEQOP). Byte
mode and sequential mode are not to be confused with
I2C byte operations and sequential operations. The
modes explained here relate to the device’s internal
address pointer and whether or not it is incremented
after each byte is clocked on the serial interface.
Byte Mode disables automatic address pointer incre-
menting. When operating in Byte Mode, the
MCP23X09 does not increment its internal address
counter after each byte during the data transfer. This
gives the ability to continually access the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes or for continually writing to the output
latches.
Sequential Mode enables automatic address pointer
incrementing. When operating in Sequential Mode, the
MCP23X09 increments its address counter after each
byte during the data transfer. The address pointer
automatically rolls over to address 00h after accessing
the last register.
These two modes are not to be confused with single
writes/reads and continuous writes/reads which are
serial protocol sequences. For example, the device
may be configured for Byte Mode and the ma ster may
perform a continuous read. In this case, the
MCP23X09 would not increment the address pointer
and would repeatedly drive data from the same
location.
1.3.2 I2C INTERFACE
1.3.2.1 I2C Write Operation
The I2C write operation includes the control byte and
register address sequence, as sh own in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23009. The operation is ended with a stop (P)
or restart (SR) condition being generated by the
master.
Data is written to the MCP23009 after every byte
transfer. If a stop or restart condition is generated
during a data transfer , the dat a will not be written to the
MCP23009.
Both “byte mode” and “sequential mode” are supported
by the MCP23009. If sequential mode is enabled
(default), the MCP23009 increments its address
counter after each ACK during the data transfer.
1.3.2.2 I2C Read Operation
I2C read operations include the control byte sequence,
as shown in the bottom of Figure 1-1. This sequence is
followed by another control byte (including the Start
condition and ACK) with the R/W bit equal to a logic
one (R/W = 1). The MCP23009 then transmits the data
contained in the addressed register. The sequence is
ended with the master generating a Stop or Restart
condition.
1.3.2.3 I2C Sequential Write/Read
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 1.3.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).
The sequence ends with the master send ing a Stop or
Restart condition.
The MCP23009 address pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.
Address Access to:
00h IODIR
01h IPOL
02h GPINTEN
03h DEFVAL
04h INTCON
05h IOCON
06h GPPU
07h INTF
08h INTCAP (Read-only)
09h GPIO
0Ah OLAT
© 2009 Microchip Technology Inc. DS22121B-page 7
MCP23009/MCP23S09
1.3.3 SPI INTERFACE
The MCP23S09 operates in Mode 0,0 and Mode 1,1.
The difference between the two modes is the idle state
of the clock.
Mode 0,0: The idle state of the clock is LOW . Input data
is latched on the rising edge of the clock; output data is
driven on the falling edge of the cl ock.
Mode 1,1: The idle state of the clock is HIGH. Input
data is latched on the rising edge of the clock; output
data is driven on the falling edge of the clock.
1.3.3.1 SPI Write Operation
The SPI write operation is started by lowering CS. The
write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
1.3.3.2 SPI Read Operation
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bi t set) is
then clocked into the device. The opcode is followed by
an address, with at l east one data byte being clocked
out of the device.
1.3.3.3 SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the address pointer. (see Section 1.3.1
“Byte Mode and Sequential Mode” for details
regarding sequential ope ration control).
The sequence ends by the raising of CS.
The MCP23S09 address pointer will roll over to
address zero after reaching the last register address.
MCP23009/MCP23S09
DS22121B-page 8 © 2009 Microchip Technology Inc.
FIGURE 1-1: MCP23009 I2C™ DEVICE PROTOCOL
S
P
SR
w
R
OP
ADDR
DOUT
DIN
- Start
- Restart
- Stop
- Write
- Read
- Device opcode
- Device address
- Data out from MCP23009
- Data in to MCP230 0 9
SP
SR
W
R
OP ADDR DIN DIN
....
S
P
W
R
OP
ADDR
DOUT DOUT
.... P
SR WOP ADDR DIN
.... P
P
SR R
DOUT DOUT
....
P
OP DOUT DOUT
.... P
SR OP DOUT
....
P
OP
DIN
S PWOP ADDR DIN DIN
....
Byte and Sequential Write
S
W
OP SR R
OP
DOUT DOUT
.... P
Byte and Sequentia l Read
S WOP ADDR DIN P
S
WOP SR ROP
DOUT
P
Byte
Sequential
Byte
Sequential
ADDR
ADDR
© 2009 Microchip Technology Inc. DS22121B-page 9
MCP23009/MCP23S09
1.4 Multi-bit Address Decoder
The ADDR pin is used to se t the slave address of the
MCP23009 (I2C only) to allow up to eight devices on
the bus using only a single pin. Typically, this would
require three pins.
The multi-bit Address Decoder employs a basic FLASH
ADC architecture (Figure 1-4). The seven comparators
generate 8 unique values based on the analog input.
This value is converted to a 3-bit code which
corresponds to the address bits (A2, A1, A0) in the
serial OPCODE.
Sequence of Operation (see Figure 1-5 for
timings):
1. Upon power up (after VDD stabilizes) the module
becomes active after time tADEN. Note, the
analog value on the ADDR pin must be stable
before this point to ensure accurate address
assignment.
2. The 3-bit address is latche d after tADDRLAT.
3. The module powers down after the first rising
edge of the serial clock is detected (tADDIS).
Once the address bits are latched, the device will keep
the slave address until a POR or reset condition
occurs.
1.4.1 CALCULATING VOLTAGE ON ADDR
When calculating the required voltage on the ADDR pin
(V2), the set point should be the mid-point of the LSb of
the ADC.
The examples in Figure 1-2 and Figure 1-3 show how
to determine the mid point voltage (V2) and the range
of voltages based on a voltage divider circuit. The
maximum tolerance is 20%, however, it is
recommended to use 5% tolerance worst case (10%
total tolerance).
FIGURE 1-2: VOLTAGE DIVIDER EXAMPLE
R2
A0
A1
A2
V2
R1
VDD MCP23009 Only
VDD
VSS
VSS
ADDR
MCP23009/MCP23S09
DS22121B-page 10 © 2009 Microchip Technology Inc.
FIGURE 1-3: VOLTAGE AND CODE EXAMPLE
Assume:
n = A2, A1 , A0 in opcode
rati o = R2/ (R1+R2)
V 2 = v olt age on A DDR pin
V2(min) = V2 - (VDD / 8) x %tol eran ce
V2(max) = V2 + (VDD/8) x %t olerance
V
DD= 1.
8
n R2=2n+1 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max)
0 1 15 0.0625
0.113 0.00 0.14
1 3 13 0.1875 0.338 0.32 0.36
2 5 11 0.3125
0.563 0.54 0.59
3790.4375
0.788 0.77 0.81
4970.5625
1.013 0.99 1.04
5 11 5 0.6875
1.238 1.22 1.26
6 13 3 0.8125 1.463 1.44 1.49
7 15 1 0.9375
1.688 1.67 1.80
V
DD= 2.
7
n R2=2n+1 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max)
0 1 15 0.0625
0.169 0.00 0.19
1 3 13 0.1875 0.506 0.48 0.53
2 5 11 0.3125
0.844 0.82 0.87
3790.4375
1.181 1.16 1.20
4970.5625
1.519 1.50 1.54
5 11 5 0.6875 1.856
1.83 1.88
6 13 3 0.8125
2.194 2.17 2.22
7 15 1 0.9375
2.531 2.51 2.70
VDD= 3.3
n R2=2n+1 R1=16-R2 R2/(R1+R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.206 0.00 0.23
1 3 13 0.1875 0.619 0.60 0.64
2 5 11 0.3125 1.031 1.01 1.05
3790.4375
1.444 1.42 1.47
4970.5625
1.856 1.83 1.88
5 11 5 0.6875 2.269 2.25 2.29
6 13 3 0.8125 2.681 2.66 2.70
7 15 1 0.9375 3.094 3.07 3.30
VDD= 5.5
n R2=2n+1 R1=16-R2 R2/(R1+R2)
V
2
V
2(min)
V
2(max)
0 1 15 0.0625 0.344 0.00 0.37
1 3 13 0.1875
1.031 1.01 1.05
2 5 11 0.3125 1.719 1.70 1.74
3790.4375
2.406 2.38 2.43
4970.5625
3.094
3.07 3.12
5 11 5 0.6875
3.781 3.76 3.80
6 13 3 0.8125
4.469 4.45 4.49
7 15 1 0.9375 5.156 5.13 5.50
10% To leran ce ( total)
10% To leran ce ( total)
10% Tolerance (total)
10% To leran ce ( total)
© 2009 Microchip Technology Inc. DS22121B-page 11
MCP23009/MCP23S09
FIGURE 1-4: FLASH ADC BLOCK DIAGRAM
MCP23009/MCP23S09
DS22121B-page 12 © 2009 Microchip Technology Inc.
FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING
1.4.2 ADDRESSING I2C DEVICES
(MCP23009)
The MCP23009 is a slave I2C device that supports 7-
bit slave addressing, with the read/write bit filling out
the control byte. The slave add ress contains four fixe d
bits and three user-defined hardware address bits
(configured via ADDR pin). Figure 1-6 shows the
control byte format.
1.4.3 ADDRESSING SPI DEVICES
(MCP23S09)
The MCP23S09 is a slave SPI device. The slave
address contains seven fixed bits(no address bits) with
the read/write bit filling out the control byte. Figure 1-7
shows the control byte format.
FIGURE 1-6: I2C™ CONTROL BYTE
FORMAT
FIGURE 1-7: SPI CONTROL BYTE
FORMAT
S 0 1 0 0 A2A1A0R/WACK
Start
bit
Slave Address
R/W bit
ACK bit
Control Byte
R/W = 0 = write
R/W = 1 = read
0100000R/W
Slave Address
R/W bit
Control Byte
R/W = 0 = write
R/W = 1 = read
CS
© 2009 Microchip Technology Inc. DS22121B-page 13
MCP23009/MCP23S09
FIGURE 1-8: I2C™ ADDRESSING REGISTERS
FIGURE 1-9: SPI ADDRESSING REGISTERS
S0100A2A1A00ACKA7A6A5A4A3A2A1A0ACK
Device Opcode Register Address
R/W = 0
The ACKs are provided by the MCP23009.
0100000R/WA7A6A5A4A3A2A1A0
Device Opcode Register Addres s
CS
MCP23009/MCP23S09
DS22121B-page 14 © 2009 Microchip Technology Inc.
1.5 GPIO Port
The GPIO module is a general purpose 8-bit wide
bidirectional port.
The outputs are open-drain.
The GPIO module contains the data ports (GPIOn),
internal pull up resistors and the Output Latches
(OLATn).
The pull up resistors are individually configured and
can be enabled when the pin is configured as an input
or output.
Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on th e po rt .
Writing to the GPIOn register actually causes a write to
the latches (OLATn). Writing to the OLATn register
forces the associated output drivers to drive to the level
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high-impedance.
© 2009 Microchip Technology Inc. DS22121B-page 15
MCP23009/MCP23S09
1.6 Configuration and Control
Registers
There are eleven (11) registers associated with the
MCP23X09 as shown in Table 1-4.
TABLE 1-4: CONFIGURATION AND CONTROL REGISTER
Register
Name Address
(hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 POR/RST
value
IODIRA 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOLA 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 0000 0000
GPINTENA 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVALA 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCONA 04 IOC7IOC6IOC5IOC4IOC3IOC2IOC1IOC00000 0000
IOCON 05 —— SEQOP ——ODRINTPOLINTCC 0000 0000
GPPUA 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTFA 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAPA 08 ICP7ICP6ICP5ICP4ICP3ICP2ICP1ICP00000 0000
GPIOA 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0000 0000
OLATA 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
MCP23009/MCP23S09
DS22121B-page 16 © 2009 Microchip Technology Inc.
1.6.1 I/O DIRECTION RE GISTER
Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
becomes an output.
REGISTER 1-1: IODIR – I/O DIRECTION REGI STER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IO7:IO0: Controls the direction of data I/O <7:0>
1 = Pin is configured as an input
0 = Pin is configured as an output
© 2009 Microchip Technology Inc. DS22121B-page 17
MCP23009/MCP23S09
1.6.2 INPUT POLARITY REGISTER
This register allows the user to configure the polarity on
the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inve rted value on the pin.
REGISTER 1-2: IPOL – INPUT POLARITY PORT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IP7:IP0: Controls the polarity inversion of the input pin s <7:0>
1 = GPIO register bit will reflect the opposite logic state of the input pin
0 = GPIO register bit will reflect the same logic state of the input pin
MCP23009/MCP23S09
DS22121B-page 18 © 2009 Microchip Technology Inc.
1.6.3 INTERRUPT-ON-CHANGE
CONTROL REGISTER
The GPINTEN register controls the interrupt-on-
change feature for each pin.
If a bit is set, the corresponding pin is enabled for
interrupt-on-change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for interrupt-on-change.
REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change pins <7:0>
1 = Enable GPIO input pin for interrupt-on-ch ange event
0 = Disable GPIO input pin for interrupt-on-change event
Refer to INTCON and DEFVAL.
© 2009 Microchip Technology Inc. DS22121B-page 19
MCP23009/MCP23S09
1.6.4 DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL re gister, an
opposite value on the associated pin will cause an
interrupt to occur.
REGISTER 1-4: DEFVAL – DEFAULT VALUE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DEF7:DEF0: Sets the comp are value for pins configured for interrupt-on-change from defaults <7:0>.
Refer to INTCON.
If the associated pin level is the opposite from the register bit, an interrupt occurs.
Refer to INTCON and GPINTEN.
MCP23009/MCP23S09
DS22121B-page 20 © 2009 Microchip Technology Inc.
1.6.5 INTERRUPT CONTROL REGISTER
The INTCON register controls ho w the associated pin
value is compared for the interrupt-on-change feature.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in th e DEFVAL regi ster. If a
bit value is clear , the corresponding I/O pin is compared
against the previous value.
REGISTER 1-5: INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IOC7:IOC0: Controls how the associated pin value is compared for interrupt-on-change <7 :0>.
1 = Pin value is compared against the associated bit is DEFVAL register
0 = Pin value is compared against the previous pin value
Refer to DEFVAL and GPINTEN.
© 2009 Microchip Technology Inc. DS22121B-page 21
MCP23009/MCP23S09
1.6.6 CONFIGURATION REGISTER
The Sequential Operation (SEQOP) controls the
incrementing function of the address pointer. If the
address pointer is disabled, the address pointer does
not automatically increment after each byte is clocked
during a serial transfer . This feature is useful when it is
desired to continuously poll (read) or modify (write) a
register.
The Open-Drain (ODR) control bit enables/disables the
INT pin for open-drain configuratio n.
The Interrupt Polarity (INTPOL) sets the polarity of the
INT pin. This bit is functional onl y when the ODR bit is
cleared, configuring the INT pin as active push-pull.
The Interrupt Clearing Control (INTCC) configures ho w
interrupts are cleared. When set (INTCC = 1), the
interrupt is cleared whe n the INTCAP register is read.
When cleared (INTCC = 0), the interrupt is cleared
when the GPIO register is read.
The interrupt can only be cleared when the interrupt
condition is inactive. Refer to Section 1.7.4 “Clearing
Interrupts” for details.
REGISTER 1-6: IOCON – I/O EXPANDER CONFIGURATION REGISTER
U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
- - SEQOP -- ODR INTPOL INTCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Re ads as 0
bit 6 Unimplemented: Re ads as 0
bit 5 SEQOP: Seque ntial Operation mode bit.
1 = Sequential operation disabled, address pointer does not increment
0 = Sequential ope ration enabled, address pointer increments
bit 4 Unimplemented: Re ads as 0
bit 3 Unimplemented: Reads as 0
bit 2 ODR: Configures the INT pin as an open-drain output.
1 = Open-drain output (overrides the INTPOL bit)
0 = Active driver output (INTPOL bit sets the polarity)
bit 1 INTPOL: Sets the polarity of the INT output pin.
1 = Active-high
0 = Active-low
bit 0 INTCC: Interrupt Clearing Control
1 = Reading INTCAP register clears the interrupt
0 = Reading GPIO register clears the inte rrupt
MCP23009/MCP23S09
DS22121B-page 22 © 2009 Microchip Technology Inc.
1.6.7 PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set the corresponding port pin is
internally pulled up with an internal resistor.
FIGURE 1-10: TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS
REGISTER 1-7: GPPU – GPIO PULL-UP RESISTOR REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PU7:PU0: Controls the internal pull-up resistors on each pin (when configured as an input or output)
<7:0>.
1 = Pull-up enabled
0 = Pull-up disabled
GPIO Pin Internal Pull-up Cur re nt v s V
DD
0
50
100
150
200
250
300
350
400
1.522.533.544.555.5
VDD (V)
IPU (µA)
T = -40°C
T = +25°C
T = +125°C
T = +85°C
© 2009 Microchip Technology Inc. DS22121B-page 23
MCP23009/MCP23S09
1.6.8 INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A ‘set’ bit indicates that the
associated pin caused the interrupt.
This register is ‘read only’. Writes to this register will be
ignored.
REGISTER 1-8: INTF – INTERRUPT FLAG REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 INT7:INT0: Reflects the interrupt condition on the port. Will reflect the change only if inte rrupts are
enabled (GPINTEN) <7:0>.
1 = Pin caused interrupt
0 = Interrupt not pending
MCP23009/MCP23S09
DS22121B-page 24 © 2009 Microchip Technology Inc.
1.6.9 INTERRUPT CAPTURE REGISTER
The INTCAP register captures the GPIO port value at
the time the interrupt occurred. The register is ‘read
only’ and is updated only when an interrupt occurs. The
register will remain unchanged until the interrupt is
cleared via a read of INTCAP or GPIO.
REGISTER 1-9: INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER
R-x R-x R-x R-x R-x R-x R-x R-x
ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ICP7:ICP0: Reflects the logic level on the port pins at the time of inte rrupt due to pin change <7:0>.
1 =Logic-high
0 = Logic-low
© 2009 Microchip Technology Inc. DS22121B-page 25
MCP23009/MCP23S09
1.6.10 PORT REGISTER
The GPIO register reflects the value on the port.
Reading from this register reads the port. Writing to this
register modifies the Output Latch (OLAT) register.
REGISTER 1-10: GPIO – GENERAL PURPOSE I/O PORT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 GP7:GP0: Reflects the logic level on the pins <7:0>.
1 =Logic-high
0 = Logic-low
MCP23009/MCP23S09
DS22121B-page 26 © 2009 Microchip Technology Inc.
1.6.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.
REGISTER 1-11: OLAT – OUTPUT LATCH REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 OL7:OL0: Reflects the logic level on the output latch <7:0>.
1 =Logic-high
0 = Logic-low
© 2009 Microchip Technology Inc. DS22121B-page 27
MCP23009/MCP23S09
1.7 Interrupt Logic
If enabled, the MCP23X09 activates the INT interrupt
output when one of the port pins changes state or when
a pin does not ma tch the pre-configure d default. Ea ch
pin is individually configurab le as follows:
• Enable/disable interrupt via GPINTEN
• Can interrupt on either pin change or change from
default as configured in DEFVAL
Both conditions are referred to as In te rrupt on C hang e
(IOC).
The Interrupt Control Module uses the following
registers/bits:
• GPINTEN - Interrupt enable register
• INTCON - Controls the source for the IOC
• DEFVAL - Contains the register default for IOC
operation
• IOCON (ODR and INTPOL) - configures the INT
pin as push-pull, open-drain, and active level
(high or low).
1.7.1 IOC FROM PIN CHANGE
If enabled, the MCP23X09 will generate an i nterrupt if
a mismatch condition exists between the current port
value and the previous port value. Only IOC enabled
pins will be compared. See GPINTEN and INTCON
registers.
1.7.2 IOC FROM REGISTER DEFAULT
If enabled, the MCP23X09 will generate an i nterrupt if
a mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins will be compared. See
GPINTEN, INTCON, and DEFVAL registers.
1.7.3 INTERRUPT OPERATION
The INT interrupt output can be configured as “active
low”, “active high”, or “open-drain” via the IOCON
register.
Only those pins that are configured as an input (IODIR
register) with interrupt-on-change (IOC) enabled
(GPINTEN register) can cause an interrupt. Pins
configured as an output h ave no effect on the interrupt
output pin.
Input change activity on a port input pin that is enabled
for IOC will generate an internal device interrupt and
the device will capture the value of the port and copy it
into INTCAP.
The first interrupt e vent will cause the port contents to
be copied into the INTCAP register. Subsequent
interrupt conditions on the port will not cause an
interrupt to occur as long as the interrupt is not cleared
by a read of INTCAP or GPIO.
1.7.4 CLEARING INTERRUPTS
The interrupt will remain active until the INTCAP or
GPIO register is read (depending on IOCON.INTCC).
Writing to these registers will not affect the interrupt.
The interrupt condition will be cleared after the LSb of
the data is clocked out during a Read operation of
GPIO or INTCAP (depending on IOCON.INTCC).
Note: Assuming IOCON.INTCC = 0 (INT cleared
on GPIO read): The value in INTCAP can
be lost if GPIO is read before INTCAP
while another IOC is pending. After read-
ing GPIO, the interrupt will clea r and then
set due to the pending IOC, causing the
INTCAP register to update.