183
TM
REFERENCE AN400
March 1997
HS-3282
CMOS ARINC Bus Interface Circuit
Features
• ARlNC Specification 429 Compatible
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
• Dual and Independent Recei vers, Connecting Directly
to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Para ll el to Serial Transmitter Data Conversi on
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Gener ate Par ity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Suppl y
• Low Pow er Dissipation
• Full Military Temperature Range
Description
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This device is intended to be used with
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circui t consists of two (2) receiver s
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is
ten (10) times the receiver data rate, which can be the same
or different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functional ly independent and each r eceives serial data asyn-
chronously. The transmitter section of the ARINC bus
inte rfa ce circ uit consis ts m ainly of a First -In Fi rst- Ou t (FIFO )
memor y and timing circuit. The FIFO memory is used to hold
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
word as required by ARINC Specification 429. Even though
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be program med to also operate with
a word length of 25 bits. The incoming receiver data word
parity is c hecked, and a parity status i s stored in the recei ver
latch and output on Pin BD08 during the 1st word. [A logic
“0” indicates that an odd number of logic “1” s were received
and stored; a logic “ 1” indicat es that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on
BD12 will cause odd parity to be used in the output data
stream.
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus int erface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt VCC supply.
Ordering Information
PACKAGE TEMP. RANGE PART NUMBER PKG.
NO.
CERDIP -55oC to +125oC HS1-3282-8 F40.6
SMD# 5962-8688001QA F40.6
CLCC -40oC to +85oC HS4-3282-9+ J44.A
-55oC to +125oC HS4-3282-8 J44.A
SMD# 5962-8688001XA J44.A
FN2964.2
CA UTION: The se devices are s ensi tiv e to el ectrosta tic di schar ge; follow proper IC H andling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyr ight © Intersil Americas Inc. 2002. All Rights Reserved
184
Pinouts
HS-3282 (CERDIP)
TOP VIEW
HS -328 2 (CLCC)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
VDD
429DI1(A)
429DI1(B)
429DI2(A)
429DI2(B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
NC
MR
TX CLK
CLK
NC
NC
CWSTR
ENTX
429D0
429D0
TX/R
PL2
PL1
BD00
BD01
BD02
BD03
BD04
BD05
GND
14
13
12
11
10
9
8
7
17
16
15
25
30
35
39
38
37
36
33
34
32
31
29
46 3
BD15
BD12
NC
D/R1
BD14
EN2
BD11
NC
NC
CWSTR
ENTX
429D0
429D0
TX/R
PL2
PL1
BD01
BD00
NC
429DI2(B)
TXCLK
CLK
429DI2(A)
NC
1
NC
BD10
BD09
BD08
BD07
BD06
BD04
BD03
GND
BD02
BD05
429DI1(A)
SEL
EN1
40414243
44
2827262524232221201918
VDD
BD13
D/R2
429DI1(B)
MR
NC
HS-3282
185
Pin Descr iption
PIN SYMBOL SECTION DESCRIPTION
1V
CC Recs/Trans Supply pin 5 volts ±5%.
2 429 DI1 (A) Receiver ARlNC 429 data input to Receiver 1.
3 429 DI1 (B) Receiver ARlNC 429 data input to Receiver 1.
4 429 Dl2 ( A) Re ce iver ARIN C 42 9 data in pu t to Rece iv er 2.
5 429 DI2 ( B) Re ce iv er ARIN C 42 9 da ta input to Re ce iv e r 2.
6D/R1Receiver Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched.
7D/R2Receiver Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched.
8 SEL Receiver Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2.
9EN1
Receiv er Input signal to enable data from Receiver 1 onto the data bus.
10 EN2 Receive r Input signal to enabl e dat a from Receiver 2 onto the data bus.
11 BD 15 Re cs/Trans Bi-directional data bus for fetching data fr om either of the Rece iver s, or for loading data int o
the Trans mitter m e mory o r c ontrol word re gist er. Se e Control W or d Table f or de scription of
Control Word bits.
12 BD 14 Re cs/Trans See Pin 11.
13 BD 13 Re cs/Trans See Pin 11.
14 BD 12 Re cs/Trans See Pin 11.
15 BD 11 Re cs/Trans See Pin 11.
16 BD 10 Re cs/Trans See Pin 11.
17 BD 09 Re cs/Trans See Pin 11.
18 BD 08 Re cs/Trans See Pin 11.
19 BD 07 Re cs/Trans See Pin 11.
20 BD 06 Re cs/Trans See Pin 11.
21 GND Recs/Trans Circuit G round.
22 BD 05 Re cs/Trans See Pin 11.
23 BD 04 Recs/Trans See Pin 11. Control Word func ti on not applicable.
24 BD 03 Recs/Trans See Pin 11. Control Word func ti on not applicable.
25 BD 02 Recs/Trans See Pin 11. Control Word func ti on not applicable.
26 BD 01 Recs/Trans See Pin 11. Control Word func ti on not applicable.
27 BD 00 Recs/Trans See Pin 11. Control Word func ti on not applicable.
28 PL1 Transm itter Parall el load input signal loading the first 16 -bit word into the Transmi tter memo ry.
29 PL2 Transmitter Parallel load input signal loading the first 16-bit word into the Transmitter memory and ini-
tiates data transfer into the memory stack.
30 TX/R Transmitter Transmitter flag outp ut to indi cate the me mory is empty.
HS-3282
186
Pinout
31 429D0 Transmitter Data output from Transmitter
32 429D0 Transmitter Data output from Transmitter.
33 ENTX Transmitter Transmitter Enable input signal to initiate data transmiss ion from FIFO memory.
34 CWSTR Recs/Trans Control word input strobe signal to latch the control word from the databus into the control
word registe r .
35 - - No co nn ec t i on . Mu st be left op en .
36 - - No connection. Must be left open or tied low but never tied high.
37 CLK Recs/Trans External clock input. May be either ten (10) or eighty (80) times the data rate. If using both
ARINC data rates it must be ten (10) times the highest data rate, (typically 1 MHz).
38 TXCLK Transmitter Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate.
39 MR Recs/Trans Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal,
TX/R and various other flags and controls. Master reset does not reset the control word
register. Usually only used on Power-Up or Syst em Reset.
40 - - No Connection.
Pin Descr iption (Continued)
PIN SYMBOL SECTION DESCRIPTION
28 40393837363534333231302927262524232221
13 12345678910111214151617181920
NCNC NC
HS-3282
187
Operational Description
The HS-3282 is designed to support ARINC Specification
429 and other serial data protocols that use a similar format
by collecting the receiving, transmitting, synchronizing,
timing and parity function s on a singl e, low power LSl circui t.
It goes beyond the ARlNC requirements by providing for
either odd or even parity, and giving the user a choice of
either 25 or 32-bi t word lengths. The receiver and transmitte r
sections operate independently of each other. The serial-to-
parallel conversion required of the receiver and the parallel-
to-serial conversion requirements of the transmitter have
been incorporated into the bus i nterface circui t.
Provisions have been made through the external clock input
to provide data rate flexibilit y. This requires an external clo ck
that is 10 times t he data rate.
To obtain the flexibility discussed above, a number of
external control signals are required, To reduce the pin
count requirements, an internal control word register is used.
The control word is latched from the data bus into the regis-
ter by the Control Word Strobe (CWSTR) signal going to a
logic “1”. Eleven (11) control functions are used, and along
with the Bus Data (BD) line are listed below:
ARlNC 429 DATA FORMAT as input to the Receiver and
output from the Tr ansm itter is as fo ll ows: This format is shuffled when seen on the sixteen bidirec-
tional input/outputs. The format shown below is used from
the receiver s and input to the transmitter :
Control Word
PIN NAME SYMBOL FUNCTION
BD05 SLFTST Connects the self test signal from the transmitter directly to the receiver shift registers, bypassing the input
r ecei vers . Rec eiv er 1 rece ives Dat a True an d Rec eive r 2 re cei ves D ata Not . Not e tha t th e tr ansm itter ou tput
remains active. (Logic “0” on SLFTST Enables Self Test).
BD06 SDENB1 Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder).
BD07 X1 If SDENB1 = “1” then this bit is compared wi th ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be
accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
BD0 8 Y 1 If SDENB I = “1 ” then th is bit is co mpa red with ARIN C D ata Bit #10 . If X1 also matc he s (se e X1 ), th e wor d wil l
be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
BD09 SDENB2 Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder).
BD10 X2 If SDENB2 = “1” then this bit is compared wi th ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be
accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
BD11 Y2 If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will
be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
BD 12 PARCK Sign al us ed to inv ert th e tr an smit te r pa rit y bi t for test of pa rit y ci rcu it s. Lo gi c “0” se le cts n orm al o dd pari t y. Log ic
“I” selects even par ity .
BD1 3 TX SEL S elec ts hi gh or lo w Tra ns mitt er da ta rate . If T XSE L = “ 0” t hen t ran smi tte r data rat e is equa l t o the cloc k r ate
divided by ten (10). If TXSEL = “1” then transmitter data rat e is equal to the clock rate divided by eighty (80).
BD14 RCVSEL Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock
r ate di vide d by te n (10), i f RC VSEL = “1 “the n the re ceiv ed da ta rate shou ld b e equ al to th e cloc k rate di vide d
by eighty (80).
BD15 WLSEL Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format
wil l be se lected.
TABLE 1. ARINC 429 32-BIT DATA F ORMAT
ARINC BIT # FUNCTION
1 - 8 Label
9 - 10 SD l or Data
11 LSB
12 - 27 Data
28 MSB
29 Sign
30, 31 SSM
32 Parity Status
TABLE 2A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT # FUNCTION ARINC BlT #
15, 14 Data 13, 12
13 LSB 11
12, 11 SDl or Dat a 10, 9
10, 9 SSM Status 31, 30
8 Parity S tatus 32
7 - 00 Label 1 - 8
HS-3282
188
Receiver Parity Statu s:
0 = Odd Parity
1 = Even Parity
If the receiver input data word string is broken before the
entire data word is received, the receiver will reset and
ignore the partially re ceived data word.
If the transmitter is used to transmit consecutive data words,
each word will be separated by a four (4) bit “null” state (bot h
positive and negative outputs will maintain a zero (0) volt
level.)
Receiver Parity Statu s:
0 = Odd Parity
1 = Even Parity
No Source/Destination (S/D) in 25- Bit format.
Rece iver Operat ion
Since the two receivers are functionally identical, only one
will be discussed in detail, and the block diagram will be
used for reference in this discussion. The receiver consists
of the following circuits:
• The Line Receiver functions as a voltage level translator.
It transforms the 10 volt differential line voltage, ARINC
429 format, into 5 volt internal logic level.
• The output of the Line Receiver is one of two inputs to the
Self-Test Data Selector (SEL). The other input to the
Data Selector is the Self-Test Signal from the Transmitter
section.
• The incoming data, either Self-Test or ARlNC 429, is
double sampled by the Word Gap Timer to generate a
Data Clock. The Receiver sample frequency (RCVCLK),
1MHz, or 125kHz, is generated by the Receiver/Transmit-
ter Timing Ci rcuit . This sampl ing freque ncy i s ten times t he
Data Rate to ensure no data ambiguity.
• The derived data clock then shifts the data down a 32-Bit
long Data Shift Register (Data S/RI). The Data Word
Length is selectable for either 25 Bits or 32 Bits long by
the Control Signal (WLSEL). As soon as the data word is
completely received, an internal signal (WDCNT1) is gen-
erated by the Word Gap Timer Circuit.
• The Source/Destination (S/D ) Decoder compares the user
set code (X and Y) with Bits 9 and 10 of the Data Word. If
the two codes are matched, a positive signal is generated
to enable the WDCNT1 signal to latch in the received
data. Otherwise, the data word is ignored and no latching
action takes place. The S/D Decoder can be Enabled and
Disabl ed by the contr ol signal S/D ENB. If the data word is
latched, an indicator flag (D/R1) is set. This indicates a
vali d data word is ready to be fetched by the user.
• After the receiver data has been shifted down the shift
register, it is placed in a holding regist er. The device ready
flag will then be set indicating that data is ready to be
fetched. If the data is ignored and left in the holding regis-
ter, it will be written over when the next data word is
received.
• The received data in the 32-bit holding register is placed
on the bus in the form of two (2)16-bit words regardless of
whether the format is for 32 or 25-bit data words. Either
word can be accessed first or repeatedly until the next
recei ved data word falls into the holding regist er.
• The parity of the incoming word is checked and the status
(i.e., logic “0” for odd parity and logic “1” for even parity)
stored in the receiver latch and output on BD08 during the
Word No. 1.
• Assumi ng the u ser desires to access the data, he fir st sets
the Data Select Line (SEL) to a Logic “0” level and pulses
the Enable (EN1) line. This action causes the Data
Selector (SELl) to select the first-data word, which con-
tains the label field and Enable it onto the Data Bus. To
obtain the second data word, the user sets the SEL line to
a Logic “1” level and pulse the Enable (EN1) line again.
The Enable pulse duration is matched to the user circuit
requirement needed to read the Data Word from the Data
Bus. The second Enable pulse is also used to reset the
Device Ready (D/R1) flip-flop. This completes a receiving
cycle.
TABLE 2B. WORD 2 FORMAT
BI-DIRECTIONAL
BlT# FUNCTION ARINC BIT#
15 Sign 29
14 MSB 28
13 - 00 Data 27 - 14
TABLE 3. ARINC 25-BIT DATA FORMAT
ARINC BIT # FUNCTION
1 - 8 Label
9LSB
11 - 23 Data
24 MSB
25 Parity Status
TABLE 4A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT# FUNCTION ARINC BIT#
15 - 9 Don’t Care XXX
8 Parity S tatus 25
7 - 0 Label 1 - 8
TABLE 4B. WORD 2 FORMAT
BI-DIRECTIONAL
BIT# FUNCTION ARINC BlT#
15 MSB 24
14 - 1 Data 23 -1 0
0LSB9
HS-3282
189
Transm itter O peration
The Transmitter section consists of an 8-word deep by 31-
Bit long FIFO Memory, Parity Generator, Transmitter Word
Gap Timing Circui t and Driver Circuit .
• The FlFO Memory is organized in such a way that data
loaded in the input register is automatically transferred to
the output register for Serial Data Transmission. This
elimi nates a large amount of data managi ng time since the
data need not be clocked from the input register to the
output register. The FIFO input register is made up of two
sets of 16 D-type flip-flops, which are clocked by the two
parallel load signals (PL1 and PL2). PL1 must always
precede PL2. Multiple PL1’s may occur and data will be
written over. As soon as PL2 is received, data is
transferred to the FIFO. The data from the Data Bus is
clocked into the D-type flip-flop on the positive going edge
of the PL signals. If the FIFO memory is initially em pty, or
the stack is not full, the data will be automatically
transferred down the Memory Stack and into the output
register or to the last empty FIFO storage register. If the
Transmitter Enable signal (ENTX) is not active, a Logic
“0”, the data remains at the output register. The FIFO
Memory has storage locations to hold eight 31-bit words. If
the memory is full and the new data is again strobed with
PL, the old data at the input register is written over by the
new data. Data will remain in the Memory until ENTX g oes
to a Logic “1”. This activates the FIFO Clock and data is
shifted out serially to the Transmitter Driver. Data may be
loaded into the FIFO only while ENTX is i nactive (low) . It is
not possible to write data into the FIFO while transmitting.
WARNING: If PL1 or PL2 is applied while ENTX is high,
i.e., while transmitting, the FlFO may be disrupted such
that it would require a MR (Master Reset) signal to
recover.
• The Output Register of the FIFO is designed such that it
can shift out a word of 24 Bits long or 31 Bits long. This
word length is again controlled by the WLSEL bit. The TX
word Gap Timer Circuit also automatically inserts a gap
equival ent to 4-Bit Ti m es bet ween each wor d. This gi ves a
minimum requ irement of 29-Bit time or 36-Bit time for each
word transmission. Assuming the signal, ENTX, remains
at a Logic “1”, a transfer to stack signal is generated to
transfer the data down the Memory Stack one position.
This action is continued until the last word is shifted out of
the FIFO memory. At this time a Transmitter Ready (TX/R)
flag is generated to signal the user that the Transmitter is
ready to receive eight more data words. During transmis-
sion, if ENTX is taken low then high again, transmission
will cease leaving a portion of the word untransmitted, and
the data integrity of the FIFO will be destroyed.
• A Bit Counter is used to detect the last Bit shifted out of
the FIFO memory and appends the Parity Bit generated
by the Parity Generator. The Parity Generator has a
control signal, Parity Check (PARCK), which establishes
whether odd or even parity is used in the output data
word. PARCK set to a logic “0” will result in odd parity and
when set to a logic “1” will res ult in even parit y.
Sampl e Int erface Tec hnique
From Figure 1, one can see that the Data Bus is time shar ed
between the Receiver and Transmitter. Therefore, bus
controlling must be synchronously shared between the
Receiver and the Tra nsm it ter.
Figure 2 shows the typical interface timing control of the
ARlNC Chip for Receiving function and for Transmitting
function. Timing sequence for loading the Transmitter FIFO
Memory is shown in Timing Interval A. A transmitter Ready
(TX/R) Flag signals the user that the Transmitter Memory is
empty. The user then Enables the Transm it ter Data, a 16- Bit
word, on the Data Bus and strobes the Transmitter with a
Parallel Load (PL1) Signal. The second part of the 32-Bit
word is similarly loaded into the Transmitter with PL2, which
also initiates data transfer to stack. This is continuous until
the Memory is full, which is eight 31-Bit words. The user
must keep track of the number of words loaded into the
Memory to ensure no data is written over by other data.
During the time the user is loading the Transmitter, he does
not have to service the Receiver, even if the Receiver flags
the user with the signal D/R1 that a valid received word is
ready to be fetched. This is shown by the Timing inte rval B. If
the user decides to obtain the received data before the
Transmitter is completely loaded, he sets the two parallel
load signals (PL1 and PL2) at a Logic “1” state, and strobes
EN1 while the signal SEL is at a Logic “0” state. After the
negative edge of EN1, the first 16-Bit segment of the
received word becomes valid on the Data Bus. At the
positive edge of EN1, the user should toggle the signal SEL
to ready the Receiver for the second 16-Bit word. Strobing
the Receiver with EN1, the second time, enables the second
16-Bit word and resets the Receiver Ready Flag D/R1. The
user should now reset the signal SEL to a Logic “0” state to
ready the Receiver for another Read Cycle. During the time
period that the user is fetching the received words, he can
load the transmitter. This is done by interlacing the PL
signals with the EN signals as shown in the Timing Interval
B. Servicing the Receiver 2 is similar and is illustrated by
Timing interval C. Timing interval D shows the rest of the
Transmitter loading sequence and the beginning of the
tran smis sion by switch ing t he signal TX Enable to a Logic “1 ”
state. Ti ming interval E i s the time it takes to tra nsm it all data
from the FlFO Memory , ei ther 288 Bit times or 232 Bit times.
Repeater Operation
This mode of operation allows a data word that has been
received to be placed di rectly i n the FIFO for transmission. A
timi ng diagram is shown in Figur e 7. A 32-bit word is used in
this example. The data word is shifted into the shift register
and the D/R flag goes low. A logic “0” is placed on the SEL
line and EN1 is strobed. This is the same as the normal
receiver operation and places half the data word (16 bits) on
the data bus. By strobing PL1 at the same time as EN1,
these 16 bits will be taken off the bus and placed in the
FIFO. SEL is brought back high and EN1 is strobed again for
the seco nd 16 bits of the data word. Again by st robing PL2 at
the same time the second 16 bits will be placed in the FIFO.
The parity bit will have been str ipped away leavi ng the 31-bit
data word in the FIFO ready for transmission as shown in
Figure 6.
HS-3282
190
FIGURE 1. SINGLE CHIP ARI NC 42 9 INTERFACE FUNCTIONAL BLOCK DI AGRAM
429D11 (A)
429D11 (B)
2
3
LINE
RECEIV.
ER 1
S/DENB
SLF
TEST
S/D
DECODER WDCNT 1
WDCNT 2
SELF
TEST
SEL
S/D CODER
WORD GAP
WLSEL
DATA CLOCK
DATA S/R 1
LATCH 1
32
16
16 SEL 1
SEL EN1
16
WDCNT 1
RCV CLK
429D12 (B)
429D12 (A)
5
4LINE
RECEIV.
ER 2
SELF
TEST
SEL
WORD GAP
WLSEL
DATA CLOCK
DATA S/R 2
LATCH 2
32
16
16
SEL 2
SEL EN2
16
WDCNT 2
RCV CLK
39
MR
6
D/R1
7
D/R2
8
SEL
9
EN1
10
EN2
BD15-
BD00
DATA
BUS PL1 PL2
22 - 27
11 - 20
16
28 29
F/FDTX WORD
GAP
TX CLK WLSEL
CONTROL
WORD
REGISTER
FIFO
16
8 x 31
F/FD
16
30
TX/R
PARITY
TXC
DRVR
CWSTR
ENTX
429D0
429D0
PARCK SELF
TEST
34
33
32
31
SLF TST
(BD05)
S/D ENB1
(BD06)
S/D ENB2
(BD09)
X1 (BD07)
Y1 (BD06)
PARCK
TXSEL
RCVSEL
WLSEL
Y2 (BD11)
X2 (BD10)
(BD15)
(BD14)
(BD13)
(BD12)
VCC GND
21
TX CLKCLK
13837
TIMING
TXRCV
RCVSEL
TXSEL
TX
CLK
RCV
CLK
11
HS-3282
191
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage Applied
(Except Pins 2 - 5) . . . . . . . . . . . . . . . . GND -0.3V to VDD +0.3V
Input Voltage Applied (Pins 2 - 5). . . . . . . . . . . . . . . . . -29V to +29V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Ope rat i ng Conditio ns
Operating Voltage Range. . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range
HS-3282-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
HS-3282-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 oC to +125oC
Thermal Resistance θJA (oC/W) θJC (oC/W)
CDIP Package. . . . . . . . . . . . . . . . . . . 35 8
CLCC Package . . . . . . . . . . . . . . . . . . 55 12
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150 oC
Maximum Le ad Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2632 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the devic e. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
PARAMETER SYMBOL CONDITIONS
LIMITS
UNITSMIN MAX
ARlNC INPUTS Pins 2-3,4-5
Logic “1” I np ut Vo lta g e VlH VDD = 5.25V 6.7 13.0 V
Logic “0” I np ut Vo lta g e VIL VDD = 5.25V -13.0 -6.7 V
Null Input Voltage VNUL VDD = 4.75V, 5.25V -2.5 +2.5 V
Common Mode Voltage VCH VDD = 4.75V, 5.25V -5.0 +5.0 V
Input Leakag e IlH VDD = 5.25V , VIN = ±6.5V - 200 µA
Input Leakag e IlL VDD = 5.25V , VIN = 0.0V -450 - µA
Differential Input Impedance RI VDD = 5.25V, VIN = +5V, -5V 12 - kΩ
Input lmpedance to VDD RH VDD = 5. 25V, VlN = 0V 12 - kΩ
Input lmpedance to GND RG VDD = Open, VlN = 5.0V 12 - kΩ
BIDIRECTIONAL INPUTS Pins 11-20, 22-27
Logic “1” I np ut Vo lta g e VIH VDD = 5.25V 2.1 - V
Logic “0” I np ut Vo lta g e V IL VDD = 4.75V - 0.7 V
Input Leakag e lIH VDD = 5.25V,VIN = 5.25V - 1. 5 µA
Input Leakag e IlL VDD = 5.25V , VIN = 0.0V -1.5 - µA
ALL OTHER INPUTS Pins 8-10, 28, 29, 33, 34, 37, 39
Logic “1” I np ut Vo lta g e VIH VDD = 5.25V 3.5 - V
Logic “0” I np ut Vo lta g e V IL VDD = 4.75V - 0.7 V
Input Leakag e IlH VDD = 5.25V , VIN = 5.25V - 10 µA
Input Leakag e IlL VDD = 5.25V , VIN = 0.0V -75 - µA
OUTPUTS Pins 6, 7, 11-20, 22-27, 30-32, 38, Supply Pin 1
Logic “1” O ut p ut Vo lta ge V OH VDD = 4. 75V , IOH = -1.5mA 2.7 - V
Logic “0” O ut p ut Vo lta ge VOL VDD = 4.75V lOL= 1.8mA - 0.4 V
Standby Supply Current lCC1 VDD = 5.25V , VIN = 0V Except 9,10,
29 = 5.25V -20mA
Operating Supply Current lCC2 VDD = 5.25 V, VIN = 5.25V Except 8,
33 = 0.0V, CLK = 1MHz -20mA
HS-3282
192
AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
PARAMETER SYMBOL CONDITIONS
LIMITS
UNITSMIN MAX
Clock Frequency FC VDD = 4.75V, 5.25V - 1 MHz
Data Rate 1/ FD VDD = 4.7 5V, 5.25V - 100 k Hz
Data Rate 2/ FD VDD = 4.7 5V, 5.25 V - 12.5 kH z
Master Reset Pulse Width TMR VDD = 4.75V, 5.25V 200 - ns
RECEIVER TIMING
Receiver Ready Time From 32nd Bit 1/ T D/R 2 VDD = 4.75V, 5.25V - 16 µs
Receiver Ready Time From 32nd Bit 2/ T D/R 2 VDD = 4.75V, 5.25V - 128 µs
Devi ce Ready to E nable Time TD /REN VDD = 4.75V, 5.25V 0 - ns
Data Enable Pulse Width TEN VDD = 4.75V, 5.25V 200 - ns
Data Enable to Data Enable Time TENEN VDD = 4.75V, 5.25V 50 - ns
Data Enable to Dev ic e Ready Reset Time TEND/R VDD = 4.75V, 5.25V - 200 ns
Ou tp ut Dat a Valid to Enabl e Time TE NDATA V DD = 4.75V, 5.25V - 200 ns
Data Enable to Data Select Time TENSEL VDD = 4.7 5V, 5.25V 20 - ns
Data Select to Data Enable Time TSELEN VDD = 4.75V, 5.25V 20 - ns
Ou t p ut D at a Di sa ble Tim e TD A T AEN VDD = 4.75V, 5.25 V - 80 ns
CONTROL WORD TIMING
Control Word Strobe Pulse W idth TCWSTR VDD = 4.75V, 5.25V 130 - ns
Control Wor d Setup Time TCWSET VDD = 4.75V, 5.25V 130 - ns
Control Wor d Hold Time TCWHLD VDD = 4.75V, 5.25V 0 - ns
TRANSMITT E R FIFO Write Timing
Parallel Load Pulse Width TPL VDD = 4.75V, 5.25V 200 - ns
Parallel Load to Parallel Load 2 Delay TPL12 VDD = 4.75V, 5.25V 0 - ns
Transmitter Ready Delay Time TTX/R VDD = 4.75V, 5.25V - 840 ns
Data Word Setup Time TDWSET VDD = 4.75V, 5.25V 110 - ns
Data Word Hold Time TDWHLD VDD = 4.75V, 5.25V 0 - ns
TRANSMITT E R Output Timing
Enable Transmit to Output Data Valid Time 1/ TENDAT VDD = 4.7 5 V, 5.25V - 25 µs
Enable Transmit to Output Data Valid Time 2/ TENDAT VDD = 4.75V, 5.25V - 200 µs
Output Data Bit Time 1/ TBlT VDD = 4.75V, 5.25V 4.95 5.05 µs
Output Data Bit Time 2/ TBlT VDD = 4.75V, 5.25V 39.6 40.4 µs
Output Data Null Time 1/ TNULL VDD = 4.75V, 5.25V 4.95 5.05 µs
Output Data Null Time 2/ TNULL VDD = 4.75V, 5.25V 39.6 40.4 µs
HS-3282
193
Data Word Gap Time 1/ TGAP VDD = 4.75V, 5.25V 39.6 40.4 µs
Data Word Gap Time 2/ TGAP VDD = 4 .75V, 5. 25V 316 .8 323.2 µs
Data Transmission Word to TX/R Set Time TDTX/R VDD = 4.75V, 5.25V - 400 ns
Enable Transmit Tur noff Time T ENTX/R VDD = 4.75V, 5.25V 0 - ns
REPEATE R OP E RATION TIMING
Data Enable to Parallel Load Delay Time TENPL VDD = 4.75V, 5.25V 0 - ns
Data Enable Hold for Parallel Load Time TPLEN VDD = 4.75V, 5.25V 0 - ns
En able Transmit Delay Ti me TTX/REN VDD = 4.75V, 5.25V 0 - ns
NOTES:
1. 100kHz Data Rate.
2. 12.5k H z Data Ra te.
Electrical Perf orman ce Speci fications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
PARAMETER SYMBOL (NOTE 1)
CONDITIONS
LIMITS
UNITSMIN MAX
Differential Input Capacita nce CD VDD = Open, f = 1MHz, Not e 2, 3 - 20 pF
In pu t Ca pa ci t a nc e to V DD CH VDD = GND, f = 1MHz, Note 2, 3 - 20 pF
lnput Capa c it a nc e to G N D CG VDD = Open, f = 1MHz, Not e 2, 3 - 20 pF
Input Capacitance Cl VDD = Open, f = 1MHz, Note 2, 4 - 15 pF
Output Capacitance CO VDD = Open, f = 1MHz, Not e 2, 5 - 15 pF
Clock Rise Time TLHC CLK = 1MHz, From 0. 7V to 3.5V - 10 ns
Clock Fall Time THLC CLK = 1MHz, From 3.5V to 0.7V - 10 ns
Input Rise Time TLHI From 0.7V to 3.5V, Note 6 - 15 ns
Input Fall Time THLI From 3.5V to 0.7V, Note 6 - 15 ns
NOTES:
1. The pa rameters listed in thi s table are con trolled via de sign or process paramet ers a nd are not directly te sted. These parameters are
characterized upon initial design and after major process and/or design changes affecting these parameters.
2. All measurements are referenced to device GND.
3. Pins 2-3, 4-5.
4. Pins 8-10, 28 , 29, 33, 34, 37, 39.
5. Pins 6, 7, 11-20, 22- 27, 30-32, 38.
6. Pins 8-20, 22-29, 33, 34.
AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8) (Continued)
PARAMETER SYMBOL CONDITIONS
LIMITS
UNITSMIN MAX
HS-3282
194
Timing Waveforms
FIGURE 2. TYPICAL INTERFACE TIMING SEQUENCE
FIGURE 3. RECE IVER TIMING
TX/R
TX ENABLE
DATA BUS
PL1
PL2
TIME
BUS IS BEING USED AS AN OUTPUT
D/R1
D/R2
EN1
EN2
SEL
INTERVAL A TIME
INTERVAL B TIME
INTERVAL C TIME
INTERVAL D TIME
INTERVAL E
BUS IS BEING USED AS AN INPUT
429DI
D/R
EN
SEL
BD00-15
SEL
OR
BD00-15 WORD
2WORD
1
WORD
1WORD
2
BIT
32 tD/R
tD/REN tENEN
tEND/R
tENSEL
tEN
tDATAEN
tENDATA
tENDATA tDATAEN
tSELEN
tSELEN
tEN
tENSEL
HS-3282
195
FIGURE 4. CONTROL W ORD TIMING
FIGURE 5. TRANSMITTER FI FO WRITE TIMING
FIGURE 6. TRANSMITTER OUTPUT TIMING
Timing Waveforms (Continued)
CWSTR
BD00-15
tCWSTR
tCWSET
CONTROL WORD
tCWHLD
tPL tPL12
tDWSET tDWHLD
WORD 2WORD 1
tDWSET tDWHLD
tTX/R
tPL
PL1
PL2
TX/R
BD00-15
tNUL
42900
ENTX
TX/R
tNUL tGAP
tBIT
tENDAT BIT
32
BIT
1
BIT
32
BIT
2
BIT
1
tNUL
tENTX/R
tDTX/R
HS-3282
196
FIGURE 7. REPEATER OPERATION TIMING
Timing Waveforms (Continued)
429DI
tD/R
BIT
32
D/R
EN
SEL
PL1
PL2
TX/R
ENTX
429D0 BIT
32
BIT
1
tD/REN tEN tENEN tEN
tENSEL
tSELEN
tENSEL
tSELEN
tPLEN
tENPL
tPLEN
tENPL
tTX/R
tTX/REN
tENDAT tNUL
tENTX/R
tDTX/R
tEND/R
HS-3282
197
All Intersil U.S. pro ducts are manufactured, assembl ed and tested uti lizin g ISO9000 qualit y systems.
Intersil Corporati on’s quali ty certifi cations can be viewed at www.intersil.com/desi gn/quali ty
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For informat ion regarding Intersil Corpora ti on and its produc ts, see www.i ntersil.com
Burn-In Circuits
HS-3282 CERDIP
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
VDD
DI1(A)
DI1(B)
DI2(A)
DI2(B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
NC
MR
TX CLK
CLK
NC
NC
CWSTR
ENTX
429D0
429D0
TX/R
PL2
PL1
BD00
BD01
BD02
BD03
BD04
BD05
F6
GND
F7
F8
F9
F10
F11
F12
F13
F14
F15
F8
VDD
F9
NC
NC
GND
F4
GND
F4
GND
NC
F5
F4
F3
F2
F1
F0
F8
F8
NC
NC
NC
GND
VDD
NC
NC
F0
NC
F15
VDD
C
HS-3282
198
HS-3282 CLCC
NOTES:
1. Resistors = 47kΩ, 5%, 1/4W (Min )
2. GND = Ground
3. VDD = +5.5V, ±0.5V
4. C = 0.01mF/Socket (Min)
5. F0 = 100kHz, F1 = F0/2, . . . F15 = F14/2
Burn-In Circuits
14
13
12
11
10
9
8
7
17
16
15
25
30
35
39
38
37
36
33
34
32
31
29
46 3
BD15
BD12
NC
D/R1
BD14
EN2
BD11
NC
NC
CWSTR
ENTX
D0
D0
TX/R
PL2
PL1
BD01
BD00
NC
DI2(B)
TXCLK
CLK
DI2(A)
NC
1
NC
BD10
BD09
BD08
BD07
BD06
BD04
BD03
GND
BD02
BD05
DI1(A)
SEL
EN1
4041424344
2827262524232221201918
VCC
BD13
D/R2
DI1(B)
MR
NC
NC
NC
NC
F9
VDD
F8
F15
F14
F13
F12
F11
NC
NC
VDD
GND
NC
NC
NC
F8
F8
F0
F1
VDD
GND
NC
F15
NC
F0
NC
F4
GND
F4
GND
NC
NC
F10
F09
F08
F07
F06
GND
F05
F04
F03
F02
C
199
All Intersil U.S. pro ducts are manufactured, assembl ed and tested uti lizin g ISO9000 qualit y systems.
Intersil Corporati on’s quali ty certifi cations can be viewed at www.intersil.com/desi gn/quali ty
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For informat ion regarding Intersil Corpora ti on and its produc ts, see www.i ntersil.com
Die Charact eris tics
DIE DIMENSIONS:
246 x 224 x 19 mils)
(6250 x 5700 x 483µm)
METALLIZATION:
Type: Si-A l
Thickness: 11kÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kA ±1kÅ
WORST CASE CURRENT DENSITY:
2 x 105 A/cm2
Metallization Mask Layout
HS-3282
(6) D/R1
(2) 429DI1(A)
(40) N/C
(3 6 ) N/ C
(4) 429DI2(A)
(5) 429DI2(B)
BD09 (17)
BD15 (11)
SEL (8)
D/R2 (7)
(3) 429DI1(B)
(1) VDD
(39) MR
(37) CLK
(38) TX CLK
EN1 (9)
EN1 (10 )
BD14 (12)
BD13 (13)
BD12 (14)
BD11 (15)
BD10 (16)
BD08 (18)
BD07 (19)
BD06 (20)
GND (21)
BD05 (22)
BD04 (23)
BD03 (24)
BD02 (25)
BD01 (26)
(3 4 ) CW S TR
(3 3 ) EN T X
(32) 429D0
(31) 429D0
(3 5 ) N/ C
(3 0 ) TX / R
(2 9 ) PL 2
(2 8 ) PL 1
(27) BD00
