FIR24S
1
The symmetrical 24-tap FIR filter macro
is constructed by cascading the symmet-
rical 8-tap FIR filter hard macro
(FIR8S). The FIR8S macro is designed
to be cascaded by breaking the delay-
line between the 4th and 5th taps and
connecting to the input and cascade out-
puts, respectively, of the next macro
block. The outputs from the filter macros
are summed by additional carry-save
adder (CSADDI) stages. In the final
macro stage, the cascade tap input/out-
puts are connected together.
The coefficients are stored as constant
cells in the Atmel AT6000 FPGA archi-
tecture. This provides the com pact and
efficient storage of a fixed-coefficient
scheme but is variable in real-time
through the use of Cache-Logic™
(dynamic partial reconfiguration of the
FPGA). Any one or more of the coeffi-
cients can be modified by sending the
approp riate bit-stre am(s) to the FP GA.
While the updates occur, the filter contin-
ues to op erate undist urbed as doe s the
rest of the circuitry in the array. This is
another unique benefit of Atmel FPGAs.
Control of the fil ter is ac hie ve d by gener-
ating an initialization signal at each new
sample time. This single clock-cycle
wide pulse is delivered to the filter as the
LSB of each sample is presented to the
FPGA Digital
Filter
Application
Note
FIR24S
0834A-A–8/97
Symmetrical 24-tap FIR Filter Macro (FIR24S)
FIR24S
CLK
R
SERIAL
DATA
INPUT
SERIAL
DATA
OUTPUT
INIT ID1 ID2 ID3
TIMING SIGNALS
Y
IN
Y
OUT
ID4 ID5
• Variable coefficient-type design
• Coefficient update in real-time via
partial dynamic reconfiguration
• Bit-Serial Digital Signal Processing
• 5M-Samples/second – maximum
sample rate
Design Statistics for “FIR24S”
Utilization Summary Utilized
Speed 76.3
Delay (ns) 13.1
Cells 1636
Size (x * y) 42 x 48
Gates (ASIC) 4686
Power (mA/MHz)
(80% duty cycle) 1.94
FIR24S
2
pre-add sta ges. This signal insures that the carry s ignals
are reset at the beginning of each process cycle. Delayed
versi ons of th is sign al ar e input to the mul tiplie rs and seri al
column adder, initializing each carry-save adder in the
SPMs and the add er tree. As ad diti onal FI R8 S stag es are
cascaded, additional initialization pulses are derived by
adding stages to the control shift register.
QuickChange
In suppo rt of the Cach eLogic capab ility, Atmel ha s devel-
oped QuickChange™, a multi-parameter specification soft-
ware tool that allows the designer to interactively specify
multipl e parameters for digital filte rs, convol vers, and othe r
compute-oriented hardware. After completing the design
with an initial set of parameters, the designer simply
invokes QuickChange from the Atmel design environment.
QuickChange searches the design for filter coefficie nts or
other parame ters, log ically group s them and displ ays them
in a graphi cal user-int erface. The designer can then sp ec-
ify as many replacement sets of parameters as desired.
The QuickChange tool then generates the FPGA bit-
streams for each new parameter or sets of parameters.
These small bitstream files, called “windowed” bit-streams,
partially reconfigure the FPGA without affecting the opera-
tion of existing logic.
FIR8S
UPSTREAM
CASCADE
OUTPUT
CLK
R
SERIAL
DATA
INPUT
UPSTREAM
CASCADE
INPUT
SERIAL
DATA
OUTPUT
DOWNSTREAM
CASCADE
OUTPUT
INIT ID1 ID2 ID3
CONTROL SIGNALS
FIR8S
UPSTREAM
CASCADE
OUTPUT
CLK
R
SERIAL
DATA
INPUT
UPSTREAM
CASCADE
INPUT
SERIAL
DATA
OUTPUT
DOWNSTREAM
CASCADE
OUTPUT
INIT ID1 ID2 ID3
CONTROL SIGNALS
YD24
OUT
SERIAL DATA
INPUT
YD20
OUT
YD4
OUT
X
CLK
R
SUMY
INIT
CSADDI
SERIAL DATA OUTPUT
FIR8S
UPSTREAM
CASCADE
OUTPUT
CLK
R
SERIAL
DATA
INPUT
UPSTREAM
CASCADE
INPUT
SERIAL
DATA
OUTPUT
DOWNSTREAM
CASCADE
OUTPUT
INIT ID1 ID2 ID3
YD16
OUT
YD8
OUT
YD12
OUT
D
R
CONTROL SIGNALS
Q
X
CLK
R
SUMY
INIT
CSADDI
ID4
ID5
Y12O
YO2 YO3YO1