FIR24S
1
The symmetrical 24-tap FIR filter macro
is constructed by cascading the symmet-
rical 8-tap FIR filter hard macro
(FIR8S). The FIR8S macro is designed
to be cascaded by breaking the delay-
line between the 4th and 5th taps and
connecting to the input and cascade out-
puts, respectively, of the next macro
block. The outputs from the filter macros
are summed by additional carry-save
adder (CSADDI) stages. In the final
macro stage, the cascade tap input/out-
puts are connected together.
The coefficients are stored as constant
cells in the Atmel AT6000 FPGA archi-
tecture. This provides the com pact and
efficient storage of a fixed-coefficient
scheme but is variable in real-time
through the use of Cache-Logic™
(dynamic partial reconfiguration of the
FPGA). Any one or more of the coeffi-
cients can be modified by sending the
approp riate bit-stre am(s) to the FP GA.
While the updates occur, the filter contin-
ues to op erate undist urbed as doe s the
rest of the circuitry in the array. This is
another unique benefit of Atmel FPGAs.
Control of the fil ter is ac hie ve d by gener-
ating an initialization signal at each new
sample time. This single clock-cycle
wide pulse is delivered to the filter as the
LSB of each sample is presented to the
FPGA Digital
Filter
Application
Note
FIR24S
0834A-A–8/97
Symmetrical 24-tap FIR Filter Macro (FIR24S)
FIR24S
CLK
R
SERIAL
DATA
INPUT
SERIAL
DATA
OUTPUT
INIT ID1 ID2 ID3
TIMING SIGNALS
Y
IN
Y
OUT
ID4 ID5
• Variable coefficient-type design
• Coefficient update in real-time via
partial dynamic reconfiguration
• Bit-Serial Digital Signal Processing
• 5M-Samples/second – maximum
sample rate
Design Statistics for “FIR24S”
Utilization Summary Utilized
Speed 76.3
Delay (ns) 13.1
Cells 1636
Size (x * y) 42 x 48
Gates (ASIC) 4686
Power (mA/MHz)
(80% duty cycle) 1.94