DM9102
10/1 00Mbps S ingle C hip L AN Controller
50 Final
Version: DM9102-DS-F03
August 30, 2000
a
Ne t work Fu nction
1. O verview
This chapter w ill introduce the norm al state machine
operation and MAC layer manageme nt like collision
backoff algorithm. In transmit mode, the DM9102
initiates a DMA cycle to access data from a transmit
buffer. It prefaces the data with the p ream ble, the
SFD patter n, and it appends a 32-bit CRC. In
receive mode, the dat a is de-serialized by recei ve
mechanism and fed into the internal FIFO. For
detailed process, pl ease see below .
2. Receive Process and State Machine
a. Reception Initiation
As a pr eamble be ing detected on the recei ve data
lines, the DM9102 synchronizes itself to the data
stream during the preamble and waits for the SFD.
The synchronization process is based on byte
boundary and the SFD byte is 10101011. If the
DM9102 receives a 00 or a 11 after the f irst 8
preamble bits and before receiving the SFD, the
reception process will be terminated.
b. Address Rec ogniti on
After initial synchronizatio n, the DM9102 will
recognize the 6-byte destination address field. The
first bit of the destination address signifies whether it
is a physical address (=0) or a multicast address
(=1). The DM9102 filters the frame based on the
node address of receive address filter setting. If the
frame passes the filter, the subsequent s erial data
will be delivered into the host memory.
c. Fram e Decapsulat ion
The DM9102 checks the CRC bytes of all received
frames before releasing the frame along with the
CRC to the ho st processor.
3. Transmit Process and State Machine
a. Tr ansmission Initiati on
Once the host processor prepares a transmit
descriptor for the transmit buffer, the host processor
signals the DM9102 to take it. After the DM9102 has
been notified of thi s tra nsmit list , the DM 9102 wil l
start to mov e the data bytes f ro m the host memory
to the internal transmit FIFO. When transmit FIFO is
adequately filled to the programmed threshold level,
or when there is a full frame buffered into the
transmit FIFO, the DM9102 begins to encapsulate
the frame. The transmit encapsulation is performed
by the transmit state machine, which delays the
actu a l tra n smis sion onto the network unt il the
network has been idle for a minimum interframe gap
time.
b. F rame Encapsulat ion
The transmit data fra me encapsulation stream
consists of two parts: Basic frame beginning and
basic frame end. The former contains 56 pream ble
bits and SFD, the later, FCS. The basic fr am e read
from the host memory includes the destination
address, the source address, the type/length field,
and the data field. If the data field is less than 46
bytes, the DM9102 will pad the frame with the
pattern 00 up to 46 bytes.
c. Collision
When concurrent transmissions from two or more
nodes occur (te rmed; collision), the DM9102 halts
the transmiss ion of data bytes and begins a jam
pattern consisting of AAAAAAAA. At the end of the
jam transmission, it begins the backoff wait ti me. I f
the collision was detected during the preamble
transmission, the jam pattern is transmitted after
completi ng the preamble. The backoff process is
called truncated binary exponential backoff. The
delay is a random integer multiple of slot times. The
num ber of slot tim es of delay before the Nth
retransmission attempt is chosen as a uniformly
dist r ibut ed random integer in the range:
0 ≤ r < 2k
k = min ( n, N ) and N=10
4. Physical Layer Overview:
The DM9102 provides 100M/10Mbps dual port
operation. It provides a direct interface either t o
Unshielded Twisted pair Cable UTP5 for 100BASE-
TX Fast E thernet, or UTP5/UTP3 Cable for
10BASE-T Et hernet. In physi cal l evel operati on, it
consists of the following blocks:
Ƒ
PCS
Ƒ
Clock generator
Ƒ
NRE/NREI, MLT 3 encoder/decoder and driver
Ƒ
MANCHESTER encoder/decoder
Ƒ
10BASE-T filter and driver