DM9102 10/100Mbps Single Chip LAN Controller T General Description The DAVICOM's DM9102 is a highly integrated singlechip Fast Ethernet controller. It fully integrated 100BASETX/10Base-T Fast Ethernet MAC, PHY and PMD. It is fully compliant with PCI Spec. 2.1 and IEEE802.3u. The DM9102 provides a direct interface to the PCI local bus and direct connection to the network wire. As a T controller, it provides the bus master capability. The DM9102 also supports auto-negotiation function that enables it to detect speed and duplex automatically. Due to the well-controlled rising/falling time, it requires no external filter to transmit signal to the media. Block Diagram EEPROM Interface PHYceiver Boot ROM Interface DMA MAC TX+/NRZI to MLT3 NRZ to NRZI Parallel to Serial Scrambler 4B/5B Encoding TX Machine TX FIFO RX Machine RX FIFO MII RX+/AEQ MLT3 to NRZI NRZI to NRZ Parallel to Serial DeScrambler 4B/5B Decoding PCI Interface LED Driver Autonegotiation Final Version: DM9102-DS-F03 August 30,2000 MII Management Control & MII Register 1 DM9102 10/100Mbps Single Chip LAN Controller Table of Contents General Description ................................................1 Block Diagram ........................................................1 13. PHY Status Register (CR12)........................... 32 14. Frame Access Register................................... 33 15. Frame Data Register (CR14) .......................... 33 16. Watching & Jabber Timer Register (CR15) ..... 33 Features .................................................................4 Pin Configuration: DM9102 QFP .............................5 Pin Description .......................................................6 - PCI Bus Interface ................................................6 - Boot ROM and EEPROM Interface ......................7 Multiplex Mode ...................................................7 Direct Mode .........................................................8 - LED Pins .............................................................9 - Network Interface ..............................................10 - Clock Pins .........................................................10 - Miscellaneous Pins............................................10 - Power Pins ........................................................11 Register Definition ................................................12 PCI Configuration Registers ..............................12 Key to Default .......................................................13 Identification ID..................................................14 Command & Status............................................14 Command Register Definition ............................16 Revision ID........................................................17 Miscellaneous Function .....................................17 I/O Base Address...............................................18 Memory Mapped Base Address .........................18 Subsystem Identification ....................................19 Expansion ROM Base Address..........................19 Capabilities Pointer............................................20 Interrupt & Latency Configuration.......................20 Device Specific Configuration Register ..............20 PHY Management Register Set ........................ 34 Key To Default ..................................................... 34 Basic Mode Control Register (BMCR) - Register 0 .......................................................... 35 Basic Mode Status Register (BMSR) - Register 1 .......................................................... 36 PHY ID Identifier Register #1 (PHYIDR1) - Register 2 .......................................................... 37 PHY ID Identifier Register #2 (PHYIDR2) - Register 3 .......................................................... 37 Auto-negotiation Advertisement Register (ANAR) - Register 4 .......................................................... 37 Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5 ......................................... 38 Auto-negotiation Expansion Register (ANER) - Register 6 .......................................................... 39 DAVICOM Specified Configuration Register (DSCR) - Register 16......................................................... 39 DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17 ........................... 40 Control and Status Register (CR)......................22 Key to Default .......................................................22 1. System Control Register (CR0) .........................23 2. Transmit Descriptor Poll Demand (CR1)............24 3. Receive Descriptor Poll Demand (CR2) ............24 4. Receive Descriptor Base Address (CR3) ...........24 5. Transmit Descriptor Base Address (CR4) ..........25 6. Network Status Report Register (CR5)..............25 7. Network Operation Register (CR6) ....................27 8. Interrupt Mask Register (CR7)...........................29 9. Statistical Counter Register (CR8).....................30 10. PROM & Management Access Register (CR9) 31 System Buffer Management .............................. 42 1. Overview .......................................................... 42 2. Data Structure and Descriptor List .................... 42 3. Buffer Management: Ring Structure Method ..... 42 4. Buffer Management: Chain Structure Method ... 43 5. Descriptor List: Buffer Descriptor Format .......... 43 (a). Receive Descriptor Format ............................. 43 11. Programming ROM Address Register (CR10) .32 12. General Purpose Timer Register (CR11) .........32 (b). Transmit Descriptor Format ............................ 45 2 10Base-T Configuration/Status (10BTSCRCSR) - Register 18......................................................... 41 Functional Description .......................................... 42 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Initialization Procedure..........................................48 Data Buffer Processing Algorithm..........................48 1. Receive Data Buffer Processing ........................48 2. Transmit Data Buffer Processing .......................49 Network Function ..............................................50 1. Overview...........................................................50 2. Receive Process and State Machine .................50 3. Transmit Process and State Machine ................50 4. Physical Layer Overview ...................................50 PCI Clock Spec. Timing.....................................56 Other PCI Signals Timing Diagram ....................56 Multiplex Mode Boot ROM Timing......................57 Direct Mode Boot ROM Timing ..........................57 EEPROM Timing ...............................................58 PHYceiver .........................................................58 Auto-negotiation and Fast Link Pulse Timing Diagram ............................................................59 Package Information.............................................60 Serial Management Interface.............................51 Ordering Information.............................................61 Configuration ROM Overview................................52 1. Subsystem ID Block ..........................................52 2. CROM Version..................................................53 3. Controller Count................................................53 4. Controller_X Information ...................................53 5. Controller Information Body Pointed By Controller_X Info Block Offset Item in Controller Information Header ............................................53 Disclaimer ............................................................61 Company Overview ..............................................61 Products ...............................................................61 Contact Windows..................................................61 Warning................................................................61 Absolute Maximum Ratings...................................55 DC Electrical Characteristics .................................55 Appendix A ...........................................................62 DM9102 SROM Format.....................................62 AC Electrical Characteristics & Timing Waveforms56 Final Version: DM9102-DS-F03 August 30,2000 3 DM9102 10/100Mbps Single Chip LAN Controller T Features T Single chip LAN controller integrated Fast Ethernet MAC, PHY and transceiver T Compliant with IEEE 802.3u 100BASE-TX, IEEE 802.3 10BASE-T and ANSI X3T12 TP-PMD standard T Direct interface to the PCI bus & fully compliant with PCI specification 2.1 T PCI bus master architecture T Support PCI bus burst mode data transfer with programmable burst size T EEPROM 93C46 interface to store configuration information and user defined message T Support up to 256K bytes Boot ROM interface T Two large independent receive FIFO (4K) & transmit FIFO (2K) with programmable FIFO threshold and full packet burst processing 4 T Support automatic packet deletion for runt packets and packet re-transmission with no FIFO reload T Support Full/Half Duplex operation T Physical, broadcast address recognition and 512-bit hash table algorithm for multicast address filtering T Compliant with IEEE802.3u Auto-negotiation protocol for automatic link type selection T High performance 100Mbps clock generator and data recovery circuit T Digital clock recovery circuit using advanced digital algorithm to reduce jitter T Adaptive equalization circuit and Baseline wandering restoration circuit for 100Mbps receiver T Provides Loopback mode for easy system diagnostics T 128 pin QFP with CMOS process Final Version: DM9102-DS-F03 August 30, 2000 PCLK August 30, 2000 Final Version: DM9102-DS-F3 DGND IRDY# TRDY# 28 29 30 31 32 33 34 35 36 37 38 23 24 25 26 27 116 117 118 119 120 121 122 123 124 125 126 127 128 CBE3# IDSEL DVDD AD23 AD22 AD21 AD20 DGND AD19 AD18 AD17 AD16 DVDD DVDD CBE2# FRAME# DGND 104 105 106 107 108 109 110 111 112 113 114 115 13 14 15 16 17 18 19 20 21 22 TAGND OSCVDD X1/OSC X2 OSCGND PWRIN DVDD DVDD DGND DGND INT# RST# REQ# NC DGND DGND AD31 AD30 AD29 AD28 DGND AD27 AD26 AD25 AD24 DVDD DGND BGRES BGGND RAVDD RXIRXI+ RAGND TAGND TAGND TXOTXO+ TAVDD TAVDD TAGND 3 4 5 6 7 8 9 10 11 12 1 2 65 68 67 66 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 95 94 93 92 98 97 96 AD1 AD2 DGND DGND AD3 AD4 DVDD DVDD BPAD2 BPAD1 BPAD0 DGND AD0 (MD0/EEDI) (MD1) (MD2) (MA8) TEST1 (MA7) TEST0 S E L R O M (MA6/SELROM) (MA5) EECS (MA4/EECK) EECK (MA3/EEDO) EEDO (MA2) EEDI B P A 1 / T E S T (MA1) (MA0) BPA0 DVDD B P C S # (ROMCS) (MD7) BPAD7 (MD6) BPAD6 B P A D 5 (MD5) (MD4) BPAD4 (MD3) BPAD3 MA15 NC MA14 NC L E D 1 0 M (MA13LED10M) L E D 1 0 0 M (MA12/LED100M) L E D F D X (MA11/LEDFDX) L E D T R F (MA10/LEDTRF) TEST2 (MA9) 100 99 MA16 NC NC 102 101 T DVDD DVDD GNT# DM9102 10/100Mbps Single Chip LAN Controller Pin Configuration 103 64 63 62 61 60 59 DM9102 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 AD5 AD6 AD7 DVDD CBE0# DGND AD8 AD9 AD10 DGND DGND AD11 AD12 DVDD DVDD AD13 AD14 AD15 DVDD CBE1# PAR SERR# PERR# STOP# DEVSEL# DGND 5 DM9102 10/100Mbps Single Chip LAN Controller T Pin Description I = Input, O = Output, I/O = Input/Output, O/D = Open Drain, P = Power LI = reset Latch Input, # = all pin name with # are asserted Low PCI Bus Interface Pin No. 1 6 Pin Name PCLK I/O I 4 GNT# I 5 REQ# O 6 20 NC IDSEL I 34 FRAME# I/O 37 IRDY# I/O 38 TRDY# I/O 40 DEVSEL# I/O 41 STOP# I/O 42 PERR# I/O 43 SERR# I/O Description PCI system clock PCI bus clock that provides timing for DM9102 related to PCI bus transactions. The clock frequency range is up to 33MHz. Bus Grant This signal is asserted low to indicate that DM9102 has been granted ownership of the bus by the central arbiter. Bus Request The DM9102 will assert this signal low to request the ownership of the bus. No Connection Initialization Device Select This signal is asserted high during Configuration Space read and write access. Cycle Frame This signal is driven low by the DM9102 master mode to indicate the beginning and duration of a bus transaction. Initiator Ready This signal is driven low when the master is ready to complete the current data phase of the transaction. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. Target Ready This signal is driven low when the target is ready to complete the current data phase of the transaction. During a read, it indicates that valid data is asserted. During a write, it indicates the target is prepared to accept data. Device Select The DM9102 asserts the signal low when it recognizes its target address after FRAME# is asserted. As a bus master, the DM9102 will sample this signal to insure that the destination address for the data transfer is recognized by a target. Stop This signal is asserted low by the target device to request the master device to stop the current transaction. Parity Error The DM9102 as a master or slave will assert this signal low to indicate a parity error on any incoming data. System Error This signal is asserted low when an address parity is detected with PCICS bit31 (detected parity error) Is Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 44 PAR I/O 19 33 45 60 C/BE3# C/BE2# C/BE1# C/BE0# I/O 9~12, 14~17, 22~25,27~30,47,48, 49,52,53,56,57,58,62, 63,64,67,68,71,72,73 AD31~AD0 I/O 127 INT# O/D 128 RST# I enabled. The system error asserts two clock cycles after the falling address if an address parity error is detected. Parity This signal indicates even parity across AD0~AD31 and C/BE0#~C/BE3# including the PAR pin. This signal is an output for the master and an input for the slave device. It is stable and valid one clock after the address phase. Bus Command/Byte Enable During the address phase, these signals define the bus command or the type of bus transaction that will take place. During the data phase these pins indicate which byte lanes contain valid data. C/BE0# applies to bit7-0 and C/BE3# applies to bit31-24. Address & Data These are multiplexed address and data bus signals. As a bus master, the DM9102 will drive address during the first bus phase. During subsequent phases, the DM9102 will either read or write data expecting the target to increment its address pointer. As a target, the DM9102 will decode each address on the bus and respond if it is the target being addressed. Interrupt Request This signal will be asserted low when an interrupt condition as defined in CR5 is set, and the corresponding mask bit in CR7 is not set. System Reset When this signal is asserted low, DM9102 performs the internal system reset to its initial state. Boot ROM and EEPROM Interface (Including Multiplex Mode or Direct Mode): Multiplex Mode: Pin No. Pin Name I/O Description 75~82 BPAD0~BPAD7 I/O Boot ROM Address and Data bus Boot ROM address and Data multiplexed lines bits 0~7. In two consecutive address cycles, these lines contain the boot ROM address pins 7~2, out_enable and write_enable of boot ROM in the first cycle; and these lines contain address pins 15~8 in second cycle. After the first two cycles, these lines contain data bit 7~0 in consective cycles. 83 BPCS# O Boot ROM Chip Select Boot ROM or external register chip select signal. 85 BPA0 O,LI Boot ROM address line. Low address bit0 interfacing to Boot ROM. 86 BPA1/TEST O Boot ROM address line. Low address bit1 interfacing to Boot ROM. This bit is also set to enable TEST mode only in multiplex mode. (debug only) Final Version: DM9102-DS-F3 August 30, 2000 7 DM9102 10/100Mbps Single Chip LAN Controller 87 EEDI I,LI 88 EEDO O 89 EECK O 90 EECS O 92 TEST0 I 93,94 TEST1,TEST2 I 99~101 NC Direct Mode Pin No. 75 Pin Name MD0/EEDI I/O I 76~82 83 85~87 88 MD1~MD7 ROMCS MA0~MA2 MA3/EEDO I O O O 89 MA4/EECK O 90 91 MA5 MA6/SELROM O O/LI 92~94 95~98 MA7~MA9 MA10/LEDTRF O O 8 EEPROM Data In The DM9102 will read the contents of EEPROM serially through this pin. EEPROM Data Out The DM9102 will use this pin to serially write op codes, addresses and data into the EEPROM. EEPROM Serial Clock This pin provides the clock for the EEPROM data transfer. EEPROM Chip Select This pin will enable the EEPROM during loading of the Configuration Data. TEST option control This pin are valid only test mode enabled. In normal operation when in multiplex mode, this pin are pulled low. TEST option control These two pins are valid only test mode is enabled. In normal operation when in multiplex mode, these two pins are pulled low. In Multiplex mode, these three pins are not connected. Description Boot ROM Data Input/EEDI Data In This pin is multiplexed by EEDI and MD0. The DM9102 will read the contents of EEPROM serially through this pin. Boot ROM Data Input Bus Boot ROM or EEPROM chip selection. Boot ROM Address Output Bus Boot ROM Address Output/EEPROM Data Out This pin is multiplexed with MA3 and EEDO. The DM9102 will use this pin to serially write op codes, addresses and data into the EEPROM. Boot ROM Address Output/EEPROM Serial Clock This pin is multiplexed with MA4 and EECK. This pin provides the clock for the EEPROM data transfer. Boot ROM Address Output Bus Boot ROM Address Output Bus/Multiplex or Direct mode selection It is also used as multiplex or direct mode selection at power-up reset. 0 = multiplex mode, 1 = direct mode. Boot ROM Address Output Bus Boot ROM Address Output Bus/Active LED When at the time of Boot ROM operation, the LED maybe flash few seconds. LED Active Low. When operates as LED pin, if Bit5 of PHY Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 96 MA11/LEDFDX O 97 MA12/LED100M O 98 MA13/LED10M O 99~101 MA14~MA16 O Pin Name LEDTRF I/O O 96 LEDFDX O 97 LED100M O 98 LED10M O LED Pins Pin No. 95 Final Version: DM9102-DS-F3 August 30, 2000 management register16 is 0, it is the Activity LED and will flash when in transmitting or receiving. If Bit5 of PHY Management register16 is 1, this pin is no use Boot ROM Address Output/Full-Duplex LED Indicates Full Duplex mode operation. Active low. When at the time of Boot ROM operation, the LED maybe flash few seconds. Boot ROM Address Output/100Mbps LED When at the time of Boot ROM operation, the LED maybe flash few seconds. LED Active Low. When operates as LED pin, if Bit5 of PHY management register16 is 0, it indicates good link to 100Mbps (default). If Bit5 of PHY management register16 is 1, it is link and activity LED. Boot ROM Address Output Bus/10Mbps LED When at the time of Boot ROM operation, the LED maybe flash few seconds. LED Active Low. When operates as LED pin, if Bit5 of PHY management register16 is 0, it indicates good link to 10Mbps (default). If Bit5 of PHY management register16 is 1, it is link and activity LED. Boot ROM Address Output Bus Description Active LED, Active Low If Bit5 of PHY management register16 is 0, it is the Activity LED and will flash when in transmitting or receiving. (default) If Bit5 of PHY Management register16 is 1, this pin is no use. Full-Duplex LED, Active Low Indicates Full-Duplex mode operation. 100Mbps LED, Active Low Indicates 100Mbps mode operation. If Bit5 of PHY management register16 is 0, it indicates good link to 100Mbps. (default) If Bit5 of PHY management register16 is 1, it is link and activity LED. 10Mbps LED, Active Low. Indicates 10Mbps mode operation. If Bit5 of PHY management register16 is 0, it indicates good link to 10Mbps. (default) If Bit5 of PHY management register16 is 1, it is link and activity LED. 9 DM9102 10/100Mbps Single Chip LAN Controller Network Interface Pin No. 107 108 Pin Name RXIRX+ I/O I TXOTXO+ O Pin Name OSCVDD X1/OSC X2 I/O P I O OSCGND P Pin Name SELROM I/O LI 102 104 NC BGRES O I 105 122 BGGND PWRIN I I 112 113 Clock Pins Pin No. 118 119 120 121 Miscellaneous Pins Pin No. 91 10 Description 100M/10Mbps Differential Input Pair. These two pins are differential receive input pair for 100BASE-TX and 10BASE-T. They are capable of receiving 100BASE-TX MLT-3 or 10BASE-T Manchester encoded data. 100M/10Mbps Differential Output Pair. These two pins are differential output pair for 100BASE-TX and 10BASE-T. This output pair provides controlled rise and fall times designed to filter the transmitter output. Description Analog Power Crystal or Oscillator Input. (25MHZ 50ppm) Crystal feedback output pin used for crystal connection only. Leave this pin open if oscillator is used. Analog Ground Description Multiplex mode/Direct mode Selection. This pin is "reset latch input at power up" to select Multiplex mode or direct mode. "0" = multiplex mode (default), "1" = direct mode. At direct mode, this is also a output pin which is used by MA6. No Connection Band-gap Voltage Reference Resistor. It connects to a 6200, 1% error tolerance resistor between this pin and BGGND pin (pin 105) to provide an accurate current reference for DM9102. Ground for Band-gap circuit VDD clamp This pin is used to identify the D3(cold) power state in a power management aware system. This pin should be connected to the PCI power, while other DVDD pins should be connected to the auxiliary power, if any. In non-power management aware systems, or there is no auxiliary power, the DVDD pins and the PWRIN pins should be connected to the PCI power Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Power Pins Pin No. 106 109 114,115 110,111,116,117 7,8,13,26,35,36,39,54 ,55,59,69,70,74,103, 125,126 2,3,18,21,31,32,46,50 ,51,61,65,66,84,123, 124 Final Version: DM9102-DS-F3 August 30, 2000 Pin Name RAVDD RAGND TAVDD TAGND DGND I/O P P P P P DVDD P Description Analog power for receive Analog ground for receive Analog power for transmit Analog ground for transmit Digital ground pins Digital power pins 11 DM9102 10/100Mbps Single Chip LAN Controller T a Register Definition PCI Configuration Registers The definitions of PCI Configuration Registers are based on the PCI specification revision 2.1 and provides the initialization and configuration information to operate the PCI interface in the DM9102. All registers can be accessed with byte, PCI Configuration Registers Mapping : Description Identifier Identification PCIID Command & Status PCICS Revision PCIRV Miscellaneous PCILT I/O Base Address PCIIO Memory Base Address PCIMEM Reserved -------Subsystem Identification PCISID Expansion ROM Base Address PCIROM Capability Pointer CAP_PTR Reserved -------Interrupt & Latency PCIINT Device Specific Configuration Register PCIUSR 12 word, or double word mode. As defined in PCI specification 2.1, read accesses to reserve or unimplemented registers will return a value of "0." These registers are to be described in the following sections. Address Offset 00H 04H 08H 0CH 10H 14H 18H - 28H 2CH 30H 34H 38H 3CH 40H Value of Reset 91021282H 02900007H 02000020H 00000000H undefined undefined load from SROM 00000000H 00000050H 281401XXH 00000000H Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Configuration Register Structure Device ID Vendor ID Status (with bit 4 set to 1) Command Revision Class Code = 020000h BIST Header Type Latency Timer Cach Line Size Bass Address Register CBIO Bass Address Register CBMA Reserved Subsystem ID Subsystem Vendor ID Expansion ROM Base Address Reserved Cap_Ptr Reserved Max_Lat Min_Gnt Interrupt Pin = 1 Device Specific Configuration Register Interrupt Line 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H Reserved 48H 4CH Key to Default In the register description that follows, the default column takes the form <Reset Value> Where <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value Final Version: DM9102-DS-F3 August 30, 2000 <Access Type>: RO = Read only RW = Read/Write R/C : means Read / Write & Write "1" for Clear. 13 DM9102 10/100Mbps Single Chip LAN Controller Identification ID (xxxxxx00 - PCIID) 31 16 15 0 Dev_ID Vend_ID Device ID Vendor ID Bit 16:31 Default 9102h Type RO 0:15 1282h RO Description The field identifies the particular device. Unique and fixed number for the DM9102 is 9102h. It is the product number assigned by DAVICOM. This field identifies the manufacturer of the device. Unique and fixed number for Davicom is 1282h. It is a registered number from SIG. Command & Status (xxxxxx04 - PCICS) 31 16 15 0 Status Command Status Command Status Register Definition: 31 30 29 28 27 26 0 0 25 1 24 23 1 22 21 20 0 0 1 19 16 Detected Parity Error Signal For System Error Master Abort Detected Target Abort Detected Send Target Abort DEVSEL Timing Data Parity Error Detected Slave mode Fast back to Back User Definable 66MHz Capability New Capability 14 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Bit 31 Default 0b Type R/C 30 0b R/C 29 0b R/C 28 0b R/C 27 0b R/C 26:25 01b R/C 24 0b R/C 23 1b R/C 22 21 20 0b 0b 1b R/C R/C R/C 19:16 0000b RO Final Version: DM9102-DS-F3 August 30, 2000 Description Detected Parity Error The DM9102 samples the AD[0:31], C/BE[0:3]#, and the PAR signal to check parity and to set parity errors. In slave mode, the parity check falls on command phase and data valid phase (IRDY# and TRDY# both active). While in master mode, the DM9102 will check during each data phase of a memory read cycle for a parity error During a memory write cycle, if an error occurs, the PERR# signal will be driven by the target. This bit is set by the DM9102 and cleared by writing "1". There is no effect by writing "0". Signal For System Error This bit is set when the SERR# signal is driven by the DM9102. This system error occurs when an address parity is detected under the condition that bit 8 and bit 6 in command register below are set. Master Abort Detected This bit is set when the DM9102 terminates a master cycle with the master-abort bus transaction. Target Abort Detected This bit is set when the DM9102 terminates a master cycle due to a target-abort signal from other targets. Send Target Abort (0 For No Implementation) The DM9102 will never assert the target-abort sequence. DEVSEL Timing (01 Select Medium Timing) Medium timing of DEVSEL# means the DM9102 will assert DEVSEL# signal two clocks after FRAME# is sample "asserted." Data Parity Error Detected This bit will take effect only when operating as a master and when a Parity Error Response Bit in command configuration register is set. It is set under two conditions: (i) PERR# asserted by the DM9102 in memory data read error, (ii) PERR# sent from the target due to memory data write error. Slave mode Fast Back-To-Back Capable (1 For Good Capability) This bit is always reads "1" to indicate that the DM9102 is capable of accepting fast back-to-back transaction as a slave mode device. User-Definable-Feature Supported (0 For No Support) 66 MHz Capable (0 For No Capability) New Capabilities This bit indicates whether this function implements a list of extended capabilities such as PCI power management. When set this bit indicates the presence of New Capabilities. A value of 0 means that this function does not implement New Capabilities. Reserved 15 DM9102 10/100Mbps Single Chip LAN Controller Command Register Definition: 15 10 Reserved 9 8 7 0 R/W 0 6 5 4 3 R/W 0 0 0 2 1 0 R/W R/W R/W Mast Mode Fast Back-To-Back SERR# Driver Enable/Disable Address/Data Steeping Parity Error Response Enable/Disable VGA Palette snoop Memory Write and Invalid Special Cycle Master Device Capability Enable/Disable Memory Space Access Enable/Disable I/O Space Access Enable/Disable 16 Bit 15:10 9 Default 000000b 0b Type RO RO 8 0b RW 7 6 0b 0b RO RW 5 4 0b 0b RO RO 3 2 0b 1b RO RW 1 1b RW 0 1b RW Description Reserved Master Mode Fast Back-To-Back (0 For No Support) The DM9102 does not support master mode fast back-to-back capability and will not generate fast back-to-back cycles. SERR# Driver Enable/Disable This bit controls the assertion of SERR# signal output. The SERR# output will be asserted on detection of an address parity error and if both this bit and bit 6 are set. Address/Data Stepping (0 For No Stepping) Parity Error Response Enable/Disable Setting this bit will enable the DM9102 to assert PERR# on the detection of a data parity error and to assert SERR# for reporting address parity error. VGA Palette Snooping (0 For No Support) Memory Write and Invalid (0 For No Implementation) The DM9102 only generates Memory write cycle. Special Cycles (0 For No Implementation) Master Device Capability Enable/Disable When this bit is set, DM9102 has the ability of master mode operation. Memory Space Access Enable/Disable This bit controls the ability of memory space access. The memory access includes memory mapped I/O access and Boot ROM access. As the system boots up, this bit will be enabled by BIOS for Boot ROM memory access. While in normal operation using memory mapped I/O access, this bit should be set by driver before memory access cycles. I/O Space Access Enable/Disable This bit controls the ability of I/O space access. It will be set by BIOS after power on. Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Revision ID (xxxxxx08 - PCIRV) 31 8 7 Class Code 0 Revision ID Class Code Revision Major Number Revision Minor Number 31 8 7 0 Class Code Revision ID Class Code Revision Major Number Revision Minor Number Bit 31:8 Default 020000h Type RO 7:4 0010b RO 3:0 0000b RO Description Class Code (020000h) This is the standard code for Ethernet LAN controller. Revision Major Number This is the silicon-major revision number that will increase for the subsequent versions of the DM9102. Revision Minor Number This is the silicon-minor revision number that will increase for the subsequent versions of the DM9102. Miscellaneous Function (Xxxxxx0c - PCILT) 31 24 BIST 23 16 15 Header Type 8 Latency Timer 7 0 Cache Line Size Built-In Self Test Header Type Latency Timer For The Bus Master Cache Line Size For Memory Read Final Version: DM9102-DS-F3 August 30, 2000 17 DM9102 10/100Mbps Single Chip LAN Controller Bit 31:24 23:16 15:8 Default 00h 00h 00h Type RO RO RW 7:0 00h RO Description Built-In-Self Test (=00h Means No Implementation) Header Type (= 00h Means single function with Predefined Header Type ) Latency Timer For The Bus Master. The latency timer is guaranteed by the system and measured by clock cycles. When the FRAME# asserted at the beginning of a master period by the DM9102, the value will be copied into a counter and start counting down. If the FRAME# is de-asserted prior to count expiration, this value is meaningless. When the count expires before GNT# is de-asserted, the master transaction will be terminated as soon as the GNT# is removed. While GNT# signal is removed and the counter is non-ZERO, the DM9102 will continue with its data transfers until the count expires. The system host will read MIN_GNT and MAX_LAT registers to determine the latency requirement for the device and then initialize the latency timer with an appropriate value. Cache-line Size For Memory Read Mode Selection (00h Means No Implementation For Use) I/O Base Address (Xxxxxx10 - PCIIO) 31 7 6 I/O Base Address 1 0 1 000000 I/O Base Address PCI I/O Range Indication I/O or Memory Space Indicator Bit 31:7 Default Undefined Type RW 6:1 000000b RO 0 1b RO Description PCI I/O Base Address This is the base address value for I/O access cycles. It will be compared to AD[31:7] in the address phase of bus command cycle for the I/O resource access. PCI I/O Range Indication It indicates that the minimum I/O resource size is 80h. I/O Space Or Memory Space Base Indicator Determines that the register maps into the I/O space.(=1 Indicates I/O Base) Memory Mapped Base Address (Xxxxxx14 - PCIMEM) 31 Memory Mapped Base Memory Base Address 7 6 1 000000 0 0 Memory Range Indication I/O or Memory Space Indicator 18 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Bit 31:7 Default Undefined Type R/W 6:1 000000b RO 0 0b RO Description PCI Memory Base Address This is the base address value for Memory access cycles. It will be compared to AD[31:7] in the address phase of bus command cycle for the Memory resource access. PCI Memory Range Indication It indicates that the minimum Memory resource size is 80h. I/O Space Or Memory Space Base Indicator Determines that the register maps into the memory space(=0 Indicates Memory Base) Subsystem Identification (Xxxxxx2c - PCISID) 31 0 Subsystem ID Subsystem Vendor ID Subsystem ID Subsystem Vendor ID Bit 31:16 Default XXXX h Type RO 15:0 XXXX h RO Description Subsystem ID Node number loaded from EEPROM word 1 and different from each card. Subsystem Vendor ID Unique number given by PCI SIG and loaded from EEPROM word 0. Expansion ROM Base Address (Xxxxxx30 - PCIROM) 31 18 17 ROM Base Address 11 0000000 00000000 10 9 1 Reserved 0 R/W ROM Base Address Bit 31:10 Default 00h Type RW 9:1 0 000000000b RO RW 0b Final Version: DM9102-DS-F3 August 30, 2000 Description ROM Base Address With 256K Boundary PCIROM bit17~10 are hardwired to 0, indicating ROM Size is up to 256K Size Reserved Bits Read As 0 Expansion ROM Decoder Enable/Disable If this bit and the memory space access bit are both set to 1, the DM9102 will responds to its expansion ROM. 19 DM9102 10/100Mbps Single Chip LAN Controller Capabilities Pointer (Xxxxxx34 - Cap _Ptr) Cap_Ptr 0 1 0 1 0 0 0 0 7 0 Bit 31:8 7:0 Default 000000h 01010000b Type RO RO Offset 34H Description Reserved Capability Pointer The Cap_Ptr provides an offset (default is 50h) into the function's PCI Configuration Space for the location of the first term in the Capabilities Linked List. The Cap_Ptr offset is DOUBLE WORD aligned so the two least significant bits significant bits are always "0"s Interrupt & Latency Configuration (Xxxxxx3c - PCIINT) 31 24 23 MAX_LAT 16 MIN_GNT 15 8 INT_PIN 7 0 INT_LINE Maximum Latency Timer Minimum Grant Interrupt Pin Interrupt Line Bit 31:24 Default 28h Type RO 23:16 14h RO 15:8 7:0 01h XXh RO RO Description Maximum Latency Timer that can be sustained (Read Only and Read As 28h) Minimum Grant Minimum Length of a Burst Period (Read Only and Read As 14h) Interrupt Pin read as 01h to indicate INTA# Interrupt Line that Is Routed to the Interrupt Controller Device Specific Configuration Register (Xxxxxx40 - PCIUSR) 31 30 29 28 27 26 25 24 23 16 15 8 7 0 Reserved Device Specific Device Specific 20 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Bit 31 30 29 28 27 26 25 Default 0b 0b 0b 0b 0b 0b 0b Type RW RW RO RO RO RO RO 24 0b RO 23:16 15:8 7:0 00h 00h 00h RO RW RO Final Version: DM9102-DS-F3 August 30, 2000 Description Device Specific Bit (sleep mode) Device Specific Bit (snooze mode) When set enable Link Status Change Wake-up Event When set enable Sample Frame Wake-up Event When set enable Magic Packet Wake-up Event When set, indicates link change and Link Status Change Event occurred When set, indicates the sample frame is received and Sample Frame Event occurred When set, indicates the Magic Packet is received and Magic packet Event occurred Reserved Bits Read As 0 Device Specific Reserved Bits Read As 0 21 DM9102 10/100Mbps Single Chip LAN Controller a Control and Status Registers (CR) The DM9102 implement 16 control and status register, which can be accessed by the host. These CRs are double long word aligned. All CRs are set to their default values by a hardware or a software Register CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 reset unless otherwise specified. All Control and Status Registers with their definitions and offset from IO or memory Base Address are shown below: Description System Control Register Transmit Descriptor Poll Demand Receive Descriptor Poll Demand Receive Descriptor Base Address Register Transmit Descriptor Base Address Register Network Status Report Register Network Operation Mode Register Interrupt Mask Register Statistical Counter Register External Management Access Register Programming ROM Address Register General Purpose Timer Register PHY Status Register Access Register Data Register Watchdog And Jabber Timer Register Offset from CSR Base Address 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H 58H 60H 68H 70H 78H Default FFC00000 FFFFFFFF FFFFFFFF 00000000 00000000 FC000000 02400040 FFFE0000 00000000 FFF097FF Unpredictable FFFE0000 FFFFFFXX XXXXXX00 Unpredictable FFFFFEC8 Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> Where <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value 22 <Access Type>: RO = Read only RW = Read/Write WO = Write only Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 1. System Control Register (CR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 Bit 21 Name MRM Default 0b,RW 20 19:17 Reserved TXAP 0b,RW 000b,RW 16 15:14 Reserved ABA 0b,RW 00b,RW BL 000000b, RW 7 6:2 Reserved DGW 0,RW 00000,RW 1 Reserved 0,RW Final Version: DM9102-DS-F3 August 30, 2000 14 13 12 11 10 9 8 7 6 0 5 4 3 2 1 0 0 Description Memory Read Multiple When set, the DM9102 will use memory read multiple command (C/BE3~0 = 1100) when it initialize the memory read burst transaction as a master device. When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same master operation. Must be Zero Transmit Automatic polling interval time When set, the DM9102 will poll the transmit descriptor automatically when it is in the suspend state due to buffer unavailable. The polling interval time is programmable based on the table shown below: Bit 17 Time Interval Bit 19 Bit 18 0 0 0 No polling 0 0 1 200us 0 1 0 800us 0 1 1 1.6ms 1 0 0 12.8us 1 0 1 25.6us 1 1 0 51.2us 1 1 1 102.4us Must be Zero Address Boundary Alignment When set, the DM9102 will execute each burst cycles to stop at the programmed address boundary. The address boundary can be programmed to be 8, 16, or 32 double-word as shown below. Bit 15 Bit 14 0 0 0 1 1 0 1 1 13:8 0 15 Alignment Boundary Reserved 8-double word 16-double word 32-double word Burst Length When reset, the DM9102's burst length in one DMA transfer is limited by the amount of data in the receive FIFO ( when receive ) or the amount of free space in the transmit FIFO (when transmit ). When set, the DMA's burst length is limited by the programmed value. The permissible values are 0, 1, 2, 4, 8, 16, or 32 doublewords. Must be Zero Descriptor Gap Width The value of this field defines the gap width ( count in double-word ) between two continuous descriptor. It is used in ring-type descriptor structure. Must be Zero 23 DM9102 10/100Mbps Single Chip LAN Controller Bit 0 Name SR Default 0,RW Description Software Reset When set, the DM9102 will make a internal reset cycle. All consequent action to DM9102 should wait at least 32 PCI clock cycles to start and no necessary to reset this 2. Transmit Descriptor Poll Demand (CR1) 29 28 27 26 25 24 23 22 21 20 19 18 31 30 Bit 31:0 Name TDP Default FFFFFFFF h ,WO 17 16 15 14 13 12 11 10 9 8 6 7 4 5 2 3 1 0 Description Transmit Descriptor Polling Command Writing any value to this port will force DM9102 to poll the transmit descriptor. If the acting descriptor is not available, transmit process will return to suspend state. If the descriptor shows buffer available, transmit process will begin the data transfer. 3. Receive Descriptor Poll Demand (CR2) 31 30 Bit 31:0 Name RDP 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default Description FFFFFFFFH Receive Descriptor Polling Command ,WO Writing any value to this port will force DM9102 to poll the receive descriptor. If the acting descriptor is not available, receive process will return to suspend state. If the descriptor shows buffer available, receive process will begin the data transfer. 4. Receive Descriptor Base Address (CR3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Bit 31:0 24 Name RDBA Default 00000000h ,RW Description Receive Descriptor Base Address This register defines base address of receive descriptor-chain ( or descriptor-ring ) and must be double-word aligned. The receive descriptor- polling command after CR3 is set will make DM9102 to fetch the descriptor at the Base-Address. In Ringtype structure, the descriptor pointer will go back to the Base-Address after Enddescriptor of ring. Bit1,0 must be "00" for double word alignment. Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 5. Transmit Descriptor Base Address (CR4) 29 28 27 26 25 24 23 22 21 20 19 18 31 30 17 16 15 14 13 12 11 10 9 8 6 7 4 5 2 3 1 0 0 0 Bit 31:0 Name TDBA Default 00000000h ,RW Description Transmit Descriptor Base Address This register defines base address of transmit descriptor-chain ( or descriptor-ring ) and must be double-word aligned. The transmit descriptor- polling command after CR4 is set will make DM9102 to fetch the descriptor at the Base-Address. In Ring-type structure, the descriptor pointer will go back to the Base-Address after End-descriptor of ring. Bit1,0 must be "00" for double word alignment. 6. Network Status Report Register (CR5) 31 Bit 25:23 Name SBEB 30 29 28 27 26 Default 000,RO 22:20 TXPS 000,RO 19:17 RXPS 000b,RO Final Version: DM9102-DS-F3 August 30, 2000 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description System Bus Error Bits These bits are read only and used to indicate the type of system bus fetal error. Valid only when System Bus Error is set. The mapping bits are shown below. Bit25 Bit24 Bit23 Bus Error Type 0 0 0 Parity error 0 0 1 Master abort 0 1 0 Slave abort 0 1 1 Reserved 1 X X Reserved Transmit Process State These bits are read only and used to indicate the state of transmit process. The mapping table is shown below. Process State Bit22 Bit21 Bit20 0 0 0 Transmit process stopped 0 0 1 Fetch transmit descriptor 0 1 0 Move Setup Frame from the host memory 0 1 1 Move data from host memory to transmit FIFO 1 0 0 Close descriptor by clearing owner bit of descriptor 1 0 1 Waiting end of transmit 1 1 0 Transmit end and Close descriptor by writing status 1 1 1 Transmit process suspend Receive Process State These bits are read only and used to indicate the state of receive process. The mapping table is shown below. Process State Bit19 Bit18 Bit17 25 DM9102 10/100Mbps Single Chip LAN Controller 0 0 0 0 1 1 1 1 26 16 NIS 0b,RW 15 AIS 0b,RW 13 SBE 0b,RW 11 GPT 0b,RW 10 TXER 0b,RW 9 RXWT 0b,RW 8 RXPS 0b,RW 7 RXDU 0b,RW 6 RXCI 0b,RW 5 TXFU 0b,RW 3 TXJT 0b,RW 2 TXDU 0b,RW 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive process stopped Fetch receive descriptor Waiting for receive packet under buffer available Move data from receive FIFO to host memory Close descriptor by clearing owner bit of descriptor Close descriptor by writing status Receive process suspended due to buffer unavailable Purge the current frame from the receive FIFO because of unavailable receive buffer Normal Interrupt Summary Normal interrupt includes any of the three conditions : CR5<0> - TXCI : Transmit Complete Interrupt CR5<2> - TXDU : Transmit Buffer Unavailable CR5<6> - RXCI : Receive Complete Interrupt Abnormal Interrupt Summary Abnormal interrupt includes any interrupt condition as shown below excluding Normal Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7), RXPS(bit8), RXWT(bit9), TXER(bit10), GPT(bit11), SBE(bit13). System Bus Error The PCI system bus errors will set this bit. The type of system bus error is shown in CR5<25:23> . General-purpose Timer Expired This bit is set to indicate the general-purpose timer (described in CR11) has expired. Transmit Early Interrupt Transmit Early Interrupt is set when the full packet data has been moved from host memory into transmit FIFO. It will inform the host to process next step before the transmission end. Transmit complete event CR5<0> will clear this bit automatically. Receive Watchdog Timer Expired This bit is set to indicate receive watchdog timer has expired. Receive Process Stopped This bit is set to indicate receive process enters the stopped state. Receive Buffer Unavailable This bit is set when the DM9102 fetches the next receive descriptor is still owned by the host. Receive process will be suspended until a new frame enters or the receive polling command is set. Receive Complete Interrupt This bit is set when a received frame is fully moved into host memory and receive status has been written to descriptor. Receive process is still running and continues to fetch next descriptor. Transmit FIFO Under-run This bit is set when the transmit FIFO has a under-run condition during the packet transmission. It may happen due to the heavy load on bus, receive process dominate in full-duplex, or transmit buffer unavailable before end of packet. In this case, transmit process is placed in the suspend state and under-run error TDES0<1> is set. Transmit Jabber Timer Expired This bit is set when the jabber timer expired with the transmitter is still active. Transmit process will be aborted and placed in the stop state. It also causes transmit jabber timeout TDES0<14> to assert. Transmit Buffer Unavailable This bit is set when the DM9102 fetches the next transmit descriptor that is still owned by the host. The transmit process will be suspended until the transmit Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller polling command is set or auto-polling timer time-out. Transmit Process Stopped This bit is set to indicate transmit process enters the stopped state. 0 TXCI 0b,RW Transmit Complete Interrupt This bit is set when a frame is fully transmitted and the transmit status has been writen to descriptor ( the TDES1<31> is also asserted). The transmit process is still running and continues to fetch next descriptor. Note: Bits 1~16 can be cleared by writing "1" 1 TXPS 0b,RW 7. Network Operation Mode Register (CR6) 31 30 29 28 0 27 26 0 Bit 30 Name RXA Default 0b,RW 28:26 25 24:23 22 Reserved Reserved Reserved TXTM 000b,RW 1b,RW 00b,RW 1b,RW 21 SFT 0b,RW 20 STI 0b,RW 18:19 17 16 MBO Reserved Reserved 00b,RW 0b,RW 0b,RW Final Version: DM9102-DS-F3 August 30, 2000 0 25 24 23 1 0 0 22 21 20 19 18 1 17 16 0 0 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 0 Description Receive All When set, all incoming packet will be received, regardless the destination address. The address match is checked according to theCR6<7>, CR6<6>, CR6<4>, CR6<2>, CR6<0>, and RDES0<30> will show this match. Must be Zero. Must be One. Must be Zero. Transmit Threshold Mode When set, the transmit threshold mode is 10Mb/s. When reset, the threshold mode is 100Mb/s. This bit is used together with CR6<15:14> to decide the exact threshold level. Store and Forward Transmit When set, the packet transmission from MAC will be started after a full frame has been moved from the host memory to transmit FIFO. When reset, the packet transmission's start will depend on the threshold value specified in CR6<15:14> Start Transmission Immediately When this bit is set, the packet transmission from MAC will be started immediately after transmit FIFO's threshold level reaches 16 bytes, regardless of the setting in CR6<22> and CR6<15:14>. This mode will make transmit FIFO underrun condition to happen more easily. Must always write "11" to these two bits. Must be Zero. Must be Zero. 27 DM9102 10/100Mbps Single Chip LAN Controller 15:14 TSB 00b,RW Threshold Bits These bits are set together with CR6<22> (chose 10Mb or 100Mb) and will decide the exact FIFO threshold level. The packet transmission will start after the data level exceeds the threshold value. Threshold(10M) Bit15 Bit14 Threshold(100M) 0 0 128 72 0 1 256 96 1 0 512 128 1 1 Reserved Reserved 13 TXSC 0b,RW 12 FCM 0b,RW 11:10 LBM 00b,RW Transmit Start/stop Command When set, the transmit process will begin by fetching the transmit descriptor for available packet data to be transmitted (running state). If the fetched descriptor is owned by the host, the transmit process will enter the suspend state and transmit buffer unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to FIFO and transmit out after reaching threshold level. When reset, the transmit process is placed in the stopped state after completing the transmission of the current frame. Force Collision Mode When set, the transmission process is forced to be the collision status. Meaningful only in the internalloopback mode. Loopback Mode These bits decide two loopback modes besides normal operation. External loopback mode expects transmitted data back to receive path and makes no collision detection. Bit11 0 0 1 28 9 FDM 0b,RW 7 PAM 0b,RW 6 PM 1b,RW 5 4 Reserved IAFM 0b,RW 0b,RO 3 PBF 0b,RW Bit10 0 1 x Loopback Mode normal internal loopback external loopback Full-duplex Mode When auto-negotiation is disabled, this bit is set to make DM9102 operate in the full-duplex mode. Transmit and receive processes can work simultaneously. There is no collision detection needed during this mode operation. Pass All Multicast When set, any packet with a multicast destination address is received by DM9102. The packet with a physical address will also be filtered based on the CR6<0> filter mode setting. Promiscuous mode When set, any incoming valid frame is received by DM9102, and no matter what the destination address. The DM9102 is initialized to this mode after reset operation. Must be Zero. Inverse Address Filtering Mode It is set to indicate the DM9102 operate in a Inverse Filtering Mode. This is a read only bit and mapped from the setup frame together with CR6<2>, CR6<0> setting. That is it is valid only during perfect filtering mode. Pass Bad Frame When set, the DM9102 is indicated to receive the bad frames including runt packets, truncated frames caused by the FIFO overflow. The bad frame also has to pass the address filtering if the DM9102 is not set in promiscuous mode. Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 2 HOFM 0b,RO 1 RXRC 0b,RW 0 HPFM 0b,RO Hash-only Filter Mode This is a read-only bit and mapped from the set-up frame together with bit4,0 of CR6. It is set to indicate the DM9102 operate in a Hash-only Filtering Mode. Receive Start/Stop Command When set, the receive process will begin by fetching the receive descriptor for available buffer to store the new-coming packet (placed in the running state). If the fetched descriptor is owned by the host (no descriptor is owned by the DM9102), the receive process will enter the suspend state and receive buffer unavailable CR5<7> sets. Otherwise it runs to wait for the packet's income. When reset, the receive process is placed in the stopped state after completing the reception of the current frame. Hash/Perfect Filter Mode This is a read only bit and mapped from the setup frame together with CR6<4>, CR6<2>. When reset, the DM9102 does a perfect address filter of incoming frames according to the addresses specified in the setup frame. When set, the DM9102 does a imperfect address filtering for the incoming frame with a multicast address according to the hash table specified in the setup frame. The filtering mode (perfect/imperfect) for the frame with a physical address will depend on CR6<2>. 8. Interrupt Mask Register (CR7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Bit 16 Name NISE Default 0b,RW 15 AISE 0b,RW 13 SBEE 0b,RW 11 GPTE 0b,RW 10 TXERE 0b,RW 9 RXWTE 0b,RW Final Version: DM9102-DS-F3 August 30, 2000 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Normal Interrupt Summary Enable This bit is set to enable the interrupt for Normal Interrupt Summary. Normal interrupt includes three conditions : CR5<0> - TXCI : Transmit Complete Interrupt CR5<2> - TXDU : Transmit Buffer Unavailable CR5<6> - RXCI : Receive Complete Interrupt Abnormal Interrupt Summary Enable This bit is set to enable the interrupt for Abnormal Interrupt Summary. Abnormal interrupt includes all interrupt condition as shown below excluding Normal Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7), RXPS(bit8), RXWT(bit9), TXER(bit10), GPT(bit11), SBE(bit13). System Bus Error Enable When set together with CR7<15>, CR5<13>, it enables the interrupt for System Bus Error. The type of system bus error is shown in CR5<24:23>. General-purpose Timer Expired Enable This bit is set together with CR7<15>, CR5<11> then it will enable the interrupt for the condition of the general-purpose timer (described in CR11) expired. Transmit Early Interrupt Enable This bit is set together with CR7<16>, CR5<10> then it enables the interrupt of the early transmit event. Receive Watchdog Timer Expired Enable When this bit and CR7<15>, (CR5<9> are set together, it enable the interrupt of the condition of the receive watchdog timer expired. 29 DM9102 10/100Mbps Single Chip LAN Controller 8 RXPSE 0b,RW 7 RXDUE 0b,RW 6 RXCIE 0b,RW 5 TXFUE 0b,RW 3 TXJTE 0b,RW 2 TXDUE 0b,RW 1 TXPSE 0b,RW 0 TXCIE 0b,RW Receive Process Stopped Enable When set together with CR7<15> and CR5<8>. This bit is set to enable the interrupt of receive process stopped condition. Receive Buffer Unavailable Enable When this bit and CR7<15>, CR5<7> are set together, it will enable the interrupt of receive buffer unavailable condition. Receive Complete Interrupt Enable When this bit and CR7<16>, CR5<6> are set together, it will enable the interrupt of receive process completed condition. Transmit FIFO Under-run Enable When set together with CR7<15>, CR5<5>, it will enable the interrupt of the transmit FIFO under-run condition. Transmit Jabber Timer Expired Enable When this bit and CR7<15>, CR5<3> are set together, it enables the interrupt of transmit Jabber Timer Expired condition. Transmit Buffer Unavailable Enable When this bit and CR7<16>, CR5<2> are set together, the transmit buffer unavailable interrupt is enabled. Transmit Process Stopped Enable When this bit is set together with CR7<15> and CR5<1>, it will enable the interrupt of the transmit process stopped Transmit Complete Interrupt Enable When this bit and CR7<16>, CR5<0> are set, transmit interrupt is enabled. 9. Statistical Counter Register (CR8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Bit 31 Name RXFU Default 0b,RO 30:17 RXDU 0000h,RO 16 RXPS 0b,RO 15:0 RXCI 0000h,RO 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Receive Overflow Counter Overflow This bit is set when the Purged Packet Counter (RXDU) has an overflow condition. It is a read only register bit. Receive Purged Packet Counter This is a statistic counter to indicate the purged received packet count upon FIFO overflow. Receive Missed Counter Overflow This bit is set when the Receive Missed Frame Counter (RXCI) has an overflow condition. It is a read only register bit. Receive Missed Frame Counter This is a statistic counter to indicate the Receive Missed Frame Count when there is a host buffer unavailable condition for receive process. Note : CR8 is cleared after read 30 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 10. PROM & Management Access Register (CR9) 31 30 30 31 29 15 14 29 28 28 27 27 2626 2525 2424 2323 22 2221 212020 1919 1818 17 14 1313 1212 1111 10 10 17 16 16 15 Bit 19 Name MDIN Default 0b,RO 18 MRW 0b,RW 17 MDOUT 0b,RW 16 MDCLK 0b,RW 14 MRC 0b,RW 13 EWC 0b,RW 12 BRS 1b,RW 11 ERS 0b,RW 10 XRS 0b,RW 7:0 DATA FFH,RW 3 CRDOUT 1b,RO 2 CRDIN 0b,RW 1 CRCLK 0b,RW 0 CRCS 0b,RW Final Version: DM9102-DS-F3 August 30, 2000 99 88 77 66 55 44 33 22 11 00 Description MII Management Data_In This is read only bit to indicate the MDIO input data. MII Management Read/Write Mode Selection This bit defines the Read/Write Mode for MII management interface for PHY access. MII Management Data_Out This bit is used to generate the output data signal for the MDIO pin. MII Management Clock This bit is used to generate the output clock signal for the MDC pin. Memory Read Control This bit is set to perform the read operation for the Boot PROM or EEPROM access. Memory Write Control This bit is set to perform the write operation for the Boot PROM (Multiplex mode) or EEPROM access. Boot ROM Selected This bit is set to select the Boot ROM access for memory interface. EEPROM Selected This bit is set to select the EEPROM access for memory interface. External Register Selected This bit is set to select an external register. Data input/output of Boot ROM This field contains the data read from or write to the Boot ROM when the Boot ROM mode is selected. (CR9<12> = 1) If EEPROM is selected (CR9<11> = 1), then CR9<3:0> are connected the serial ROM control pins. Data_Out from EEPROM This bit is set to reflect the signal status of EEDI pin when EEPROM mode is selected. Data_In to EEPROM This bit is set to generate the output signal to EEDO pin when EEPROM mode is selected. Clock to EEPROM This bit is set to generate the output clock to EECLK pin when EEPROM mode is selected. Chip_Select to EEPROM This bit is set to generate the output signal to EECS pin when EEPROM mode is selected. 31 DM9102 10/100Mbps Single Chip LAN Controller 11. Programming ROM Address Register (CR10) 31 30 Bit 17:0 Name BADR 29 28 27 26 25 24 23 22 21 20 19 18 Default Unpredictable 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Boot ROM Address This field contains the address pointer for Boot ROM when the mode of programming by register is selected. 12. General Purpose Timer Register (CR11) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Bit 16 Name TCON Default 0b,RW 15:0 MBCLK 0000h,RW 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description Continuous Mode of Timer When this bit is set, the timer will continuously re-initiated upon the set time is up. When reset, the timer will be one-shot response after BCLK value is programmed. Multiple of Base Clock This field set the iteration number of base clock. The base clock duration is defined to be 81.92us --- for MII port/100M is selected 2us --- for MII port/10M is selected 13. PHY Status Register (CR12) 31 30 32 29 28 27 26 25 24 23 22 21 20 19 18 Bit 8 Name GEPC Default X b, RW 7 GEPD(7) X b, RW 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description GEPD Bits Control When in initialization, this bit is set and the unique "80h" must be written to the GEPD(7:0). After initialization, this bit is reset and it controls the functional mode of GEPD in bit0~7. General PHY Reset Control It must be set to "1" if CR12<8> is set. When CR12<8> is reset, write "1" to this bit will reset the PHY of the DM9102. Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 6:0 GEPD(6:0) XXXXXXX b ,RW General PHY Status When CR12<8> is set at initialization, it operates the only write operation and write the unique "0000000" to these seven bits. After initialization, CR12<8> is reset, write operation is meaningless and read these seven bits to indicate the PHY status. These status bits are shown below. bit 6:UTP-SIG bit 5:Signal Detection bit 4:RX-lock bit 3:Link status (the same as bit2 of PHY Register) bit 2:Full-duplex bit 1:Speed 100Mbps link bit 0:Speed 10Mbps link 14. Access Register (CR13) 31 30 29 28 27 26 25 24 23 register TxFIFO RxFIFO DiagReset 22 21 20 19 18 17 16 15 14 13 12 11 10 general definition transmit FIFO access port receive FIFO access port general reset for diagnostic pointer port 9 8 7 6 5 4 3 2 1 bit8 ~ 3 32h 35h 38h 0 R/W r/w r/w w 15. Data Register (CR14) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16. Watchdog and Jabber Timer Register (CR15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 Bit 8 5 Name Reserved TWDR Default 0b,RW 0b,RW 4 TWDE 0b,RW Final Version: DM9102-DS-F3 August 30, 2000 Description Must be Zero. Time Interval of Watchdog Release This bit is used to select the time interval between receive Watchdog timer expiration until re-enabling of the receive channel. When this bit is set, the time interval is 40~48 bits time. When this bit is reset, it is 16~24 bits time. Watchdog Timer Disable When set, the Watchdog Timer is disabled. Otherwise it is enabled. 33 DM9102 10/100Mbps Single Chip LAN Controller a 2 JC 0b,RW 1 TUNJ 0b,RW 0 TJE 0b,RW Jabber Clock When set, the transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted. When reset, transmission for the 10Mbps port is cut off after a range of 26ms to 33ms. When reset, transmission for the 100Mbps port is cut off after a range of 2.6ms to 3.3ms. Transmit Un-jabber Interval This bit is used to select the time interval between the transmit jabber timer expiration until re-enabling of the transmit channel. When set, the transmit channel is released right after the jabber expiration. When reset, the time interval is 365~420ms for 10Mb/s port and 36.5~42.0ms for 100Mb/s. Transmit Jabber Disable When set, the transmit Jabber Timer is disabled. Otherwise it is enabled. PHY Management Register Set Register Address 0 1 2 3 4 5 6 7-15 16 17 18 Others Register Name BMCR BMSR PHYIDR1 PHYIDR2 ANAR ANLPAR ANER Reserved DSCR DSCSR 10BTCSR Reserved Description Basic Mode Control Register Basic Mode Status Register PHY Identifier Register #1 PHY Identifier Register #2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Reserved DAVICOM Specified Configuration Register DAVICOM Specified Configuration/Status Register 10BASE-T Configuration/Status Register Reserved For Future Use-Do Not Read/Write To These Registers Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset 34 <Access Type>: RO = Read only RW = Read/Write <Attribute (s)>: SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Basic Mode Control Register (BMCR) - Register 0 Bit 0.15 Name Reset Default 0b, RW/SC 0.14 Loopback 0b, RW 0.13 Speed Selection 1b, RW 0.12 Autonegotiation Enable 1b, RW 0.11 Power Down 0b, RW 0.10 Isolate (PHYAD=00000b) ,RW 0.9 Restart Autonegotiation 0b,RW/SC 0.8 Duplex Mode 1b,RW Final Version: DM9102-DS-F3 August 30, 2000 Description Reset: 1=Software reset 0=Normal operation This bit sets the status and controls the PHY registers of DM9102 to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed Loopback: Loop-back control register 1=Loop-back enabled 0=Normal operation When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appear at the MII receive outputs Speed Select: 1=100Mbps 0=10Mbps Link speed may be selected either by this bit or by Autonegotiation. When Auto-negotiation is enabled and bit 12 is set, this bit will return Auto-negotiation selected media type. Auto-negotiation Enable: 1= Auto-negotiation enabled: bit 8 and 13 will be in Autonegotiation status 0= Auto-negotiation disabled: bit 8 and 13 will determine the link speed and mode Power Down: Setting this bit will power down the whole chip except crystal oscillator circuit. 1=Power Down 0=Normal Operation Isolate: 1= Isolates the DM9102 from the MII with the exception of the serial management. 0= Normal Operation Restart Auto-negotiation: 1= Restart Auto-negotiation. Re-initiates the Auto-negotiation process. When Auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning a value of 1 until Auto-negotiation is initiated by the DM9102. The operation of the Auto-negotiation process will not be affected by the management entity that clears this bit 0= Normal Operation Duplex Mode: 1= Full Duplex operation. Duplex selection is allowed when Autonegotiation is disabled (bit 12 of this register is cleared). With Auto-negotiation enabled, this bit reflects the duplex capability selected by Auto-negotiation 0= Normal operation 35 DM9102 10/100Mbps Single Chip LAN Controller 0.7 Collision Test 0b,RW 0.6:0.0 Reserved 0000000b,RO Collision Test: 1= Collision Test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN 0= Normal Operation Reserved: Write as 0, ignore on read Basic Mode Status Register (BMSR) - Register 1 Bit 1.15 Name 100BASE-T4 Default 0b,RO/P 1.14 100BASE-TX Full Duplex 1b,RO/P 1.13 100BASE-TX Half Duplex 1b,RO/P 1.12 10BASE-T Full Duplex 1b,RO/P 1.11 10BASE-T Half Duplex 1b,RO/P 1.10-1.7 Reserved 1.6 MF Preamble Suppression 0000b ,RO 0b,RO 1.5 Auto-negotiation Complete 0b,RO 1.4 Remote Fault 0b, RO/LH 1.3 Auto-negotiation Ability 1b,RO/P 1.2 Link Status 0b ,RO/LL 1.1 Jabber Detect 0b, 36 Description 100BASE-T4 Capable: 1=DM9102 is able to perform in 100BASE-T4 mode 0=DM9102 is not able to perform in 100BASE-T4 mode 100BASE-TX FULL DUPLEX CAPABLE: 1= DM9102 able to perform 100BASE-TX in Full Duplex mode 0= DM9102 not able to perform 100BASE-TX in Full Duplex mode 100BASE-TX Half Duplex Capable: 1=DM9102 is able to perform 100BASE-TX in Half Duplex mode 0=DM9102 is not able to perform 100BASE-TX in Half Duplex mode 10BASE-T Full Duplex Capable: 1=DM9102 is able to perform 10BASE-T in Full Duplex mode 0=DM9102 is not able to perform 10BASE-T in Full Duplex mode 10BASE-T Half Duplex Capable: 1=DM9102 is able to perform 10BASE-T in Half Duplex mode 0=DM9102 is not able to perform 10BASE-T in Half Duplex mode Reserved: Write as 0, ignore on read MII Frame Preamble Suppression: 1=PHY will accept management frames with preamble suppressed 0=PHY will not accept management frames with preamble suppressed Auto-negotiation Complete: 1=Auto-negotiation process completed 0=Auto-negotiation process not completed Remote Fault: 1= Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9102 implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0= No remote fault condition detected Auto Configuration Ability: 1=DM9102 able to perform Auto-negotiation 0=DM9102 not able to perform Auto-negotiation Link Status: 1=Valid link established (for either 10Mbps or 100Mbps operation) 0=Link not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the Link Status bit to be cleared and remain cleared until it is read via the management interface Jabber Detect: Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller RO/LH 1.0 Extended Capability 1b,RO/P 1=Jabber condition detected 0=No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9102 reset. This bit works only in 10Mbps mode Extended Capability: 1=Extended register capability 0=Basic register capability only PHY ID Identifier Register #1 (PHYIDR1) - Register 2 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9102. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. Bit 2.15-2.0 Name OUI_MSB Default <0181H> Description OUI Most Significant Bits: This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2) PHY Identifier Register #2 (PHYIDR2) - Register 3 Bit 3.15-3.10 Name OUI_LSB Default <101110b> ,RO/P 3.9-3.4 VNDR_MDL <000000b> ,RO/P 3.3-3.0 MDL_REV <0000b>,RO/P Description OUI Least Significant Bits: Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively Vendor Model Number: Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) Model Revision Number: Four bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3) Auto-negotiation Advertisement Register (ANAR) - Register 4 This register contains the advertised abilities of this DM9102 device as they will be transmitted to its link partner during Auto-negotiation. Bit 4.15 Name NP Default 0b,RO/P 4.14 ACK 0b,RO 4.13 RF 0b, RW Final Version: DM9102-DS-F3 August 30, 2000 Description Next Page Indication: 0=No next page available 1=Next page available The DM9102 has no next page, so this bit is permanently set to 0 Acknowledge: 1=Link partner ability data reception acknowledged 0=Not acknowledged The DM9102's Auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the Auto-negotiation process. Software should not attempt to write to this bit. Remote Fault: 1=Local Device senses a fault condition 37 DM9102 10/100Mbps Single Chip LAN Controller 4.12-4.11 Reserved 00b, RW 4.10 FCS 0b, RW 4.9 T4 0b, RO/P 4.8 TX_FDX 1b, RW 4.7 TX_HDX 1b, RW 4.6 10_FDX 1b, RW 4.5 10_HDX 1b, RW 4.4-4.0 Selector <00001b>, RW 0=No fault detected Reserved: Write as 0, ignore on read Flow Control Support: 1=Controller chip supports flow control ability 0=Controller chip doesn't support flow control ability 100BASE-T4 Support: 1=100BASE-T4 supported by the local device 0=100BASE-T4 not supported The DM9102 does not support 100BASE-T4 so this bit is permanently set to 0 100BASE-TX Full Duplex Support: 1=100BASE-TX Full Duplex supported by the local device 0=100BASE-TX Full Duplex not supported 100BASE-TX Support: 1=100BASE-TX supported by the local device 0=100BASE-TX not supported 10BASE-T Full Duplex Support: 1=10BASE-T Full Duplex supported by the local device 0=10BASE-T Full Duplex not supported 10BASE-T Support: 1=10BASE-T supported by the local device 0=10BASE-T not supported Protocol Selection Bits: These bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports IEEE 802.3 CSMA/CD. Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit 5.15 Name NP Default 0b, RO 5.14 ACK 0b, RO 5.13 RF 0b, RO 5.12-5.10 Reserved 000b, RO 5.9 T4 0b, RO 5.8 TX_FDX 0b, RO 38 Description Next Page Indication: 0= Link partner, no next page available 1= Link partner, next page available Acknowledge: 1=Link partner ability data reception acknowledged 0=Not acknowledged The DM9102's Auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit. Remote Fault: 1=Remote fault indicated by link partner 0=No remote fault indicated by link partner Reserved: Write as 0, ignore on read 100BASE-T4 Support: 1=100BASE-T4 supported by the link partner 0=100BASE-T4 not supported by the link partner 100BASE-TX Full Duplex Support: Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 5.7 TX_HDX 0b, RO 5.6 10_FDX 0b, RO 5.5 10_HDX 0b, RO 5.4-5.0 Selector <00000b>, RO 1=100BASE-TX Full Duplex supported by the link partner 0=100BASE-TX Full Duplex not supported by the link partner 100BASE-TX Support: 1=100BASE-TX Half Duplex supported by the link partner 0=100BASE-TX Half Duplex not supported by the link partner 10BASE-T Full Duplex Support: 1=10BASE-T Full Duplex supported by the link partner 0=10BASE-T Full Duplex not supported by the link partner 10BASE-T Support: 1=10BASE-T Half Duplex supported by the link partner 0=10BASE-T Half Duplex not supported by the link partner Protocol Selection Bits: Link partner's binary encoded protocol selector Auto-Negotiation Expansion Register (ANER)-Register 6 Bit 6.15-6.5 Name Reserved Default 0b, RO 6.4 PDF 0b, RO/LH 6.3 LP_NP_ABLE 0b, RO 6.2 NP_ABLE 0b,RO/P 6.1 PAGE_RX 0b, RO/LH 6.0 LP_AN_ABLE 0b, RO Description Reserved: Write as 0, ignore on read Local Device Parallel Detection Fault: PDF=1: A fault detected via parallel detection function. PDF=0: No fault detected via parallel detection function Link Partner Next Page Able: LP_NP_ABLE=1: Link partner, next page available LP_NP_ABLE=0: Link partner, no next page Local Device Next Page Able: NP_ABLE=1: DM9102, next page available NP_ABLE=0: DM9102, no next page DM9102 does not support this function, so this bit is always 0. New Page Received: A new link code word page received. This bit will be automatically cleared when the register (Register 6) is read by management Link Partner Auto-negotiation Able: A "1" in this bit indicates that the link partner supports Auto-negotiation. DAVICOM Specified Configuration Register (DSCR) - Register 16 Bit 16.15:16.13 16.12 16.11 16.10 16.9 Name Reserved Reserved Reserved TX UTP Default 0b, RW 0b, RW 0b, RW 1b, RW 1b, RW 16.8 16.7 Reserved F_LINK_100 0b, RW 0b, RW 16.6 Reserved 1b, RW Final Version: DM9102-DS-F3 August 30, 2000 Description Reserved This bit must set to be 0. This bit must set to be 0 This bit must set to be 1 UTP Cable Control: 1=The media is a UTP cable, 0=STP Reserved Force Good Link in 100Mbps: 0=Normal 100Mbps operation 1=Force 100Mbps good link status This bit is useful for diagnostic purposes. This bit must forced to be 1. 39 DM9102 10/100Mbps Single Chip LAN Controller 16.5 LED_CTL 0b,RW 16.4 16.3 Reserved SMRST 0b,RW 0b,RW 16.2 MFPSC 0b,RW 16.1 SLEEP 0b,RW 16.0 RLOUT 0b,RW LED Mode Select: (control LEDTRF, LED100M, LED10M) 0 = LEDTRF is Activity LED, and LED100M indicates good link to 100Mbps, LED10M indicates good link to 10Mbps . 1 = LEDTRF is no use, LED100M, LED10M indicate Link and Activity. When good links to 100Mbps, LED100M actives and flashes if any traffic exists. When good links to 10Mbps, LED10M actives and flashes if any traffic exists. This bit must forced to be 0 Reset State Machine: When write 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed. MF Preamble Suppression Control: MII frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off Sleep Mode: Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset Remote Loop out Control: When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17 40 Bit 17.15 Name 100FDX Default 1b, RO 17.14 100HDX 1b, RO 17.13 10FDX 1b, RO 17.12 10HDX 1b, RO Description 100M Full Duplex Operation Mode: After Auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100Mbps Full Duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. 100M Half Duplex Operation Mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100Mbps half-duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. 10M Full Duplex Operation Mode: After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10Mbps Full Duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. 10M Half Duplex Operation Mode: After Auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10Mbps Half Duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 17.11-17.9 Reserved 000b, RW 17.8-17.4 PHYAD[4:0] 00001b, RW 17.3-17.0 ANMB[3:0] 0000b, RO Reserved: Write as 0, ignore on read PHY Address Bit 4:0: The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY. A PHY address of <00000> will cause the isolate bit of the BMCR (bit 10, Register Address 00) to be set. Auto-negotiation Monitor Bits: These bits are for debug only. The Auto-negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 0 0 0 0 In IDLE state Ability match 0 0 0 1 0 1 0 1 Acknowledge match Acknowledge match fail 0 0 1 0 1 0 0 1 Consistency match Consistency match fail 0 0 1 1 1 1 0 1 Parallel detects signal_link_ready Parallel detects signal_link_ready fail 1 0 0 0 Auto-negotiation completed successfully 10BASE-T Configuration/Status (10BTCSRCSR) - Register 18 Bit 18.15 Name Reserved Default 0b, RO 18.14 LP_EN 1b, RW 18.13 HBE 1b,RW 18.12 Reserved 0b, RO 18.11 JABEN 1b, RW 18.10 18.9-18.1 18.0 Reserved Reserved Reserved 0b,RW 0b, RO 0b, RO Final Version: DM9102-DS-F3 August 30, 2000 Description Reserved: Write as 0, ignore on read Link Pulse Enable: 1=Transmission of link pulses enabled 0=Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation. Heartbeat Enable: 1=Heartbeat function enabled 0=Heartbeat function disabled When the DM9102 is configured for Full Duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in Full Duplex mode). It must set to be 1. Reserved: Write as 0, ignore on read Jabber Enable: Enables or disables the Jabber function when the DM9102 is in 10BASE-T Full Duplex or 10BASE-T Transceiver Loopback mode 1= Jabber function enabled 0= Jabber function disabled Reserved Reserved Reserved 41 DM9102 10/100Mbps Single Chip LAN Controller T a Functional Description System Buffer Management 1. Overview The data buffers for reception and transmission which data reside in the host memory. They are directed with the descriptor lists that are located in another region of the host memory. All actions for the buffer management are operated by the DM9102 in conjunction with the driver. The data structures and processing algorithms are described in the following text. buffer, count of the buffer, command and status for the packet to be transmitted or received. Each descriptor list starts from the address setting of CR3 (receive descriptor base address) and CR4 (transmit descriptor base address). The descriptor lists have two types of structure, Ring structure and Chain structure. 2. Data Structure and Descriptor List As the Ring structure depicted below, the descriptors are linked directly one after another. The first and last descriptor on the list has the necessary information for the DM9102 to return to the beginning of the list after the bottom descriptor is accessed. Each descriptor points to the two buffer regions and one packet may cross many descriptor boundaries. 3. Buffer Management: Ring Structure Method There are two types of buffers that reside in the host memory, the transmit buffer and the receive buffer. The buffers are composed of many distributed regions in the host memory. They are linked together and controlled by the descriptor lists that reside in another region of the host memory. The content of each descriptor includes pointer to the own control status buffer 2 length buffer 1 length Buffer 1 buffer address 1 buffer address 2 Buffer 2 Descriptor 1 Buffer 1 Buffer 2 Descriptor N 42 Packet N Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 4. Buffer Management: Chain Structure Method As the Chain structure depicted below, each descriptor contains two pointers, one point to a single buffer and the other to the next descriptor chained. The first descriptor is chained with the last descriptor under host driver's control. With this structure, a descriptor can be allocated anywhere in host memory and is chained to the next descriptor. The Chain Structure and the Ring Structure may be combined to make the buffer structure more flexible. status own control not valid Buffer 1 buffer 1 length buffer address 1 next descriptor address Buffer 1 Descriptor 1 Packet N Descriptor N 5. Descriptor List: Buffer Descriptor Format (a). Receive Descriptor Format Each receive descriptor has four double-word entries and may be read or written by the host or the DM9102. The descriptor format is shown below with a detailed functional description. 31 0 OOW WNN RDES0 Status Control bits Buffer 2 Length Buffer 1 Length RDES1 Buffer Address 1 RDES2 Buffer Address 2 RDES3 Receive Descriptor Format Final Version: DM9102-DS-F3 August 30, 2000 43 DM9102 10/100Mbps Single Chip LAN Controller RDES0: Owner bit with receive status 31 OWN 30 29 28 27 26 25 24 23 OWN: 1=owned by DM9102, 0=owned by host This bit should be reset after packet reception is completed. It will be set by the host after received data are removed. 14 ES DUE 13 12 20 19 18 17 16 LBOM FL: Frame length indicating total byte count of received packet. AUN: Received address unmatched. 11 10 9 8 RF MF BD ED This word-wide content includes status of received frame. They are loaded after the received buffer that belongs to the corresponding descriptor is full. All status bits are valid only when the last descriptor (End Descriptor) bit is set. Bit 15: ES, Error Summary It is set for the following error conditions: Descriptor Unavailable Error (DUE =1), Runt Frame (RF=1), Excessive Frame Length (EFL=1), Late Collision Seen (LCS=1), CRC error (CE=1), FIFO Overflow error (FOE=1). Valid only when ED is set. Bit 14: DUE, Descriptor Unavailable Error It is set when the frame is truncated due to the buffer unavailable. It is valid only when ED is set. Bit 13,12: LBOM, Loopback Operation Mode These two bits show the received frame is derived from 00 --- normal operation 01 --- internal loopback 10 --- external loopback 11 --- reserved Bit 11: RF, Runt Frame It is set to indicate the received frame has the size smaller than 64 bytes. Valid only when ED is set and FOE is reset. Bit 10: MF, Multicast Frame It is set to indicate the received frame has a multicast address. Valid only when ED is set. Bit 9: BD, Begin Descriptor This bit is set for the descriptor indicating start of a received frame. 44 21 Frame Length ( FL ) AUN 15 22 7 6 TELFFL L C S 5 FT 4 3 RWT PLE 2 1 0 AE CE FOE Bit 8: ED, Ending Descriptor This bit is set for the descriptor indicates end of a received frame. Bit 7: EFL, Excessive Frame Length It is set to indicate the received frame length exceeds 1518 bytes. Valid only when ED is set. Bit 6: LCS: Late Collision Seen It is set to indicate a late collision found during the frame reception. Valid only when ED is set. Bit 5: FT, Frame Type It is set to indicate the received frame is the Ethernet-type. It is reset to indicate the received frame is the EEE802.3- type. Valid only when ED is set Bit 4: RWT, Receive Watchdog Timeout It is set to indicate receive Watchdog time-out during the frame reception. CR5<9> will also be set. Valid only when ED is set. Bit 3: PLE, Physical Layer Error It is set to indicate a physical layer error found during the frame reception. Bit 2: AE, Alignment Error It is set to indicate the received frame ends with a non-byte boundary. Bit 1: CE, CRC Error It is set to indicate the received frame ends with a CRC error. Valid only when ED is set. Bit 0: FOE, FIFO Overflow Error This bit is valid for Ending Descriptor is set. (ED = 1) It is set to indicate a FIFO Overflow error happens during the frame reception. Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller RDES1: Descriptor Status and Buffer Size 31 30 29 28 27 26 25 24 23 21 ~ 11 10 ~ 0 Buffer 2 Length Buffer 1 Length 22 EOR CE Bit 25: EOR, End of Ring Set to indicate that the descriptor is located on the bottom of the descriptor list. Bit 21-11: Buffer 2 Length Indicates the size of the second buffer. It has no meaning in chain type descriptor. Bit 24: CE, Chain Enable Set to indicate that the second address is the chained descriptor instead of the other buffer. Used as the indication of the Chain structure. Bit 10-0: Buffer 1 Length Indicates the size of the first buffer in Ring type structure and single buffer in Chain type structure. RDES2: Buffer 1 Starting Address Indicates the physical starting address of buffer 1. 31 0 Buffer Address 1 RDES3: Buffer 2 Starting Address Indicates the physical starting address of buffer 2 under the Ring structure and that of the chained descriptor under the Chain descriptor structure. 31 0 Buffer Address 2 (b). Transmit Descriptor Format Each transmit descriptor has four doubleword content and may be read or written by the host or by the DM9102. The descriptor format is shown below with detailed description. 31 0 OWN Status Control bits Buffer 2 Length TDES0 Buffer 1 Length TDES1 Buffer Address 1 TDES2 Buffer Address 2 TDES3 Transmit Descriptor Format Final Version: DM9102-DS-F3 August 30, 2000 45 DM9102 10/100Mbps Single Chip LAN Controller TDES0: Owner Bit with Transmit Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OWN Bit 31: OWN, 1=owned by DM9102, 0=owned by host, this bit should be set when the transmitting buffer 15 14 ES TX JT 13 12 is filled with data and ready to be transmitted. It will be reset by DM9102 after transmitting the whole data buffer. 11 10 9 8 7 LOC NC LC EC HF This word wide content includes status of transmitted frame. They are loaded after the data buffer that belongs to the corresponding descriptor is transmitted. Bit 15: ES, Error Summary It is set for the following error conditions: Transmit Jabber Time-out (TXJT=1), Loss of Carrier (LOC=1), No Carrier (NC=1), Late Collision (LC=1), Excessive Collision (EC=1), FIFO Underrun Error (FUE=1). Bit 14: TXJT, Transmit Jabber Time Out It is set to indicate the transmitted frame is truncated due to transmit jabber time out condition. The transmit jabber time out interrupt CR5<3> is set. Bit 11: LOC, Loss of Carrier It is set to indicate the loss of carrier during the frame transmission, not valid in internal loopback mode. Bit 10: NC, No Carrier It is set to indicate that no carrier signal from transceiver is found, not valid in internal loopback mode. Bit 9: LC, Late Collision It is set to indicate a collision occurs after the collision window of 64 bytes. Not valid if FUE is set. 46 6 5 4 CC 3 2 LF 1 FUE 0 DF Bit 8: EC, Excessive collision It is set to indicate the transmission is aborted due to 16 excessive collisions. Bit 7: HF, Heartbeat Fail It is set to indicate the Heartbeat check failed after complete transmission. Not valid if FUE is set. When TDES0<14> is set, this bit is not valid. Bits 6-3: CC, Collision Count These bits show the number of collision before transmission. Not valid if excessive collision bit is also set. Bit 2: LF, Link test Fail It is set to indicate the link test fails before the frame transmission. Bit 1: FUE, FIFO Underrun Error It is set to indicate the transmission aborted due to transmit FIFO underrun condition. Bit 0: DF, Deferred It is set to indicate the frame is deferred before ready to transmit. Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller TDES1: Transmit buffer control and buffer size 31 30 29 28 27 26 25 CI ED B D FMB1 S E T F C A D E O R 24 23 22 21 ~ 11 CE PD FMB0 Buffer 2 Length Bit 31: CI, Completion Interrupt It is set to enable transmit interrupt after the present frame has been transmitted. It is valid only when TDES1<30> is set or when it is a setup frame. Bit 30: ED, Ending Descriptor It is set to indicate the pointed buffer contains the last segment of a frame. Bit 29: BD, Begin Descriptor It is set to indicate the pointed buffer contains the first segment of a frame. Bit 28: FMB1, Filtering Mode Bit 1 This bit is used with FMB0 to indicate the filtering type when the present frame is a setup frame. Bit 27: SETF, Setup Frame It is set to indicate the current frame is a setup frame. Bit 26: CAD, CRC Append Disable It is set to disable the CRC appending at the end of the transmitted frame. Valid only when TDES1<29> is set. Bit 25: EOR, End of Ring Descriptor It is set to indicate the descriptor is located on the bottom of the descriptor list. 10 ~ 0 Buffer 1 Length This bit is set to indicate the second address (TDES3) is the chained descriptor instead of the other buffer. It is used as the indication of the Chain structure. When reset, it indicates the Ring structure. Bit 23: PD, Padding Disable This bit is set to disable the padding field for a packet shorter than 64 bytes. Bit 22: FMB0, Filtering Mode Bit 0 This bit is used with FMB1 to indicate the filtering type when the present frame is a setup frame. FMB1 FMB0 Filtering Type 0 0 Perfect Filtering 0 1 Hash Filtering 1 0 Inverse Filtering 1 1 Hash-Only Filtering Bits 21-11: Buffer 2 length Indicates the size of second buffer. It has no meaning with chain structure descriptor type. Bit 10-0: Buffer 1 length Indicates the size of the first buffer in Ring type structure and single buffer in Chain type structure. Bit 24: CE, Chain Enable TDES2 : Buffer 1 Starting Address indicates the physical starting address of buffer 1. 31 0 Buffer Address 1 BA1: TDES3 : Buffer 2 Starting Address indicates the physical starting address of buffer 2 under the Ring structure. 31 0 Buffer Address 2 BA2: Final Version: DM9102-DS-F3 August 30, 2000 47 DM9102 10/100Mbps Single Chip LAN Controller 1. Receive Data Buffer Processing The DM9102 always attempts to acquire an extra descriptor in anticipation of the incoming frames. Any incoming frame size covers a few buffer regions and descriptors. The following conditions satisfy the descriptor acquisition attempt: Initialization Procedure After hardware or software reset, transmit and receive processes are placed in the STOP state. The DM9102 can accept the host commands to start operation. The general procedure for initialization is described below: (1) Read/write suitable values for the PCI configuration registers. (2) Write CR3 and CR4 to provide the starting address of each descriptor list. (3) Write CR0 to set global host bus operation parameters. (4) Write CR7 to mask unnecessary interrupt causes. (5) Write CR6 to set global parameters and start both the receive and transmit processes. The receive and transmit processes will enter the running state and attempt to acquire descriptors from the respective descriptor lists. (6) Wait for any interrupt. z z z z z Data Buffer Processing Algorithm The data buffer process algorithm is based on the cooperation of the host and the DM9102. The host sets CR3 (receive descriptor base address) and CR4 (transmit descriptor base address) for the descriptor list initialization. The DM9102 will start the data buffer transfer after the descriptor polling and get the ownership. For detailed processing procedure, please see below. Stop State When start/stop receive sets immediately after being placed in the running state. When the DM9102 begins writing frame data to a data buffer pointed to by the current descriptor and the buffer ends before the frame ends. When the DM9102 completes the reception of a frame and the current receive descriptor is closed. When receive process is suspended due to no free buffer for the DM9102 and a new frame is received. When receive poll demand is issued. After acquiring the free descriptor, the DM9102 processes the incoming frame and places it in the acquired descriptor's data buffer. When the whole received frame data has been transferred, the DM9102 will write the status information to the last descriptor. The same process will repeat until it encounters a descriptor flagged as being owned by the host. If this occurs, receive process enters the suspended state and waits the host to service. Stop Receive Command or Reset Command Start Receive Command Or Receive Poll Command Descriptor Access New Frame Coming Or Receive Poll Command Receive Buffer Unavailable Buffer Full Suspended Buffer Available ( OWN bit = 1 ) FIFO Threshold Reached Datat Transfer Frame Fully Received Write Status Buffer not Full Receive Buffer Management State Transition 48 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller 2. Transmit Data Buffer Processing copying the first frame, it immediately polls the transmit descriptor list for the second frame. If the second frame is valid, transmit process copies the frame before writing the status information of the first frame. When start/stop transmit command is set and the DM9102 is in running state, transmit process polls transmit descriptor list for frames requiring transmission. When it completes a frame transmission, the status related to the transmitted frame will be written into the transmit descriptor. If the DM9102 detects a descriptor flagged as owned by the host and no transmit buffers are available, transmit process will be suspended. While in the running state, transmit process can simultaneously acquire two frames. As transmit process completes Both conditions below will make transmit process be suspended: (i) The DM9102 detects a descriptor owned by the host. (ii) A frame transmission is aborted when a locally induced error is detected. Under either condition, the host driver has to service the condition before the DM9102 can resume. Stop Transmit Command Or Reset Command Stop State Start Transmit Command Or Transmit Poll Command Descriptor Access Transmit Poll Command Transmit Buffer Unavailable ( Owned By Host ) Buffer Empty Suspended Buffer Available ( OWN bit = 1 ) Under FIFO Threshold Data Transfer Frame Fully Transmited Write Status Buffer not Empty Transmit Buffer Management State Transition Final Version: DM9102-DS-F3 August 30, 2000 49 DM9102 a Network Function 1. Overview This chapter will introduce the normal state machine operation and MAC layer management like collision backoff algorithm. In transmit mode, the DM9102 initiates a DMA cycle to access data from a transmit buffer. It prefaces the data with the preamble, the SFD pattern, and it appends a 32-bit CRC. In receive mode, the data is de-serialized by receive mechanism and fed into the internal FIFO. For detailed process, please see below. 2. Receive Process and State Machine a. Reception Initiation As a preamble being detected on the receive data lines, the DM9102 synchronizes itself to the data stream during the preamble and waits for the SFD. The synchronization process is based on byte boundary and the SFD byte is 10101011. If the DM9102 receives a 00 or a 11 after the first 8 preamble bits and before receiving the SFD, the reception process will be terminated. b. Address Recognition After initial synchronization, the DM9102 will recognize the 6-byte destination address field. The first bit of the destination address signifies whether it is a physical address (=0) or a multicast address (=1). The DM9102 filters the frame based on the node address of receive address filter setting. If the frame passes the filter, the subsequent serial data will be delivered into the host memory. 10/100Mbps Single Chip LAN Controller by the transmit state machine, which delays the actual transmission onto the network until the network has been idle for a minimum interframe gap time. b. Frame Encapsulation The transmit data frame encapsulation stream consists of two parts: Basic frame beginning and basic frame end. The former contains 56 preamble bits and SFD, the later, FCS. The basic frame read from the host memory includes the destination address, the source address, the type/length field, and the data field. If the data field is less than 46 bytes, the DM9102 will pad the frame with the pattern 00 up to 46 bytes. c. Collision When concurrent transmissions from two or more nodes occur (termed; collision), the DM9102 halts the transmission of data bytes and begins a jam pattern consisting of AAAAAAAA. At the end of the jam transmission, it begins the backoff wait time. If the collision was detected during the preamble transmission, the jam pattern is transmitted after completing the preamble. The backoff process is called truncated binary exponential backoff. The delay is a random integer multiple of slot times. The number of slot times of delay before the Nth retransmission attempt is chosen as a uniformly distributed random integer in the range: 0 r < 2k k = min ( n, N ) and N=10 c. Frame Decapsulation The DM9102 checks the CRC bytes of all received frames before releasing the frame along with the CRC to the host processor. 3. Transmit Process and State Machine a. Transmission Initiation Once the host processor prepares a transmit descriptor for the transmit buffer, the host processor signals the DM9102 to take it. After the DM9102 has been notified of this transmit list, the DM9102 will start to move the data bytes from the host memory to the internal transmit FIFO. When transmit FIFO is adequately filled to the programmed threshold level, or when there is a full frame buffered into the transmit FIFO, the DM9102 begins to encapsulate the frame. The transmit encapsulation is performed 50 4. Physical Layer Overview: The DM9102 provides 100M/10Mbps dual port operation. It provides a direct interface either to Unshielded Twisted pair Cable UTP5 for 100BASETX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. In physical level operation, it consists of the following blocks: PCS Clock generator NRE/NREI, MLT 3 encoder/decoder and driver MANCHESTER encoder/decoder 10BASE-T filter and driver Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller a Serial Management Interface The serial management interface uses a simple, twowired serial interface to obtain and control the status of PHY management register set through an MDC and MDIO. The Management Data Clock (MDC) is equipped with a maximum clock rate of 2.5MHz, while Management Data Input /Output (MDIO) works as a bi-directional, shared by up to 32 devices. (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code (OP):<10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Resistor Address field and Data field is provided for MDIO to avoid contention. "Z" stands for high impedance state. Following turnaround time, a 16-bit data is read from or written onto management registers. In read/write operation, the management data frame is 64-bit long start with 32 contiguous logic one bits Management Interface - Read Frame Structure MDC MDIO Read 32 "1"s Idle 0 Preamble 1 SFD 1 0 A4 Op Code A3 A0 PHY Address R4 R3 R0 Register Address // // 0 Z D15 D14 D1 Turn Around D0 Data Read Write Idle Management Interface - Write Frame Structure MDC MDIO Write 32 "1"s Idle Preamble Final Version: DM9102-DS-F03 August 30, 2000 0 1 SFD 0 Op Code 1 A4 A3 PHY Address A0 R4 R3 Register Address Write R0 1 0 Turn Around D15 D14 D1 Data D0 Idle 51 DM9102 10/100Mbps Single Chip LAN Controller T Configuration ROM Overview The purpose of Configuration ROM (EEPROM) is to support the DM9102 information to the driver for the card. The CROM must support 64 words or more The format of EEPROM. Field Name Subsystem ID block CROM version Controller count Controller_0 Information Controller_1 Information : (depends on controller count) CRC checksum 1. Subsystem ID Block space for configuration data. The format of the CROM is as followed: Offset 0 18 19 20 20+n : 126 Size 18 1 1 n m : 2 value due to Every card must have a Subsystem ID to indicate the system vendor information. The content will be transferred into the PCI configuration space during a Hardware reset function. (b) incorrectly auto-load operation. CRC check circuit of EEPROM contents to decide the auto-load operation of Vendor ID & Subsystem. (a) Vendor ID & Device ID can be set in EEPROM content & auto-loaded to PCI configuration register after reset. (default value = 1282, 9102) This function must be selectable for enable/disable by Auto_Load_Control ( offset 08 of EEPROM) setting to avoid damaging default Subsystem ID Block Byte Offset. Subsystem Vendor ID 0 Subsystem ID 2 Reserved 4 Reserved 6 NCE 8 Auto_load_control 10 PCI Vender ID PCI Device ID 12 14 Reserved Reserved I D _ b l o c k _ C R C 17,16 Reserved 52 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 Byte Offset (08): Auto_Load_Control 7 4 3 0 Bit3~0: "1010" to enable auto-load of PCI Vendor_ID & Device_ID, "0" to disable. Bit7~4: "1X1X" to enable auto-load of NCE, to PCI configuration space. Byte Offset (09): New_Capabilities_Enable 7 1 0 Bit0: Directly mapping to bit20 (New Capabilities) of the PCICS Byte Offset (16): ID_BLOCK_CRC 7 0 This field is implemented to confirm the correct reading of the EEPROM contents. 2. CROM Version Current version number is 03. 3. Controller Count The configuration ROM supports multiple controllers in one board. Every controller has its unique controller information block. Controller count indicates the number of controllers put in the card. 4. Controller_X Information Each controller has its information block to address its node ID, GPR control, supported connect media types Final Version: DM9102-DS-F03 August 30, 2000 (Media Information Block) and other application circuit information block. Controller Information Header ITEM Offset Node Address 0 Controller_x Number 6 Controller_x Info. Block Offset 7 Size 6 1 1 5. Controller Information Body Pointed By Controller_X Info Block Offset Item In Controller Information Header: Item Connection Type Selected GPR Control Block Count Block_1 : Offset 0 Size 2 2 3 4 4+n 1 1 n m * Connect Type Selected indicates the default connect media type selected. * GPR Control defines the input or output direction of GPR. There are three types of block: 1. PHY Information Block (type=01) 2. Media Information Block (type=00) 3. Delay Period Block (type=80) PHY information Block (type=01) Item Offset Block Length 0 Block Type(01) 1 PHY Number 2 GPR Initial Length(G_i) 3 GPR Initial Data 4 Reset Sequence 4+G_i Length(R_i) Reset Data 5+G_i Media Capabilities 5+G_i+R_i Nway Advertisement 7+G_i+R_i FDX Bit Map 9+G_i+R_i TTM Bit Map 11+G_i+R_i Size 1 1 1 1 G_i 1 R_i 2 2 2 2 Note 1: The definition of Media Capabilities and Nway Advertisement is the same with 802.3U in terms of Auto-negotiation. 53 DM9102 10/100Mbps Single Chip LAN Controller Media Information Block (Type = 00) ITEM Offset Size Block Length 0 1 Block Type(00) 1 1 Media Code 2 1 GPR Data 3 1 Command 4 2 Delay Period Block (Type = 80) Define the delay time unit in us. ITEM Block Length Block Type(80) Time Unit Offset 0 1 2 Size 1 1 2 Note 1: Media Code: 10BASE_T Half Duplex 00 10 BASE_T Full Duplex 04 100 BASE_T Half Duplex 01 100 BASE_T Full Duplex 05 Note 2: Command Format 54 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller T Absolute Maximum Ratings* Supply Voltage (VCC) ........................... -0.5V to 5.5V Maximum DC Input Voltage (VIN) -0.5V to VCC+0.5V DC Output Voltage (V OUT) .........-0.5V to VCC +0.5V Storage Temperature Rang (Tstg) .. -65 to +150 Case Temperature Range....................0 to 85 Infrared Solder Reflow Peak Temp. (10 to 20 sec.) .......................................................... 220 to 225 ESD Rating (Rzap=1.5K, Czap=100Pf) .......... 4000V a Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol VCC TOP VIL VIH VOL VOH IIL IDD IPD Parameter Supply Voltage Operation Temperature Input Low Voltage Input High Voltage Output Low Voltage (Iol = 8mA) Output High Voltage (Ioh = -2mA) Input Leakage Current Operation Supply Current Power down Supply Current Receiver Symbol Parameter VICM RXI+/RXI- Input Common-Mode Voltage Transmitter ITD100 100TXO+/- 100BASE-TX Mode Differential Output Current ITD10 10TX+/- 10BASE-T Differential Output Current Min. 4.75 -20 2.0 2.4 - Typ. 230 T/D Max. 5.25 70 0.8 0.5 10 250 - Unit V C V V V V uA mA uA Min. 1.5 Typ. 2.0 Max. 2.5 Unit V 21 mA Absolute Value 56 mA Absolute Value 19 44 50 Conditions - 100 termination Across * -: No defined value *T/D: To be determined Final Version: DM9102-DS-F03 August 30, 2000 55 DM9102 10/100Mbps Single Chip LAN Controller a AC Electrical Characteristics z PCI Clock Specifications Timing tH I G H 2.0V tLOW 0.8V tR tF tC Y C L E Symbol z Parameter Min. Typ. Max. Unit Conditions tR tF PCI_CLK rising time PCI_CLK falling time 4 4 - - ns ns - tCYCLE tHIGH tLOW Cycle time PCI_CLK High Time PCI_CLK Low Time 30 12 12 - - ns ns ns - Other PCI Signals Timing Diagram 2.5V c LK t V A L (max) t V A L (min) Output tO F F tO N Input tH tS U Symbol tVAL tON tOFF tSU tH 56 Parameter Clk-To-Signal Valid Dealy Float-To-Active Delay From Clk Active-To-Float Dealy From Clk Input Signal Valid Setup Time Before Clk Input Signal Hold Time From Clk Min. 2 2 7 0 Typ. - Max. 11 28 - Unit ns ns ns ns ns Conditions Cload = 50 pF - Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller z Multiplex Mode Boot ROM Timing tA D S tA D H Address=<7;2> oe=1,we=0 BPAD <7;0> tA D S tA D H Address <15;8> Date<7;0> Valld Address<1> BPA1 BPA0 Address<17> Address<0> Address<16> BPCS# tO H tELQX tELQV tE H Q Z tAVAV Symbol TAVAV tELQV tEHQZ tOH tADS tADH z Parameter Read Cycle Time BPCS# To Output Delay BPCS# Rising Edge To Output High Impedance Output Hold From BPCS# Address Setup To Latch Enable High Address Hold From Latch Enable High Min. 0 - Type 31 1 Max. 7 - Unit PCI clock PCI clock PCI clock Conditions - 0 4 4 - - PCI clock PCI clock PCI clock - Direct Mode Boot ROM Timing t1ADL tCBAD t2ADL t3ADL t4ADL ROMCS MA[17:0] MD[7:0] AD[31:0] CBEL[3:0] Frame# tADTD tRC Irdy# Trdy# Devsel# Final Version: DM9102-DS-F03 August 30, 2000 57 DM9102 10/100Mbps Single Chip LAN Controller Symbol tRC tCBAD t1ADL t2ADL t3ADL t4ADL tADTD z Parameter Read Cycle Time Bus Command to first address delay first address length second address delay third address delay fourth address delay end of address to Tardy active Min. - Type 50 18 8 8 8 7 1 Max. - Unit PCI clock PCI clock PCI clock PCI clock PCI clock PCI clock PCI clock Conditions - EEPROM Timing tECSC tCSKD ROMCS tECKC EECK EEDO tEDSP Symbol tECKC tECSC tCSKD tEDSP z Parameter Serial ROM clock EECK period Read Cycle Time Delay from ROMCS High to EECK High Setup Time of EEDO to EECK Typ. - Max. - Unit PCI clock PCI clock PCI clock PCI clock Conditions - PHYceiver : Symbol Parameter Transmitter tTR/F 100TXO+/- Differential Rise/Fall Time tTM 100TXO+/- Differential Rise/Fall Time Mismatch tTDC 100TXO+/- Differential Output Duty Cycle Distortion tT/T 100TXO+/- Differential Output Peak-toPeak Jitter XOST 100TXO+/- Differential Voltage Overshoot 58 Min. 64 1792 28 24 Min. Typ. Max. Unit 3.0 -0.5 5.0 0.5 ns ns -0.5 0.5 ns 800 Conditions ps 5 % Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller z Auto-negotiation and Fast Link Pulse Timing Diagram Clock Pulse FAST LINK PULSES Data Pulse t1 t2 Clock Pulse t3 FLP Burst FLP Burst 10TX0+/t4 t5 Symbol t1 t2 t3 t4 t5 - Parameter Clock/Data Pulse Width Clock Pulse To Data Pulse Period Clock Pulse To Clock Pulse Period FLP Burst Width FLP Burst To FLP Burst Period Clock/Data Pulses Per Burst Final Version: DM9102-DS-F03 August 30, 2000 Min. 33 Typ. 100 62.5 125 2 13.93 33 Max. 33 Unit ns us us ms ms ea Conditions DATA = 1 59 DM9102 10/100Mbps Single Chip LAN Controller Package Information QFP 128L Outline Dimensions Unit: Inches/mm D D1 102 65 B 103 64 With Plating E1 E C 39 128 Base Metal Detail A 1 38 B A A2 See Detail F D A1 y 0.10 y Seating Plane See Detail A Detail F Symbol Dimension In Inch Dimension In mm A 0.134 Max. 3.40 Max. A1 0.010 Min. 0.25 Min. A2 0.112 0.005 2.85 0.12 B 0.009 0.002 0.220.05 C 0.006 0.002 0.145 0.055 D 0.913 0.007 23.20 0.20 D1 0.787 0.004 20.00 0.10 E 0.677 0.008 17.20 0.20 E1 0.551 0.004 14.00 0.10 e 0.020 BSC 0.5 BSC L 0.035 0.006 0.88 0.15 L1 0.063 BSC 1.60 BSC y 0.004 Max. 0.10 Max. 0~12 0~12 e L L1 Note: 1. Dimension D1 and E1 do not include resin fins. 2. All dimensions are based on metric system. 3. General appearance spec. should base itself on final visual inspection spec. 60 Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Ordering Information Part Number DM9102F Pin Count 128 Package QFP Disclaimer DAVICOM`s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer's orders shall be based on these terms. Company Overview The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry's best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5798858 Taipei Sales & Marketing Office: 8F, No. 3, Lane 235, Bao-chiao Rd., Hsin-tien City, Taipei, Taiwan, R.O.C. TEL: 886-2-29153030 FAX: 886-2-29157575 Email: sales@davicom.com.tw Davicom USA Sunnyvale, California 1135 Kern Ave., Sunnyvale, CA94085, U.S.A. TEL: 1-408-7368600 FAX: 1-408-7368688 Email: sales@davicom8.com WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Final Version: DM9102-DS-F03 August 30, 2000 61 DM9102 10/100Mbps Single Chip LAN Controller Appendix A DM9102 SROM Format Total Size: 128 Bytes Field Name Sub-Vendor ID Sub-Device ID Reserved1 Auto_Load_Control Offset (Bytes) 0 2 4 8 Size (Bytes) 2 2 4 1 Value (Hex) 0291 8212 00000000 00 Commentary ID Block Auto-load function definition: Bit 3..0 = 1010 Auto-Load PCI Vendor ID/Device ID enabled Bit 7..4 = 1010 Auto-Load PMC/PMCSR enabled (P.S.: For DM9102 E7 and later Bit 7..4 = 1x1x Auto-Load PMC/PMCSR enabled) Please refer to DM9102 Spec. AE AE AE New_Capabilities_Enable (NCE) PCI Vendor ID PCI Device ID 9 10 12 1 2 2 00 1282 9102 Reserved Reserved ID_BLOCK_CRC Reserved2 SROM Format Version Controller Count IEEE Network Address Controller_0 Dev Number Controller_0 Info Leaf Offset Reserved3 Selected Connected Type General Purpose Control Block Count F(1)+Length Type PHY Number GPR Length Reset Sequence Length Reset Sequence Media Capabilities Nway Advertisement FDX Bit Map TTM Bit Map 14 15 16 17 18 19 20 26 27 29 30 32 33 34 35 36 37 38 39 41 43 45 47 1 1 1 1 1 1 6 1 2 1 2 1 1 1 1 1 1 1 2 2 2 2 2 00 00 00 03 01 00 001E 00 0800 80 06 8E 01 01 00 02 0080 7800 01E0 5000 1800 62 If Auto-Load PCI Vendor ID/Device ID function disabled, the PCI Vendor ID/Device ID will use the default values (1282h, 9102h). Please refer to DM9102 Spec. Please refer to DM9102 Spec. Offset 0..15, 17 ID CRC Version 3.0 Controller Info Header Offset 30 Controller_0 Info Leaf Block MAC CR12 Register 6 Blocks Block 1 (PHY Info Block) PHY Information Block PHY Address Final Version: DM9102-DS-F03 August 30, 2000 DM9102 10/100Mbps Single Chip LAN Controller Field Name F(1)+Length Type Delay Sequence F(1)+Length Type Media Code GPR Data Command F(1)+Length Type Media Code GPR Data Command F(1)+Length Type Media Code GPR Data Command F(1)+Length Type Media Code GPR Data Command SROM_CRC Final Version: DM9102-DS-F03 August 30, 2000 Offset (Bytes) 49 50 51 55 56 57 58 59 61 62 63 64 65 67 68 69 70 71 73 74 75 76 77 Size (Bytes) 1 1 4 1 1 1 1 2 1 1 1 1 2 1 1 1 1 2 1 1 1 1 2 Value (Hex) 85 80 40002000 85 00 00 00 0087 85 00 01 00 0087 85 00 04 00 0087 85 00 05 00 0087 126 2 - Commentary Block 2 (Delay Period Block) Delay Period Block MicroSecond Block 3 (Media Info Block) Media Information Block 10Base-T Half_Duplex Block 4 (Media Info Block) Media Information Block 100Base-TX Half_Duplex Block 5 (Media Info Block) Media Information Block 10Base-T Full_Duplex Block 6 (Media Info Block) Media Information Block 100Base-TX Full_Duplex Offset 0..125 SROM CRC 63