DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 1
Version: DM9102-DS-F03
August 30,2000
T
General Description
The DAVICOM’s DM9102 is a hig hly integrated single-
ch ip Fa s t Et he rn et co n tr ol ler . It f ully integrated 100BASE-
TX/10Base-T Fast Ethernet MAC , PHY and PMD. It is
fully compliant w ith PCI Spec. 2.1 and IEEE802.3u.
The DM9102 provides a direct interface to the PCI local
bus and direct connection to the network wire. A s a
controller, it provides the bus master capability. Th e
DM9102 also supports auto-negotiation function that
enables it to detect s peed and duplex automatically. Due
to the well-controlled rising/ falling time, it requires no
external filter to transmit signal to the media.
T
Block Diagram
DMA
EEPROM
Interface Boot ROM
Interface
PCI
Interface
TX+/-
RX+/-
MII Management Control
& MII Register
Autonegotiation
LED Driver
RX
Machine RX
FIFO
TX
FIFO
TX
Machine
MAC
MII
NRZ to NRZINRZI to MLT3 Parallel to
Serial Scrambler 4B/5B
Encoding
MLT3 to NRZI NRZI to NRZ Parallel to
Serial De-
Scrambler 4B/5B
Decoding
AEQ
PHYceiver
DM9102
10/1 00Mbps S ingle C hip L AN Controller
2Final
Version: DM9102-DS-F03
August 30, 2000
Table of Contents
General Descripti on................................................1
Block Diagram........................................................1
Features.................................................................4
Pin Configuration: DM9102 QFP.............................5
Pin D esc r ip tion .......................................................6
- PCI Bus Interface................................................6
- Boot ROM and EEPROM Interfac e ......................7
Mul ti plex Mode ...................................................7
Dire ct Mod e.........................................................8
- LED Pins.............................................................9
- Network Interface..............................................10
- Clock Pins.........................................................10
- Miscellaneous Pi ns............................................10
- Power Pins........................................................11
Register Definition................................................12
✧ PCI Configuration Registers..............................12
Key to Default.......................................................13
Ident ificati on ID..................................................14
Command & Status............................................14
Command Register Definition ............................16
Revision ID........................................................17
Miscellaneous Func tion .....................................17
I/O B a se Ad d re ss...............................................18
Memory Mapped Base Address.........................18
Subsystem Identification....................................19
Expansion ROM Base Address..........................19
Capabilities Pointer............................................20
Int errupt & Latenc y Configuration.......................20
Device Sp ecific Co nfiguration Register ..............20
✧ Control and Status Register (CR)......................22
Key to Default.......................................................22
1. System Control Register (CR0).........................23
2. Transmit Descriptor Poll Demand (CR1)............24
3. Receive Descript or Poll Dem and (CR2) ............24
4. Receiv e Descriptor Base Address (CR3)...........24
5. Transmit Descriptor Base Address (CR4)..........25
6. Net work Status Report Register (CR5)..............25
7. Network Operation Register (CR6)....................27
8. Interrupt Mask Register (CR7)........................... 29
9. Statistical Counter Register (CR8).....................30
10. PROM & Management A c c ess Register (CR9)31
11. Programmi ng ROM Address Register (CR10 ) .32
12. General Purpose Timer Register (CR11).........32
13. PHY Status Register (CR12) ...........................32
14. Frame Access Register ...................................33
15. Frame Data Register (CR14)..........................33
16. Watching & Jabber Timer Register (CR15) .....33
✧ PHY Management Register Set ........................34
Key To Default .....................................................34
Basic Mode Control Register (BMCR)
- Register 0 ..........................................................35
Basic Mode Status Register (BMSR)
- Register 1 ..........................................................36
PHY ID Identifier Register #1 (PHYIDR1)
- Register 2 ..........................................................37
PHY ID Identifier Register #2 (PHYIDR2)
- Register 3 ..........................................................37
Auto-negotiation Advertise ment Register (ANAR)
- Register 4 ..........................................................37
Auto-negotiation Link Partner Ability Register
(ANLPAR) - Register 5.........................................38
Auto-negotiation Expansion Register (ANER)
- Register 6 ..........................................................39
DAVICOM Specified Configuration Register (DSCR)
- Register 16.........................................................39
DAVICOM Spec i fied C o nfigura tion and Statu s
Register (DSCSR) - Register 17 ...........................40
10Base-T Confi gur ati on/Stat us (10BTSCRCS R)
- Register 18.........................................................41
Functional Descripti on..........................................42
✧ System Buffer Management..............................42
1. Overvi ew..........................................................42
2. Dat a Struc ture and Descriptor List ....................42
3. Buffer Managem ent : Ring Stru cture Method .....42
4. Buffer Managem ent : Chain Structure Method ...43
5. Descriptor Li st: Buffer Descriptor Format..........43
(a). Receive Descri ptor Format.............................43
(b). Transmit Descriptor Format............................45
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 3
Version: DM9102-DS-F03
August 30,2000
Initia lization Procedure..........................................48
Da ta Buffer Processing A lg o rithm..........................48
1. Receiv e Data Buffer Processing........................48
2. Transmit Data Buffer Processing.......................49
✧ Network Function ..............................................50
1. Overvi ew...........................................................50
2. Receive P r oc ess and S tate Mac hine .................50
3. T ransmit Pr oc ess and State Machine ................50
4. Physi cal Layer Overview...................................50
✧ Serial Management Interface.............................51
Co nfiguration ROM Ove rview................................52
1. Subsystem ID Block..........................................52
2. CROM Version ..................................................53
3. Cont roll er Count................................................53
4. Controller_X Inform ation ...................................53
5. Cont roll er Inform ation Body Pointed By
Controller_X Info Block Offset Ite m in Co ntrolle r
Information Header............................................53
Absolu te Maxim um Ratings...................................55
DC Electrical Characteristics.................................55
AC Elec trical Char ac teristics & Timing Waveforms56
PCI Clock Spec. Timing.....................................56
Other PCI Signals Timing Diagram ....................56
Mul ti plex Mode Boot RO M Timi ng......................57
Direct Mode Boot ROM Timing ..........................57
EEPROM Timing...............................................58
PHYceiver.........................................................58
Auto-negotiation and Fast Link Pulse Timing
Diagram ............................................................59
Package Information.............................................60
Ordering Information.............................................61
Disclaimer ............................................................61
Company Overview ..............................................61
Products...............................................................61
Contact Windows..................................................61
Warning................................................................61
Appendix A...........................................................62
DM9102 SROM Format.....................................62
DM9102
10/1 00Mbps S ingle C hip L AN Controller
4Final
Version: DM9102-DS-F03
August 30, 2000
T
Features
T
Single chip LAN controller integrated Fast Ethernet MAC,
PHY and transceiver
T
Compl iant w ith IEEE 80 2.3u 100BASE -TX, I EEE 802.3
10BASE-T and ANSI X3T12 TP-PMD s tandard
T
Dire ct in te rface to th e PCI b us & fu ll y c om plia nt wit h PCI
specification 2.1
T
PCI bus master architecture
T
Support PCI bus burst mode data transfer with
programmable burst size
T
EEPR OM 93C46 inter face to s tore con figuration
information and user defined message
T
Support up to 2 5 6K bytes Boot ROM interface
T
Two large independent receive FIFO (4K) & transmit
FIFO (2K) w ith programmable FIFO threshold and full
packet burst processing
T
Support auto matic packet de letion for runt packets and
packet re-transmission with no FIFO reload
T
Support Full/Half Dupl ex operati on
T
Physical, broadcast address recognition and 512-bit hash
table algorithm for mu lticast address filtering
T
Compliant with IEEE802.3u Auto-negotiat ion protocol f or
automatic link type selection
T
High performance 100Mbps clock generator and data
reco ve ry circu it
T
Digita l c lo ck re cove ry c ir cu i t u s ing adva n ced digi t al
algorithm to reduce jitter
T
Adaptive equalization circuit and Baseline wandering
restoration c ircuit for 100Mbps receiver
T
Provides Loopback mode for easy sys tem d iagnostics
T
128 pin QFP with CMOS process
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 5
Version: DM9102-DS-F3
August 30, 2000
T
Pin Configuration
11
DM9102
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
60
59
58
57
56
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
55
54
53
52
51
61
81
82
83
84
85
86
87
88
89
INT#
RST#
DVDD
GNT#
REQ#
PCLK
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
CBE3#
DGND
NC
IDSEL
AD23
AD21
AD20
AD19
AD18
AD17
AD16
CBE2#
AD22
DVDD
DGND
FRAME#
STOP#
IRDY#
TRDY#
DEVSEL#
PERR#
SERR#
CBE0#
BGGND
BGRES
OSCVDD
X1/OSC
X2
OSCGND
LEDTRF
LEDFDX
LED100M
DGND
LED10M
BPA0
BPA1/TEST
EEDI
EEDO
EECK
EECS
SELROM
TEST0
TEST1
TEST2
BPAD4
BPAD5
BPAD6
BPAD7
BPCS#
BPAD0
BPAD1
BPAD2
BPAD3
AD0
AD1
AD2
AD6
AD7
DVDD
AD5
AD3
DGND
AD4
AD9
AD10
DGND
AD11
DVDD
AD13
AD14
AD15
AD12
AD8
CBE1#
PAR
(MA10/LEDTRF)
(MA11/LEDFDX)
(MA12/LED100M)
(MA13LED10M)
(MD0/EEDI)
(MD1)
(MD2)
(MD3)
(MD4)
(MD5)
(MD6)
(MD7)
(ROMCS)
(MA0)
(MA1)
(MA2)
(MA3/EEDO)
(MA4/EECK)
(MA5)
(MA6/SELROM)
(MA7)
(MA8)
(MA9)
DVDD
DGND
DGND
DVDD
DGND
DVDD
DVDD
DGND
DGND
DVDD
27
DVDD
DVDD
DGND
DVDD
DGND
DGND
DVDD
DGND
DGND
DVDD
MA16
102
101
MA15
MA14
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
127
128
126
DGND
DVDD
PWRIN
RAVDD
RXI-
RXI+
RAGND
TAGND
TXO-
TXO+
TAVDD
TAGND
TAGND
TAGND
TAVDD
NC
NC
NC
NC
DM9102
10/1 00Mbps S ingle C hip L AN Controller
6Final
Version: DM9102-DS-F03
August 30, 2000
T
Pin Description
I = Input, O = Output, I/O = Input/Output, O/D = Open Drain, P = Power
LI = r eset Latch Inp ut, # = a ll pin name with # are asserted Low
PCI Bus Interface
Pin No. Pin Name I/O Description
1 PCL K I PCI syste m clo ck
PCI bus clock tha t pro vides timing for DM9102 related to
PCI bus t ransactions. The clock frequency range is up to
33MHz.
4 GNT # I Bus Grant
This signal is ass erted low to indicate that D M9102 has
been granted ownership of the bus by the ce n tral arbi ter.
5 REQ# O Bus Request
The DM9102 w ill as sert this signal low to request the
ownership of the bus.
6 NC No Connection
20 IDSEL I Initialization Device Select
This signal is ass erted high du ring Configuration Space
read and write access.
34 FRAME# I/O Cycle Frame
This signal is driven low by the DM9102 master mode to
indicate the beginning and duration of a bus transaction.
37 IRDY# I/ O I nitiator Ready
This signal is driven low w hen the master is ready to
complete the current data phase of the transaction. A data
phase is completed on any clock bo th IRDY# and TRD Y#
are sampled asserted.
38 TRDY# I/ O Target Ready
This signal is driven low w hen the target is ready to
complete the current data phase of the transaction. During
a read, it indicates that valid data is as serted. During a
write, it indicates the target is prepared to a ccept data.
40 DEVSEL# I/O Device Select
The DM9102 as serts the signal low w hen it recogn izes its
target address a fter FRAME# is asserted. As a bus
master, the DM9102 will sample this signal to insure that
the destination address for the data tr a n sfer i s recognized
by a target.
41 STOP# I/O Stop
This signal is asserted low by the target device to request
the master device to stop the current transaction.
42 PERR# I/O Parity Error
The DM9102 as a master or s lave w ill as sert this s ignal
low to indicate a parity error on any incoming data.
43 SERR# I/O System Error
This signal is ass erted low w hen an address parity is
detected with PC ICS bit31 (detected parity error) Is
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 7
Version: DM9102-DS-F3
August 30, 2000
enabled. The s ystem error asserts two clock cyc les a fter
the falling address if an address parity error is detected.
44 PAR I/O Parity
This signal indicates e ven par ity across AD0~AD31 and
C/BE0#~C/BE3# including the PAR pin. This signal is an
output for the master and an input for the slave device. It is
s t a b le and val id o ne cl o c k a f t er the addres s phase.
19
33
45
60
C/BE3#
C/BE2#
C/BE1#
C/BE0#
I/ O B us Command/ B yte Enable
During the address phase, these signals de fine the bus
command or the type of bus transaction that will take
place. During the data phase these pins indicate which
byte lanes contain valid data. C/BE0 # applies to bit7-0 and
C/BE3# ap plies to bit31-24.
9~12, 14~ 17,
22~25,27~30,47,48,
49,52,53,56,57,58,62,
63,64,67,68,71,72,73
AD31~ A D0 I/ O A ddr es s & Data
These are multiplexed address and data bu s signals. As a
bus master, the DM9102 w ill drive address during the first
bus phas e. During s ubsequent phases, the DM9102 w ill
either read or write data expecting the target to increment
its address pointer. As a target, the DM9102 w ill decode
each address on the bus and respond if it is the tar get
being addressed.
127 INT# O/ D I nterrupt Request
This signal will be ass erted low w hen an interrupt condition
as defined in CR5 is set, and the corresponding mask bit
in CR 7 is n o t s et .
128 RST# I System Reset
When this signal is ass erted low, DM9102 performs the
internal system reset to its initial state.
Boo t RO M and EEPROM Interf ace (Inclu di ng Mult ip lex Mode or Direct Mode):
Multiple x Mode:
Pin No. Pin Name I/O Description
75~82 BPAD0~BPAD7 I / O Boot ROM Address and Data bus
Boot ROM address and Data multiplexed lines bits
0~7. In two consecutive address cycles, these lines
contain th e boot R O M address pins 7~2 , out _enabl e
and writ e_enable of boot ROM in the first cycle; and
these lines contain address pins 15~8 in second cy cle.
After the first two cycles, these lines contain data bit
7~0 in consective cycles.
83 BPCS# O Boot ROM Chip Select
Boot ROM or external register chip select signal.
85 BPA0 O,LI Boot ROM address li ne.
Low address bit0 interfacing to Boot ROM.
86 BPA1/TEST O Boot ROM address l ine.
Low address bit1 interfacing to Boot ROM.
This bit is also set to enable T EST mode only in
multiplex mode. (debug only)
DM9102
10/1 00Mbps S ingle C hip L AN Controller
8Final
Version: DM9102-DS-F03
August 30, 2000
87 EEDI I,LI EEPROM Data In
The DM9102 will read the contents of EEPROM serially
through this pin.
88 EEDO O EEPROM Data Out
The DM9102 w ill us e this p in to s erially w rite op codes,
addresses and data into the EEPROM.
89 EECK O EEPROM Serial Clock
This p in p r ovid e s th e cl oc k f or th e EEP RO M d ata t ra n sf er.
90 EECS O EEPROM Chip Select
This pin will enable the EEPROM during loading of the
Configuration Data .
92 TEST0 I TEST option control
This pin are valid only test mode enabled.
In normal operation when in multiplex mode, this pin
are pulled low.
93,94 TEST 1,TEST 2 I TEST option contr ol
These two pins are valid only test mode is enabled.
In normal operation when in multiplex mode, these two
pins are pulled low.
99~101 NC In Multiplex mode, these three pins are not connected.
Direct Mode
Pin No. Pin Name I/O Description
75 MD0/EEDI I Boot ROM Data Input/EEDI Da ta In
This p in is multiplexed by EEDI and MD0.
The DM9102 will read the contents of EEPROM serially
through this pin.
76~82 MD1~MD7 I Boot ROM Data Input Bus
83 ROMCS O Boot R OM or EEPROM ch ip selec tion.
85~87 MA0~MA2 O Boot ROM Address Output Bus
88 MA3/ E EDO O Boot ROM Address Output/ E EPRO M Data Out
This p in is multip lexed w ith MA3 and EED O.
The DM9102 w ill us e this p in to s erially w rite op codes,
addresses and data into the EEPROM.
89 MA4/ E ECK O B oot ROM Address Output/E EPRO M Serial C lock
This p in is multip lexed w ith MA4 and EEC K.
This p in p r ovid e s th e cl oc k f or th e EEP RO M d ata t ra n sf er.
90 MA5 O Boot ROM A ddr ess Output Bus
91 MA6/SELROM O/LI Boot ROM A ddr ess Output Bus/Multiplex or Direct
mode selection
I t is also used a s multiplex or direct mode selection
at power-up reset. 0 = multiplex mode, 1 = direct
mode.
92~94 MA7~MA9 O Boot ROM A ddr ess Output Bus
95~98 M A 10/LEDT RF O Boot ROM A ddr ess Output Bus/Ac tive LED
When at the time o f Boot ROM operation, the LED
m aybe fl ash f ew seconds. LED Active Low.
When operates as LED pin, if Bi t5 of P HY
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 9
Version: DM9102-DS-F3
August 30, 2000
m anagement r egister 16 i s 0, it is the Activity LED
and will flash w hen in transmitting or re ceiving.
If Bit5 of PHY Management register16 is 1, t his pin i s
no use
96 MA11/LEDFDX O Boot ROM Address Output/ Full-Duplex LED
Indicates Full Duplex mode operation. Active low.
When at the time o f Boot ROM operation, the LED
maybe flash few seconds.
97 MA12/LED100M O Boot ROM A ddr ess Output/100M bps LED
When at the time o f Boot ROM operation, the LED
m aybe fl ash f ew seconds. LED Active Low.
When operates as LED pin, if Bi t5 of P HY
m anagement r egister 16 i s 0, it indicates good li nk to
100Mbps (default). If Bit5 of PHY management
register16 is 1, it is link and activity LED .
98 MA13/LED10M O Boot ROM Address Output B us/10M bps LED
When at the time o f Boot ROM operation, the LED
m aybe fl ash f ew seconds. LED Active Low.
When operates as LED pin, if Bi t5 of P HY
m anagement r egister 16 i s 0, it indicates good li nk to
10Mbps (default). If B it5 of P HY management
register16 is 1, it is link and activity LED .
99~101 MA14~ M A16 O Boot ROM A ddr ess Output Bus
LED Pins
Pin No. Pin Name I/O Description
95 LEDTRF O Active LED, Act ive L ow
If Bit5 of PHY management register 16 i s 0, it i s the
Activity LED and will flash when in transmitting or
receiving. (defaul t )
If Bit5 of PHY Management register 16 i s 1, this pin i s
no use.
96 LEDFDX O Full-Duplex LED, Active Low
Indicates Full-Duplex mode operat ion.
97 LED100M O 100Mbps LED, Act ive Low
Indicates 100Mbps mode operation.
If Bit5 of PHY management register 16 i s 0, it i ndic ates
good link to 100Mbps. (defa ult)
If Bit5 of PHY management register 16 i s 1, it i s link
and activity LED.
98 LE D10M O 10Mbps LED, Ac tive Low.
Indicates 10Mbps mode operation.
If Bit5 of PHY management register 16 i s 0, it i ndic ates
good link to 10Mbps. (defa ult)
If Bit5 of PHY management register 16 i s 1, it i s link
and activity LED.
DM9102
10/1 00Mbps S ingle C hip L AN Controller
10 Final
Version: DM9102-DS-F03
August 30, 2000
Network Interface
Pin No. Pin Name I/O Description
107
108 RXI-
RX+ I 100M/10Mbps Differential Input Pair.
These two pins are differential receive input pair for
100BASE-TX and 10BASE-T. They are capable of
receiving 100BASE-T X MLT-3 or 10BASE-T
Manchester encoded data.
112
113 TXO-
TXO+ O 100M/10Mbps Differential Output P air.
These two pins are differential output pair for
100BASE-TX and 10BASE-T. This output pair
provides cont rolled rise and fall tim es des igned to
filt er the tr ansmitter out put.
Clock Pins
Pin No. Pin Name I/O Description
118 OSCVDD P Analog Power
119 X1/OSC I Crystal or Oscillator Input. (25MHZ
50ppm)
120 X2 O Crystal feedback output pin used for crystal
connection only. Leave this pin open if oscillator is
used.
121 OSCGND P Analog Ground
Miscellaneous Pins
Pin No. Pin Name I/O Description
91 SELROM LI Multiplex mode/Direct mode Selection.
This pin is “reset latch input at power up” to select
Multiplex mode or direct mode.
“0” = multiplex mode (default),
“1” = direct m ode. At direct mode, this is also a ou tput
pin which is used by MA6.
102 NC O No Connection
104 BGRES I Band-gap Voltage Reference Resistor.
It connect s to a 6200
, 1% error t oleranc e resi stor
between this pin and BGGND pin (pin 105) t o p rovid e
an accurate current reference for DM9102.
105 BGGND I Ground for Band-gap circuit
122 PWRIN I VDD clamp
This pin is used to identif y t he D3(cold) power st ate in
a power management aware system. This pin should
be connected to the PCI power, while other DVDD
pins should be connected to the auxiliary power, if
any. In non-power management aware systems, or
th ere is no auxiliary power, the DVDD pins and the
PWRIN pins should be connected to the PCI power
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 11
Version: DM9102-DS-F3
August 30, 2000
Power Pins
Pin No. Pin Name I/O Description
106 RAV DD P Anal og power for receive
109 RAGND P Analog ground for receive
114,115 TAVDD P Analog power for transmit
110,111,116,117 TAGND P Analog ground for transmit
7,8,13,26,35,36,39,54
,55,59,69,70,74,103,
125,126
DGND P Digital ground pins
2,3,18,21,31,32,46,50
,51,61,65,66,84,123,
124
DVDD P Digital pow er pins
DM9102
10/1 00Mbps S ingle C hip L AN Controller
12 Final
Version: DM9102-DS-F03
August 30, 2000
T
Register D efinition
a
PCI Configuration Registers
Th e definitions of PCI Con figura tion Registers are
based on the PCI specification revision 2.1 and
provides the initialization and configuration
information to operate the PCI interface in the
DM9102. All registers can be accessed with byte,
word, or doubl e word mode. As defined i n PCI
s pecification 2.1, read ac cesses to reserve or
unimple mented registers will return a value of “0.”
These registers are to be described in th e following
sections.
PCI Configuration Registers Mapping :
Description Identifier Address Offset Value of Reset
Identification PCIID 00H 91021282H
Command & Status PCICS 04H 02900007H
Revision PCIRV 08H 02000020H
Miscellaneous PCILT 0CH 00000000H
I/O Base Address PCIIO 10H undefined
Memory Bas e Address PCIMEM 14H undefined
Res erved -------- 18H - 28H
Subsystem Identification PCISID 2CH load from SROM
Expansion ROM Base Address PCIROM 30H 00000000H
Capability Po inter CAP_PTR 34H 00000050H
Reserved -------- 38H
Interrupt & Latency PCIINT 3CH 281401XXH
De vice Specific Configuration Register PCIUSR 40H 00000000H
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 13
Version: DM9102-DS-F3
August 30, 2000
Vendor IDDevice ID
Status (with bit 4 set to 1) C ommand Revision
Latency Timer Cach Line Size
Class Code = 020000h
Header TypeBIST Bass Address Register CBIO
Bass Address Register CBMA
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
Reserved
Subsystem Vendor IDSubsystem ID
Expansion ROM Base Address
Reserved Reserved Cap_Ptr
Max_Lat Min_Gnt Interrupt Pin = 1 Interrupt Line
Configuration Register Structure
40H
44H
48H
4CH
Reserved
Device Specific Configuration Register
Key to Default
In the register description that fo llows, the default
column takes the form <Reset Value>
Where
<Reset V a lue>:
1 Bit set to logic one
0 Bit set to log ic zero
X No default value
<Access Type>:
RO = Read only
RW = Read/ Write
R/C : means Read / Write & Wri te "1" for Clear .
DM9102
10/1 00Mbps S ingle C hip L AN Controller
14 Final
Version: DM9102-DS-F03
August 30, 2000
Identification ID (xxxxxx00 - PCIID)
31 16 15 0
Dev_ID Vend_ID
Device ID
Vendor ID
Bit Default Type Description
16:31 9102h RO The field identifies the particular device. Unique and fixed nu mber for the
DM9102 is 9102h. It is th e product nu mber assigned by DAVICOM.
0:15 1282h RO This fi eld identifies the manuf acturer of the device. Unique and fi xed
number for Davicom is 1282h. It is a registered number from SIG.
Command & Status (xxxxxx04 - PCICS)
31 16 15 0
Status Command
Status
Command
Status Register Def inition:
31 30 29 28 27 26 25 24 23 22 21 20 16
0 0 1 1 00
19
1
Detected Parity Error
Signal For System Error
Master Abort Detected
Target Abort Detected
DEVSEL Timing
Data Parity Error Detected
Slave mode Fast back to Back
New Capability
66MHz Capability
User Definable
Send Target Abort
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
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Bit Default Type Description
31 0 b R/ C Detected Parity Error
The DM9102 samples the AD[0:31], C /BE[0:3]#, and the PAR
signal to check parity and to set parity errors. In slave mode,
the parity check falls on com mand phase and data valid phase
(IRDY# and TRD Y# both active). While in master mode, the
DM9102 will check during each data phase of a memory read
cycle for a parity error During a memory write cycl e, if an error
occurs, the PERR# signal will be driven by the target. This bit
is set by t he DM9102 and cleared by writing "1". There is no
effect by writing "0".
30 0 b R/ C Signal For System Error
This bit is set when the SERR# signal is driv en by the DM 9102.
Thi s syst em error occurs when an addr ess parity is detected
under the condition that bit 8 and bit 6 in command register
below are set.
29 0b R/C Master Abort Detected
This bit is set when the DM9102 terminates a master cycle with
the m ast er - abor t bus transact ion.
28 0b R/C Target Abort Detected
This bit is set when the DM9102 terminates a master cycle due
to a target-abort signal from other targets.
27 0b R/C Send Target A bort ( 0 For No Implem entation)
The DM9102 w ill ne ver ass ert the target-abort sequence.
26:25 01b R /C DEVSEL Timing (0 1 Se lect Mediu m Ti ming)
Medium timing of DEVSEL# means the DM9102 will assert
DEVSEL# signal tw o clocks a fter FR AME# is sample
“asserted.”
24 0b R/C Data Parity Error Detected
This bit will take effect only when operating as a master and
w hen a Parity Error Response Bit in command co nfiguration
register i s set. I t is set under two conditions:
(i) PERR# asserted by the DM9102 in memory data read error,
(ii) PERR# sent from the target due to memory data write error.
23 1 b R/ C Slave mode Fast Back-To-Back Capable (1 For Good
Capability)
This bit is always reads "1" to indicate that the DM9102 is
capable of accepting fast back-to-back transaction as a slave
mode device.
22 0 b R/ C User-Definable-Feature Supported (0 For No Support)
21 0b R/C 66 MHz Capable (0 For No Capability)
20 1b R/C New Capabilities
This b it indicates whether this function implements a list o f e xtended
capabilities such as PCI power management. When set this bit
indicates the presence o f New Capabilities. A value o f 0 means that
this function does not implement New Capabilities.
19:16 0000b RO Reserved
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10/1 00Mbps S ingle C hip L AN Controller
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Version: DM9102-DS-F03
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Command Register Definition:
15 109876543210
Reserved R/W 0R/W 00
R/W R/W R/W00
Parity Error Response Enable/Disable
I/O Space Access Enable/Disable
Memory Space Access Enable/Disable
Master Device Capability Enable/Disable
SERR# Driver Enable/Disable
Mast Mode Fast Back-To-Back
Address/Data Steeping
VGA Palette snoop
Special Cycle
Memory Write and Invalid
Bit Default Type Description
15:10 000000b RO Reserved
9 0b RO Master Mode Fast Back-To-Back (0 For No Support)
The DM9102 does not support master mode fast back-to-back capability
and will not generate fast back-to-back cycles.
8 0b RW SERR# Driver Enable/Disable
This bit controls the asser tion of SERR# s ignal output. T he SE RR# output
w ill be asserted on detection of an address parity error and if both this bit
and bit 6 are set.
7 0b RO Address/Data Stepping (0 For No Stepping)
6 0b RW Parity Error Response Enable/Disable
Setting th is bit will enable the DM9102 to assert PERR# on the detection of
a data parity error and to assert SERR# for reporting address parity error.
5 0b RO VGA Palette Snooping (0 For No Support)
4 0b RO Memory Write and Invalid (0 For No Implementation)
The DM9102 only generates Memory write c ycle.
3 0b RO Special Cycles (0 For No Implementation)
2 1b RW Master Device Capability Enable/Disable
When this bi t is set, DM9102 has the ab ility of master mode operation.
1 1b RW Memory Space Access Enable/Disable
Thi s bit control s the abil ity of memory space access. The memory access
includes mem or y mapped I/O access and Boot ROM acc ess. As t he system
boots up, t his bit will be enabled by B I OS for Boot ROM memory access.
While in normal opera tion using memory mapped I/O access, this bit should
be set by driv er bef ore memory access cycles.
0 1b RW I/O Space Access Enable/Disable
This bit controls the abili t y of I/O space acc ess. It will be set by BIOS afte r
power on.
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10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
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Revision ID (xxxxxx08 - PCIRV)
31 078
Revision IDClass Code
Class Code
Revision Major Number
Revision Minor Number
31 078
Revision IDClass Code
Class Code
Revision Major Number
Revision Minor Number
Bit Default Type Description
31:8 020000h RO Class Code ( 020000h)
This is the standard code for Et her net LAN controller .
7:4 0010b RO Revision Major Number
This is the silicon-m ajor re vision number that will increase for the
subsequent ver si ons of the DM9102.
3:0 0000b RO Revision Minor Number
This is the silicon-minor revision number tha t will increase for the
subsequent ver si ons of the DM9102.
Miscell aneous Function (Xxxxxx0c - PCILT )
31 16 15 0872324
BIST Header Type Latency Timer Cache Line Size
Built-In Self Test
Header Type
Latency Timer For The Bus Master
Cache Line Size For Memory Read
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Bit Default Type Description
31:24 00h RO B uilt-In-Self T est ( =00h Means No Implementation)
23:16 00h RO Header Type (= 00h Means single function with Predefined Header Type )
15:8 00h RW Latenc y Timer For T he Bus Master.
The latency timer is guaranteed by the system and measured by clock
cycles. When the FRAME# ass erted at the beginning of a master period by
the DM9102, the value will be copied into a counter and start counting
down . If the F R AM E# i s de -asser ted pri or to count expirati on, this value is
meaningless . When the count expires before GNT# is de-asserted, the
master transaction will be terminated as soon as the GNT# is removed.
While GNT# signal is removed and the counter is non-ZERO, the DM9102
will continue with its data transfers until the count expires. The system host
will read MIN_GNT and MAX_LAT registers to determine the latency
requirement for the device and then initialize the la tency timer with an
appropriate value .
7:0 00h RO Cache-line Size For Memory Read Mode Selection (00h Means No
Implementation For Use)
I/O Base Address (Xxxxxx10 - PCIIO)
31 0167
1
000000
I/O Base Address
I/O Base Address
PCI I/O Range Indication
I/O or Memory Space Indicator
Bit Default Type Description
31:7 Undefined RW PCI I/O Base Addr es s
This is the base address value for I/O access cycles. It will be compared to
AD[31:7] in the address phase of bus command cycle for the I/O resource
access.
6:1 000000b RO P CI I/O Range I ndic ation
It indicates that the minimum I/O resource size is 80h.
0 1b RO I/O Space Or Memory Space Base Indicator
Determi nes that the register maps int o the I/ O spa ce .(=1 Indica tes I/ O
Base)
Memory Mapped Base A ddress (Xxxxxx14 - PCIMEM)
31 0167
000000
Memory Mapped
Base 0
Memory Base Address
Memory Range Indication
I/O or Memory Space Indicator
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10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
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Bit Default Type Description
31:7 Undefined R/W PCI Memory Base Address
Thi s i s the base address value for Memory access cycles. I t wi ll be
compared to AD[31:7] in the address phase of bus command cycle for the
Memory resource access.
6:1 000000b RO P CI Memory Range Indication
It indicat es that the minimum Memory resource s i ze is 80h.
0 0b RO I/O Space Or Memory Space Base Indicator
Determines that the register maps into the memory space(=0 Indicates
Memory Base)
Subsystem Identification (Xxxxxx2c - PCISID)
031
Subsystem ID Subsystem Vendor ID
Subsystem ID
Subsystem Vendor ID
Bit Default Type Description
31:16 XXXX h RO Subsy stem ID
Node number loaded from EEPROM word 1 and different from each card.
15:0 XXXX h RO Subsy stem Vendor ID
Unique number give n by PCI SIG and loaded from EEPROM word 0.
Expansion ROM Base Address (Xxxxxx30 - PCIROM)
31 01
ROM Base Address R/W
11 10
Reserved
18 17
0000000
ROM Base Address
9
00000000
Bit Default Type Description
31:10 00h RW ROM Base Address With 256K Boundary
PCIROM bit17~10 are hardwired to 0, indica t i ng ROM Size i s up t o 256K
Size
9:1 000000000b RO Reserved Bits Read As 0
0 0b RW Expansion ROM Decoder Enable/Disable
If this bit and the memory space access bit are both set to 1, the D M9102
wil l responds to its expansion ROM.
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10/1 00Mbps S ingle C hip L AN Controller
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Version: DM9102-DS-F03
August 30, 2000
Capab il ities Pointer (Xxxxxx34 - Cap _ Ptr)
0 0 000011
Cap_Ptr Offset 34H
07
Bit Default Type Description
31:8 000000h RO Reserved
7:0 01010000b RO Capability Po inter
The Cap_Ptr pro vides an o ffset (default is 50h) into the function ’s PCI Configuration
Spa ce for th e loca tion o f the f ir st t er m i n th e Capabilitie s Linked List. The Cap_Ptr
offse t is DOUBLE WORD a ligned so the two least s ignificant bits s ignificant bits are
always “0”s
Interrupt & Latency Configuration (Xxxxxx3c - PCIINT)
31 16 15 0872324
MAX_LAT MIN_GNT INT_PIN INT_LINE
Maximum Latency Timer
Minimum Grant
Interrupt Pin
Interrupt Line
Bit Default Type Description
31:24 28h RO Maximum Latency Timer that can be sustained (Read Only and Read As
28h)
23:16 14h RO Min imum Grant
Minimum Length of a Burst Period (Read Only and Read As 14h)
15:8 01h RO Interrupt Pin read as 01h to indicate INTA#
7:0 XXh RO I nterr upt Line that Is Routed to the Inter r upt Controller
Device Specific Configuration Register (Xxxxxx40 - PCIUSR)
31 30 29 16 15 8 0
Reserved
27 2628 725 24 23
Device Specific
Device Specific
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
August 30, 2000
Bit Default Type Description
31 0b RW Devic e Specific Bit ( sl eep mode)
30 0b RW Devic e Specific Bit ( snooze m ode)
29 0b RO When set enable Link Status Change Wake-up Event
28 0b RO When set enable Samp le Frame Wake-up Event
27 0b RO When set enable Magic Packet Wake-up Event
26 0b RO When set, indi c ates li nk change and Link St atus Change Event occurred
25 0b RO When set , indicates t he sample frame is received and Samp le Frame Event
occurred
24 0b RO When set, indi c ates the Magi c Pack et is received and Mag ic packet Event
occurred
23:16 00h RO Reserved Bits Read As 0
15:8 00h RW Device Specific
7:0 00h RO Reserved Bits Read As 0
DM9102
10/1 00Mbps S ingle C hip L AN Controller
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Version: DM9102-DS-F03
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a
Control and Status Registers (CR)
The DM9102 implement 16 contro l and status
registe r, wh ich ca n b e a ccesse d b y the h o st. These
CRs are double long word aligned. All CRs are set
to their default values by a hardware or a software
reset unless otherwise specif ied. A ll Control and
Status Register s with their definitions and offset
from IO or memory Base Address are shown
below:
Register Description Offset from CSR
Base Address Default
CR0 System Control Register 00H FFC00000
CR1 Transmit Descriptor Poll Dem and 08H FFFFFFF F
CR2 Receive Descriptor Poll Demand 10H FFFFFFFF
CR3 Receive Descriptor Base Address Register 18H 00000000
CR4 Tr ansmit Descriptor Base Address Register 20H 00000000
CR5 Network St atus Report Register 28H FC000000
CR6 Network Operation Mode Register 30H 02400040
CR7 Interrupt Mask Register 38H FFFE0000
CR8 Stati st i c al Count er Register 40H 00000000
CR9 External Management Access Register 48H FFF097FF
CR10 Progr am m ing ROM Address Register 50H Unpredict able
CR11 General P urpose Timer Register 58H FFF E0000
CR12 PHY Status Register 60H FFFFFFXX
CR13 Access Register 68H XXXXXX00
CR14 Data Register 70H Unpredictable
CR15 Watchdog And Jabber Timer Register 78H FFFFFEC8
Key to Default
In the register description that fo llows, the default
column takes the form:
<Reset V alue>, < A c c ess Type>
Where
<Reset V a lue>:
1 Bit set to logic one
0 Bit set to log ic zero
X No default value
<Access Type>:
RO = Read only
RW = Read/ Write
WO = Write only
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10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
August 30, 2000
1. Syst em Cont rol Regi st er (CR0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 2 10
0000
Bit Name Default Description
21 MRM 0b,RW Me mory Read Mu ltiple
When set, the DM9102 will use memory read multiple command (C/BE3~0 = 1100)
when it initialize the memory read burst transaction as a master device.
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation.
20 Reserved 0b,RW Must be Zero
19:17 TXAP 000b,RW Transmit Automatic polling inter va l time
When set, the DM9102 will poll the transmit descriptor auto matically w hen it is in the
suspend state due to buffer unavailab le. T he po l ling in te rval t ime is progra mmable
based on the ta ble shown below:
Bit 19 Bit 18 Bit 17 Time Interval
0 0 0 No polling
0 0 1 200us
0 1 0 800us
0 1 1 1.6ms
1 0 0 12.8us
1 0 1 25.6us
1 1 0 51.2us
1 1 1 102.4us
16 Reserved 0b,RW Must be Zero
15:14 ABA 00b,RW Address Boundary Alignment
When set, the DM9102 will execute each burst cycles to stop at the programmed
address boundary. The address boundary can be progra mm e d t o b e 8 , 16, or 3 2
double-word as shown below.
Bit 15 Bit 14 Alignment Boundary
0 0 Reserved
0 1 8-double word
1 0 16-double word
1 1 32-double word
13:8 BL 000000b,
RW Burst Length
When reset, the DM9102’s burs t length in one DMA transfer is limited by the
amount o f data in the receive FIFO ( when rece ive ) or the a mount of free space in
the transmit FIFO (when transmit ). When set, the DMA’s burst length is limited b y the
pr og ram med value . The per missible v alues are 0, 1, 2, 4, 8, 16 , or 32 doublewords.
7 Reserved 0,RW Must be Zero
6:2 DGW 00000,RW Descriptor Gap Width
The value of this field d efines the gap width ( count in double-word ) between two
continuous descriptor. It is used in ring-type descriptor structu re.
1 Reserved 0,RW Must be Zero
DM9102
10/1 00Mbps S ingle C hip L AN Controller
24 Final
Version: DM9102-DS-F03
August 30, 2000
Bit Name Default Description
0SR0,RW
So ftware Res et
When set, the DM9102 will make a internal reset cycle. All consequent action to
DM9102 should w ait at least 32 PC I clock cyc les to start and no necessary to reset this
2. Transmit Descriptor Poll Demand (CR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
31:0 TDP FFFFFFFF h
,WO Transmit Descriptor Po lling Co mmand
Writing any value to this port will force DM9102 to poll the transmit des criptor. If the
ac tin g d e scri pt or i s no t a v ailabl e, transmit proce ss will retu rn to s uspend state. If the
descriptor show s buffer a va ilable, tran smit proces s will b e gin t he da ta t ransfer.
3. Recei ve Descriptor Poll Deman d (CR2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
31:0 RDP FFFFFFFFH
,WO Receive Des criptor Polling Command
Writing any value to this port will force DM9102 to poll the receive descriptor. If the
ac tin g d e scri pt or i s no t a v ailabl e, re ceiv e process will r e turn to suspend state. If the
descriptor shows buffer a vailable , recei ve process will begin the data tran sfer.
4. Receive Descriptor Base Address (CR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
00
Bit Name Default Description
31:0 RDBA 00000000h
,RW Receive Descriptor Base Address
This register defines bas e address of receive descriptor-cha in ( or descriptor-ring )
and must be double-word aligned. The receive descriptor - polling command after
CR3 is set will make DM9102 to fetch the descriptor at the Base-Address. In Ring-
type structure, the descriptor po inter will go back to th e Base-Address after End-
de sc riptor o f ring . Bi t1 ,0 mus t be “00” for double word alignment.
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
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5. Transmit Descriptor Base Address (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
00
Bit Name Default Description
31:0 TDBA 00000000h
,RW Transmit Descriptor Base Address
This register defines base address of tra nsmit descriptor-chain ( or descriptor-ring )
and must be double-word aligned. T he transmit descriptor- polling command after
CR4 is set will make DM9102 to fetch the descriptor at the Base-Address.
In Ring-type structure, the descriptor pointer will go ba ck to the Base-Address after
End-descriptor o f ring. Bit1,0 must be “00” for double w ord alignment.
6. Network Status Report Register (CR5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 2 10
Bit Name Default Description
25:23 SBEB 000,RO Syste m Bus E rror B its
Thes e bits are read only and used to indicate the type of system bus fetal error. Valid
only w hen System Bus Error is set. The mapping bits are s hown below.
Bit25 Bit24
Bit23 Bus Error Type
0 0 0 Parity error
0 0 1 Master abort
0 1 0 Slave abort
0 1 1 Reserved
1 X X Reserved
22:20 TXPS 000,RO Transmit Process State
Thes e bits are read only and used to indicate the state of transmit process.
The mapping table is shown below.
Bit22 Bit21 Bit20 Process State
0 0 0 Transmit process stopped
0 0 1 Fetch transmit descriptor
0 1 0 Move Setup Frame from the host memory
0 1 1 Move data from host memory to transmit FIFO
1 0 0 Close descriptor by clearing owner bit of descriptor
1 0 1 Waiting end of transmit
1 1 0 Transmit end and Close descriptor by writing status
1 1 1 Transmit process suspend
19:17 RXPS 000b,RO Receive Process State
Thes e bits are read only and used to indicate the state of receive process.
The mapping table is shown below.
Bit19 Bit18 Bit17 Process State
DM9102
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26 Final
Version: DM9102-DS-F03
August 30, 2000
0 0 0 Receive process stopped
0 0 1 Fetch receive descriptor
0 1 0 Waiting for receive packet under buffer available
0 1 1 Move data from receive FIFO to host memory
1 0 0 Close descriptor by clearing owner bit of descriptor
1 0 1 Close descriptor by writing status
1 1 0 Receive process suspended due to buffer unavailable
1 1 1 Purge the current frame from the rec eiv e FIFO
because of unavailable r eceive buf fer
16 NIS 0b,RW Normal In terrupt Su mmary
Normal interrupt includes any of the t hree conditi ons :
CR5<0> – TXCI : Transmit Complete Interrupt
CR5<2> – TX DU : Tra ns mit B u ffe r U na va ilab le
CR5<6> – RX CI : Receive Complete Interrupt
15 AIS 0b,RW Abnormal Interrupt Summary
Abnormal interrupt includes any interrupt condition as show n below excluding Normal
Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7),
RXPS(bit8), RXWT(bit9), TXER(b it10), GPT(bit11) , SBE(bit13).
13 SBE 0b,RW Sys te m Bus E rror
The PC I sys tem bus errors w ill set this bit. The type of sy stem bus error is shown in
CR5<25:23> .
11 GPT 0b,RW General-purpose Timer Expired
This b it is se t to indicate the gener al-purpose timer (de scribe d in CR11) has expired.
10 TXER 0b,RW Trans mit Ea rly Interrup t
Transmit Early Interrupt is set w hen the full packet data has been moved from host
memory into transmit FIFO. It will inform the host to process next step befor e the
tran smis sion end. Tra n smit compl ete ev e n t CR5<0> wi ll cl ear th i s bit au toma ti cally.
9 RXWT 0b,RW Receive Watchdog Timer Expired
This b it is s et to indicate recei ve w atchdog timer has e xpired.
8 RXPS 0b,RW Receive Process Stopped
This b it is s et to indicate recei ve process enters the stopped state.
7 RXDU 0b,RW Receive Bu ffer Una vailable
This b it is s et w hen the DM9102 fetches the next receive descriptor is s till owned by
th e h ost. Rece ive proc e ss will b e s uspended until a new frame enters or th e receive
polling command is s et.
6 RXCI 0b,RW R ece ive Co mp lete Inte rr upt
This b it is s et w hen a rec eived frame is fully m oved into host memory and receive
status has been written to descriptor. Receive process is still running and continues to
fetch ne xt des criptor.
5 TXFU 0b,RW Tran smit FIF O Under-ru n
This bit is set when the trans mit FIFO has a under-run condition during the packet
transmission. It may happen due to the heavy load on bus, receive process dominate
in full-duplex, or trans mit bu ffer unavailable before end of packet. In this case, transmit
process is placed in the suspend s tate and under-run error TDES0<1> is set.
3 TXJT 0b,RW Transmit Jabber Timer Expired
This b it is s et when the jabber timer expired w ith the trans mitter is still a ctive.
Transmit process will be aborted and placed in the stop state. It also causes transmit
jabber timeout TD ES0<14> to ass ert.
2 TXDU 0b,RW Transmit Buffer Una vailable
This b it is s et when the DM9102 fetches the n ext transmit descriptor that is still
owned by the host. The transmit process will be suspended un ti l th e tr ans mit
DM9102
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Version: DM9102-DS-F3
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polling command is s et or auto-polling t imer time-out.
1 TXPS 0b,RW Transmit Process Stopped
This b it is s et to indicate transmit process enters the s topped s tate.
0 TXCI 0b,RW Tr ans mi t Co mp le te In terr up t
This b it is s et w hen a frame is fully transmitted and the transmit s tatus has been writen
to descriptor ( the TDES1<31> is also asserted). The transmit process is still running
and continues to fetch next des criptor.
Note: Bits 1~16 can be cleared b y writing “1”
7. Network Operation Mode Register (CR6)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543 2 10
0
00 1
1 0000 0
0
Bit Name Default Description
30 RXA 0b,RW Receive A ll
When s et, all incoming pa cket will be received, regardless the destination address .
The address match is checked accordi ng to theCR6<7>, CR6<6>, CR6<4>,
CR6<2>, CR6<0>, and RDE S0<30> will show this match.
28:26 Reserved 000b,RW Mus t be Zero .
25 Reserved 1b,RW Must be One.
24:23 Reserved 00b,RW Mus t be Zero .
22 TXTM 1b,RW Transmit Threshold Mode
When set, the trans mit threshold mode is 10Mb/s. When reset, the threshold mode
is 100Mb/s. This bit is used together with CR6<15:14> to decide the e xact threshold
level.
21 SFT 0b,RW Store and Forward Tran smit
When se t, the pa cket tra nsmission from MAC will be starte d after a full fr ame has
been moved from the host memory to transmit FIFO. When reset, the packet
transmission’s start will depend on the threshold value specified in CR6<15:14>
20 STI 0b,RW Start Transmission Immediately
Wh en t his b it is s et , th e pac ket t r ans miss io n fr om MAC wi ll b e st ar t ed imme diat ely
afte r tr ansmit F IFO’s thres hold level reaches 16 b ytes, regardless o f the s etting in
CR6<22> and CR6<15:14>. This mode will make trans mit FIFO underrun condition
t o happen mo r e e a s i l y .
18:19 MBO 00b,RW Must always write “11” to th es e tw o b its.
17 Reserved 0b,RW Mus t be Zero.
16 Reserved 0b,RW Mus t be Zero.
DM9102
10/1 00Mbps S ingle C hip L AN Controller
28 Final
Version: DM9102-DS-F03
August 30, 2000
15:14 TSB 00b,RW Threshold Bits
These bits are set tog ether with CR 6<22> (chose 10Mb or 100Mb) and will decide
the exact FIFO threshold level. The pac ket trans mission w i ll st a r t after the data level
exceeds the threshold value.
Bit15 Bit14 Threshold(100M) Threshold(10M)
0 0 128 72
0 1 256 96
1 0 512 128
1 1 Reserved Reserved
13 TXSC 0b,RW Transmit Start/stop Command
When set, the trans mit process will begin by fetching the transmit des criptor for
available packe t data to be transmitted (running s tate). If the fetched d escriptor is
owned by the host, the transmit process will enter the su spend state and transmit
buffer unavailable (CR5<2>) is set. Otherwise it will be gin to move data f rom host to
FIFO and transmit out after reach ing threshold level.
When reset, the trans mit process is placed in the stopped state after completing the
transmission of the current frame.
12 FCM 0b,RW Force Collision Mode
When set, the trans mission process is forced to be the coll ision status. Meaningful
on ly in the internal loopback mode.
11:10 LBM 00b,RW Loopback Mode
These bits decide two loopback modes bes ides nor mal operation. E xternal loopback
mode e xpects transmitted data b ack to receive path and makes no c ollision
detection.
Bit11 Bit10 Loopback Mode
0 0 normal
0 1 internal loopback
1 x external loopback
9 FDM 0b,RW Full-duplex Mode
When auto-negotiation i s di sabled, this bit is set to make DM9102 operate in the
full-duplex mode. Transmit and receive processes can work simultaneously.
There is no collision detection needed during this mode operation.
7 PAM 0b,RW Pas s All Mu lticas t
When set, any pac ket w ith a multicast destination address is received by DM9102.
The packet with a physical address will also be filtered based on the CR6<0> filter
mode s etting.
6 PM 1b,RW Promiscuous mode
When set, any incoming valid frame is received by DM9102, and no matter w hat the
destination address. The DM9102 is initialized to this mode after reset operation.
5 Reserved 0b,RW Must be Zero.
4 IAFM 0b,RO Inverse Address Filtering Mode
It is s et t o i n dicate th e DM9102 operate in a Inverse Filtering Mode. This is a read o nly
bit and mapped from the setup frame together with CR6<2>, CR6<0> setting. That is
it is valid only dur ing p erfect filtering m ode.
3 PBF 0b,RW Pass Bad Frame
When set, the DM9102 is indicated to receive the bad frames including runt packets,
trun cate d fram es cau s ed by th e FIFO ove rflo w. The bad frame also has
to pass the address filtering if the DM9102 is not set in promiscuous mode.
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
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2 HOFM 0b,RO Hash-only Filter Mode
This is a read-only bit and mapped from the set-up frame together with bit4,0 of CR6.
It is s et t o i n dicate th e DM9102 operate in a Hash-only Filtering Mode.
1 RXRC 0b,RW Receive Start/Stop Co mmand
Wh en se t, the re ce ive pr oces s wil l begi n by fetchin g the receive descriptor for
available bu ffer to store the new-coming packet (placed in the running state). If the
fetched de scriptor is owned by the host (no des criptor is owned by the DM9102),
the receive process will enter the s uspend s tate and receive buff er unavailable
CR5<7> sets. Otherwise it runs to wait fo r the pack et’s income. When reset, the
receive process is placed in the stopped state after completing the reception of the
current frame.
0 HPFM 0b,RO Hash/Perfect Filter Mode
This is a read only bit and mapped from the setup frame together with CR6<4>,
CR6<2>. When reset, the DM9102 does a perf ect address filter of in coming f rames
according to the addresses specified in the setup frame. When set, the DM9102
does a imperfect address filtering for the incoming frame w ith a multicast address
according to the hash table specified i n the setup frame. The filtering mode
(perfect/imperfect) for the frame with a physica l address will depend o n CR6<2 >.
8. Interrupt Mask Register (CR7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543 210
Bit Name Default Description
16 NISE 0b,RW Nor mal Interrupt Summary Enable
This b it is s et to enable the interrupt for Nor mal In terrupt Su mmary.
Normal interrupt includes three conditions :
CR5<0> – TXCI : Transmit Complete Interrupt
CR5<2> – TX DU : Tra ns mit B u ffe r U na va ilab le
CR5<6> – RX CI : Receive Complete Interrupt
15 AISE 0b,RW Abnormal Interrupt Summary Enable
This b it is s et to enable the interrupt for Abnormal In terrupt Summary.
Abnormal interrupt includes all interrupt condition as s hown below excluding N ormal
Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7),
RXPS(bit8), RXWT(bit9), TXER(b it10), GPT(bit11) , SBE(bit13).
13 SBEE 0b,RW Syste m Bus E rror Enable
When set together with CR 7<15>, CR5<13>, it enables the interrupt for System Bus
Error. The t ype of sys tem bus error is s hown in CR5 <24:23>.
11 GPTE 0b,RW General-purpose Timer Expired Enable
This b it is s et together w ith CR7<15>, CR5 <11> then it w ill enable the interrupt for
the condition of the general-purpose timer (described in CR11) expired.
10 TXERE 0b,RW Transmit Early Interrupt Enable
This b it is s et together w ith CR7<16>, CR5<10> then it enables the interrupt o f the
early trans mit e vent.
9 RXWTE 0b,RW Receive Watchdog Timer E xpired Enable
When this bit and CR7 <15>, (CR5<9> are set together, it enable the interru pt of th e
condition of the receive watchdog timer expired.
DM9102
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August 30, 2000
8 RXPSE 0b,RW Receive Process Stopped Enable
When set together with CR 7<15> and CR 5<8>. Thi s bit is set to enable the interrupt
of receive process stopped condition.
7 RXDUE 0b,RW Receive Buffer Una va ilable Enable
When this bit and CR7 <15>, CR5<7> are set together, it will enable the interrupt of
receive bu ffer unavailable condition.
6 RXCIE 0b,RW R ece ive Co mp lete Inte r rup t Ena b le
When this bit and CR7 <16>, CR5<6> are set together, it will enable the interrupt of
receive process co mpleted cond ition.
5 TXFUE 0b,RW Tran smit FIF O Under-ru n En ab le
When set together with CR 7<15>, CR5<5>, i t wil l enabl e th e i nterrupt of th e transmit
FIFO under-run condition.
3 TXJTE 0b,RW Transmit Jabber Timer E xpired Enable
When this bit and CR7 <15>, CR5<3> are set together, it enables the interrupt of
transmit Jabber Time r Expired condition.
2 TXDUE 0b,RW Transmit Buffer Una va ilable Enab le
When this bit and CR7 <16>, CR5<2> are set together, the trans mit bu ffer unavailable
interrupt is enabled.
1 TXPSE 0b,RW Transmit Process Stopped Enable
When this bit is s et together w ith CR7<15> and CR5<1>, it w ill enable the interrupt
of the trans mit process stopped
0 TXCIE 0b,RW Tra ns mi t Co mp lete In terru p t Ena b le
When this bit and CR7 <16>, CR5<0> are set, tran smit interrupt is enabled.
9. St atistical Counter Register (CR8)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543 210
Bit Name Default Description
31 RXFU 0b,RO Receive O ver flow Counter Overflow
This b it is set w hen the Purged Packet Counte r (RXDU) has an o ve rflow condition.
It is a read only register bit.
30:17 RXDU 0000h,RO Receive Purged Packet Counter
This is a s tatist ic counter to indica te the purged rec eived p acket count upon FIFO
overflow.
16 RXPS 0b,RO Receive Miss ed Counter Over flow
This b it is s et w hen the Receive Missed Frame Counter (RXCI) has an o verflow
condition. It is a read only register bit.
15:0 RXCI 0000h,RO Receive Missed Frame Counter
This is a statistic counter to indicate the Receive Missed Frame Count when there is
a host buffer unavailabl e condition for receive process.
Note : CR8 is cleared after read
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 31
Version: DM9102-DS-F3
August 30, 2000
10. PROM & Management Access Register (CR9)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543 210
7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 14 13 12 11 10
15 9 8
Bit Name Default Description
19 MDIN 0b,RO MII Management Data_In
This is read only bit to indi cate the MDIO input data.
18 MRW 0b,RW MII Manage ment Read/ Write Mode Se lection
This b it de fines the Read/ Write Mode for MII management interface for PHY access.
17 MDOUT 0b,RW MII Management Data_Out
This b it is us ed to generate the output data signal for the MDIO pin.
16 MDCLK 0b,RW MII Management Clock
This b it is us ed to generate the output clock signal for the MDC pin.
14 MRC 0b,RW Me mory Read Control
This b it is s et to per form the read operation for the Bo ot PROM or EEPROM a ccess.
13 EWC 0b,RW Memory Write Con trol
This b it is s et to per form the w rite operation for the Boot PROM (M ultiplex mode) or
EEPR OM acces s.
12 BRS 1b,RW Boot ROM Selected
This b it is s e t to se lect th e Boo t RO M a c ces s for memo ry interface.
11 ERS 0b,RW EEPR OM Selected
This b it is s e t to se lect th e EE PRO M a c ces s for memor y interface.
10 XRS 0b,RW External Register Selected
This b it is s e t to se lect a n e xtern a l reg is ter.
7:0 DATA FFH,RW Data input/output of Boot ROM
This field contains the data read from or write to the Boot ROM w hen the Boot ROM
mode is selected. (CR9<12> = 1)
If EEPROM is selected (CR9<11> = 1), then CR9<3:0> are connected the serial
ROM control pins.
3 CRDOUT 1b,RO Data_Out from EEPROM
This b it is s et to reflect the sig nal status of EEDI pin when EEPROM mode i s
selected.
2 CRDIN 0b,RW Data_In to EEPROM
This b it is s et to generate the o utput sig n al to E E DO pi n wh en EEP ROM mo d e is
selected.
1 CRCLK 0b,RW C lock to EE PROM
This b it is s et to generate the o utput cl ock to EE CLK pin when EEPROM mode is
selected.
0 CRCS 0b,RW Chip_Select to EEPROM
This b it is s et to generate the o utput sig na l to E ECS pin when EEPROM mode i s
selected.
DM9102
10/1 00Mbps S ingle C hip L AN Controller
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Version: DM9102-DS-F03
August 30, 2000
11. Prog ramming ROM Address Register (CR10)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
Bit Name Default Description
17:0 BADR Unpredictable Boot ROM Address
This field contains the address pointer for Boot ROM w hen the mode o f
programming by register is selected.
12. General P urpose Timer Register (CR11)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
16 TCON 0b,RW Continuous Mode o f Timer
Wh en this b it is s et, the timer will con tinuously re-initiated upon the set time is up.
When res et, the timer will be one-shot response after BCLK value is prog rammed.
15:0 MBCLK 0000h,RW Mul tip le of Ba s e Clo c k
This field set the iteration number of base clock. The base clock durat ion is defined
to be
81.92us --- for M II po rt/100M is selected
2us --- for M II port/10 M is s elec ted
13. PHY Status Reg ister (CR12)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
Bit Name Default Description
8 GEPC X b, RW GEPD B its Con tr ol
Wh en in in itializa tio n , this bit is set and the unique “80h” must be written to the
GEPD(7:0). After initialization, this bit is reset and it controls the functional mode of
GEPD in bit0~7.
7 GEPD(7) X b, RW General PHY Reset Control
It mus t be set to “1” if CR12 <8> is set.
When CR12<8> is reset, w rite “1” to this bit will reset the PHY o f the DM9102.
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10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
August 30, 2000
6:0 GEPD(6:0) XXXXXXX b
,RW Gener al P HY St at us
When CR12<8> is set at initi aliz ation, it operates the only w ri te operation
and write the unique “0000000” to these seven bits.
After initial ization, CR12<8> is reset, wri te operation is meaningless and
read these seven bits to indicate the PHY status.
These status bits are shown below.
bit 6:UTP-SIG
bit 5:Signal Detecti on
bit 4:RX-loc k
bit 3:Li nk status (t he same as bit2 of PHY Register )
bit 2:Full- duplex
bit 1:Speed 100Mbps lin k
bit 0:Speed 10Mbps lin k
14. Access Register (CR13)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543 210
register general definition bit8 ~ 3 R/W
TxFIFO transmit FIFO access port 32h r/w
RxFIFO receive FIFO access port 35h r/w
DiagReset general reset for diagnostic pointer port 38h w
15. Data Register (CR14)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
16. Watchdog and Jabber Timer Register (CR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
0
Bit Name Default Description
8 Reserved 0b,RW Mus t be Zero .
5 TWDR 0b,RW Time Interval o f Watchdog Release
This bit is used to select the time inte rval between rec eive Watchdog timer e x pira tion
until re-enabling o f the receive channel. When this bit is set, the time inter val is 40~48
bits time . Whe n th is b it is res et, it is 1 6~24 b its ti me.
4 TWDE 0b,RW Watchdog T imer D isable
When set, the Watchdog Timer is disabled. Otherwise it is enabled.
DM9102
10/1 00Mbps S ingle C hip L AN Controller
34 Final
Version: DM9102-DS-F03
August 30, 2000
2 JC 0b,RW Jabber Clock
When set, the trans miss ion is cu t off after a range o f 2048 b ytes to 2560 bytes is
transmitted.
Wh en re s e t, t ra n s mission fo r the 10Mbps port i s c ut off afte r a range of 26ms to
33ms.
Wh en re s e t, t ra n s mission for the 100Mbps port is cut off after a range of 2.6ms to
3.3ms.
1 TUNJ 0b,RW Transmit Un-jabber Interval
This bit is used to select the time inte rval between the trans mit jabber timer expiration
until re-enabling o f the transmit channel. When s et, the trans mit channel is released
right after the jabber expiration. When reset, the time interval is 365~420ms for
10Mb/s port and 36.5 ~42.0ms for 100Mb/s.
0 TJE 0b,RW Transmit Jabber Disable
When set, the trans mit Jabber Timer is disabled. Otherwise it is enabled.
a
PHY Management Register Set
Register Address Register Name Description
0 BMCR Basic Mode Control Register
1 BMSR Basic Mode Status Register
2 PHYIDR1 PHY Identifier Register #1
3 PHYIDR2 PHY Identifier Register #2
4 ANAR Auto-Negotiation Advertisement Register
5 ANLPAR Auto-Negotiation Link Partner Ability Register
6 ANER Auto-Negotiation Expansion Register
7-15 Reserved Reserved
16 DSCR DAVICOM Specified Configuration Register
17 DSCSR DAVICOM Specified Configuration/Status Register
18 10BTCSR 10 BASE-T Co nfiguration/ Status Regis ter
Others Reserved Reserved For Future Use-Do Not Read/Write To These Registers
Key to Default
In the register description that fo llows, the default
column takes the form:
<Reset Val ue>, < A ccess Type> / < Attribute(s)>
Where
<Reset V a lue>:
1 Bit set to logic one
0 Bit set to log ic zero
X No default value
(PIN#) Value latched in from p in # at r eset
<Access Type>:
RO = Read only
RW = Read/ Write
<Attribute (s)>:
SC = Se l f clearing
P = Value permanently set
LL = Latching low
LH = Latching high
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 35
Version: DM9102-DS-F3
August 30, 2000
Basic Mode Control Register (BMCR) - Register 0
Bit Name Default Description
0.15 Reset 0b, RW/SC Reset:
1=So ftware re set
0=Normal operation
This bit sets the status and contr ols the PHY register s of DM9102
to their default states. T his bit, whi c h i s self -clearing, will keep
returning a value of one until the reset process is completed
0.14 Loopback 0b, RW Loopback:
Loop-back control register
1=Loop-back enabled
0=Normal operation
When in 100Mbps operati on mode, setting this bit may cause the
descrambler to lose s ynchronization and produce a 720ms "dead
time" before any valid data appear at the MII re ceive outputs
0.13 Speed
Selection 1b, RW Speed Sel ec t:
1=100Mbps
0=10Mbps
Link speed may be selected eit her by this bit or by Auto-
negotiation. When Auto-negotiation is enabled and bit 12 is set,
this bit will retur n Auto-negot iation selec ted media type.
0.12 Auto-
negotiation
Enable
1b, RW Auto-negotiati on Enable:
1= Auto-negotiation enabled: bit 8 and 13 will be in Auto-
negotiation status
0= A uto-negoti ation disabled: bit 8 and 13 will determine the link
speed and mode
0.11 Power Down 0b, RW Power Down:
Setting th is bit will power dow n the whole chip except crystal
oscillator circuit.
1=Power Down
0=Normal Operation
0.10 Isolate (PHYAD=00000b)
,RW Isolate:
1= Isolates the DM9102 from the MII with the exception of the
serial management.
0= Normal Operation
0.9 Restart Auto-
negotiation 0b,RW/S C Restart Auto-negot iation:
1= Restar t Auto-negot iation. Re- initiates the Auto-negot iation
process. When Auto-negotiation is disabled (bit 12 o f this
register cleared) , this bit has no function and it should be
cl eared. Thi s bit is self - cl eari ng and it will keep returning a
value of 1 until Auto-negotiation is initiated by th e D M9102.
The operation of the Auto-negotiation proce ss will not be
affected by the management entity that c lears th is bit
0= Normal Operation
0.8 Duplex Mode 1b,RW Duplex Mode:
1= Full Duplex oper ati on. Duplex selec tion is allowed when Auto-
negotiati on i s disabled (bit 12 of this regi ster is cleared). With
Auto-negotiation enabled, this bit reflects the dupl ex capability
selected by Auto-negotiation
0= Norm al oper ati on
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36 Final
Version: DM9102-DS-F03
August 30, 2000
0.7 Collision Test 0b,RW Collision Test:
1= Collision Test enabled. When set , t his bi t will cause the COL
signal to be asserted in response to the assertion of TX_EN
0= Normal Operation
0.6:0.0 Reserved 0000000b,RO Reserved:
Write as 0, ignore on read
Basic Mode Status Register (BMSR) - Register 1
Bit Name Default Description
1.15 100BASE-T4 0b,RO/P 100BASE-T4 Capable:
1=DM 9102 i s abl e to perform in 100BASE-T4 mod e
0=DM9102 is not able to perform in 100BASE-T4 m ode
1.14 100BASE-TX
Full Duplex 1b,RO/P 100BASE-TX FULL DUPLEX CAPABLE:
1= DM 9102 able to perform 100BASE-TX in Full Duplex mode
0= DM9102 not able to perform 100BASE-TX in F ull Dup lex mode
1.13 100BASE-TX
Half Duplex 1b,RO/P 100BASE-TX Half Duplex Capable:
1=DM9102 is able to pe rform 100BASE -TX in Half Duplex mode
0=DM9102 is not able to perform 100BASE-TX i n Half Duplex mode
1.12 10BASE-T
Full Duplex 1b,RO/P 10 BASE-T Full Du p le x Capable:
1=DM9102 is able to pe rform 10BASE-T in Full Duplex mode
0=DM9102 is not able to perform 10BASE-T in Full Duplex mode
1.11 10BASE-T
Half Duplex 1b ,RO/P 10 BASE-T H a l f Duplex Capable:
1=DM9102 is able to pe rform 10BASE-T in Half Duplex mode
0=DM9102 is not able to perform 10BASE-T in Half Duplex mode
1.10-1.7 Reserved 0000b
,RO Reserved:
Write as 0, ignore on read
1.6 MF Preamble
Suppression 0b,RO MII Fra me Preamble Suppression:
1=PHY will accept management frames with preamble suppressed
0=P HY will not accept managem ent fra mes wi th preamble
suppressed
1.5 Auto-negotiation
Complete 0b,RO Auto-negotiation Complete:
1=A uto-negot iation process c ompleted
0=A uto-negot iation process not completed
1.4 Remote Fault 0b,
RO/LH Remote Fault:
1= Remote fault condition detecte d (cleared on read or by a chip
reset). Fault criter ia and dete ction method is DM9102
im pl em entation specific. This bit will set after the RF bit in the
ANLPAR (bit 13, register address 05) is set
0= No remo te fault condition detected
1.3 Auto-negotiation
Ability 1b,RO/P Auto Configuration Ability:
1=DM9102 able to perform Auto-negotiation
0=DM9102 not able to perf orm Auto-negotiation
1.2 Link Status 0b
,RO/LL Link Status:
1=Valid link established (for either 10Mbps or 100Mbps operation)
0=Link not established
The link stat us bi t i s implemented wi th a latching function, so t hat the
occurrence of a link failure condition causes the Link Status bit to be
cleared and remain cleared until it is read via the management
interface
1.1 Jabber Detect 0b, Jabber Detect:
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
August 30, 2000
RO/LH 1=Jabber condition detected
0=No jabber
This bit is implemented with a latc hing function. Jabber c onditi ons
wil l set thi s bit unless i t i s cleared by a read to this register through a
management interface or a DM9102 reset. This bit works only in
10Mbps m ode
1.0 Extended Capability 1b,RO/P Extended Capability:
1=Extended register capability
0=Basic register capability only
PHY ID Identifier Register #1 (PHYIDR1) - Register 2
The PHY Identifier Registers #1 and #2 work together in a sin gle identifier of the DM9102. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM S emiconductor's IEEE a ssigned OUI is 00606E.
Bit Name Default Description
2.15-2.0 OUI _M S B <0181H> OUI Most Signific ant Bits:
This regi ster stor es bi t 3 to 18 of the OUI (00606E ) t o bit 15 to 0
of t his register respe ctively. The most significant two bits of the
OUI are ignored (the IEEE s tandard re fers to these as bit 1 and 2)
PHY Identifier Register #2 (PHYIDR2) - Register 3
Bit Name Default Description
3.15-3.10 OUI_LSB <101110b>
,RO/P OU I Least Signif ic ant Bits:
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 1 0 of this
register respectively
3.9-3.4 VNDR_MDL <000000b>
,RO/P Vendor Model Number:
Six bit s of vendor model number mapped to bit 9 to 4 (most
significant bit to b it 9)
3.3-3. 0 MDL_RE V <0000b> , RO/ P M odel Rev i sion Number:
Four bits of vendor model re vis ion number mapped to bit 3 to 0
(most significant bit to bit 3)
Auto-negotiation Advertisement Register (ANAR) - Register 4
Thi s regi ster contai ns the adv er tised abi liti es of th is DM9102 dev i ce as they wil l be transmit ted t o i ts li nk part ner
during Auto-negotiation.
Bit Name Default Description
4.15 NP 0b,RO/P Next Page Ind ication:
0=No next page available
1=Nex t page available
The DM9102 has no next page, so this bit is permanently set to 0
4.14 ACK 0b,RO Acknowledge:
1=Link partner ability data recepti on acknowledged
0=Not acknowledged
The DM9102's Auto-negotiation state machine will automatically
control this bit in the outgoing FLP b u rsts and set it at the
appropriate time during the Auto-negotiation process. Software
should not attempt to write to this bit.
4.13 RF 0b, RW Remot e Fault :
1=Local Device senses a fault condition
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0=No fau lt detected
4.12-4.11 Reserved 00b, RW Reserved:
Write as 0, ignore on read
4.10 FCS 0b, RW Fl ow Control Support:
1=Controller chip supports fl ow control abilit y
0=Controller chip doesn’t support flow contr ol abili ty
4.9 T4 0b, RO/P 100BASE-T4 Support:
1=100BASE-T4 supported by the local device
0=100BASE-T4 not s upporte d
The DM9102 does not support 100BASE-T4 so this bit is
permanentl y set t o 0
4.8 TX_FDX 1b, RW 100BASE-T X Full Duplex Support:
1=100BASE-TX Full Duplex supported by the local device
0=100BASE-TX Full Duplex not supported
4.7 TX_HDX 1b, RW 100BASE-T X Support:
1=100BASE-TX supported by the local device
0=100BASE-TX not supported
4.6 10_FDX 1b, RW 10BASE-T Full Dupl ex Support:
1=10BASE-T Full Duplex supported by the local d evice
0=10BASE-T Full Duplex not s upported
4.5 10_HDX 1b, RW 10BASE-T Support:
1=10BASE-T supported by the loc al d evice
0=10BASE-T not supported
4.4-4.0 S elector <00001b>, RW Protocol Selection Bits:
These bits contain the binary encoded protocol selector
supported by this node.
<00001> indicates that t his device support s IEEE 802.3
CSMA/CD.
Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit Name Default Description
5.15 NP 0b, RO Next Page Indication:
0= Link partner, no next page available
1= Link partner, next page available
5.14 ACK 0b, RO A c k nowledge:
1=Link partner ability data recepti on acknowledged
0=Not acknowledged
The DM9102's Auto-negotiation state machine will automatically
control this bit from the incoming F LP bursts. Software should not
attempt to write to this bit.
5.13 RF 0b, RO Remote Fault :
1=Remote fau lt indicated by link partner
0=No re mote fault indicated by link partner
5.12-5.10 Reserved 000b, RO Reserved:
Write as 0, ignore on read
5.9 T4 0b, RO 100BASE-T4 Support:
1=100BASE-T4 supported by the link partner
0=100BASE-T4 not supported by the link partner
5.8 TX_FDX 0b, RO 100BASE-TX Full Duplex Support:
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
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Version: DM9102-DS-F3
August 30, 2000
1=100BASE-TX Full Duplex supported by the link partner
0=100BASE-TX Full Duplex not supported by the link partner
5.7 TX_HDX 0b, RO 100BASE-TX Support:
1=100BASE-TX Half Dupl ex supported by the link partner
0=100BASE-TX Half Dupl ex not supported by the link partner
5.6 10_FDX 0b, RO 10BASE-T Full Duplex Support:
1=10BASE-T Full Duple x supported by the link partner
0=10BASE-T Full Duplex not s upported by the link partner
5.5 10_HDX 0b, RO 10BASE-T Support:
1=10BASE-T Ha lf Dup le x supported by the link pa rtner
0=10BASE-T Ha lf Dup le x not supported by the link partner
5.4-5.0 S elector < 00000b>, RO Protocol Selection Bit s:
Link partner’s binary encoded protocol selector
Auto-Negotiation Ex pans ion Registe r (ANER ) - Regist er 6
Bit Name Default Description
6.15-6.5 Reser ved 0b, RO Reser ved:
Write as 0, ignore on read
6.4 PDF 0b, R O/LH Local De vice Parallel Detection Fault:
PD F=1 : A fau lt de tected via p arallel detecti on fu nctio n.
PDF=0: No fault detected via parallel detection function
6.3 LP_NP_ABLE 0b, RO Link Partner Ne xt Page Ab le:
LP_NP_ABLE=1: Link partner, next page available
LP_NP_ABLE=0: Link partner, no next page
6.2 NP_ABLE 0b,RO/P Local Device Next Page Able:
NP_ABLE=1: DM9102, next page available
NP_ABLE=0: DM9102, no next page
DM9102 does not support this function, so this bit is always 0.
6.1 PAGE_RX 0b, RO/LH New Page Received:
A new link code word page received. This bit will be automatically cleared
when the register (Register 6) is read by management
6.0 LP_AN_ABLE 0b, RO Link Partner Au to-negotiation Able:
A “1” in th is bit indicates that the link partner supports Auto-negotiation.
DAVICOM Specified Configuration Register (DSCR) - Register 16
Bit Name Default Description
16.15: 16.13 Reserved 0b, RW Reserved
16.12 Reserved 0b, RW This bit must set t o be 0.
16.11 Reserved 0b, RW This bit must set to be 0
16.10 TX 1b, RW This bit must set to be 1
16.9 UTP 1b, RW UTP Cable Control:
1=The media is a UTP cable , 0=STP
16.8 Reserved 0b, RW Reserved
16.7 F_LINK_100 0b, R W Force Good Link in 100Mbp s:
0=Normal 100Mbps operation
1=Force 100Mbps good link status
This bit is useful for diagnostic pur poses.
16.6 Reserved 1b, RW This bit must for ced to be 1.
DM9102
10/1 00Mbps S ingle C hip L AN Controller
40 Final
Version: DM9102-DS-F03
August 30, 2000
16.5 LED_CTL 0b,RW LED Mode Select: (contro l LEDTRF, LED100M, LED10M)
0 = LEDTRF is Activit y LED, and LED100M ind i cates good lin k
to 100Mbps, LED10M indicates good link to 10Mbps .
1 = LEDTRF is no use, LED100M, LED10M indicate Link and
Activity. When good links to 100Mbps, LED100M actives and
flashes if any traffic exists. When good links to 10Mbps, LED10M
acti ves and fl ashes if any traffic exists.
16.4 Reserved 0b,RW Thi s bit must force d to be 0
16.3 SMRST 0b,RW Reset State Machine:
When writ e 1 t o this bit, all stat e machines of PHY will be r eset.
This bit is self-clear after rese t is completed.
16.2 MFPSC 0b,RW MF Preamble Suppression Control:
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
16.1 SLEEP 0b,RW Sleep Mode:
Writing a 1 to this bit will cause PHY entering the Sleep mode
and power down all circuit except oscillator and clock generator
circuit. When waking up from Sleep mode (w rite this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
16.0 RLO UT 0b,RW Rem ote Loop o ut Con t rol:
When this bit is set to 1, the received data will loop out to the
transmit c hannel. T his is useful for bit error rate test ing
DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17
Bit Name Default Description
17.15 100FDX 1b, RO 100M Full Duplex Operat ion Mode:
After Auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100Mbps
Full Duplex mode. The so ftware can read bit[15:12] to see which
mode is selected after Auto-negotiation. This bit is invalid when it
is not in the Auto-negotia tion mode.
17.14 100HDX 1b, RO 100M Half Duplex Operation Mode:
After auto-negot iation is completed, r esul ts will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100Mbps
half-duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-negotiation. This bit is invalid when it
is not in the Auto-negotia tion mode.
17.13 10FDX 1b, RO 10M F ull Dup lex Operation Mode:
After auto-negot iation is completed, r esul ts will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10Mbps Full
Duplex mode. The software can read bit[15:12] to see which
mode is selected after Auto-negotiation. This bit is invalid when it
is not in the Auto-negotia tion mode.
17.12 10HDX 1b, RO 10M Half Duplex Operation Mode:
After Auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10Mbps
Half Duplex mode. The so ftware can read bit[15:12] to see which
mode is selected after Auto-negotiation. This bit is invalid when it
is not in the Auto-negotia tion mode.
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 41
Version: DM9102-DS-F3
August 30, 2000
17.11-17.9 Reserved 000b, RW Reserved:
Write as 0, ignore on read
17.8-17.4 PHYAD[ 4:0] 00001b, RW PHY Address Bit 4:0:
The first P HY address bit transmitted or received is t he MSB of
the address (bit 4). A station management entity connected to
mu ltiple PHY ent ities must know the appropriate address of each
PHY. A PHY address of <00000> will c ause the isolate bit of the
BMCR (bit 10, Register Addr ess 00) to be set.
17.3-17.0 ANMB[ 3:0] 0000b, RO Auto-negoti ation Monitor Bit s:
These bits are for debug only . The Auto-negotiation status will
be writte n to these bits.
b3 b2 b1 b0
0
0
0
0
I
n
I
D
L
E
s
t
a
t
e
0 0 0 0 Ability match
0
0
1
0
A
c
k
n
o
w
l
e
d
g
e
m
a
t
c
h
0011Acknowledge match fail
0
1
0
0
C
o
n
s
i
s
t
e
n
c
y
m
a
t
c
h
0101Consistency match fail
0
1
1
0
P
a
r
a
l
l
e
l
d
e
t
e
c
t
s
s
i
g
n
a
l
_
l
i
n
k
_
r
e
a
d
y
0 1 1 1 Parallel detects signal_link_ready
fail
1
0
0
0
A
u
t
o
-
n
e
g
o
t
i
a
t
i
o
n
c
o
m
p
l
e
t
e
d
successfully
10BASE-T Configu rat ion/St at us (10BTCS RCS R) - Regist er 18
Bit Name Default Description
18.15 Reserved 0b, RO Reser ved:
Write as 0, ignore on read
18.14 LP_EN 1b, RW Link Pulse Enable:
1=Transmission of link pulses enabled
0=Link pulses disabl ed, good link condit ion forced
This bit is valid only in 10Mbps opera t io n.
18.13 HB E 1b, RW Hear tbeat E nable:
1=Hear tbeat function enabled
0=Hear tbeat function disabled
When the DM9102 is configured for Full Duplex operation, this bit
will be ignored (the collision/heartbeat function is invalid in Full
Duplex mode). It must set to be 1.
18.12 Reserved 0b, RO Reser ved:
Write as 0, ignore on read
18.11 JABEN 1b, RW Jabber Enable:
Enables or disables the Jabber function when the DM9102 is in
10BASE-T Full Duplex or 10BASE-T Transceiver Loopback mode
1= J abber function enabled
0= J abber function disabl ed
18.10 Reserved 0b,RW Reserved
18.9-18.1 Reserved 0b, RO Reserved
18.0 Reserved 0b, RO Reserved
DM9102
10/1 00Mbps S ingle C hip L AN Controller
42 Final
Version: DM9102-DS-F03
August 30, 2000
T
Functional Description
a
System Buffer Ma nagement
1. O verview
The data buffers for reception and transmission
which data reside in the host memory. They are
directed with the descriptor lists that are located in
another regio n of the host memory. All actions for
the buffer management are operated by the
DM9102 in conjunction with the driver. The data
structures and processing algorithms are described
in t he follo wing t ext.
2. Data Str ucture and Descriptor List
There are two types of b uffers that reside in the host
memory, the transmit buffer and the receive buffer.
The buffers are composed of many distributed
regions in the host memory. They are linked
together and controlled by the descriptor lists that
reside in another region of the host memory. The
content of each descri ptor i ncl udes pointer t o the
buffer, count of t he buffer, com mand and status for
the packet to be transmitted or rece ived. Eac h
descriptor list st arts from the address setting of CR3
(receive de scriptor base address) and CR4 (transmit
descriptor base address). The descriptor lists have
two types of structure, Ring structure and Chain
structure.
3. Buffer Management: Ring Structure Method
As the Ring structure depicted below, the
descri ptors are linked dir ectly one after another.
The first and last descriptor on the list has the
necessary information for the DM9102 to return to
the beginning of the list after the bottom descriptor is
accessed. Each de scriptor points to the two buffer
regions and one packet may cross man y descriptor
boundaries.
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Descriptor 1
Descriptor N Packet N
control
buffer address 1
buffer address 2
status
own
buffer 2 length buffer 1 length
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 43
Version: DM9102-DS-F3
August 30, 2000
4. Buffer Management: Chain Structure Method
As the Chain structure depicte d below, each
descriptor contains two pointers, one point to a
single buffer and the other to the next descriptor
chained. The fi rst descri ptor is chained wit h the last
descriptor under host driver’s control. Wi th this
structure, a descriptor can be allo cated anywhere in
host memory and is chained to the next descriptor.
The Chain Structure and the Ring Structure may be
combined to make the buffer structure more flexible.
Buffer 1
Buffer 1
Descriptor 1
Descriptor N
Packet N
control
buffer address 1
status
own
not valid
next descriptor address
buffer 1 length
5. Descriptor List: Buffer Descriptor Format
(a). Receive Descri ptor Format
Each receive descriptor has four double-word
entries and may be read or written by the host or the DM9102. T he desc r iptor for mat is sh own b elo w w it h
a detailed functional de scription.
31 0
OWN
Status
Control bits
Buffer Address 1
Buffer Address 2
RDES0
RDES1
RDES2
RDES3
Buffer 1 Length
Buffer 2 Length
OWN
Receive Descriptor Format
DM9102
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44 Final
Version: DM9102-DS-F03
August 30, 2000
RDES0: Owner bit with receive status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OWN
Frame Length ( FL )
AUN
OWN: 1=owned by DM9102, 0=owned by ho st
This bit should be reset a fter packet
recepti on i s completed. It will be set by the
host after receiv ed data are re moved.
FL: Frame length indicating total byte count o f
received packet.
AUN: Rec eived addr es s unmat c hed.
151413121110 9 8 7 6 5 4 3 2 1 0
ES RF CE
MFDUE LBOM BD ED TLF LCS FT RWT PLE AE FOE
EFL
This wor d-wide content includes status of received
frame. They are loaded after the received buffer that
belongs to the corresponding de scriptor is f ull. All
status bits are valid only when the last descriptor
(End D e scriptor) bit is s e t.
Bit 15: ES, Error Su mmary
It is set for the following error conditions:
Descriptor Una vailable Error (DUE =1), Runt
Fra me (RF=1), Excessive Frame Length ( EFL =1),
Late Collision Seen (LCS=1), CRC error (CE=1),
FIFO Overflow error (FOE=1). Valid only w hen
ED is set.
Bi t 14: DUE, Descriptor Unavailable Error
It is set w hen the frame is truncated due to the
buffer unavailable. It is valid only when ED is set.
Bit 13,12: LBOM, Loopback Operation Mode
These two bits show the received frame is
derived from
00 --- normal operation
01 --- internal loopback
10 --- externa l loopback
11 --- reserved
Bit 11: RF, Runt Fra me
It is se t to in dic ate th e rec eived f rame has the size
smaller than 64 bytes. Valid onl y when ED is set
and FOE is reset.
Bit 10: MF, Multic ast Fram e
It is se t to in dic ate th e rec eived f rame has a
multicast address. Valid only when ED is s et.
Bi t 9: BD, Begin Descriptor
This bit is set for the descriptor indicating start of a
received frame.
Bit 8: ED, E nding Descri ptor
This bit is set for the descriptor indi cates end of a
received frame.
Bit 7: EF L, Excessive Frame Length
It is s et to indicate the recei ved frame length
exceeds 1518 bytes. Valid only when ED is set.
Bi t 6: LCS: Late Colli si on Seen
It is set to indicate a late collision found du ring the
frame recep tion. Va lid only when ED is set.
Bit 5: FT, Fram e Ty pe
It is se t to in dic ate th e rec eived f rame is the
Ethernet-type. It is reset to indi cate the received
frame is the EEE802.3- type. Valid on ly when
ED is set
Bi t 4: RWT, Rec eiv e Watchdog Tim eout
It is set to indicate receive Watchdog time-out
during the frame reception. CR5<9> will also be set.
Valid o nly when ED is set.
Bit 3: PLE, Phys ical Laye r Erro r
It is set to indicate a physical layer error found
during the frame reception.
Bit 2: AE, Alignmen t Error
It is se t to in dic ate th e rec eived f rame ends with a
non-byte boundary.
Bit 1: CE, CRC Error
It is se t to in dic ate th e rec eived f rame ends with a
CRC error. Valid only when ED is set.
Bit 0: FOE , FIFO Overflo w Erro r
This bit is valid for Ending Descriptor is set. (ED = 1)
It is set to in dicate a FIFO Overflow error happens
during the frame reception.
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 45
Version: DM9102-DS-F3
August 30, 2000
RDES1: Descriptor Status and Buffer Size
31 30 29 28 27 26 25 24 23 22
21 ~ 11 10 ~ 0
EOR CE Buffer 2 Length Buffer 1 Length
Bit 25: EOR, End of R ing
Set to indicate that the descriptor i s located
on the bottom of the descriptor list.
Bi t 24: CE, Chain Enabl e
Set to indicate that the second addre ss is the
chained de scriptor instead of the other
buffer.
Used as the indication of the Chain structure.
Bit 21- 11: Buffer 2 Length
Indicates the size of the second buffer. It
has no meaning in chain type descriptor.
Bit 10- 0: Buffer 1 Length
Indicates the size of the first buffer in Ring
type structure and single buff er in Chai n
type structure.
RDES2: Buffer 1 Starting Address
Indicates the physical starting address of buffer 1.
31 0
Buffer Address 1
RDES3: Buffer 2 Starting Address
Indicates the physical starting address of buffer 2
under the Ring structure and that o f the chained descriptor under the Chain descriptor structure.
31 0
Buffer Address 2
(b). Transmit Descriptor Format
Each transmit des criptor has four doubleword
content and may be read or written by the host or by t he DM9102. The descr iptor format is shown below
with detailed description.
31 0
OWN
Status
Control bits
Buffer Address 1
Buffer Address 2
TDES0
TDES1
TDES2
TDES3
Buffer 2 Length Buffer 1 Length
Transmit Descriptor Format
DM9102
10/1 00Mbps S ingle C hip L AN Controller
46 Final
Version: DM9102-DS-F03
August 30, 2000
TDES0: Owner Bit with Transmit Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OWN
Bit 31: O WN,
1=owned by DM9102, 0=owned by h ost, this
bit should be set when the transmitting buffer
is filled with data and ready to be transmit t ed.
It will be reset by DM9102 after transmitting
the whole data buffer.
151413121110 9 8 7 6 5 4 3 2 1 0
ES
EC HF CC
TX
JT LOC NC LC LF FUE DF
This wor d wide content incl udes status of transm itt ed
frame. They are loaded after the data buffer that
belongs to the corresponding de scriptor is
transmitted.
Bit 15: ES, Error Su mmary
It is s et for the following error conditions:
Transmit Jabber Time-out (TXJ T=1), Loss of Carrier
(LOC =1), No C arrier (NC =1), La te C ollision (LC =1),
Excessive Collision (EC =1), FIFO Underrun Error
(FUE=1).
Bit 14: TXJT, Transmit Jabber Time Out
It is se t to in dic ate th e tran smitted fr ame i s truncated
due to transmit jabber time out condition. The
transmit jabber time o ut interrupt
CR5<3> is set.
Bit 11: LOC, Los s of Carrier
It is se t to in dic ate th e los s of c ar rier during the frame
transmission, not valid in internal loopback mode.
Bi t 10: NC, No Carrier
It is se t to in dic ate th at n o car rie r signal from
transceiver is found, not valid in internal loopback
mode.
Bi t 9: LC, Late Colli si on
It is s e t t o i n dic at e a c ollisi o n o cc ur s aft er th e co llisi on
window of 64 b ytes. Not valid if FUE is s et.
Bit 8: E C, Excessive col lision
It is s et t o indi cate the transmission i s aborted due to
16 excessive collisions.
Bit 7: HF, Heartbeat Fail
It is set to i ndic ate the Heartbeat chec k fail ed
after complete transmission. Not valid if FUE is
set. When TDE S 0<14> is set, t his bi t is not
valid.
Bi ts 6-3: CC, Colli si on Count
These bits show the numbe r of collision before
transmission. Not valid if exc essive collisi on bit
is a lso set.
Bit 2: LF , L ink tes t Fa il
It is se t to in dic ate th e lin k te st fa ils be fore the fra me
transmission.
Bi t 1: F UE, FIFO Underrun Error
It is s et t o in di cate the transmissio n aborted due to
transmit FIFO underrun condition.
Bit 0: DF, Deferred
It is s e t to in dicate th e frame is d eferred before ready
to transmit.
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 47
Version: DM9102-DS-F3
August 30, 2000
TDES1: Transmit buffer control and buffer size
31 30 29 28 27 26 25 24 23 22 21 ~ 11 10 ~ 0
CI ED BD FMB1 SETF CAD EOR CE PD FMB0 Buffer 2 Length Buffer 1 Length
Bi t 31: CI, Com pletion Inter r upt
It is s et to enable transmit inter ru pt after the present frame
has been transmitted. It is valid only when TDES1<30> is
set or when it is a setup frame.
Bit 30: ED, E nding Descri ptor
It is se t to in dic ate the pointe d buffer contains the
last segment of a frame.
Bit 29: BD, B egin Descri ptor
It is se t to in dic ate the pointe d buffer contains the
firs t s eg men t o f a fra me.
Bi t 28: F M B 1, F iltering Mode Bit 1
This bit is used with FMB0 to indicate the filtering
type when the present frame is a setup frame.
Bit 27: SETF, Setup Fra me
It is se t to in dic ate th e current frame i s a setup
frame.
Bi t 26: CAD, CRC Append Disable
It is set to disable the C RC appending at the end of
the transmitted frame. Valid only when
TDES1<29> is set.
Bit 25: EOR, End of R ing Descriptor
It is se t to in dic ate the de script or is located o n t he
bottom o f the desc riptor list.
Bi t 24: CE, Chain Enabl e
This b it is s et to indicate the second addre ss
(TDES3) is the chained descrip tor instead o f the
other buffer. It is used as the indication of the
Chain structure. When reset, it indicates the R ing
structure.
Bit 23: PD, P adding Disable
This b it is s et to disable the padding field for a
packet shorter than 64 bytes.
Bit 22: FMB0, F iltering Mode Bit 0
This bit is used with FMB1 to indicate the filtering type
when the present frame is a setup frame.
FMB1 FMB0 Filtering Type
0 0 Perfect Filtering
0 1 Hash Filtering
1 0 Inverse Filtering
1 1 Hash-Only Filtering
Bits 21-11: B uffer 2 length
Indicates the size of second buffer. It ha s
no meaning with chain structure descriptor
type.
Bit 10- 0: Buffer 1 length
Indicates the size of the first buffer in Ring
type structure and single buff er in Chai n
type structure.
TD ES2 : Buffer 1 Starting Address indicates the physical starting address of buffer 1.
BA1:
31 0
Buffer Address 1
TDES3 : Buffer 2 Starting Address indicates the physical starting address of buf fer 2 under the Ring structure.
BA2:
31 0
Buffer Address 2
DM9102
10/1 00Mbps S ingle C hip L AN Controller
48 Final
Version: DM9102-DS-F03
August 30, 2000
I n itialization P r ocedur e
After hardware or software reset, tran smit and
receive processes are placed in the STOP state.
The DM9102 can accept the host commands to start
operation. The general procedure for initialization is
described belo w:
(1) Read/write suitable values for the PCI
configuration registers.
(2) Write CR3 and CR4 to provide the starting
address of each descr iptor list.
(3) Wri te CR0 to set global host bus operation
parameters.
(4) Write CR7 to mask unnecessary interrupt
causes.
(5) Wri te CR6 to set global parameters and st ar t
bo th the re c ei ve and tr ansmit processes. The
receive and transmit proces ses will enter the
running state and attempt to acquire descriptors
from the respective de scriptor lists.
(6) Wait for any interrupt.
Data Buffer Processing Algorithm
The data buffer process algori t hm is ba se d on th e
cooperation of the host and the DM9102. The host
sets CR3 (receive descriptor base address) and
CR4 (transmit descriptor base address) for the
descriptor list initialization. The DM9102 will start the
data buffer transfer after the descriptor polling and
get the ownership. For detailed processing
procedure, please see below.
1. Receive Data Buffer Processing
The DM9102 always attempts to acq uire an extra
descriptor in anticipation of the incoming frames.
Any inco ming frame size covers a few buffer regions
and de scriptors. The following cond i t ions sat isf y the
descriptor acquisition attempt:
z
When start /stop receive sets immediately after
being placed in the running state.
z
When the DM9102 begins writin g frame data to
a data buffer pointed to by the current
descriptor and the buffer ends before the frame
ends.
z
When the DM9102 completes the reception of
a frame and the curre n t receive descriptor is
closed.
z
When receive process is suspended due to no
free buffer for the DM9102 and a new frame is
received.
z
When receive poll dem and i s i ssued.
After acquiring the free de scriptor, the DM9102
processes the incoming frame and places it in
the acquired descriptor' s data buffer. When the
whole received frame data has been transferred,
the DM9102 will write the status information to
the last descriptor. The same process will
repeat until it encounter s a desc riptor flagged
as being o wn e d b y the h ost . If thi s oc curs,
receive process enters the suspended state and
waits the ho st to service.
Stop
State
Descriptor
Access
Datat
Transfer Write
Status
Suspended
Start Receive Command Or
Receive Poll Command
Buffer Available
( OWN bit = 1 )
FIFO Threshold
Reached
Frame Fully
Received
Buffer not
Full
Receive Buffer
Unavailable
New Frame Coming Or
Receive Poll Command
Stop Receive Command or
Reset Command
Buffer Full
Receive Buffer Management State Tra nsition
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 49
Version: DM9102-DS-F3
August 30, 2000
2. Transmit Data Buff er Processing
When start /stop transmit c ommand is set and the
DM9102 is in running state, transmit process polls
transmit descriptor list for frames requiring
transmission. When it complet es a frame
transmission, the st atus rel ated to the transmi tted
frame will be written into the transmit descriptor. If
the DM9102 detects a descriptor flagged as owned
by the host and no transmit buffers are ava ilable,
transmit process will be suspended. While in the
running state, transm it proc ess can simult aneousl y
acquire two frames. A s tr ansmit pr oc ess compl etes
cop ying the fir st f rame, it immediately polls th e
transmit descriptor l ist fo r the second frame. If the
second frame is valid, transmit process copies the
frame before writing the status i nformatio n of the
first frame.
Both conditi ons bel ow will mak e tr ansmit process be
suspended: (i) The DM9102 detects a descriptor
owned by the host. (ii ) A frame transm ission is
aborted when a locally induced error is detected.
Under either conditi on, the host driver has to service
the condition before the DM9102 can resume.
Stop State
Descriptor
Access
Data
Transfer Write
Status
Suspended
Buffer Available
( OWN bit = 1 )
Frame Fully Transmited
Start Transmit Command Or
Transmit Poll Command
Under FIFO Threshold
Buffer not Empty
Buffer Empty
Transmit Buffer Unavailable
( Owned By Host )
Transmit Poll Command
Stop Transmit Command Or
Reset Command
Transmit Buffer Management State Transition
DM9102
10/1 00Mbps S ingle C hip L AN Controller
50 Final
Version: DM9102-DS-F03
August 30, 2000
a
Ne t work Fu nction
1. O verview
This chapter w ill introduce the norm al state machine
operation and MAC layer manageme nt like collision
backoff algorithm. In transmit mode, the DM9102
initiates a DMA cycle to access data from a transmit
buffer. It prefaces the data with the p ream ble, the
SFD patter n, and it appends a 32-bit CRC. In
receive mode, the dat a is de-serialized by recei ve
mechanism and fed into the internal FIFO. For
detailed process, pl ease see below .
2. Receive Process and State Machine
a. Reception Initiation
As a pr eamble be ing detected on the recei ve data
lines, the DM9102 synchronizes itself to the data
stream during the preamble and waits for the SFD.
The synchronization process is based on byte
boundary and the SFD byte is 10101011. If the
DM9102 receives a 00 or a 11 after the f irst 8
preamble bits and before receiving the SFD, the
reception process will be terminated.
b. Address Rec ogniti on
After initial synchronizatio n, the DM9102 will
recognize the 6-byte destination address field. The
first bit of the destination address signifies whether it
is a physical address (=0) or a multicast address
(=1). The DM9102 filters the frame based on the
node address of receive address filter setting. If the
frame passes the filter, the subsequent s erial data
will be delivered into the host memory.
c. Fram e Decapsulat ion
The DM9102 checks the CRC bytes of all received
frames before releasing the frame along with the
CRC to the ho st processor.
3. Transmit Process and State Machine
a. Tr ansmission Initiati on
Once the host processor prepares a transmit
descriptor for the transmit buffer, the host processor
signals the DM9102 to take it. After the DM9102 has
been notified of thi s tra nsmit list , the DM 9102 wil l
start to mov e the data bytes f ro m the host memory
to the internal transmit FIFO. When transmit FIFO is
adequately filled to the programmed threshold level,
or when there is a full frame buffered into the
transmit FIFO, the DM9102 begins to encapsulate
the frame. The transmit encapsulation is performed
by the transmit state machine, which delays the
actu a l tra n smis sion onto the network unt il the
network has been idle for a minimum interframe gap
time.
b. F rame Encapsulat ion
The transmit data fra me encapsulation stream
consists of two parts: Basic frame beginning and
basic frame end. The former contains 56 pream ble
bits and SFD, the later, FCS. The basic fr am e read
from the host memory includes the destination
address, the source address, the type/length field,
and the data field. If the data field is less than 46
bytes, the DM9102 will pad the frame with the
pattern 00 up to 46 bytes.
c. Collision
When concurrent transmissions from two or more
nodes occur (te rmed; collision), the DM9102 halts
the transmiss ion of data bytes and begins a jam
pattern consisting of AAAAAAAA. At the end of the
jam transmission, it begins the backoff wait ti me. I f
the collision was detected during the preamble
transmission, the jam pattern is transmitted after
completi ng the preamble. The backoff process is
called truncated binary exponential backoff. The
delay is a random integer multiple of slot times. The
num ber of slot tim es of delay before the Nth
retransmission attempt is chosen as a uniformly
dist r ibut ed random integer in the range:
0 ≤ r < 2k
k = min ( n, N ) and N=10
4. Physical Layer Overview:
The DM9102 provides 100M/10Mbps dual port
operation. It provides a direct interface either t o
Unshielded Twisted pair Cable UTP5 for 100BASE-
TX Fast E thernet, or UTP5/UTP3 Cable for
10BASE-T Et hernet. In physi cal l evel operati on, it
consists of the following blocks:
Ƒ
PCS
Ƒ
Clock generator
Ƒ
NRE/NREI, MLT 3 encoder/decoder and driver
Ƒ
MANCHESTER encoder/decoder
Ƒ
10BASE-T filter and driver
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 51
Version: DM9102-DS-F03
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a
Serial Management Interface
The serial management interface uses a simple, two-
wired serial interface to obtain and cont rol the status
of PHY management register set through an MDC
and MDIO. The Management Data Clock (MDC) is
equipped with a maximum clock rate of 2.5MHz, while
Management Data Input /Output (MDIO) works as a
bi-directional, shared by up to 32 devices.
In read/write operation, the management da ta frame
is 64-bit long start with 32 contiguous logic one bits
(preamble) synchronization clock cycles on MDC. The
Start of Frame De limiter (SFD) is indicated by a <01>
pattern followed by the operation code (OP):<10>
indicates Read operation and <01> indicates Write
operation. For read operation, a 2-bit turnaround (TA)
filing between Resistor Address field and Data field is
provided for MDIO to avoid contention. “Z” stands for
high impedance state. Following turnaround time, a
16-bit data is read from or writt en onto management
registers.
Management Interface - Read Frame Structure
32 "1"s 0110A4A3A0R4R3R0
Z0
Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle
Read
Write
MDC
MDIO Read D15 D14 D1 D0
// //
Management Interface - Write F ra me S t ruc ture
32 "1"s 0 1 10 A4 A3 A0 R4 R3 R0 1 0 D15 D14 D1 D0
Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle
Write
MDC
MDIO Write
DM9102
10/1 00Mbps S ingle C hip L AN Controller
52 Final
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T
Configuration ROM Overview
The purpose of Configuration RO M (EEPROM) is to
support the DM9102 information to the driver for the
card. The CROM m ust support 64 words or more
space for configuration data. The format of the
CROM is as followed:
The format of EEPROM.
Fi eld Name Offset Size
Subsystem ID block 0 18
CROM version 18 1
Controller count 19 1
Controller_0 Information 20 n
Controller_1 Information 20+n m
: (depends on controller count) : :
CRC checksum 126 2
1. Subsystem ID Bl ock
Every card must have a Subsystem ID to indicate
the system vendor information. The content will be
transferred into the PCI configuration space du ring a
Hardware reset function.
(a) Vendor ID & De vice ID can be s et in EEPR OM
content & auto-loaded to PCI configuration
register after reset. (default value = 1282, 9102)
This function must be selectable for
enable/disable by Auto_Load_Control ( offset 08
of EEPROM) setting to avoid damagin g default
value due to
(b ) incorre ctly auto-load oper ation.
CRC check c ircuit o f EEPROM contents to d ecide
the auto-load operation of Vendor ID & Su bsy stem.
Subsystem Vendor ID
Subsystem ID
Reserved
Reserved
ID_block_CRC
Reserved
Reserved
Reserved
PCI Device ID
PCI Vender ID
NCE
Auto_load_control
0
2
4
6
8
10
12
14
17,16
Byte Offset.Subsystem ID Block
DM9102
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Version: DM9102-DS-F03
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Byte Offs et (08 ): Auto_Load_C ontrol
0347
Bi t3~0 : “1010” to enable a uto-load of PCI Vendor_ID &
Device_ID, “0” to disable.
Bi t7~4 : “1X1X” to enable auto-load of NCE, to PCI
configurat ion space.
Byte Offset (09): New_Capabilities_Enable
017
Bit0: Directly mapping to bit20 (New Capabilities) of the
PCICS
Byte Offset (16): ID_BLOCK_CRC
07
This field is implemented to confirm the correct reading of
the EEPROM contents.
2. CRO M Versi on
Current version numb e r is 03 .
3. Controller Count
The configuration ROM supports multipl e cont r ollers
in one board . Every controller has its unique controller
inform ation block. Controller count indicates the
num ber of cont rollers put in the card.
4. Controller_X Information
Each controller has its infor mation b lock to address its
node ID, GPR control, supported connect media types
(Media Information Block) and other ap plication circuit
information block.
Controller Information Header
ITEM Offset Size
Node Address 0 6
Controller_x Number 6 1
Controller_x Info. Block Offset 7 1
5. Controller Information Body Pointed By Controller_X
Info Bl ock Offset Item In Controller Information Header:
Item Offset Size
Connection Type
Selected 02
GPR Control 2 1
Bl ock Count 3 1
Block_1 4 n
: 4+n m
* Connect Type Selected indicates the default
connect medi a type selec ted.
* GPR Contro l de fines the input or output direction o f GPR.
There are three types of block:
1. PHY Information Block (type=01)
2. Media Information Block (type=00)
3. Delay Period Block (type=80)
PHY information Block (type=01)
Item Offset Size
Block Length 0 1
Block Type(01) 1 1
PHY Number 2 1
GPR Initial Length(G_i) 3 1
GPR Initial Data 4 G_i
Reset Sequence
Length(R_i) 4+G_i 1
Reset Data 5+G_i R_i
Media Capabilities 5+G_i+R_i 2
Nway Advertisement 7+G_i+R_i 2
FDX Bit Map 9+G_i+R_i 2
TTM Bit Map 11+G_i+R_i 2
Note 1: The definit io n of Media Capabilitie s and Nway
Advertisement i s the sam e wit h 802.3U in
terms of A uto-negoti ation.
DM9102
10/1 00Mbps S ingle C hip L AN Controller
54 Final
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Media Information Block (Type = 00)
ITEM Offset Size
Block Length 0 1
Block Type( 00) 1 1
Media Code 2 1
GPR Data 3 1
Command 4 2
Note 1: Media Code: 10BASE_T Half Duplex 00
10 BASE_T Full Duplex 04
100 BASE_T Half Duplex 01
100 BASE_T Full Duplex 05
Note 2: Command Format
Delay Period Block (Type = 80) Define the delay
time unit in us.
ITEM Offset Size
Block Length 0 1
Block Type( 80) 1 1
Time Unit 2 2
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
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T
Absolute Maximum Ratings*
Supply Voltage (VCC)...........................-0.5V to 5.5V
Maximum DC Input Voltage (VIN) -0.5V to VCC+0. 5V
DC Output Voltage (VOUT).........-0.5V to VCC +0.5V
Storage Temperature Rang (Tstg) ..-65
to +150
Case Temperature Range……………..…0
to 85
Infrared So lder Reflow Peak Temp. (10 to 20 sec.)
..........................................................220
to 225
ESD Rating (Rzap=1.5K, Czap=100Pf) .......... 4000V
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
sections of this specifi c ation is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect devic e reliability .
a
DC Electrical Characteristics
Symbol Parameter Min. Typ. Max. Unit Conditions
VCC Supply Voltage 4.75 - 5.25 V -
TOP Operation Temperature -20 - 70 C -
VIL Input Low Voltage - - 0.8 V -
VIH Input High Voltage 2.0 - - V -
VOL Output Low Voltage (Iol = 8mA) - - 0.5 V -
VOH Output High Voltage (Ioh = -2mA) 2.4 - - V -
IIL Input Leakage Current - - 10 uA -
IDD Operation Supply Current - 230 250 mA -
IPD Power down Supply Current - T/D - uA -
Receiver
Symbol Parameter Min. Typ. Max. Unit
VICM RXI+/RXI- Input Common-Mode Voltage 1.5 2.0 2.5 V 100 Ω termination
Across
Transmitter
ITD100 100TXO+/- 100BASE-TX M ode
Differential Output Current 19 21 mA Absolute Value
ITD10 10TX+/- 10BASE-T Differential Output
Current 44 50 56 mA Absolute Value
* -: N o defi ned value
*T/D: To be det ermined
DM9102
10/1 00Mbps S ingle C hip L AN Controller
56 Final
Version: DM9102-DS-F03
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a
AC Electrical Characteristics
z
PCI Clock Specifications Timing
t
HIGH
2.0V
0.8V
t
R
t
F
t
LOW
t
CYCLE
Symbol Parameter Min. Typ. Max. Unit Conditions
tRPCI_CLK rising time 4 - - ns -
tFPCI_CLK falling time 4 - - ns -
tCYCLE Cycle time 30 - - ns -
tHIGH PCI_CLK High Time 12 - - ns -
tLOW PCI_CLK Low Time 12 - - ns -
z
Other PCI Sig nals Timing Diagr am
t
OFF
t
H
t
SU
Input t
ON
Output
c
LK
2.5V t
VAL
(max) t
VAL
(min)
Symbol Parameter Min. Typ. Max. Unit Conditions
tVAL Clk -To- Signal V alid Dealy 2 - 11 ns Cload = 50 pF
tON Float-To-Active De lay From Clk 2 - - ns -
tOFF Activ e- To-Float Dealy From Clk - - 28 ns -
tSU Input Signal Valid Se tup Time Before Clk 7 - - ns -
tHInput Signal Hold Time From Clk 0 - - ns -
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 57
Version: DM9102-DS-F03
August 30, 2000
z
Multiplex Mode Boot ROM Timing
t
OH
t
EHQZ
t
ELQV
tAVAV
t
ELQX
Address=<7;2>
oe=1,we=0 Address
<15;8> Date<7;0>
Valld
t
ADS
t
ADH
t
ADS
t
ADH
BPAD
<7;0>
BPA1
BPCS#
Address<1>
Address<17> Address<16>
BPA0 Address<0>
Symbol Parameter Min. Type Max. Unit Conditions
TAVAV Read Cycle Time - 31 - PCI clock -
tELQV BPCS# To Output Delay 0 - 7 PCI clock -
tEHQZ BPCS# Rising Edge To Output High
Impedance -1-PCI clock -
t
OH Out put Hold From BPCS# 0 - - PCI clock -
t
ADS Address Setup To Latch Enable High 4 - - PCI clock -
t
ADH Address Hold From Latch Enable High 4 - - PCI clock -
z
Direct Mode Boot ROM Timing
Frame#
Irdy#
Trdy#
Devsel#
CBEL[3:0]
AD[31:0]
MD[7:0]
MA[17:0]
ROMCS
tCBAD t1ADL t2ADL t3ADL t4ADL
tADTD
tRC
DM9102
10/1 00Mbps S ingle C hip L AN Controller
58 Final
Version: DM9102-DS-F03
August 30, 2000
Symbol Parameter Min. Type Max. Unit Conditions
tRC Read Cycle Time - 50 - PCI clock -
t
CBAD Bus Command to first address delay - 18 - PCI cl oc k -
t1ADL fi rst address length - 8 - PCI clock -
t2ADL second address delay - 8 - PCI clock -
t3ADL third address delay - 8 - PCI clock -
t4ADL fourth address delay - 7 - PCI clock -
tADTD end of address to Tardy active - 1 - PCI clock -
z
EEPROM Timi ng
ROMCS
EECK
EEDO
tCSKD
tECKC
tEDSP
tECSC
Symbol Parameter Min. Typ. Max. Unit Conditions
tECKC Serial ROM cl oc k EECK period 64 - - PCI cl oc k -
tECSC Read Cycle Time 1792 - - PCI clock -
tCSKD Delay from R OMCS High to EECK High 28 - - PCI clock -
tEDSP Setup Time of EEDO to EECK 24 - - PCI clock -
z
PHYceiver :
Symbol Parameter Min. Typ. Max. Unit Conditions
Transmitter
tTR/F 100TXO+/- Differential Rise/Fall Time 3.0 5.0 ns
tTM 100TXO+/- Differential Rise/Fall Time
Mismatch -0.5 0.5 ns
tTDC 100TXO+/- Differential Output Duty Cycle
Distortion -0.5 0.5 ns
tT/T 100TXO+/- Differential Output Peak-to-
Peak Jitter 800 ps
XOST 100TXO+/- Differential Voltage Overshoot 5 %
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 59
Version: DM9102-DS-F03
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z
Auto-negotiatio n and Fast Li nk Pulse Timing Diagr am
FAST LINK
PULSES
Clock Pulse Data Pulse Clock Pulse
t
1
t
2
t
3
FLP Burst FLP Burst
t
4
t
5
10TX0+/-
FAST LINK
PULSES
Clock Pulse Data Pulse Clock Pulse
t
1
t
2
t
3
FLP Burst FLP Burst
t
4
t
5
10TX0+/-
Symbol Parameter Min. Typ. Max. Unit Conditions
t1Cloc k/Data Pulse Width - 100 - ns
t2Clock Pu lse To Data Pulse Period - 62.5 - us DATA = 1
t3Clock Pulse To Clock Pulse Period - 125 - us
t4FLP Burst Width - 2 - ms
t5FLP Burst To FLP Burst Period - 13.93 - ms
- Clock/Data Pulses Per Burst 33 33 33 ea
DM9102
10/1 00Mbps S ingle C hip L AN Controller
60 Final
Version: DM9102-DS-F03
August 30, 2000
Packag e In form ation
QFP 128L Outline Dimensions
Unit: In che s/mm
L
L1
Detail F
θ
θθ
θ
Seating Plane
See Detail F
D
y
0.10
See Detail A
A
A2A
1
y
B
e
138
128
103
65
102
D
D1
E1 E
64
39
With Plating
Base
Metal
Detail A
C
B
Symbol Dimension In Inch Dimension In mm
A 0.134 Max. 3.40 Max.
A1 0.010 Min. 0.25 Min.
A2 0.112± 0.005 2.85± 0.1 2
B0.009± 0.002 0.22±0.05
C0.006± 0.002 0.145± 0.055
D0.913± 0.007 23.20± 0.20
D1 0.787± 0.004 20.00 ± 0.10
E0.677± 0.008 17.20± 0.20
E1 0.551± 0.004 14.00± 0.10
e
0.020 BSC 0.5 BSC
L0.035± 0.006 0.88± 0.1 5
L1 0.063 BSC 1.60 BSC
y 0.004 Max. 0.10 Max.
θ0°~12°0°~12°
Note:
1. Dimension D1 and E1 do not include resin fins.
2. All d imensions are based on metric sy stem.
3. General appearance spec. should base itself on final visu al inspection spec.
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 61
Version: DM9102-DS-F03
August 30, 2000
Ordering Information
Part Number Pin C ount Package
DM9102F 128 QFP
Disclaimer
The information appearing i n this publication is b elieved to
be accurate. Inte g ra t ed c irc uit s sol d by DA VICOM
Semiconductor are covered by the warranty and patent
ind e mnificatio n pr ovision s stipulated in the t e rms of sale only.
DAVICOM makes no warranty, express, statutory, implied
or by description regarding the information in this publication
or regarding the i nforma tion in this publication or regarding
the freedom of the described chip(s) f rom patent
infringement. FURTHER, DAVICOM MAKES NO
WAR RANTY OF MER CHAN TABILIT Y OR FITNE SS FOR
ANY PURPOSE. DAVICO M reserves the right to halt
production or alter the specifications and prices at any time
without notice. According ly, the reader is cautioned to ve rify
tha t th e da t a sheets and othe r information in this publication
are current before p lacing order s. Products described he rein
are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability
requirements, e.g. military equipment or medical life s upport
equipment, are specifically not recommended w ithout
additional process ing by DAVICOM for such applications.
Please note that application circuits illustrated in this
document are for re ference purposes only.
DAVICOM‘s ter ms and cond itions pr inted o n the order
acknow ledgmen t govern a ll sa les by DAVICOM. DAVICOM
will not be bound by any terms inconsisten t with these
unless DAVICOM agrees otherwise in w riting. Acceptance
of the buyer’s orders s hall be based on t hese terms.
Company Overview
DAVICOM Semiconductor, Inc. develops and manufactures
integrated circuits for integration into data commu nication
products. Our mission is to design and p roduce IC products
that are the industry’s best value for Data, Audio, V ideo, and
Internet/Intranet applications. To achieve this goal, we have
built an orga nization that is able to devel op chipsets in
response to the e vo lving technology requ irements o f our
cus tomers wh ile s till de li ver ing produ cts th at meet th eir cost
requirements.
Products
We o ffer only products that satis fy high p erformance
requirements and which are c ompatible with major
hardware and software standards. Our currently available
and soon to be released produc t s a re b ased on our
proprietary designs and d eliver high quality, high
performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact th e sales department at:
Headquarters
Hsin-chu Off ice:
3F, No. 7-2, Industry E. Rd., IX,
Science-based Park,
Hs in-c hu C ity , Ta iw an , R. O.C .
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Sunnyvale, California
1135 Kern A ve., Sunnyvale,
CA94085, U.S.A.
TEL: 1-408-7368600
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Email: sales@davicom8.com
WARNING
C ondit i ons b ey on d th os e lis t ed for the absolute m axi m u m m ay d estr oy or d am ag e th e products. In addit ion, condit io n s for s u s tai ned
periods at near the limits of the operating range s will stress and may temporarily (and permanently) affect and damage structure,
performance and/ or func tion.
DM9102
10/1 00Mbps S ingle C hip L AN Controller
62 Final
Version: DM9102-DS-F03
August 30, 2000
A ppendix A
DM 9102 SROM Form at
Total Size: 128 Bytes
Field Name Offset
(Bytes) Size (Bytes) Value
(Hex) Commentary
Sub-Vendor ID 0 2 0291 ID B lock
Sub-Device ID 2 2 8212
Reserved1 4 4 00000000
Auto_Load_Control 8 1 00 Auto-load function definition:
Bit 3..0 = 1010
Æ
Auto-Load PCI Vendor
ID/Device ID enabled
Bit 7..4 = 1010
Æ
Auto-Load
PMC/PMCSR enabled
(P.S.: For DM9102 E7 and later Bit 7. .4 =
1x1x
Æ
Auto-Load PMC/PMCSR
enabled)
New_Capabilities_Enable (NCE) 9 1 00 Please re fer to DM9102 Spec.
PCI Vendor ID 10 2 1282
PCI Device ID 12 2 9102 If Au to-Load PC I Vendor ID/Dev ice ID function
disabled, the PCI Vendor ID/Device ID will u se
the d e fau l t va lue s ( 1282h, 9102h).
Reser ved 14 1 00 Please re fer to DM9102 Spec.
Reser ved 15 1 00 Please re fer to DM9102 Spec.
ID_BLOCK_CRC 16 1 - Offset 0..15, 17 ID CRC
Reserved2 17 1 00
SROM Fo rmat Version 18 1 03 Version 3.0
Controller Count 19 1 01
IEEE Network Address 20 6 - Controller Info Header
Controller_0 Dev Number 26 1 00
Controller_0 In fo Lea f Offset 27 2 001E Offset 30
Reserved3 29 1 00
Selected Connected Type 30 2 0800 Controller_0 Info Leaf Block
General Purpose Control 32 1 80 MAC CR12 Register
Bloc k Count 33 1 06 6 B lock s
F(1)+Length 34 1 8E Block 1 (PHY Info Block)
Type 35 1 01 PHY Information Block
PHY Number 36 1 01 PHY Address
GPR Length 37 1 00
Reset Sequence Length 38 1 02
Reset Sequence 39 2 0080
Media Capabilities 41 2 7800
Nway Ad vertisement 43 2 01E0
FDX Bit Map 45 2 5000
TTM Bit Map 47 2 1800
DM9102
10/ 100 Mbps Si ngle Chi p LAN Controller
Final 63
Version: DM9102-DS-F03
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Field Name Offset
(Bytes) Size (Bytes) Value
(Hex) Commentary
F(1)+Length 49 1 85 Block 2 (Delay Period Block)
Type 50 1 80 Delay Period Block
Delay Sequence 51 4 40002000 MicroSecond
F(1)+Length 55 1 85 Block 3 (Media Info Block)
Type 56 1 00 Media Information Block
Media Code 57 1 00 10Base-T Half_Duplex
GPR Data 58 1 00
Command 59 2 0087
F(1)+Length 61 1 85 Block 4 (Media Info Block)
Type 62 1 00 Media Information Block
Media Code 63 1 01 100Base-TX Half_Duplex
GPR Data 64 1 00
Command 65 2 0087
F(1)+Length 67 1 85 Block 5 (Media Info Block)
Type 68 1 00 Media Information Block
Media Code 69 1 04 10Base-T Full_Duplex
GPR Data 70 1 00
Command 71 2 0087
F(1)+Length 73 1 85 Block 6 (Media Info Block)
Type 74 1 00 Media Information Block
Media Code 75 1 05 100Base-TX Full_Duplex
GPR Data 76 1 00
Command 77 2 0087
SROM_CRC 126 2 - Offset 0..125 SROM CRC
