CY14B101LA
CY14B101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-42879 Rev. *R Revised May 8, 2017
1-Mbit (128 K × 8/64 K × 16) n vSRAM
Features
20 ns, 25 ns, and 45 ns access times
Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16
(CY14B101NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20% to –10% operation
Industrial temperature
Packages
32-pin small-outline integrated circuit (SOIC)
44-/54-pin thin small outline package (TSOP) Type II
48-pin shrink small-outline package (SSOP)
48-ball fine-pitch ball grid array (FBGA)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 128 K bytes of 8 bits each or 64 K words
of 16 bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independen t nonvolatile da ta resides in the hi ghly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory .
Both the STORE and RECALL operations are also available
under software control.
For a complete list of related resources, click here.
STATIC RAM
ARRAY
1024 X 1024
R
O
W
D
E
C
O
D
E
R
COLUMN I/O
COLUMN DEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum Trap
1024 X 1024
STORE
RECALL
VCC VCAP
HSB
A0A1A2A3A4A10 A11
SOFTWARE
DETECT A14 - A2
OE
CE
WE
BHE
BLE
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Logic Block Diagram [1, 2, 3]
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 2 of 30
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................5
Device Operation ..............................................................6
SRAM Read ................................................................6
SRAM Write .................................................................6
AutoStore Operation ....................................................6
Hardware STORE Operation ........................... ............6
Hardware RECALL (Power-up) ...................................7
Software STORE .........................................................7
Software RECALL .......................................................7
Preventing AutoStore ..................................................8
Data Protection ............ .............. ... .............. ... ..............8
Maximum Ratings .............................................................9
Operating Range ..................... .. .............. ... .............. ... ......9
DC Electrical Characteristics ......................... .................9
Data Retention and Endurance .....................................1 0
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads ........................ .............. .. .............. ... ... ....11
AC Test Conditions .................. .............. ... .............. ... ....11
AC Switching Characterist ics .......... ... .. .............. ... .......12
SRAM Read Cycle ....................................................12
SRAM Write Cycle .....................................................12
Switching Waveforms ....................................................12
AutoStore/Power-Up RECALL .......................................15
Switching Waveforms ....................................................15
Software Controlled STORE/RECALL Cycle ................16
Switching Waveforms ....................................................16
Hardware STORE Cycle .................................................17
Switching Waveforms ....................................................17
Truth Table For SRAM Operations ................................18
Ordering Information ......................................................19
Ordering Code Definitions .........................................20
Package Diagrams ..........................................................21
Acronyms ........................................................................ 26
Document Conventions ................................ ... ... ...........26
Units of Measure .......... .............. ... ... .............. ... ... .....26
Document History Page ........................ ... .............. ... .. ...27
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support .......................30
Products .................................................................... 30
PSoC Solutions ................................... ... .. .............. ...30
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 3 of 30
Pinouts Figure 1. Pin Diagram – 44-pin TSOP II
Figure 2. Pin Diagram – 48-pin SSOP and 32-pin SOIC
NC
A
8
NC
NC
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44-pin TSOP II
Top View
(not to scale)
A
10
NC
WE
DQ
7
HSB
NC
V
SS
V
CC
V
CAP
NC
(× 8)
[6]
[7]
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44-pin TS OP II
Top View
(not to scale)
WE
DQ
7
A
0
V
SS
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
(× 16)
[8]
[4]
[5]
[4]
[5]
NC
A
8
NC
NC
V
SS
DQ6
DQ5
DQ4
V
CC
A
13
DQ3
A
12
DQ2
DQ1
DQ0
OE
A
9
CE
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
11
A
7
A
14
A
15
A
16
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
10
NC
WE
DQ7
HSB
NC
V
SS
V
CC
V
CAP
NC
45
46
47
48
NC
NC
NC
NC
48-pin SSOP
(×8) (x8)
(×8)
32-pin SOIC
Top View Top View
(not to scale) (not to scale)
Notes
4. Address expansion for 2-Mbit. NC pin not connected to di e.
5. Address expansion for 4-Mbit. NC pin not connected to di e.
6. Address expansion for 8-Mbit. NC pin not connected to di e.
7. Address expansion for 16-Mbit. NC pin not connected t o die.
8. HSB pin is not available in 44-pin TSOP II (× 16) package.
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 4 of 30
Figure 3. 48-ball FBGA and 54-pin TSOP II pinout
Pinouts (continued)
NC
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
DQ
3
DQ
2
DQ
1
DQ
0
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CAP
WE
A
8
A
10
A
11
A
12
A
13
A
14
A
15
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
Top View
(
not to scale)
OE
CE
V
CC
NC
V
SS
NC
A
9
NC NC
NC
NC
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
DQ
11
DQ
10
DQ
9
DQ
8
(x16)
[11]
[12]
[9]
[10]
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
NC
DQ
0
A
4
A
5
NC
DQ
2
DQ
3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
NC
NC
A
2
A
1
NC
V
CC
DQ
4
NC
DQ
5
DQ
6
NC DQ
7
NC
A
15
A
14
A
13
A
12
HSB
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
NC NC
DQ
1
48-FBGA
(not to scale)
Top View
(x8)
[11]
[9]
[10]
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 5 of 30
Pin Definitions
Pin Name I/O Type Description
A0–A16 Input Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration.
A0–A15 Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration.
DQ0–DQ7Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
DQ0–DQ15 Bidirectional Data I/O Lines for × 16 configuration. Used as input or output lines depending on operation.
WE Input Write Enable input, Active LOW. When the chip is enabled and WE is LOW , data on the I/O pins is written
to the specific address location.
CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HI GH, deselects the chip.
OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
BHE Input Byte High Enable, Active LOW. Controls DQ15–DQ8.
BLE Input Byte Low Enable, Active LOW. Controls DQ7–DQ0.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VCC Power supply Power supply inputs to the device. 3.0 V +20%, –10%
HSB[13] Input/Output Hardware STORE Busy (HSB). When LOW , this output indicates that a Hardware STORE is in progress.
When pulled LOW , external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC No connect No connect. This pin is not connected to the die.
Note
13.HSB pin is not available in 44-pin TSOP II (× 16) package.
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 6 of 30
Device Operation
The CY14B101LA/CY14B101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumT rap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B101LA/CY14B101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See the Truth Table For SRAM Operations on page
18 for a complete description of read and write modes.
SRAM Read
The CY14B101LA/CY14B101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–16 or A0–15 determines which of the 131,072
data bytes or 65,536 wo rds of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address chang es within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ 0–15
are written into the memory if the data is valid tSD before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buff ers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B101LA/CY14B101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the
CY14B101LA/CY14B101NA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor .
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the store. This
corrupts the data stored in nvSRAM.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. See the DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on po wer-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStor e Mode
Hardware STORE Operation
The CY14B101LA/CY14B101NA provides the HSB[14] pin to
control and acknowledge the STORE operations. Use the HSB
pin to request a Hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B101LA/CY14B101NA conditionally
initiates a STORE operation after tDELAY. An actual ST ORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
0.1 uF
VCC
10 kOhm
VCAP
WE VCAP
VSS
VCC
Note
14.HSB pin is not available in 44-pin TSOP II (× 16) package.
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 7 of 30
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t DELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B101LA/CY14B101NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B101LA/CY14B101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-up)
During power-up or after any low power condition
(VCC<V
SWITCH), an internal R ECALL request is latched. W hen
VCC again exceeds the VSWITCH on power up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101LA/CY14B101NA
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed , followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth addre ss in the sequence is entered,
the STORE cycle commences and the chip is d isabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To in itiate the RECALL cycle,
the following sequence of CE or OE controlled read operation s
must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally , RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
CE WE OE BHE, BLE[15] A15–A0[16] Mode I/O Power
H X X X X Not selected Output high Z S tandby
L H L L X Read SRAM Output data Active
L L X L X Write SRAM Input data Active
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output data
Output data
Output data
Output data
Output data
Output data
Active[17]
Notes
15.BHE and BLE are applicable for x16 configuration only.
16.While there are 17 address lines on the CY14B101LA (16 address lines o n the CY14B101NA), only the 13 add ress lines (A14 - A 2) are used to control software mo des.
Rest of the address lines are do not care.
17.The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 8 of 30
Preventing AutoSt ore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner simila r to the So ftware STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStor e Disable
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoSto r e Enable
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power-down
cycles. The part comes from the factory with AutoStore enabled
and 0x00 written in all cells.
Data Protection
The CY14B101LA/CY14B101NA protects data from corruption
during low voltage conditions by inh ibitin g a ll externally i nitiated
STORE and write operations. The low voltage condition is
detected when VCC is less than VSWITCH. If the
CY14B101LA/CY14B101NA is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until th e SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power-up
or brown out conditions.
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[18]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Output high Z
Active ICC2[18]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output high Z
Active[18]
Table 1. Mode Selection (continued)
CE WE OE BHE, BLE[15] A15–A0[16] Mode I/O Power
Note
18.The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
CY14B101LA
CY14B101NA
Document Number: 001-42879 Rev. *R Page 9 of 30
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time:
At 150 C ambient temperature ................... ... 1000 h
At 85 C ambient temperature .................... 20 Years
Maximum junction temperature ................................. 150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Voltage applied to outputs
in High Z state .......................... .. ... .....–0.5 V to VCC + 0.5 V
Input voltage .......................................–0.5 V to VCC + 0.5 V
Transient voltage (< 20 ns) on
any pin to ground potential .................–2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) .................................................1.0 W
Surface mount Pb soldering
temperature (3 Seconds) ......................................... +260 C
DC output current (1 output at a time , 1s duration) ....15 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch up current .................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85 C 2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [19] Max Unit
VCC Power supply voltage 2.7 3.0 3.6 V
ICC1 Average VCC current tRC = 20 ns
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
––70
70
52
mA
mA
mA
ICC2 Average VCC current during
STORE All inputs don’t care, VCC = Max
Average current for duration tSTORE ––10mA
ICC3 Average VCC current at
tRC = 200 ns, VCC(Typ), 25 °C All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA)
–35–mA
ICC4 Average VCAP current during
AutoStore cycle All inputs don’t care. Average current for
duration tSTORE ––5mA
ISB VCC standby current CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolati le cycle
is complete.
Inputs are static. f = 0 MHz
––5mA
IIX[20] Input leakage current (except
HSB)VCC = Max, VSS < VIN < VCC –1 +1 µA
Input leakage current (for HSB)V
CC = Max, VSS < VIN < VCC –100 +1 µA
IOZ Of f-state output leakage current VCC = Max, VSS < VOUT < VCC,
CE or OE > VIH or BHE/BLE > VIH or WE < VIL
–1 +1 µA
VIH Input HIGH voltage 2.0 VCC + 0.5 V
VIL Input LOW voltage VSS – 0.5 0.8 V
VOH Output HIGH voltage IOUT = –2 mA 2.4 V
VOL Output LOW vo ltage IOUT = 4 mA 0.4 V
Notes
19.Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
20.The HSB pin has IOUT = -2 µA for VOH of 2.4 V when both active high and low drivers are disabled. When they are enabled st andard VOH and VOL are valid. This
parameter is characterized but not tested.
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VCAP[21] Storage capacitor Between VCAP pin and VSS 61 68 180 µF
VVCAP[22, 23] Maximum voltage driven on VCAP
pin by the device VCC = Max VCC V
Data Retention and Endurance
Over the Operating Range
Parameter Description Min Unit
DATARData retention 20 Years
NVCNonvolatile STORE operations 1,000 K
Capacitance
Parameter[23] Description Test Conditions Max Unit
CIN Input capacitance (except BHE, BLE and HSB)T
A = 25 C, f = 1 MHz, VCC = VCC(Typ) 7pF
Input capacitance (for BHE, BLE and HSB)8pF
COUT Output capacitance (except HSB) 7 pF
Output capacitance (for HSB) 8 pF
Thermal Resistance
Parameter[23] Description Test Conditions 54-pin
TSOP II 48-pin
SSOP 48-ball
FBGA 44-pin
TSOP II 32-pin
SOIC Unit
JA Thermal resistance
(junction to ambient) Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, in
accordance with
EIA/JESD51.
36.4 37.47 48.19 41.74 41.55 C/W
JC Thermal resistance
(junction to case) 10.13 24.71 6.5 11.90 24.43 C/W
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter Description Test Conditions Min Typ [19] Max Unit
Notes
21.Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor
on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore
it is always recommended to use a capacitor within the specified min and max limits. See application note AN43593 for more details on VCAP options.
22.Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage.
23.These parameters are guaranteed by design and are not tested.
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AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels .......................1.5 V
AC Test Loads Figure 5. AC Test Loads
3.0 V
OUTPUT
5 pF
R1
R2
789
3.0 V
OUTPUT
30 pF
R1
R2
789
for tristate specs
577 577
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AC Switching Characteristics
Over the Operating Range
Parameters [24]
Description 20 ns 25 ns 45 ns Unit
Cypress
Parameter Alt Parameter Min Max Min Max Min Max
SRAM Read Cycle
tACE tACS Chip enable access time –20–25–45ns
tRC[25] tRC Read cycle time 20 2 5 45 ns
tAA[26] tAA Address access time 20 25 45 ns
tDOE tOE Output enable to data valid 10 12 20 ns
tOHA[26] tOH Output hold after address change 3–3–3–ns
tLZCE[27, 28] tLZ Chip enable to output active 3–3–3–ns
tHZCE[27, 28] tHZ Chip disable to output inactive 8 10 15 ns
tLZOE[27, 28] tOLZ Output enable to output active 0–0–0–ns
tHZOE[27, 28] tOHZ Output disable to output inactive 8 10 15 ns
tPU[27] tPA Chip enable to power active 0–0–0–ns
tPD[27] tPS Chip disable to power standby 20 25 45 ns
tDBE[[27] Byte enable to data valid 10 12 20 ns
tLZBE[27] Byte enable to output active 0–0–0 ns
tHZBE[27] Byte disable to output inactive 8 10 15 ns
SRAM Write Cycle
tWC tWC Write cycle time 20–25–45–ns
tPWE tWP Write pulse width 15 20 3 0 ns
tSCE tCW Chip enable to end of write 15 20 30 ns
tSD tDW Data setup to end of write 8 10 15 ns
tHD tDH Data hold after end of write 0–0–0–ns
tAW tAW Address setup to end of write 15 20 30 ns
tSA tAS Address setup to start of write 0–0–0–ns
tHA tWR Address hold after end of write 0–0–0–ns
tHZWE[27, 28, 29] tWZ Write enable to output disable 8 10 15 ns
tLZWE[27, 28] tOW Output active after end of write 3–3–3–ns
tBW Byte enable to end of write 15 20 30 ns
Switching Waveforms Figure 6. SRAM Read Cycle #1 (Address Controlled) [25, 26, 30]
Address
Data Output
Address Valid
Previous Data Valid Output Data Valid
tRC
tAA
tOHA
Notes
24.Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse l evels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 5 on page 11.
25.WE must be HIGH during SRAM read cycles.
26.Device is continuously selected with CE, OE, and BHE/BLE LOW.
27.These parameters are guaranteed by design and are not test ed.
28.Measured ±200 mV from steady sta te output voltage.
29.If WE is low when CE goes low, the outputs remain in the high impedance state.
30.HSB must remain HIGH during Read and Write cycles.
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Figure 7. SRAM Read Cycle #2 (CE and OE Controlled) [31, 32, 33]
Figure 8. SRAM Write Cycle #1 (WE Controlled) [31, 33, 34, 35]
Switching Waveforms (continued)
Address ValidAddress
Data Output Output Data Valid
Standby Active
High Impedance
CE
OE
BHE, BLE
ICC
tHZCE
tRC
tACE
tAA
tLZCE
tDOE
tLZOE
tDBE
tLZBE
tPU tPD
tHZBE
tHZOE
Data Output
Data Input Input Data Valid
High Impedance
Address ValidAddress
Previous Data
tWC
tSCE tHA
tBW
tAW
tPWE
tSA
tSD tHD
tHZWE tLZWE
WE
BHE, BLE
CE
Notes
31.BHE and BLE are applicable for × 16 configuration only.
32.WE must be HIGH during SRAM read cycles.
33.HSB must remain HIGH during Read and Write cycles.
34.CE or WE must be > VIH during address transitions.
35.If W E is low when CE goes low, the outputs remain in the high impedance state.
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Figure 9. SRAM Write Cycle #2 (CE Controlled) [36, 37, 38, 39]
Figure 10. SRAM Write Cycle #3 (BHE and BLE Contro lle d ) [36, 37, 38, 39]
Switching Waveforms (continued)
Data Output
Data Input Input Data Valid
High Impedance
Address Valid
Address
tWC
tSD tHD
BHE, BLE
WE
CE
tSA tSCE tHA
tBW
tPWE
Data Output
Data Input Input Data Valid
High Impedance
Address ValidAddress
tWC
tSD tHD
BHE, BLE
WE
CE
tSCE
tSA tBW tHA
tAW
tPWE
Notes
36.BHE and BLE are applicable for × 16 configuration only.
37.If WE is low when CE goes low, the outputs remain in the high-impedance state.
38.HSB must remain HIGH during Read and Write cycles.
39.CE or WE must be > VIH during address transitions.
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AutoStore/Power-Up RECALL
Over the Operating Range
Parameter Description 20 ns 25 ns 45 ns Unit
Min Max Min Max Min Max
tHRECALL[40] Power-Up RECALL duration 20 20 20 ms
tSTORE [41] STORE cycle duration 8 8 8 ms
tDELAY [42] T ime allowed to complete SRAM
write cycle –20–25–25ns
VSWITCH Low voltage trig ger level 2.65 2.65 2.65 V
tVCCRISE[43] VCC rise time 150 150 150 µs
VHDIS[43] HSB output disable voltage 1.9 1.9 1.9 V
tLZHSB[43] HSB to output active time 5 5 5 µs
tHHHD[43] HSB High active time 500 500 500 ns
Switching Waveforms Figure 11. AutoStore or Power-Up RECALL [44]
VSWITCH
VHDIS
tVCCRISE tSTORE tSTORE
tHHHD
tHHHD
tDELAY
tDELAY
tLZHSB tLZHSB
tHRECALL
tHRECALL
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write POWER
DOWN
AutoStore
Note Note
Note
Note
VCC
41 41
45
45
Notes
40.tHRECALL starts from the time VCC rises higher than VSWITCH.
41.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
42.On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for ti me tDELAY.
43.These parameters are guaranteed by design and are not tested.
44.Read and Write cycles are ignored during STORE, RECALL, and while VCC is lower than VSWITCH.
45.During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
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Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameter[46, 47] Description 20 ns 25 ns 45 ns Unit
Min Max Min Max Min Max
tRC STORE/RECALL initiation cycle time 20 25 45 ns
tSA Address setup time 0 0 0 ns
tCW Clock pulse width 15–20–30–ns
tHA Address hold time 0 0 0 ns
tRECALL RECALL duration 200 200 200 µs
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle [47]
Figure 13. AutoStore Enable /Disable Cycle [47]
tRC tRC
tSA tCW
tCW
tSA
tHA
tLZCE
tHZCE
tHA
tHA
tHA
tSTORE/tRECALL
tHHHD
tLZHSB
High Impedance
Address #1 Address #6Address
CE
OE
HSB (STORE only)
DQ (DATA)
RWI
tDELAY Note
48
tRC tRC
tSA tCW
tCW
tSA
tHA
tLZCE
tHZCE
tHA
tHA
tHA
tDELAY
Address #1 Address #6Address
CE
OE
DQ (DATA)
tSS
Note
RWI
48
Notes
46.The software sequence is clocked with CE controlled o r OE controlled reads.
47.The six consecutive addresses must be read in the order li sted in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
48.DQ output data at the sixth read may be invalid because the output is disabled at tDELAY tim e.
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Hardware STORE Cycle
Over the Operating Range
Parameter Description 20 ns 25 ns 45 ns Unit
Min Max Min Max Min Max
tDHSB HSB to output active time when write latch not set 20 25 25 ns
tPHSB Hardware STORE pulse width 15–15–15–ns
tSS [49, 50] Soft sequence processing time 100 100 100 s
Switching Waveforms
Figure 14. Hardware STORE Cycle [51]
Figure 15. Soft Sequence Processing [49, 50]
tPHSB
tPHSB
tDELAY tDHSB
tDELAY
tSTORE
tHHHD
tLZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to VCC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low
.
HSB driver is disabled
tDHSB
100 kOhm resistor,
Address #1 Address #6 Address #1 Address #6
Soft Sequence
Command
tSS tSS
CE
Address
VCC
tSA tCW
Soft Sequence
Command
tCW
Notes
49.This is the amount of time it takes to take action on a soft sequence command. VCC power must remai n HIGH to effectively register command.
50.Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
51.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
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Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations
Tabl e 2. Truth Table for × 8 Configuration
CE WE OE Inputs/Outputs[52] Mode Power
H X X High Z Deselect/Power-down Standby
L H L Data Out (DQ0–DQ7); Read Active
L H H High Z Output disabl ed Active
L L X Data in (DQ0–DQ7); Write Active
Tab le 3. Truth Table for × 16 Configuration
CE WE OE BHE[53] BLE[53] Inputs/Outputs[52] Mode Power
H X X X X High Z Deselect/Power-down Standby
L X X H H High Z Output disabled Active
L H L L L Data Out (DQ0–DQ15) Read Active
L H L H L Data Out (DQ0–DQ7);
DQ8–DQ15 in High Z Read Active
L H L L H Data Out (DQ8–DQ15);
DQ0–DQ7 in High Z Read Active
L H H L L High Z Output disabled Active
L H H H L High Z Output disabled Active
L H H L H High Z Outpu t disabled Active
L L X L L Data In (DQ0–DQ15) Write Active
L<