$6&017'$ December 2002 Advance Information 90[65$0ZLWK17'TM Features * Organization: 1,048,576 words x 18 bits * NTDTM1 architecture for efficient bus operation * Fast clock speeds to 250 MHz in LVTTL/LVCMOS * Fast clock to data access: 2.6/2.8/3/3.4 ns * Fast OE access time: 2.6/2.8/3/3.4 ns * Fully synchronous operation * Flow-through or pipelined mode * Asynchronous output enable control * Available in 100-pin TQFP and 165-ball BGA package * Byte write enables * Clock enable for operation hold * Multiple chip enables for easy expansion * 2.5V core power supply * Self-timed write cycles * Interleaved or linear burst modes * Snooze mode for standby operation 1. NTDTM is a trademark of Alliance Semiconductor Corporation. Logic block diagram $>@ ' $GGUHVV UHJLVWHU EXUVWORJLF 4 &/. ' 4 :ULWHGHOD\ DGGUUHJLVWHUV &( &( &( &/. 5: &RQWURO ORJLF %:D %:E &/. :ULWH%XIIHU $'9/' )7 /%2 == '4>DE@ &/. ' 0[ 65$0 DUUD\ 'DWD 4 LQSXW UHJLVWHU &/. &/. &(1 &/. 2( 2XWSXW UHJLVWHU 2( '4>DE@ Selection guide -250 -225 -200 -166 Units 4 4.4 5 6 ns Maximum pipelined clock frequency 250 225 200 166 MHz Maximum pipelined clock access time 2.6 2.8 3.0 3.4 ns Maximum operating current 425 400 370 340 mA Maximum standby current 110 110 110 90 mA Maximum CMOS standby current (DC) 70 70 70 70 mA Minimum cycle time Y $OOLDQFH6HPLFRQGXFWRU 3RI &RS\ULJKW$OOLDQFH6HPLFRQGXFWRU$OOULJKWVUHVHUYHG $6&017'$ Pin and ball assignment 165-ball BGA - top view A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 10 11 $ &( %:E 1& &( &(1 8 ADV/LD 9 1& $ $ $ 1& $ &( NC %:D &/. 5: 2( $ $ 1& 1& 1& 9''4 966 966 966 966 966 9''4 1& '43D 1& '4E 9''4 9'' 966 966 966 9'' 9''4 1& '4D 1& '4E 9''4 9'' 966 966 966 9'' 9''4 1& '4D 1& '4E 9''4 9'' 966 966 966 9'' 9''4 1& '4D 1& '4E 9''4 9'' 966 966 966 9'' 9''4 1& '4D )7 1& 1& 9'' 966 966 966 9'' 1& 1& == '4E 1& 9''4 9'' 966 966 966 9'' 9''4 '4D 1& '4E 1& 9''4 9'' 966 966 966 9'' 9''4 '4D 1& '4E 1& 9''4 9'' 966 966 966 9'' 9''4 '4D 1& '4E 1& 9''4 9'' 966 966 966 9'' 9''4 '4D 1& '43E 1& 9''4 966 1& 1& 1& 9''4 1& 1& 1& 1& $ $ 7', $ 966 7'2 $ $ $ 1& 706 $ 7&. $ $ $ $ /%2 1& $ $ 1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. 74)3[PP $ 1& 1& 9''4 9664 '4D '4D '4D '4D 9664 9''4 '4D '4D 966 1& 9'' == '4D '4D 9''4 9664 '4D '4D 1& 1& 9664 9''4 1& 1& 1& /%2 $ $ $ $ $ $ 1& 1& 966 9'' 1& 1& $ $ $ $ $ $ $ 9''4 9664 1& 1& '4E '4E 9664 9''4 '4E '4E )7 9'' 1& 966 '4E '4E 9''4 9664 '4E '4E '4E 1& 9664 9''4 1& 1& 1& 1& 1& 1& $ $ &( &( 1& 1& %:E %:D &( 9'' 966 &/. 5: &(1 2( $'9/' $ $ $ $ 100-pin TQFP - top view Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Functional description The AS7C251MNTD18A family is a high performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words x 18 bits and incorporates a LATE LATE Write. This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTDTM) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modifywrite operations. NTDTM devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flowthrough read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTDTM, write and read operations can be used in any order without producing dead bus cycles. Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write operations to be completed. Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C251MNTD18A operates with a 2.5V 5% power supply for the device core (VDD). These devices are available in a 100-pin TQFP package and 165 BGA Ball Grid Array package. Capacitance Parameter Symbol Signals Input capacitance CIN Address and control pins I/O capacitance CI/O I/O pins Test conditions Max Unit Vin = 0V 5 pF Vin = Vout = 0V 7 pF Burst order Interleaved burst order LBO = 1 Linear burst order LBO = 0 A1A0 A1A0 A1A0 A1A0 Starting address 0 0 0 1 1 0 1 1 First increment 0 1 0 0 1 1 Second increment 1 0 1 1 Third increment 1 1 1 0 Y A1A0 A1A0 A1A0 A1A0 Starting Address 0 0 0 1 1 0 1 1 1 0 First increment 0 1 1 0 1 1 0 0 0 0 0 1 Second increment 1 0 1 1 0 0 0 1 0 1 0 0 Third increment 1 1 0 0 0 1 1 0 $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Signal descriptions Signal I/O Properties Description Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock. CLK I CLOCK CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, CE2 I SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. ADV/LD I SYNC Advance or Load. When sampled high, the internal burst address counter will increment in the order defined by the LBO input value. (refer to table on page 2) When low, a new address is loaded. R/W I SYNC A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. BW[a,b] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO I STATIC Count mode. When driven high, count sequence follows Intel XOR convention. When driven low, count sequence follows linear convention. This input should be static when the device is in operation. FT I STATIC Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. TDO O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only) TDI I SYNC Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only) TMS I SYNC This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. (BGA only) TCK O SYNC Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only) ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connects. Absolute maximum ratings Parameter Symbol Min Max Unit VDD, VDDQ -0.3 +3.6 V Input voltage relative to GND (input pins) VIN -0.3 VDD + 0.3 V Input voltage relative to GND (I/O pins) VIN -0.3 VDDQ + 0.3 V Power dissipation PD - 1.8 W DC output current IOUT - 50 mA Storage temperature (plastic) Tstg -65 +150 o C +150 o C Power supply voltage relative to GND Temperature under bias (junction) Tbias -65 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Synchronous truth table CE0 CE1 CE2 ADV/LD R/W BW[a,b] OE CEN H X X L X X L X L X X H L H L L H L X X L NA L to H Deselect, high-Z X X X L NA L to H Deselect, high-Z L X X X L NA L to H Deselect, high-Z L H X X L External L to H Begin read L L L X L External L to H Begin write X L Burst counter L to H Burst2 X H Stall L to H Inhibit the CLK X X X H X X1 X X X X X X Address source CLK Operation 1 Should be low for burst write unless specific bytes need to be inhibited 2 Refer to state diagram below. Key: X = don't care, L = low, H = high State diagram for NTD SRAM 5HDG %XUVW 5HDG 5HDG HD 'VHO 'V 'VHO %XUVW HO LWH :U %XUVW :ULWH 'VHO : ULW H G :ULWH 'V HO 5H DG %XUVW 'VHO 5 :ULWH 5HDG :ULWH %XUVW 5HDG %XUVW :ULWH %XUVW Recommended operating conditions Parameter Supply voltage Address and control pins Input voltages I/O pins Ambient operating temperature Symbol Min Nominal Max VDD, VDDQ 2.35 2.5 2.65 GND 0.0 0.0 0.0 VIH 2.0 - VDD + 0.3 VIL -0.51 - 0.4 VIH 2.0 - VDDQ + 0.3 VIL -0.51 - 0.4 TA 0 - 70 Unit V V V C 1 VIL min = -2.0V for pulse width less than 0.2 x tRC. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ DC electrical characteristics for 2.5V I/O operation 250 Parameter Input leakage current 1 Output leakage current Operating power supply current Standby power supply current2 Output voltage 225 200 166 Sym Test conditions Min Max Min Max Min Max Min Max Unit | ILI | VDD = Max, Vin = GND to VDD - 2 - 2 - 2 - 2 A | ILO | OE VIH, VDD = Max, Vout = GND to VDD -1 1 -1 1 -1 1 -1 1 A ICC CE = VIL, CE = VIH, CE = VIL, f = fmax, Iout = 0 mA - 425 - 400 - 370 - 340 mA ISB Deselected, f = fmax - 110 - 110 - 110 - 90 ISB1 Deselected, f = 0, all VIN 0.2V or (VDD, VDDQ) - 0.2V - 70 - 70 - 70 - 70 ISB2 Deselected, f = fMax, ZZ (VDD, VDDQ) - 0.2V, all VIN VIL or VIH - 30 - 30 - 30 - 30 VOL IOL = 2 mA, VDDQ = 2.65V - 0.7 - 0.7 - 0.7 - 0.7 V VOH IOH = -2 mA, VDDQ = 2.35V 1.7 - 1.7 - 1.7 - 1.7 - V mA 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 2 LBO pin has an internal pull-up, and input leakage = 10 mA. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Timing characteristics over operating range 250 Parameter Sym Clock frequency 225 200 166 Max Min Max Min Max Unit 225 - 200 - 166 MHz 4.4 - 5 - 6 - ns - 6.9 - 7.5 - 8.5 - ns Min Max FMAX - 250 Cycle time (pipelined mode) tCYC 4 - Cycle time (flow-through mode) tCYCF 6.5 Min Notes1 Clock access time (pipelined mode) tCD - 2.6 - 2.8 - 3.0 - 3.4 ns Clock access time (flow-through mode) tCDF - 6.5 - 6.9 - 7.5 - 8.5 ns Output enable low to data valid tOE - 2.6 - 2.8 - 3.0 - 3.4 ns Clock high to output low Z tLZC 0 - 0 - 0 - 0 - ns 2, 3, 4 Data output invalid from clock high tOH 1.5 - 1.5 - 1.5 - 1.5 - ns 4 Output enable low to output low Z tLZOE 0 - 0 - 0 - 0 - ns 2, 3, 4 Output enable high to output high Z tHZOE - 2.6 - 2.8 - 3.0 - 3.4 ns 2, 3, 4 Clock high to output high Z tHZC - 2.6 - 2.8 - 3.0 - 3.4 ns 2, 3, 4 Clock high to output high Z tHZCN - 1.5 - 1.5 - 1.5 - 1.5 ns 5 Clock high pulse width tCH 1.5 - 1.8 - 1.8 - 1.8 - ns 8 Clock low pulse width tCL 1.5 - 1.8 - 1.8 - 2.2 - ns 8 Address and Control setup to clock high tAS 1.2 - 1.4 - 1.4 - 1.5 - ns 9 Data setup to clock high tDS 1.2 - 1.4 - 1.4 - 1.5 - ns 9 Write setup to clock high tWS 1.2 - 1.4 - 1.4 - 1.5 - ns 9 Chip select setup to clock high tCSS 1.2 - 1.4 - 1.4 - 1.5 - ns 9 Address hold from clock high tAH 0.3 - 0.4 - 0.4 - 0.5 - ns 9 Data hold from clock high tDH 0.3 - 0.4 - 0.4 - 0.5 - ns 9 Write hold from clock high tWH 0.3 - 0.4 - 0.4 - 0.5 - ns 9 Chip select hold from clock high tCSH 0.3 - 0.4 - 0.4 - 0.5 - ns 9 Clock enable setup to clock high tCENS 1.2 - 1.4 - 1.4 - 1.5 - ns 9 Clock enable hold from clock high tCENH 0.3 - 0.4 - 0.4 - 0.5 - ns 9 ADV setup to clock high tADVS 1.2 - 1.4 - 1.4 - 1.5 - ns 9 ADV hold from clock high tADVH 0.3 - 0.4 - 0.4 - 0.5 - ns 9 1 See "Notes" on page 17 Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ IEEE 1149.1 serial boundary scan (JTAG) The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG feature If the JTAG function is not being implemented, its pins/balls can be left unconnected. At power-up, the device will come up in a reset state which will not interfere with the operation of the device. TAP controller state diagram TAP controller block diagram 7(67 /2*,& 5817(67 ,'/( 6(/(&7 '56&$1 6(/(&7 ,56&$1 &$3785('5 7'2 ,GHQWLILFDWLRQ5HJLVWHU [ 6+,)7,5 6HOHFWLRQ &LUFXLWU\ ,QVWUXFWLRQ5HJLVWHU 6+,)7'5 %RXQGDU\6FDQ5HJLVWHU (;,7'5 (;,7,5 7&. 3$86('5 3$86(,5 (;,7'5 7$3&RQWUROOHU 706 [ IRU WKH [ FRQILJXUDWLRQ [ IRU WKH [ (;,7,5 83'$7('5 6HOHFWLRQ &LUFXLWU\ 7', &$3785(,5 %\SDVV5HJLVWHU 83'$7(,5 1RWH7KHRUQH[WWRHDFKVWDWHUHSUHVHQWVWKHYDOXHRI706DWWKHULVLQJHGJHRI7&. Test access port (TAP) Test clock (TCK) The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test mode select (TMS) The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Test data-in (TDI) The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See the TAP Controller Block Diagram.) Test data-out (TDO) The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP Controller State Diagram.) Performing a TAP RESET You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP registers Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK. Data is output on the TDO pin/ball on the falling edge of TCK. Instruction register You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO pins/ balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and also if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level series test data path. Bypass register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set low (Vss) when the BYPASS instruction is executed. Boundary scan register The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 70-bit-long register and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO. Identification (ID) register The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ TAP instruction set Eight different instructions are possible with the 3-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are reserved and should not be used. Note that the TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD. Instead, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins/balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction, which executes whenever the instruction register is loaded with all 0s, is not implemented in this SRAM TAP controller. The TAP controller, however, does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a high-Z state. EXTEST is a mandatory 1149.1 instruction. this device, therefore, is not compliant with 1149.1. IDCODE The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins/balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins/balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a high-Z state. SAMPLE/PRELOAD When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. Note that the SAMPLE/PRELOAD is a 1149.1 mandatory instruction, but the PRELOAD portion of this instruction is not implemented in this device. The TAP controller, therefore, is not fully 1149.1 compliant. Be aware that the TAP controller clock can operate only at a frequency up to 10 Mhz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output can undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is possible to capture all other signals and ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/ PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Reserved Do not use a reserved instruction.These instructions are not implemented but are reserved for future use. TAP timing diagram 7HVW&ORFN 7&. W7+7/ W7/7+ W7+7+ 7HVW0RGH6HOHFW 706 W097+ W7+0; 7HVW'DWD,Q 7', W7/29 W7/2; W'97+ W7+'; 7HVW'DWD2XW 7'2 'RQWFDUH 8QGHILQHG TAP AC electrical characteristics For notes 1 and 2, +10oC < TJ < +110oC and +2.4V < VDD < +2.6V. Description Symbol Min Max Units Clock cycle time tTHTH 100 Clock frequency fTF Clock high time tTHTL 40 ns Clock low time tTLTH 40 ns TCK low to TDO unknown tTLOX 0 ns TCK low to TDO valid tTLOV Clock ns 10 MHz Output Times 20 ns TDI valid to TCK high tDVTH 10 ns TCK high to TDI invalid tTHDX 10 ns tMVTH 10 ns 10 ns 10 ns 10 ns Setup Times TMS setup Capture setup 1 tCS Hold Times TMS hold Capture hold tTHMX tCH 1 1 tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2 Test conditions are specified using the load in the figure TAP AC output load equivalent. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ TAP AC test conditions TAP AC output load equivalent 9 Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V Input rise and fall times. . . . . . . . . . . . . . . 1 ns Input timing reference levels. . . . . . . . . . 1.25V 7'2 Output reference levels . . . . . . . . . . . . . . 1.25V S) =2 Test load termination supply voltage. . . . 1.25V TAP DC electrical characteristics and operating conditions (+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted) Description Conditions Symbol Min Max Units Notes Input high (logic 1) voltage VIH 1.7 VDD + 0.3 V 1, 2 Input low (logic 0) voltage VIL -0.3 0.7 V 1, 2 0V VIN VDD ILI -5.0 5.0 A Outputs disabled, 0V VIN VDDQ(DQx) ILO -5.0 5.0 A Output low voltage IOLC = 100A VOL1 0.2 V 1 Output low voltage IOLT = 2mA VOL2 0.7 V 1 Output high voltage IOHS = -100A VOH1 2.1 V 1 Output high voltage IOHT = -2mA VOH2 1.7 V 1 Input leakage current Output leakage current 1. All voltage referenced to VSS(GND). 2. Overshoot: VIH(AC) VDD + 1.5V for t tKHKH/2 Undershoot: VIL(AC) -0.5 for t tKHKH/2 Power-up: VIH +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than tKHKL(Min) or operate at frequencies exceeding fKF(Max). Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Identification register definitions Instruction field 1M x 18 Description Revision number (31:28) xxxx Reserved for version number. Device depth (27:23) xxxxx Defines the depth of 1Mb words. Device width (22:18) xxxxx Defines the width of x18 bits. Device ID (17:12) xxxxxx Reserved for future use. JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor. ID register presence indicator (0) 1 Indicates the presence of an ID register. Scan register sizes Register name Bit size Instruction 3 Bypass 1 ID 32 Boundary scan x18:51 x36:70 Instruction codes Instruction Code EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to high-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high-Z state. Reserved 011 Do not use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. Reserved 101 Do not use. This instruction is reserved for future use. Reserved 110 Do not use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Y Description $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ 165-ball BGA boundary scan order (x18) Bit #s Signal Name Ball ID Bit #s 1 SA 8P 2 SA 9R 3 SA 4 Signal Name Ball ID 28 CE2 6A 29 BWa 5B 9P 30 BWb 4A SA 10R 31 CE1 3B 5 SA 10P 32 CE0 3A 6 SA 11R 33 SA 2A 7 SA 8R 34 SA 2B 8 DQa 10M 35 DQb 2D 9 DQa 10L 36 DQb 2E 10 DQa 10K 37 DQb 2F 11 DQa 10J 38 DQb 2G 12 ZZ 11H 39 FT 1H 13 DQa 11G 40 DQb 1J 14 DQa 11F 41 DQb 1K 15 DQa 11E 42 DQb 1L 16 DQa 11D 43 DQb 1M 17 DQPa 11C 44 DQPb 1N 18 SA 11A 45 LB0 1R 19 SA 10B 46 SA 3P 20 SA 10A 47 SA 3R 21 SA 9A 48 SA 4P 22 SA 9B 49 SA 4R 23 ADV/LD 8A 50 SA1 6P 6R 24 OE 8B 51 SA0 25 CEN 7A 52 - 26 R/W 7B 53 - 27 CLK 6B Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Key to switching waveforms 5LVLQJLQSXW )DOOLQJLQSXW 8QGHILQHGGRQW FDUH Timing waveform of read/write cycle W&+ W&<& W&/ &/. W&(16 W&(1+ &(1 &( W&6+ W&66 &(&( W$'9+ W$'96 $'9/' W:6 W:+ 5: W:6 W:+ %:Q W$6 W$+ $''5(66 $ $ $ $ $ W'6 '$ '$ W2( W/=& 4$ '$e $ W+=& W&' W'+ '4 SLSHOLQHG $ 4$ 4$e '$ 4$ 4$ 4$ W2+ W+=2( W/=2( 2( '4 IORZWKURXJK &RPPDQG WRITE D(A1) '$ :5,7( '$ '$ %8567 :5,7( '$e '$e 5($' 4$ 4$ 5($' 4$ 4$ %8567 5($' 4$e 4$e :5,7( '$ '$ 5($' 4$ :5,7( '$ '6(/ 1RWHe ;25ZKHQ/%2 KLJK1R&RQQHFWe $''ZKHQ/%2 ORZ%:>DE@LVGRQWFDUH Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ NOP, stall and deselect cycles &/. &(1 &( &(&( $'9/' 5: %:Q $''5(66 $ $ 4$ '4 SLSHOLQHG '4 IORZWKURXJK &RPPDQG 5($' 4$ 4$ 4$e %8567 67$// 4$e 4$e '$ 4$e 4$e %8567 '6(/ 4$e $ '$ %8567 '6(/ :5,7( '$ %8567 %8567 :5,7( 123 '$e 123 '$ '$e 1RWHe ;25ZKHQ/%2 KLJK1R&RQQHFWe $''ZKHQ/%2 ORZ2(LVORZ Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ AC test conditions * Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. * Input pulse level: GND to 3V. See Figure A. 7KHYHQLQHTXLYDOHQW * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. * Input and output timing reference levels: 1.5V. +9 *1' '287 9 = S) )LJXUH$,QSXWZDYHIRUP 50 9/ 9''4 )LJXUH%2XWSXWORDG$ DOUT S) *1' LQFOXGLQJVFRSH DQGMLJFDSDFLWDQFH )LJXUH&2XWSXWORDG% Notes: 1) For test conditions, see "AC test conditions", Figures A, B, C 2) This parameter measured with output load condition in Figure C. 3) This parameter is sampled, but not 100% tested. 4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage. 5) tCH measured high above VIH and tCL measured as low below VIL 6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. 7) Write refers to R/W and BW[a,b]. 8) Chip select refers to CE0, CE1, and CE2. Y $OOLDQFH6HPLFRQGXFWRU 3RI $6&017'$ Package dimensions 100-pin quad flat pack (TQFP) +G ' TQFP Min Max 0.05 0.15 1.35 1.45 0.22 0.38 0.09 0.20 13.90 14.10 19.90 20.10 0.65 nominal 15.90 16.10 21.90 22.10 0.45 0.75 1.00 nominal 0 7 A1 A2 b c D E e Hd He L L1 E H +H ( Dimensions in millimeters F / $ $ / 165-ball BGA (ball grid array) $FRUQHULQGH[DUHD ) = * = ) $ + 6LGH9LHZ Y ' & , % 0$; + $ % & ' ( ) * + . / 0 1 3 5 $ * ( & ' 0D[ % $ 7\S %RWWRP9LHZ $ % & ' ( ) * + . / 0 1 3 5 $OOPHDVXUHPHQWVDUHLQPP 0LQ 7RS9LHZ $OOLDQFH6HPLFRQGXFWRU ( ' , ; 0 = ; < 0 = 'HWDLORI6ROGHU%DOO 3RI $6&017'$ Ordering information Package &Width -250 MHz TQFP x18 AS7C251MNTD18A250TQC BGA x18 AS7C251MNTD18A250BC -225 MHz -200 MHz -166 MHz AS7C251MNTD18A225TQC AS7C251MNTD18A200TQC AS7C251MNTD18A166TQC AS7C251MNTD18AA225TQI AS7C251MNTD18A200TQI AS7C251MNTD18A166TQI AS7C251MNTD18A225BC AS7C251MNTD18A200BC AS7C251MNTD18A166BC AS7C251MNTD18A225BI AS7C251MNTD18A200BI AS7C251MNTD18A166BI Part numbering guide AS7C 25 1M NTD 18 A -XXX TQ or B C/I 1 2 3 4 5 6 7 8 9 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 25 = 2.5V 3. Organization: 1M 4. NTDTM = No Turn-Around Delay. Pipelined/flow-through mode (each device works in both modes) 5. Organization: 18 = x 18 6. Production version: A = first production version 7. Clock speed (MHz) 8. Package type: TQ = TQFP; B = BGA 9. Operating temperature: C = commercial (0 C to 70 C); I = industrial (-40 C to 85 C) Y $OOLDQFH6HPLFRQGXFWRU 3RI (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.