OBSOLETE 100302 www.ti.com SNOS119B - AUGUST 1998 - REVISED APRIL 2013 100302 Low Power Quint 2-Input OR/NOR Gate Check for Samples: 100302 FEATURES DESCRIPTION * * * * The 100302 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k pulldown resistors and all outputs are buffered. 1 2 * 43% Power Reduction of the 100102 2000V ESD Protection Pin/Function Compatible with 100102 Voltage Compensated Operating Range = -4.2V to -5.7V Standard Microcircuit Drawing - (SMD) 5962-9152802 Table 1. Pin Descriptions Logic Symbol Pin Names Description Dna-Dne Data Inputs E Enable Input Oa-Oe Data Outputs Oa-Oe Complementary Data Outputs TRUTH TABLE (1) (1) D1X D2X L L L L L H E OX OX L L H H H L L H L L H H H L H L L H L H L H H L H H L H L H H H H L H = HIGH Voltage Level L = LOW Voltage Level 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1998-2013, Texas Instruments Incorporated OBSOLETE 100302 SNOS119B - AUGUST 1998 - REVISED APRIL 2013 www.ti.com Connection Diagram Figure 1. 24-Pin CERDIP 2 Figure 2. 24-Pin CPGA See NAQ0024C Package Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 100302 OBSOLETE 100302 www.ti.com SNOS119B - AUGUST 1998 - REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Above which the useful life may be impaired -65C to +150C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic +175C -7.0V to +0.5V VEE Pin Potential to Ground Pin Input Voltage (DC) VEE to +0.5V -50 mA Output Current (DC Output HIGH) ESD (1) (2) (3) (3) 2000V Absolute Maximum Ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. ESD testing conforms to MIL-STD-883, Method 3015. RECOMMENDED OPERATING CONDITIONS Case Temperature (TC) -55C to +125C Military -5.7V to -4.2V Supply Voltage (VEE) DC ELECTRICAL CHARACTERISTICS - MILITARY VERSION VEE = -4.2V to -5.7V, VCC = VCCA = GND, TC = -55C to +125C Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage VOHC Output HIGH Voltage VOLC Output LOW Voltage (1) Min Max Units TC -1025 -870 mV 0C to +125C -1085 -870 mV -55C -1830 -1620 mV 0C to +125C -1830 -1555 mV -55C -1035 mV 0C to +125C -1085 mV -55C -1610 mV 0C to +125C -1555 mV -55C Conditions Notes VIN = VIH(Max) or VIL (Min) Loading with 50 to -2.0V See (1) (2) (3) VIN = VIH(Max) or VIL (Min) Loading with 50 to -2.0V See (1) (2) (3) See (1) (2) (3) (4) See (1) (2) (3) (4) VIH Input HIGH Voltage -1165 -870 mV -55C to +125C Ensured HIGH Signal for All Inputs VIL Input LOW Voltage -1830 -1475 mV -55C to +125C Ensured LOW Signal for All Inputs IIL Input LOW Current A -55C to +125C VEE = -4.2V VIN = VIH (Max) See (2) (3) (1) IIH Input HIGH Current 240 A 0C to +125C VEE = -5.7V See (1) (2) (3) 340 A -55C VIN = VIL(Min) -17 mA -55C to +125C Inputs Open See (1) (2) (3) (4) IEE (1) (2) (3) (4) Power Supply Current 0.50 -48 Sample tested (Method 5005, Table I) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8. F100K 300 Series cold temperature testing is performed by temperature soaking (to ensure junction temperature equals -55C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8. Ensured by applying specified input condition and testing VOH/VOL. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 100302 3 OBSOLETE 100302 SNOS119B - AUGUST 1998 - REVISED APRIL 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.7V, VCC = VCCA = GND Symbol Parameter TC = -55C TC = +25C TC = +125C Min Max Min Max Min Max Units tPLH tPHL Propagation Delay Data to Output 0.30 1.80 0.40 1.50 0.40 1.70 ns tPLH tPHL Propagation Delay Enable to Output 0.60 2.60 0.80 2.30 0.80 2.80 ns tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.30 1.20 0.30 1.20 0.30 1.20 ns (1) (2) (3) (4) (5) Conditions Notes See (1) (2) (3) (4) (5) See Figure 3 and Figure 4 See (4) F100K 300 Series cold temperature testing is performed by temperature soaking (to ensure junction temperature equals -55C), then testing immediately after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures. Screen tested 100% on each device at +25C temperature only, Subgroup A9. Sample tested (Method 5005, Table I) on each manufactured lot at +25C, Subgroup A9, and at +125C and -55C temperatures, Subgroups A10 and A11. Not tested at +25C, +125C, and -55C temperature (design characterization data). The propagation delay specified is for single output switching. Delays may vary up to 100 ps with multiple outputs switching. TEST CIRCUITRY VCC, VCCA = +2V, VEE = -2.5V L1 and L2 = equal length 50 impedance lines RT = 50 terminator internal to scope Decoupling 0.1 F from GND to VCC and VEE All unused outputs are loaded with 50 to GND CL = Fixture and stray capacitance 3 pF Figure 3. AC Test Circuit 4 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 100302 OBSOLETE 100302 www.ti.com SNOS119B - AUGUST 1998 - REVISED APRIL 2013 Switching Waveforms Figure 4. Propagation Delay and Transition Times Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 100302 5 OBSOLETE 100302 SNOS119B - AUGUST 1998 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B * 6 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 5 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 100302 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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