65540 / 545 High Performance Flat Panel / CRT VGA Controller Highly integrated design (flat panel / CRT VGA controller, RAMDAC, clock synthesizer) Multiple Bus Architecture Integrated Interface Local Bus (32-bit CPU Direct and VL) EISAASA (PC/AT) 16-bit Bus * PCI Bus (65545) Flexible display memory configurations * One 256Kx16DRAM (512KB) Four 256Kx4 DRAMs = (512KB) * Two 256Kx16DRAMs (1MB) Advanced frame buffer architecture uses available display memory, maximizing integration and minimizing chip count Integrated programmable linear address feature accelerates GUI performance Hardware windows acceleration (65545) * 32-bit graphics engine - System-to-screen and screen-to-screen BitBLT - 3 operand ROP's - Color expansion - Optimized for Windows BitBLT format * Hardware line drawing 64x64x2 hardware cursor Hardware pop-up icon (65545) * 64x64 Pixels by 4 colors * 128x128 pixels by 2 colors High performance resulting from zero wait-state writes (write buffer) and minimum _ wait-state reads (internal asynchronous FIFO design) Mixed 3.3V +0.3V /5.0V +10% Operation Interface to CHIPS' PC Video to display live video on flat panel displays Supports panel resolutions up to 1280 x 1024 resolution including 800x600 and 1024x768 Supports non-interlaced CRT monitors with resolutions up to 1024 x 768 / 256 colors True-color and Hi-color display capability with flat panels and CRT monitors up to 640x480 resolution Direct interface to Color and Monochrome Dual Drive (DD) and Single Drive (SS) panels (supports 8, 9, 12, 15, 16, 18 and 24-bit data interfaces) Advanced power management features minimize power consumption during: * Normal operation * Standb (Sleep) modes * Panel-Off Power-Saving Mode Flexible on-board Activity Timer facilitates ordered shut-down of the display system Power Sequencing control outputs regulate application of Bias voltage, +5V to the panel and +12 V to the inverter for backlight operation SMARTMAP intelligent color to gray scale conversion enhances text legibility Text enhancement feature improves white text contrast on flat panel displays Fully Compatible with IBM VGA EJAJ-standard 208-pin plastic flat pack Address RGB _ To CRT Be Dat 65540 H/V Syne-_ Display ata or 32-bit 386/486 Panel Control _ To Flat cru Direct oe [Control 65545 Panel Data+__+_ pane Bus, or 16-bit ISA {__14.31818 MHz 32 16/24 24 pey System Bus Optional 512KByte or PCVideo IMByte Video Multi-Media Memory Interface System Diagram Revision 1.2 65540 / 545 Mz 2096116 OOL17e9 436Revision 1.1 1.2 Date 9/94 1195 By DH BB/MP Revision History Revision History Comment Added note: Refer to Electrical Specs for maximum clock frequencies in Supported Video Modes' table Added note: Not all above resolutions can be supported at 3.3V and/or 5V Changed Mode 50 in Supported Video Modes-Extended Resolution Table from 16 to 16M Reset column in Reset/Setup/Test/Standby/Panel-Off Mode table was incorrect. Now reads: "RESET#/Low/+//High/High" Changed note for Pin List-Bus Interface: from "Drive=5V low drive and 3V high drive to "IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C)" Changed pin description: pin 25 LDEV# pin type "Out/OC" to "Out Changed Config Reg XRO1 bits 2-1 VL-Bus description for pin 23=CRESET should read pin 23=RDYRTN# Changed Ext Reg XR2D and XR2E to (CMPR Enabled) and (CMPR Disabled) and added note: "For DD panels without frame acceleration, the programmed value should be doubled Updated tables for "No FRC" and "2-Frame FRC" Updated Flat Panel Timing "CD: 010 should read "CD: 001 Updated Programming: FLM delay programmed in XR2C should be equal to: CRT blank time FLM front porch FLM width XR2D LP Delay (CMPR enabled) & XR2E LP Delay (CMPR disabled) Added note: "Can use external 14.31818 MHz oscillator into XTALI (203) with XTALO (204) as no connect Updated Elec Specs: changed "Max" under "Normal Operating Conditions" from 90 to 100; "memory clock is assumed to be 68 MHz not 65 MHz;" and "VL-Bus timing is compatible with VL-Bus Specification 2.0" Added timing for VL-Bus LDEV#, 14.31818 MHz, DRAM R/M/W and PC-Video and modified timing for PCI Bus Frame Clarified function of ACTI output. Updated Supported Video Modes table Updated I/O Map section Added 64310 to CHIPS VGA Product Family in Register Summary Updated Extension Registers table Updated XR33, XR6C, XR6F in the Extension Registers section Added Rset formula to CRT Panel Interface Circuit Updated Interface-Optrex DMF-5035 INC-FW (640x480 Color STN-DD) LCD Panel Interface example Updated 65540/545 DC Characteristics in timing section Updated Local Bus Input Setup & Hold, Local Bus Output Valid, Local Bus Output Float Delay, VL-Bus LDEV#, CRT Output, Panel Output Timing diagrams Added 65545B2 specifications Revision 1.2 2 65540 / 545 MM 20946116 00317350 556Table of Contents Table of Contents Section Page Section Page Introduction / OVErview .......c.ccccccssesseseescesaes 7 Pinouts (65540)......ccsccscesesessereeessseseeeeseeeneanens 23 Minimum Chip Count / Board Space .......- 8 Pinouts (65545) pacseerensaeccasecncaececseccsccssceseestaneees 24 Display Memory Interface..................s Pin Diagram (65540)........sscssesseeeseeeeeceeees 23 CPU Bus Interface...............0. 10 Pin Diagram (65545) ......cscccssessssereersereeres 24 High Performance Features 10 Pin LiSts .......sesssccssceessssorsevsevsavsecosessnssesoesones 25 65545 Acceleration... ceecccescsetseeeeeeseees 10 Pin Descriptions - ISA/VL-Bus Interface..... 31 65545 Hardware Cursot.........cccccsccsessceerseees 10 Pin Descriptions - PCI Bus Interface PC Video / Overlay Suppott..............c.cce 10 (65545 OMY)... seecsssssessssseessssesseteneteasnens 34 Display Interface... cee ceseeeeeseeeeeseees 11 Pin Descriptions - Display Memory............ 37 lat Panel DisplayS...........eccssssresesseeeee 11 Pin Descriptions - Flat Panel Interface........ 39 Panel Power Sequencing ............scseeeeeeeeees 11 Pin Descriptions - CRT and Clock Interface 40 CRT DisplayS ............:ccescceeeceecceeeseeeeteeeeee 11 Pin Descriptions - Power / Gnd / Standby... 42 Simultaneous Flat Panel / CRT Display.. 14 . . Display Enhancement Features ..................- 14 Register and Port Address Summaries "True-Gray" Gray Scale Algorithm......... 14 VO Map RGB Color to Gray Scale Reduction...... 14 CGA, MDA, and Hercules Registers........... 44 SmartMap ooo. eeeeseceseeseceecesseeeseees 14 ; EGA Registers .........cececcesesessessesnseneeeeeeeenes 44 Text Enhancement..............:cssseeseeseesneee 15 : . . : VGA ReSiSters......... cc secesesesscescereseaserteereee 44 Vertical and Horizontal Compensation... 15 VGA Indexed Resisters 45 Advanced Power Management.............0000 16 Extension Re isters aires 46 Normal Operating Mode wr 16 32-Bit Registers (65543). 49 P anel Off Mod e PETAMOT s-sseseeseeseee 16 PCI Configuration Registers (65545).......... 50 Standby Mode ..0........esescessessecssseesereees 16 : as CRT Power Management (DPMS) 46 Register Descriptions ............. ce seececeeeeseereeees 51 CPU Activity Indicator / Timer............0006 17 Global Control (Setup) Registers ................ 53 Pull Compatibility biseeeesnessseascesaeeesesnesssnsseaees 17 PCI Configuration Registers.................2.006 55 Write Protection ose eeeteeeeeeeeeeeeeenee 17 General Control & Status Registers............. 59 Extension Registers ...............:seseseeseeeee 17 CGA / Hercules Registers... erseseeees 61 Panel Interface Registers.............csceeeee 17 Sequencer REQIStETS........ ce eecesscesserseseereeeseees 63 Alternate Panel Timing Registers ........... 17 CRT Controller Registers .............:::seeeeeee 67 Context Switching... eee eeceeeeeeeeeee 17 Graphics Controller Registers ..............-.++ 81 Reset, Setup, and Test Modes...............20. 18 Attribute Controller an Reset Mode... eeecessescesessesesesceseresenes 18 VGA Color Palette Registers 0.0.0.0... 89 Setup Mode woo... cece cesses eeaneaenaes 18 Extension Registers .00...0..cccccccssessesseseseneeees 95 Tri-State Mode ...........cccccssecseseccscsceeeeeeees 18 32-Bit Registers (65545 only) .........-.ceeeee 155 ICT (In-Circuit-Test) Mode ............c cee 18 Chip APChiteCture ..... ccc ees cesseesestesseeseeseeseee 19 CQUCNCEL 0... eee ceeeeeeeeeeeeeeeeeenecetesenneesees 19 CRT Controler..... cece eseseeeeereeveree 19 Graphics Controller........scceseeserssesseeeees 19 Attribute Controller... eee eee 19 VGA / Color Palette DAC... ee 19 Clock Synthesizers 0.0.0... eeeeeeeseeeeeeee 20 Configuration Inputs...... . 21 Virtual Switch Register... eee eeeeeeeeeeee 21 Light Pen Registers...............teeeeeeeeeeeeeees 21 BIOS ROM Interface... cece ceeeeseeeeeees 21 Package...u......esesccsssessoneenecrsccecceasessensensenseens 21 Application Schematics 0.0.0.0... seeeeseeres 22 Revision 1.2 3 65540 / 545 Mz 2098116 0011731 454atSth3e GE EE Getiesttiiz LA i r> Table of Contents Table of Contents Section Page Section Page Functional Description ............:::sccscesesesseneens 165 Programming and Parameters ...........:cseceeees 195 System Interface ...........ccccscsssssesessseseesrees 165 General Programming Hints................00008 195 Functional Blocks ............ccccceccessecssseesees 165 Parameters for Initial Boot ..............cccceseeeee 197 Bus Interface ............cccceccssseereereesseronvees 165 Parameters for Emulation Modes ................ 198 TSA Interface .....ccccscssscsssssessssncseees 165 Parameters for Monochrome LCD Panels VL-Bus Interface ...........cccseceeeeeeeee 165 (Panel Mode Onlly)...........c:ccccsccessssceseeees 199 Direct Processor Interface .............00. 165 Parameters for Monochrome LCD Panels PCI Interface ooo... ccc ceccccccssecsseeeeeeees 165 (Simultaneous Mode Display)................. 200 Di Parameters for Color TFT Panels isplay Memory Interface .......----ssssseessseee 166 (Panel Mode Only)........ssssssssssessssssssesseen 201 Memory Arc itecture seeeesennscneescceseesccseees 108 Parameters for Color TET Panels emory Chip Requirements ............+.00+. (Simultaneous Mode Display)................+ 202 Clock Synthesizer ....... MCLK Operation ... Parameters for Color STN SS Panels (Panel & Simultaneous Mode Display)... 203 VCLK Operation .....cccccccssssssesssseeessseeeees Parameters for Color SIN SS Panels Programming the Clock Synthesizer . 168 (Extended 4-bit Pack)..............ccccssccseeseee 204 Programming Constraints ................ 168 Parameters for Color STN DD Panels Programming Example ...........:0000+ 169 (Panel & Simultaneous Mode Display)... 205 PCB Layout Considerations ..............00. 169 Parameters for Plasma Panels................0006 206 VGA Color Palette DAC 170 Parameters for EL Panels ............::sscssceeceees 207 BitBLT Engine (65545 only) .......esesseseeee 171 Application Schematics......cccsccsssseesseecenses 209 Bit Block Transfer .......sssssssssssesserssetsssees 171 System Bus Interface............ccssesseeseseeeseeees 210 Sample Screen-to-Screen Transfer ......... 172 L-Bus / 486 CPU Local Bus Interface...... 11 Compressed Screen-to-Screen Transfer . 173 PCI Local Bus Interface ............cccccccceceees 212 System-to-Screen BitBLTs Dis lay Memory / PC Video Interface........ 213 Hardware Cursor (65545 only) . CRT / Panel Interface ............ecccsceesesseeeeeee 214 ProgramMing ..........scsccessesseescssssssessesreees ursor Data Array Format & Layout 177 Panel Interface Examples ..........ccseeesseeseseseeee 215 Display Mem Base Addr Formation . 178 . Loe gs VGA Controller Programming .......... 178 Electrical Specifications... sseeseeeeeeeee 241 Copying Cursor Data to Disp Mem... 178 Absolute Maximum Conditions.................. 241 Setting Position, Type, & Base Addr 178 Normal Operating Conditions ..........0..000+ 241 . DAC Characteristics ............c:cccsccsssneserreees 241 Flat Panel Timing... eee eeeeeeeeeeneneeeeeees 179 DC Characteristics... ebb bub beeeeseseeseeeeceeecese 242 OVELVICW occ cesecsccesesseveccsacsecenassesensesnsacesees 179 TIVE CNaLACterIStiCs......-eeeesereeeeeseees Panel Size 179 AC Test Conditions .......esssceceesessesseesseessnees 243 Panel] Type ........cccssccscsscsecsesessessseeseessesssseevee 179 AC Characteristics TFT Panel Data Width........scecsssssssssesseseees 179 Reference Clock Timing .......-....-ssssseeesoe 243 Display Quality Settings... cesses 180 Clock Generator Timing.............--- 244 rame Rate Control (FRC) ceeeccecevecevensvarce 180 Reset Timing Pee new ren reer eneem reser eens eee enesereeees 245 Dithe......ssseeseeseccsseessereccensecenseessneesssnssee 180 Bus TUming...ersesseseescsscsssseeseeensssecescnneneee 246 M Signal Timing w..cececccsscsccseccecsseee 180 DRAM Timing ..........cceesececssesseeeseeeeneeres 254 Gray / Color Levels ...........cccecseseseseeeeees 180 CRT Output Timing ........--eseseseeereens 258 Pixels Per Shift Clock................ .. 181 PC Video Timing ........c.cscssssessesessesesesees 258 Color SIN Pixel Packing ... . 182 Panel Output Timing 000 eeeeeneee 259 tput iming...... TP Signal Timing. wee ... 183 Mechanical Specifications..........ccseesseeneeee 261 FLM Output Signal Timing.......... .. 183 i . i i Blank# IDE Output Signal Timing 133 Plastic 208-PFP Package Dimensions......... 261 Shift Clock Output Signal Timing .......... 183 Pixel Timing Sequence Diagrams............... 183 Revision 1.2 65540 / 545 MH 20594116 0011732 320List of Tables List of Tables Table Page Table Page Feature Differences ..0...........::.sseeceeseseceeeereseee 7 Parameters - Initial Boot 0.0... ee eeeeeeeeeeeee 197 Display Capabilities 000.0... tect eeetseseseeee 9 Parameters - Emulation Modes.............:ese0 198 Supported Video Modes - VGA...............02 12 Parameters - Monochrome LCD-DD Supported Video Modes - Extended............... 13 Panel Mode Only ou... cc essessessessersesseseenoenee 199 Supported Video Modes - High Refresh......... 13 Simultaneous Mode Display.............eeeeeeee 200 Vcc Pin to Interface Pin Correspondence... 16 Parameters - Color TFT LCD Reset/Setup/Test/Standby/Panel-Off Modes... 18 Panel Mode Only .....0.........csecessessesseseeesasnaes 201 Configuration Pin Summiary..........00. eee 21 Simultaneous Mode Display...........0..00000 202 Pin Li 25 Parameters - Color STN-SS LCD in 1st seesteesaceeaneanscscnreneeersssneseatesseensaseeneenenses Panel & Simultaneous Mode Display voeeceeece 203 Pin Descriptions .............-cseccessessersercereeeseneeees 31 Parameters - Color STN-DD LCD Standby Mode Panel Output Signal Status ..... 41 Sn aertace E nite FAY DIE PACK sesereenee sos Standby Mode Memory Output Signal Status. 41 Parameters - Monochrome Plasma. ccsccsseeee se 206 vOMe Bus Output Signal Status........ io Parameters - Monochrome EL ..........sscssseseee 207 Recister Summary - Be Megs Here Modes id Panel Interface Examples Summary ............... 215 Register Summary - VGA Mode................. 4A DK Board Connector Summary .............cc00 216 peeister qummary ~ pdexed Register Serseeserses ig Absolute Maximum Conditions ........ eee 241 egister summary - Extension Kegisters....... Normal Operating Conditions .0....0. ccc 241 Register Summary - 32-Bit Registers (65545) 49 DAC Characteristics 241 Register Summary - PCI Confg Regs (65545) 50 STISLICS soessesseessssssessenvenssessessecens DC Characteristics ...........ccccsseescesccsseeeeeeseees 242 Register List - Setup Registers................-.200+ 53 DC Drive Characteristics sosavsansecseccascceescrseseens 242 Register List - PCI Configuration .............0. 55 AC Test Conditions siseasensneensseneeesneeneennssnaeenes 243 Register List - General Control & Status........ 59 AC Timing Characteristics 0000.0... esecsereee 243 Register List - CGA / Hercules Registers vecaeee 6l Reference ClOck .........cccccccceeseesccesssneccesnesnee 243 Register List - Sequencer ................:eececeseeeeeee 63 Clock Generatot...........cccecesceeescereesreeeeeeeees 244 Register List - CRT Controller................0.00cee- 67 ReSet ww. eeeceeseneeeeseeneaee 245 Register List - Graphics Controller ...............66 81 Local Bus CIOcK ...........:ccsssscssssceseneereeneesteees 246 Register List - Attribute Controller Local Bus Input Setup & Hold... 247 and VGA Color Palette.......ccccssscssesesssrees 89 Local Bus Output Valid... eee 248 Register List - Extension Registers.................. 95 Local Bus Float Delay .............:eesseseereereee 248 Register List - 32-Bit Registers (65545)......... 155 VI-Bus LDEV# oo. ccececcccceesceesneeceeeeeneeeee 249 PCI Bus Frame.........csesscesscssssserscenevsesseseass 250 DRAM Speed vs. Memory Clock Frequency. 166 PCI Bus Stop ...eeeeceeceescesceeeeececceseeeneeneee 252 USA. BUS.........ceeccesscesccseeceseceesesenseceereeseareeees 253 DRAM Read / Write........cccccccsceessseseeereenes 254 DRAM Read / Modify / Write.............::00 256 DRAM CBR-Refresh ...00.......ecceceeseeeseeeeee 257 DRAM Self-Refresh 00.0... ceescsesscssesseeeeees 257 CRT Output 20 eee eeeeeeeeeceeeeecereasesnenees 258 PC VideO oo.eeecccccsessccteesssscsecsecesessseteseeeentens 258 Panel Output 2.000 ee eeceeeeeeereenensesreere 259 Revision 1.2 65540 / 545 M@ 2094116 0011733 2b?QEneees Geos seenee sense > LAr Ss List of Figures List of Figures Figure Page Figure Page System Diagram............scsescssssssssssenseesssnsenes 1 Flat Panel Interface Schematics Panel Power Sequencing.............ceeeseeeeeeeeee 11 16. : Color Palette / DAC Block Diagram............... 19 masa: Shan ie shita S804 were a Clock Synthesizer Register Structure.............. a . Mono DD - Epson EG9005F-LS.................5 219 Pinouts (65540) ooo. eeecccstcccsesseseecsncrsenerceseseesenee 23 Mono DD - Citizen G6481L-FF.................. 220 Pinouts (G5545) ..cccceetccssssccsessceeessscenceeessneaecs 24 Mono DD - Sharp LM64P80......s...scsseeeee 92] Pin List sssstessescensenecnssnesnessenssesesosnsenasoessnoeseesenees 25 Mono DD - Sanyo LCM6494-24NTK......... 222 Pin Descriptions ..........:ceescesceeeccceneeeeeteneceneeeee 26 Mono DD - Hitachi LMG5364XUEC......... 923 Fn Destin SD Sere ee a ae Clock Synthesizer Register Structure.......... 167 Le FACE AR Clock Synthesizer PLL Block Diagram...... 167 Color TET - Hitachi TM26D50VC2AA...... 226 Clock Filter Circuit...cccssssssssssssssuesssssesensn 169 Color TET - Sharp LQODOM 1 sss ssessseee 227 Clock Power / Ground Layout Example...... 169 Color TET - Toshiba LTM-09CO15-1......... 228 VGA Color Palette DAC Data Flow.......... 170 Color TFT - Sharp LQ1OD3 11 .........eseseee 229 Possible BitBLT Orientations With Overlap 171 Color TFT - Sharp LQIODX01 ............ 230 Screen-to-Screen BitBLT 0... cece 172 Color STN SS - Sanyo LM-CK53-22NEZ.. 231 BitBLT Data Transfer.............:.ccsccssseeeseeeees 173 Color STN SS - Sanyo LCM5327-24NAK. 232 Differential Pitch BitBLT Data Transfer...... 174 Color STN SS - Sharp LM64C031.............. 233 Flat Panel Timing Color STN DD - Kyocera KCL6448........... 234 Monochrome 16 Gray-Level EL .............+ 184 er orn pp . Ree erret er cian a3 Monochrome LCD DD 8-bit Interface ....... 185 Color STN DD . SanvoLCMS5331.09NTE 237 Monochrome LCD DD 16-bit Interface ..... 186 Color STN DD - Hit Ohi LMG9721XUFC. 238 Color LCD TFT 9/12/16-bit Interface ........ 187 Color STN DD - Tosh. TLX-80628-C3X .. 239 Color LCD TFT 18/24-bit Interface ........... 188 Color STN DD - Opt DME-50351NC_FW.. 240 Color LCD STN 8-bit Interface ...........-.+-- 189 er uP - Color LCD STN 16-bit Interface ................ 190 Electrical Specifications Color LCD STN-DD 8-bit Interface Reference Clock Timing...........ccccccccsseeees 243 (with Frame Acceleration)........-..-++ 191 Clock Generator Timing .........ccccccscseseseseseees 244 Color LCD STN-DD 8-bit Interface Reset Timing......ccsccccssccsessssseesscnsesessseveon 245 (without Frame Acceleration) ................ 192 Local Bus Clock Timing eee 246 Color LCD STN-DD 16-bit Interface Local Bus '2x' Clock Synch Timing............. 246 (with Frame Acceleration) .............c0008 193 Local Bus Input Setup & Hold Timing ....... 47 Color LCD STN-DD 16-bit Interface Local Bus Output Valid Timing -.......00..000 248 (without Frame Acceleration) ................ 194 Local Output Float Delay Timing ........0..... 248 Application Schematics pores OEE Timing Oe oe veer een ee noeeeeetereereee at ISA Bus Interface sscsssssssssssssessnseesneee 210 PCI Bus Stop Timing 7 359 VL-Bus / 486 Processor Direct Interface ... 211 ISA Bus Timing.......ceceesseeseeseseseeceeeeetens 253 PCI Bus Interface .............cccsscscccesserecescenenee 212 i. Display Memory Interface ......0.c.cceceee 213 DRAM Page Mode Read Cycle Timing....... 255 CRT / Panel Interface .......scsesesscsseeseeneeee 214 DRAM Page Mode Write Cycle Timing..... 255 DRAM Read/Modify/Write Cycle Timing... 256 DRAM CAS-Before-RAS (CBR) Timing... 257 DRAM Self-Refresh' Cycle Timing ........... 257 CRT Output Signal Timing ....00.. ee 258 PC Video Timing............esesseseseeseeseeeeeeee 258 Panel Output Signal Timing 0... 259 Mechanical Specifications Plastic 208-PFP Package Dimensions......... 261 Revision 1.2 65540 / 545 M@ 20594116 0011734 173cidsee ogecee to eee Introduction / Overview Introduction / Overview The 65540 / 545 High Performance Flat Panel / CRT Controllers initiate a family of 208-pin, high performance solutions for full-featured notebook / sub-notebook and other portable applications that require the highest graphics performance available. The 65545 is pin-to-pin compatible with the 65540 and adds a sophisticated graphics hardware engine for Bit Block Transfer (BitBLT), line drawing, hardware cursor, and other functions intensively used in Graphical User Interfaces (GUIs) such as Microsoft Windows. The 65540 and 65545 also use the same video BIOS, offering the system manufacturer a wide range of price / performance points while minimizing overhead for system integration and improving time-to-market. The following table indicates feature differences between the 65540 and 65545: Features 65540 | 65545 Support for all flat panels vf / VESA Local Bus / 16-bitISA Bus| / / 32-bit PCI Bus / Linear Addressing / v Hardware Accelerator _ / Hardware Cursor _ / Pin Compatible / BIOS Compatible v / The 65540 / 545 family achieves superior performance through direct connection to system processor buses up to 32-bits in width. When combined with CHIPS' advanced linear acceleration software driver technology, these devices exhibit exceptional performance compared with devices of similar architecture. The 65540 / 545 architecture provides a fast throughput to video memory, maximizing the capability of today's powerful microprocessors to manipulate graphics operations. Based on the architecture of the 65540, the 65545 adds a powerful 32-bit graphics engine to offload graphics processing from the microprocessor for maximum performance. Minimum chip-count, low-power graphics subsystem implementations are enabled through the high integration level of the 65540 / 545 family. These devices integrate the VGA-compatible graphics controller, true color RAMDAC, and dual PLL clock synthesizers. The entire graphics sub- system can be implemented with a single 256Kx16 DRAM. The 32-bit local bus interface of the 65540 / 545 family eliminates external buffers. For maximum performance, the 65540 / 545 supports an additional 256Kx16 DRAM, which provides a 32-bit video memory bus and additional display memory to support resolutions up to 1024x768 with 256 colors, 800x600 with 256 colors, and 640x480 with 16M colors. In addition, the 65540 / 545 family can support PC Video multi- media features while interfacing to a 32-bit local bus and one MByte of video memory. The 65540 / 545 family supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD) passive STN and active matrix TFT / MIM LCD, EL, and plasma panels. The 65540 / 545 family supports panel resolutions of 800x600, 1024x768, and 1280x1024. For monochrome panels, up to 64 gray scales are supported. Up to 226,981 different colors can be displayed on passive STN LCDs and up to 16M colors on 24-bit active matrix LCDs using the 65540 / 545 controllers. The 65540 / 545 family offers a variety of programmable features to optimize display quality. For text modes which do not fill all 480 lines of a standard VGA panel, the 65540 / 545 provides tall font stretching in the hardware. Fast vertical centering and programmable vertical stretching in graphics modes offer more options for handling modes with less than 480 lines. Three selectable color-to-grayscale reduction techniques and SMARTMAP are available for improving the viewability of color applications on monochrome panels. CHIPS polynomial FRC algorithm reduces panel flicker on a wider range of panel types with a single setting for a particular panel type. The 65540 / 545 employs a variety of advanced power management features to reduce power consumption of the display subsystem and extend battery life. The 65540 / 5345's internal logic, memory interface, bus interface, and flat panel interfaces can be independently configured to operate at either 3.3 V or 5.0 V. The 65540 / 545 is optimized for minimum power consumption during normal operation and provides two power-saving modes - Panel Off and Standby. During Panel Off mode, the 65540 / 545 turns off the flat panel while Revision 1.2 65540 / 545 MS 2098116 0011735 03Tthe VGA subsystem remains active. The palette may also be automatically shut off during Panel Off mode to further reduce power consumption. During Standby mode, the 65540 / 545 suspends all CPU, memory and display activities. In this mode, the 65540 / 545 places the DRAM in self-refresh mode and the 65540 / 545 reference input clock can be turned off. The 65540 / 545 also provides a programmable activity timer which monitors VGA activity. After all display activity ceases, the timer will automatically shut down the panel by either disabling the backlight or putting the 65540 / 545 in Panel Off mode. The 65540 / 545 is fully compatible with the VGA graphics standard at the register, gate, and BIOS levels. The 65540 / 545 provides full backwards compatibility with the EGA and CGA graphics standards without using NMIs. CHIPS and third- party vendors supply fully VGA-compatible BIOS, end-user utilities and drivers for common application programs (e.g., Microsoft Windows, OS/2, WordPerfect, Lotus, etc.). CHIPS' drivers for Windows include a Big Cursor (to increase the cursor's legibility on monochrome flat panels) and panning / scrolling capability (to increase performance). MINIMUM CHIP COUNT / BOARD SPACE The 65540 / 545 provides a minimum chip count / board space, yet highly flexible VGA subsystem. The 65540 / 545 integrates a high-performance VGA flat panel / CRT controller, industry-standard RAMDAC, clock synthesizer, monitor sense circuitry and an activity timer in a 208-pin plastic flat pack package. In its minimum configuration, the 65540 / 545 requires only a single 256Kx16 DRAM, such that a complete VGA subsystem for motherboard applications can be implemented with just two ICs. This configuration consumes less than 2 square inches (1290 sq mm) of board space and is capable of supporting simultaneous flat panel / CRT display requirements while directly interfacing to a 32-bit local bus. As an option, a second memory chip may be implemented to increase performance (via a 32-bit data path to display memory) and support graphics modes which require more than 512 KBytes of display memory. No external buffers or glue logic are required for the 65540 / 545's bus interface, memory interface, or panel Introduction / Overview interface. The 65540 / 545 employs separate address and data buses with sufficient drive capability such that the bus can be driven directly. The 65540 / 545 also provides up to 24 bits of panel data with sufficient drive capability such that virtually all flat panels can be driven directly. DISPLAY MEMORY INTERFACE The 65540 / 545 supports multiple display memory configurations, providing the OEM with the flexibility to use the same VGA controller in several designs with differing cost, power consumption and performance criteria. The 65540 / 545 supports the following display memory configurations: @ One 256Kx16 DRAM (512 KBytes) B Two 256Kx16 DRAMs (1 MBytes) @ Four 256Kx4 DRAMs (512 KBytes) Performance is significantly improved when the 65540 / 545 is configured with a 32-bit data path to display memory, which is accomplished by using two 256Kx16 DRAMs. Two 256Kx16 DRAMs support all standard, Super, and Extended VGA resolutions up to 1024x768 256 colors as well as high 16bpp color and "true" 24bpp color modes. The table on the following page summarizes the display capabilities of the 65540 / 545. Display memory control signals are derived from the integrated clock synthesizer's memory clock. The 65540 / 545 serves as a DRAM controller for the system's display memory. It handles DRAM refresh, fetches data from display memory for display refresh, interfaces the CPU to display memory, and supplies all necessary DRAM control signals. The 65540 / 545 supports 'two-CAS / one-WE' and one-CAS / two-WE' 256Kx16 DRAMs. The 65540 / 545 supports the self-refresh features of 256Kx16 DRAMs and certain 256Kx4 DRAMs during Standby mode, enabling the 65540 / 545 to be powered down completely during suspend/resume operation. Revision 1.2 65540 / 545 Mi 20598116 001173b T7hEE snrsnes cals senneumeense LAIFr>S Introduction / Overview 65540 / 545 Display Capabilities CRT Mode Mono LCD DDSTNLCD | 9-BitTFT LCD | Video | Simultaneous Resolution _ Color Gray Scales 4 Colors 2 3,4 Colors 12, 3,4 Memory Display 320x200 [256 / 256KT 61/61 256 / 226,981 256 / 185,193 512KB Yes 640x480 | 16/256Kt 16/61 16 / 226,981 16 / 185,193 512KB Yes 640x480 [256 / 256KF 61/61 256 / 226,981 256 / 185,193 512KB Yes 800x600 | 16/256Kt 16/61 16 / 226,981 16 / 185,193 512KB_ | Yes with IMB 800x600 [256 / 256Kt 61/61 256 / 226,981 256 / 185,193 512KB | Yes with IMB 1024x768 | 16/256Kt 16/61 16 / 226,981 16 / 185,193 512KB_ | Yes with IMB 1024x768 [256 / 256Kt 61/61 256 / 226,981 256 / 185,193 IMB Yes 1280x1024 | 16 / 256Kt 16/61 n/a n/a 1MB n/a Notes: 1 Larger color palettes and simultaneous colors can be displayed on 12-bit, 18-bit, and 24-bit TFT panels via the 65540 / 545 video input port 2 Includes dithering 3 Includes frame rate control 4 Colors are described as number of simultaneous on-screen colors and number of unique colors available in the color palette f 256K colors assumes DAC output mode is set to 6 bits of R, G, & B. If DAC is set to 8-bit output mode, the number of available colors is 16M Revision 1.2 9 65540 / 545 Mi 2094116 0011737 102EEEE TESTG, pH Introduction / Overview CPU BUS INTERFACE The 65540 / 545 provides a direct interface to: @ 32-bit VL-Bus @ 32-Bit 386/486 CPU local bus m@ EISAASA (PC/AT) 16-bit bus m@ PCI Bus (65545 only) Strap options allow the user to configure the chip for the type of interface desired. Control signals for all interface types are integrated on chip. All operations necessary to ensure proper functioning in these various environments are handled in a fashion transparent to the CPU. These include internal decoding of all memory and V/O addresses, bus width translations, and generation of necessary control signals. HIGH PERFORMANCE FEATURES The 65540 / 545 includes a number of performance enhancement techniques including: H Direct 32-bit local bus CPU support m@ 32-bit interface to video memory m@ Linearly addressable display memory m@ 32-bit graphics hardware engine (65545 only) @ 64x64x2 hardware cursor (65545 only) The 65540 /545 provides an optimized 32-bit path from 32-bit CPUs direct to the video memory. Running the 32-bit local bus of the 65540 / 545 at CPU speeds up to 33 MHz maximizes data throughput and drawing speed for today's powerful CPU architectures. Addressing pixels linearly maximizes the efficiency of software drivers, enabling the CPU to make the most use of the full 32-bit path through the 65540 / 545 controller. Software drivers optimized for linear addressing are available from CHIPS and improve performance up to 80% over standard software methods. 65545 ACCELERATION Several functions traditionally performed by software have been implemented in hardware in the 65545 to off load the CPU and further improve performance. Three-Operand BitBLT logic supports all 256 logical combinations of Source, Destination, and Pattern. All BitBLTs are executed up to 32-bits per cycle, maximizing the efficiency of memory accesses. A 32-bit color expansion engine allows the host CPU to _ transfer monochrome "maps" of color images over the system bus at high speeds to the 65545, which decodes the monochrome images into their color form. Line drawing is also accelerated with hardware assistance. 65545 HARDWARE CURSOR A programmable-size hardware cursor frees software from continuously generating the cursor image on the display. The 65545 supports four types of cursors: 32x32 x 2bpp 64x64 x 2bpp 64x64 x 2bpp 128 x 128 x Ibpp The first two hardware cursor types indicated as 'and/xor' above follow the MS Windows AND/XOR cursor data plane structure which provides for two colors plus _ transparent (background color) and inverted (background color inverted). The last two types in the list above are also referred to as Pop-Ups because they are typically used to implement pop-up menu capabilities. Hardware cursor / pop-up data is stored in display memory, allowing multiple cursor values to be stored and selected rapidly. The two or four colors specified by the values in the hardware cursor data arrays are stored in on-chip registers as high-color (5-6-5) values independent of the on- chip color lookup tables. (and/xor) (and/xor) (4-color) (2-color) The hardware cursor can overlay either graphics or video data on a pixel by pixel basis. It may be positioned anywhere within screen resolutions up to 2048x2048 pixels. 64x64 'and/xor' cursors may also be optionally doubled in size to 128 pixels either horizontally and/or vertically by pixel replication. Hardware cursor screen position, type, color, and base address of the cursor data array in display memory may be controlled via the 32-bit 'DR' extension registers. PC VIDEO / OVERLAY SUPPORT The 65540 / 545 allows up to 24 bits of external RGB video data to be input and merged with the intemal VGA data stream. The 65540 / 545 supports two forms of video windowing: (i) color key input and (ii) X-Y window keying. The X-Y window key input can be used to position the live video window coordinates. The 65540 / 545 can be used in conjunction with Chips and Technologies, Inc. PC Video products to provide portable multi- media solutions. Revision 1.2 10 65540 / 545 M@ 20946116 00117358 645elScces Bese cecusensasss ne Es Vnirs Introduction / Overview DISPLAY INTERFACE The 65540 / 545 is designed to support a wide range of flat panel and CRT displays of all different types and resolutions Flat Panel Displays The 65540 / 545 supports all flat panel display technologies including plasma, electroluminescent (EL) and liquid crystal displays (LCD). LCD panel interfaces are provided for single panel-single drive (SS) and dual panel-dual drive (DD) configurations. A single panel sequences data similar to a CRT (i.e., sequentially from one area of video memory). In contrast, a dual panel requires video data to be provided alternating from two separate areas of video memory. In addition, a dual drive panel requires the data from the two areas to be provided to the panel simultaneously. Due to its integrated frame buffer and 24-data-line panel interface, the 65540 / 545 supports all panels directly. Support for LCD-DD panels does not require external hardware such as a frame buffer. Support for high- resolution, high color flat panels also does not require additional components. The 65540 / 545 handles display data sequencing transparently to applications software, providing full compatibility on both CRT and flat panel displays. 9-bit 12-bit '512-Color '4096-Color' Dither FRC 512 (8) 4096 (16) No No 3,375 (15) 29,791 (313) No Yes 24,389 (293) 226,981 (615) Yes No 185,193 (57) -1,771,561(1213) Yes Yes There is currently no standard interface for flat panel displays. Interface signals and timing requirements vary between panel technologies and suppliers. The 65540 / 545 provides register programmable features to allow interfacing to the widest possible range of flat panel displays. The 65540 / 545 provides a direct interface to panels from vendors such as Sharp, Sanyo, Epson, Seiko Instruments, Oki, Toshiba, Hitachi, Fujitsu, NEC, Matsushita/Panasonic, and Planar. PANEL POWER SEQUENCING Flat panel displays are extremely sensitive to condi- tions where full biasing voltage VEE is applied to the liquid crystal material without enabling the control and data signals to the panel. This resuits in severe damage to the panel and may disable the panel permanently. e 65540 / 545 provides a simple and elegant method to sequence power to the flat panel display during various modes of operation to conserve power and provide safe operation to the flat panel. The 65540 / 545 provides three pins called ENAVEE, ENAVDD and ENABKL to regulate the LCD Bias Voltage (VEE), the driver electronics logic voltage (VDD), and the backlight voltage (BKL) to provide intelligent power sequencing to the panel. The timing diagram below illustrates the power sequencing cycle. In the 65540 / 545, the power on/off delay time (TPo) is programmable (with a default of 32 mS). The 65540 / 545 initiates a panel off sequence if the STNDBY# input is asserted (low), or if XR52 bit-4 is set to a 'l' putting the chip into STNDBY mode. The 65540 / 545 also initiates a panel off sequence if the chip is programmed to enter panel off mode (by setting extension register XR52 bit- 3=1), or if the Display Type is programmed to CRT (extension register XR51 bit-2 transitions from 't' to '0'). The 65540 / 545 initiates a panel on sequence if the STNDBY# input is high and the chip is programmed to panel _on' (XR52 bit-3 transitions from a 'l' to '0') and flat panel display (XR51 bit-2 is set to '1). Panel On Panel Off ENAVDD Tpo >Tpo ENABKL Flat Panel : Valid Control & aa Data Signals > Tpo >|Tpo ENAVEE (Panel Power Sequencing CRT Displays The 65540 / 545 supports high resolution fixed frequency and variable frequency analog monitors in interlaced and non-interlaced modes of operation. Digital monitor support is also built in. The 65540 / 545 supports resolutions up to 1024x768 256 colors, 800x600 256 colors or 640x480 16,777,216 colors in 1 MByte display memory configurations, 1024x768 16 colors, 800x600 256 colors in 512 KBytes display memory configurations. The tables starting on the following page list all 65540 / 545 CRT monitor video modes. Revision 1.2 11 65540 / 545 Mm 2096116 0011739 745Introduction / Overview Supported Video Modes - VGA Standard Horizontal | Vertical Mode#! Display Text |Font| Pixel DotClock | Frequency Frequency, Video (Hex) Mode ___|Colors|Display| Size Resolution) (MHz) + (KHz) (Hz) |Memory| CRT 0,1 Text 16 |40x 25] 8x8 | 360x400 28.322 31.5 70 256 KB | A,B,C O*, 1* 40 x 25| 8x14} 320x350 25.175 0+, 1+ 40 x 25] 8x8 | 320x200 25.175 2,3 Text 16 | 80x 25 | 9x16] 720x400 28.322 31.5 70 256 KB | A,B,C 2*, 3* 80 x 25); 8x14| 640x350 25.175 2+, 3+ 80 x 25} 8x8 | 640x200 25.175 4 Graphics 4 |40x 25| 8x8 | 320x200 25.175 31.5 70 256 KB | A,B,C 5 Graphics 4 |40x 25} 8x8 | 320x200 25.175 31.5 70 256 KB | A,B,C 6 Graphics 2 |80x 25] 8x8 | 640x200 25.175 31.5 70 256 KB | A,B,C 7 Text Mono | 80 x 25 | 9x16} 720x400 28.322 31.5 70 256 KB | A,B,C 7+ 80 x 25 | 9x14} 720x350 D Planar 16 |40x25| 8x8 | 320x200 25.175 31.5 70 256 KB | A,B,C E Planar 16 |80x25| 8x8 | 640x200 25.175 31.5 70 256 KB | A,B,C F Planar Mono | 80 x 25 | 8x14} 640x350 25.175 31.5 70 256 KB | A,B,C 10 Planar 16 | 80x 25| 8x14} 640x350 25.175 31.5 70 256 KB | A,B,C 11 Planar 2 | 80x 30] 8x16| 640x480 25.175 31.5 60 256 KB | A,B,C 12 Planar 16 | 80x 30| 8x16} 640x480 25.175 31.5 60 256 KB | A,B,C 13. {Packed Pixel] 256 |40x 25} 8x8 | 320x200 25.175 31.5 70 256 KB | A,B,C Note: * All of the above VGA standard modes are supported directly in the 65548 BIOS (both 32K and 40K BIOS versions). All of the above VGA standard modes are supported at both 3.3V and SV. All VGA modes using 25.175 MHz and 28.322 MHz can also be supported using 32 MHz and 36 MHz respectively. Note: Not all above resolutions can be supported at both 3.3V and 5V. In this case, the horizontal frequency becomes 40.000 KHz and the vertical frequency becomes 89 Hz. (see XR33 bit-7 "ISO Mode Control" for selection of VGA dot clock frequencies) + Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation. CRT Codes: A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification) B Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent) C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent) Revision 1.2 12 Mi 2094116 OO11740 4T? 65540 / 545LAIrS Introduction / Overview Supported Video Modes - Extended Resolution Horizontal; Vertical Mode#| Display Text | Font} Pixel DotClock | Frequency Frequency, Video (Hex) Mode __|Colors|Display| Size [Resolution| (MHz) + (KHz) (Hz) |Memory| CRT 20 |4bitLinear| 16 | 80x 30] 8x16] 640x480 25.175 31.5 60 512 KB | A,B,C 22 |4bitLinear| 16 {100 x 37|8x16| 800x600 40.000 37.5 60 512 KB | B,C 24 |4bitLinear| 16 [128 x 48) 8x16| 1024x768| 65.000 48.5 60 512KB}] C 241 |4bitLinear}| 16 [128 x 48] 8x16| 1024x768| 44.900 35.5 43 $12 KB| B,C 281 |4bitLinear| 16 [128 x 48] 8x16|1280x1024| 65.000 42.5 39 1 MB Cc 30 | 8 bitLinear| 256 | 80x 30] 8x16] 640x480 25.175 31.5 60 512 KB | A,B,C 32 | 8bitLinear| 256 |100x 37) 8x16| 800x600 | 40.000 37.5 60 512 KB; _ B,C 34 | 8 bitLinear| 256 |128 x 48} 8x16| 1024x768| 65.000 48.5 60 1 MB C 341 | 8 bitLinear| 256 |128 x 48] 8x16} 1024x768| 44.900 35.5 43 1MB | B,C 40 | 15bit Linear! 32K | 80x 30| 8x16} 640x480 50.350 31.5 60 1 MB | A,B,C 41 |16bitLinear| 64K | 80x 30| 8x16} 640x480 50.350 31.5 60 1 MB | A,B,C 50 | 24bit Linear] 16M | 80x 30] 8x16} 640x480 65.000 27.1 51.6 1MB | BC 60 Text 16 |132 x 25) 8x16| 1056x400] 40.000 30.5 68 256 KB | A,B,C 61 Text 16 [132 x 50) 8x16| 1056x400| 40.000 30.5 68 256 KB | A,B,C 6A,70| Planar 16/100 x 37| 8x16} 800x600 40.000 38.0 60 256 KB |_B,C 72,75 Planar 16 (128 x 48) 8x16 | 1024x768| 65.000 48.5 60 512KB| C 72, 751| Planar 16 {128 x 48) 8x16 | 1024x768] 44.900 35.5 43 512 KB; B,C 78 (Packed Pixell 16 | 80x 25)|8x16| 640x400 25.175 31.5 70 256 KB |.A,B,C 79 _|Packed Pixel) 256 | 80x30} 8x16| 640x480 25,175 31.5 60 512 KB | A,B,C 7C__|Packed Pixel] 256 {100 x 37| 8x16! 800x600 | 40.000 37.5 60 512 KB| B,C 7E_|Packed Pixel] 256 j128 x 48] 8x16] 1024x768] 65.000 48.5 60 1 MB Cc TEI |Packed Pixel] 256 |128 x 48} 8x16} 1024x768| 44.900 35.5 43 1MB | B,C 761 |4bitPlanar} 16 |128 x 48] 8x16}1280x1024)| 65.000 42.5 39 i MB Cc Note: Support for the modes in the above table is included directly in the BIOS (both 32K and 40K versions). The "I" in the mode # column indicates "Interlaced". Supported Video Modes - High Refresh Horizontal} Vertical Mode#| Display Text | Font| Pixel DotClock | Frequency |Frequency| Video (Hex) Mode ___|Colors| Display| Size |Resolution| (MHz) + (KHz) (Hz) |Memory| CRT 12* Planar 16 | 80x 30) 8x16} 640x480 31.500 37.5 75 256 KB | B,C 30 | 8 bit Linear} 256 | 80x 30| 8x16| 640x480 31.500 37.5 75 256 KB Cc 79 {Packed Pixel) 256 | 80x 30| 8x16! 640x480 31.500 37.5 75 512 KB Cc 6A,70; Planar 16 {100 x 37| 8x16) 800x600 49.500 46.9 75 512 KB Cc 32 | 8 bit Linear; 256 |100x37| 8x16} 800x600 49,500 46.9 75 1 MB C 7C_ |Packed Pixel] 256 |100x 37] 8x16} 800x600 49.500 46.9 75 1 MB Cc Note: Not all above resolutions can be supported at both 3.3V and 5V. + Refer to Electrical Specifications section for maximum clock frequencies for 5V and 3.3V operation. CRT Codes: A PS/2 fixed frequency analog CRT monitor or equivalent (31.5 / 35.5 KHz Horizontal Frequency Specification) B_ Multi-Frequency CRT monitor (37.5 KHz Minimum Horizontal Frequency Specification) (NEC MultiSync 3D or equivalent) C Multi-Frequency High-Performance CRT Monitor (48.5 KHz Min H Freq Specification) (Nanao Flexscan 9070s, MultiSync 5D, or equivalent) Revision 1.2 13 Mi 2098116 0011741 333 65540 / 545Simultaneous Flat Panel / CRT Display The 65540 / 545 provides simultaneous display operation with Multi-Sync variable frequency or PS/2 fixed frequency CRT monitors and single panel-single drive LCDs (LCD-SS), dual panel-dual drive LCDs (LCD-DD), and plasma and EL panels (which employ single panel-single drive interfaces). Single drive panels sequence data in the same manner as CRTs, so the 65540 / 545 provides simultaneous CRT display with LCD-SS, Plasma, and EL panels by driving the panels with CRT timing. LCD-DD panels require video data alter- nating between two separate locations in memory. In addition, a dual drive panel requires data from both locations simultaneously. A framestore area, also called the frame buffer, is required to achieve this operation. The 65540 / 545 innovative archi- tecture implements the frame buffer in an unused area of display memory, reducing chip count and subsystem cost. As an option, an extra 16-bit wide DRAM can be used as an external frame buffer, improving performance while in simultaneous flat pane/CRT modes. The 65540 / 545 provides simultaneous display with monochrome and color LCD-DD panels with a single 256Kx16 DRAM. DISPLAY ENHANCEMENT FEATURES Display quality is one of the most important features for the success of any flat panel-based system. The 65540 / 545 provides many features to enhance the flat panel display quality. "TRUE-GRAY" Gray Scale Algorithm A proprietary polynomial-based Frame Rate Control (FRC) and dithering algorithm in the 65540 / 545's hardware generates a maximum of 61 gray levels on monochrome panels. The FRC technique simulates a maximum of 16 gray levels on monochrome panels by turning the pixels on and off over several frames in time. The dithering technique increases the number of gray scales from 16 to 61 by altering the pattern of gray scales in adjacent pixels. |The persistence (response time) of the pixels varies among panel manufacturers and models. By re-programming the polynomial (an 8- bit value in Extension Register XR6E) while viewing the display, the FRC algorithm can be adjusted to match the persistence of the particular panel without increasing the panel's vertical refresh rate. With this technique, the 65540 / 545 produces up to 61 flicker-free gray scales on the latest fast response "mouse quick" film-compensated mo- nochrome STN LCDs. The alternate method of reducing flicker -- increasing the panel's vertical Introduction / Overview refresh rate -- has several drawbacks. As the vertical refresh rate increases, panel power consumption increases, ghosting (cross-talk) increases, and contrast decreases. CHIPS polynomial FRC gray scale algorithm reduces flicker without increasing the vertical refresh rate. RGB Color To Gray Scale Reduction The 24 bits of color palette data from the VGA standard color lookup table (CLUT) are reduced to 6 bits for 64 gray scales via one of three selectable RGB color to gray scale reduction techniques: 1) NTSC Weighting: 5/16 Red 9/16 Green 2/16 Blue 2) Equal Weighting: 5/16 Red 6/16 Green 5/16 Blue 3) Green Only: 6 bits of Green only NTSC is the most common weighting, which is used in television broadcasting. Equal weighting increases the weighting for Blue, which is useful for Applications such as Microsoft Windows 3.1 which often uses Blue for background colors. Green-Only is useful for replicating on a flat panel the display of software optimized for IBM's monochrome monitors which use the six green bits of palette data. SmartMap SmartMap is a proprietary feature that can be invoked to intelligently map colors to gray levels in text mode. SmartMap improves the legibility of flat panel displays by solving a common problem: Most application programs are optimized for color CRT monitors using multiple colors. For example, a word processor might use a blue background with white characters for normal text, underlined text could be displayed in green, italicized text in yellow, and so on. This variety of colors, which is quite distinct on a color CRT monitor, can be illegible on a monochrome flat panel display if the colors are mapped to adjacent gray scale values. In the example, underlined and italicized text would be illegible if yellow is mapped to gray scale 4, green to gray scale 6 with the blue background mapped to gray scale 5. SmartMap compares and adjusts foreground and background grayscale values to produce adequate display contrast on flat panel displays. The minimum contrast value and the foreground / background grayscale adjustment values are programmed in the 65540 / 545's Extension Registers. This feature can be disabled if desired. Revision 1.2 14 65540 / 545 MB 2098116 0011742 erT@ Introduction / Overview Text Enhancement Text Enhancement is another feature of the 65540 / 545 that improves image quality on flat panel displays. When enabled, the Text Enhancement feature displays Dim White as Bright White, thereby optimizing the contrast level on flat panels. Text Enhancement can be enabled and disabled by changing a bit in one of the Extension Registers. Vertical & Horizontal Compensation Vertical & Horizontal Compensation are program- mable features that adjust the display to completely fill the flat panel display. Vertical Compensation increases the useable display area when running lower resolution software on a higher resolution panel. Unlike CRT monitors, flat panels have a fixed number of scan lines (e.g., 200, 400, 480 or 768 lines). Lower resolution software displayed on a higher resolution panel only partially fills the useable display area. For instance, 350-line EGA software displayed on a 480-line panel would leave 130 blank lines at the bottom of the display and 400-line VGA text or Mode 13 images would leave 80 blank lines at the bottom. The 65540 / 545 offers the following Vertical Compensation techniques to increase the useable screen area: Vertical Centering displays text or graphics images in the center of the flat panel, with a border of unused area at the top and bottom of the display. Automatic Vertical Centering automatically adjusts the Display Start address such that the unused area at the top of the display equals the unused area at the bottom. Non-Automatic Vertical Centering enables the Display Start address to be set (by programming the Extension Registers) such that text or graphics images can be positioned anywhere on the display. Line replication (referred to as "stretching") duplicates every Nth display line (where N is programmable), thus stretching text characters and graphic images an adjustable amount. The display can be stretched to completely fill the flat panel area. Double scanning, a form of line replication where every line is replicated, is useful for running 200-line software on a 400-line panel or 480-line software on a 1024-line panel. Blank line insertion, inserts N lines (where N is programmable) between each line of text characters. Thus text can be evenly spaced to fill the entire panel display area without altering the height and shape of the text characters. Blank line insertion can be used in text mode only. The 65540 / 545 implements the Tall Font scheme so that there are very few blank lines on the flat panel in text modes. For example, using an 8x19 Tall Font would fill 475 lines on a 480-line panel in VGA mode 3. Lines 1, 9, 12 of the 16 line font may be replicated to generate the 8x19 font. Alternately, line 0 may be replicated twice and line 15 replicated once. The Tall Font scheme is implemented in hardware thereby avoiding any compatibility issues. Each of these Vertical Compensation techniques can be controlled by programming the Extension Registers. Each Vertical Compensation feature can be individually disabled, enabled, and adjusted. A combination of Vertical Compensation features can be used by adjusting the features priority order. For example, text mode vertical compensation consists of four priority order options: @ Double Scanning+Line Insertion, Double Scanning, Line Insertion @ Double Scanning+Line Insertion, Double Scanning @ Double Scanning+Tall Scanning, Tall Fonts @ Double Scanning+Tall Fonts, Tall Fonts, Double Scanning Insertion, Line Fonts, Double Text and graphics modes offer two Line Replication priority order options: m@ Double Scanning+ Line Replication, Double Scanning, Line Replication m Double Scanning+ Line Replication, Line Replication, Double Scanning Horizontal Compensation techniques include Horizontal Compression, Horizontal Centering, and Horizontal Doubling. Horizontal Compression will compress 9-dot text to 8-dots such that 720-dot text in Hercules modes will fit on a 640-dot panel. Automatic Horizontal Centering automatically centers the display on a larger resolution panel such that the unused area at the left of the display equals the unused area at the right. Non-Automatic Horizontal Centering enables the left border to be set (by programming the Horizontal Centering Extension Register) such that the image can be positioned anywhere on the display. Automatic Horizontal Doubling will automatically double the display in the horizontal direction when the horizontal display width is equal to or less than half of the horizontal panel size. Revision 1.2 15 65540 / 545 M@ 205948116 0011743 106BEER gre Subject to change without notice Introduction / Overview ADVANCED POWER MANAGEMENT Normal Operating Mode The 65540 / 545 is a full-custom, sub-micron CMOS integrated circuit optimized for low power consumption during normal operation. The 65540 / 545 provides CAS-before-RAS refresh cycles for the DRAM display memory. The 65540 / 545 provides "mixed" 3.3V and 5.0V operation by providing dedicated Vcc pins for the 65540 / 545's internal logic, bus interface, memory interface, and display interface. If the 65540 / 545 internal logic operates at 3.3V, the memory, bus, and panel interfaces can independently operate at either 3.3V or 5.0V. The clock Vcc must be the same as the Vcc of the internal logic. The 65540 / 545 provides direct interface to 386/486 local bus which conserves power when 3.3V microprocessors are used. <A flexible clock synthesizer is used to generate independent memory and video clocks. The 65540 / 545's performance-enhancement features minimize the memory clock frequency (and thus power consumption) required to achieve a given performance level. The 65540 / 545's proprietary gray scaling algorithm produces a flicker-free display with a minimum video clock and panel vertical refresh rate. (Note: the power consumption of the controller increases linearly with video clock frequency). Panel Off Mode In 'Panel Off mode, the 65540 / 545 turns off both the flat panel and CRT interface logic. The VGA subsystem remains active, such that the CPU can read/write display memory and I/O registers. The 65540 / 545's video clock can be reduced significantly, saving power. Panel Off mode is activated by programming Extended Register XR52 bit-3=1. Standby Mode In 'Standby' mode, the 65540 / 545 suspends all CPU, memory and display activities. The 65540 / 545 places the DRAM in its self-refresh mode of operation, and the 65540 / 545's clock can be shut off. The VGA subsystem dissipates a minimum amount of power during Standby. Since the 65540 / 545 is a fully static device, the contents of the controller's registers and on-chip palette are maintained during Standby. Therefore, Standby mode provides fast Suspend / Resume modes. The Standby mode may be activated by forcing the STNDBY# pin low or programming XR52 bit-4 to l'. The state of all 65540 / 545 pins during Standby mode is summarized in the tables on the following page. CRT Power Management (DPMS) The 65540 / 545 supports the VESA DPMS (Display Power Management Signaling) protocol. This includes the ability to independently stop HSYNC and/or VSYNC and hold them at a static level to signal the CRT to enter various power- saving states. Additionally, the RAMDAC may be powered down and the clock frequencies lowered for further power savings. Mixed 3.3V and 5.0V Operation The 65540 supports operation at either 5.0V +10% or 3.3V +0.3V. The 65540 also provides "mixed" 5V and 3.3V operation by providing dedicated Vcc pins for the 65540's internal logic, bus interface, memory interface, and display interface. Each dedicated Vcc can be either 5V or 3.3V, such that the 65540 internal logic operates at 3.3V and the various interfaces at either 3.3V or 5V. The clock VCC must be the same as the Vcc of the internal logic. The following table shows the relationship between the VCC inputs to the 65540 and the interface pins controlled by each Vcc input. Vcc Pins Interface Pins Affected 80,181 Internal Logic -- 9, 42 Bus 1-54, 178-201, 207 158 Memory A 145-177 142 Memory B 123-144 108 Memory C 90-122 66 Display 61-89 205, 206 Clock* 203, 204 59 DAC 55,57,58,60 * Must be same as the Vcc of the internal logic. The 65545B1/B2 and 65545B1-5/B2-5 are the same part (die) that has been tested for operation at different voltage requirements. The 65545B1/B2 provides a dedicated Vcc (Voltage) pins for the internal logic, clock synthesizer, bus interface, memory interface and the display interface. Each dedicated Vcc can be either 5V or 3.3V independently except for the internal core and clock synthesizer which must be at the same voltage level. The 65545B1-5/B2-5 limits the internal core and clock synthesizer Vcc to 5V only operation and meets all 5V data sheet requirements. Revision 1.2 16 65540 / 545 MH 2098116 0011744 O42 |CPU ACTIVITY INDICATOR / TIMER The 65540 / 545 provides an output pin called ACTI (pin 53) to facilitate an orderly power-down sequence. The ACTI output is an active high signal which is driven high every time a valid VGA memory read/write operation or VGA VO read/write operation is executed by the CPU. This signal may be used by power management circuitry to put the 65540 / 545 in Panel Off or Standby power down modes. The 65540 / 545 may also evoke its own low power operation by using the activity timer which monitors the ACTI signal. The activity timer will either disable the backlight or evoke Panel Off mode after a specified time interval. This time interval is programmed in 30 second intervals via Extension Register XR5C. FULL COMPATIBILITY The 65540 / 545 is fully compatible with the IBM VGA standard at the hardware, register, and BIOS level. The 65540 / 545 also provides enhanced backward compatibility to EGA and CGA standards without using NMIs. These controllers include a variety of features to provide compatibility on flat panel displays in addition to CRT monitors. Internal compensation techniques ensure that industry-standard software designed for different displays can be executed on the single flat panel used in an implementation. Mode initialization is supported at the BIOS and register levels, ensuring compatibility with all application software. Write Protection The 65540 / 545 has the ability to write protect most of the standard VGA registers. This feature is used to provide backwards compatibility with software written for older generation display types. The write protection is grouped into register sets and controlled by the Write Protect Register (XR15). Extension Registers The 65540 / 545 employs an "Extension" Register set to control its enhanced features. These Extension Registers provide control of the flat panel interface, flat panel timing, vertical compensation, SMARTMAP, and Backwards Compatibility. These registers are always accessible as an index/data register set at port addresses 3D6-3D7h. None of the unused bits in the regular VGA registers are used for extensions. Introduction / Overview Panel Interface Registers Flat Panel Interface characteristics are controlled by a subset of the Extension Registers. These Registers select the panel type, data formatting, panel configuration, panel size, clock selection and video polarity. Since the 65540 / 545 is designed to support a wide range of panel types and sizes, the control of these features is fully programmable. The video polarity of text and graphics modes is independently selectable to allow black text on a white background and still provide normal graphics images. Alternate Panel Timing Registers Flat panel displays usually require sync signal timing that is different from a CRT. To provide full compatibility with the IBM VGA. standard, alternate timing registers are used to allow independent timing of the sync signals for flat panel displays. Unlike the values programmed into the standard CRT timing registers, the value programmed into the alternate timing registers is dependent on the panel type used and is independent of the display mode. Context Switching For support of multi-tasking, windowing, and context switching, the entire state of the 65540 / 545 (internal registers) is readable and writable. This feature is fully compatible with IBM's VGA. Additional registers are provided to allow read back of internal latches not readable in the IBM VGA. Revision 1.2 17 65540 / 545 @@ 2096116 0011745 T89iE gene Introduction / Overview RESET, SETUP, AND TEST MODES Reset Mode When this mode is activated by pulling the RESET# pin low, the 65540 / 545 is forced to VGA-compati- ble mode and the CRT is selected as the active dis- play. In addition, the 65540 / 545 is disabled; it must be enabled after deactivating the RESET# pin by writing to the Global Enable Register (102h in Setup Mode for ISA bus configurations or to port 3C3h or Local Bus configurations). Access to all Extension Registers is always enabled after reset (at 3D6/3D7h). The RESET# pin must be active for at least 64 clock cycles. Setup Mode In this mode, only the Global Enable register is accessible. In IBM-compatible PC implementa- tions, setup mode is entered by writing a 1 to bit-4 of port 46E8h. This port is incorporated in the 65540 / 545. While in Setup mode, the video output is active if it was active prior to entering Setup mode and inactive if it was inactive prior to entering Setup mode. After power up, video BIOS can optionally disable the video 46E8 or 3C3 registers (via XR70) for compatibility in case other non-IBM-compatible peripheral devices use those ports. Tri-State Mode In this mode, all output pins of the 65540 / 545 chip may be disabled for testing of circuitry external to the chip. The 65540/ 545 will enter Tri-State mode if it sees a rising edge on XTALI during RESET with one of the display memory data pins pulled low (MADO pin 162). The 65540 / 545 will exit Tri-State mode with the enabling memory data pin (MAD0) high or RESET# low. ICT (In-Circuit Test) Mode In this mode, all digital pins of the 65540 / 545 chip may be tested individually to determine if they are properly connected (the analog RGB and RESET# pins cannot be tested in ICT mode). The 65540 / 545 will enter ICT mode if it sees a rising edge on XTALI during RESET with one of the display memory data pins pulled low (a different pin from the one used to enable Tri-state mode: MAD1). In ICT mode, all digital signal pins become inputs which are part of a long path starting at ENAVDD (pin 62) and proceeding to lower pin numbers around the chip to pin 1 (except analog pins 55, 57, 58, and 60) then to pin 208 and ending at VSYNC (pin 64). If all pins in the path are high, the VSYNC output will be high. If any pin is low, the VSYNC output will be low. Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a time (XTALI last) and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XTALI with either of the enabling memory data pins high or RESET# low will exit ICT mode. As a side effect, ICT mode effectively Tri-States all pins except VSYNC. , Display Mode of RESET# STNDBY# Memory Video Operation Pintt Pin Access Output Reset Low XXX eee Setup ee wee No Yes Test eee No Yes Standbyf High Low No No Panel-Oftt High High Yes No f It is illegal to go from Panel-Off Mode to Standby Mode. Panel-Off Mode must be exited first and a delay must occur of twice the value programmed into XR5B[7-4] prior to entering Standby Mode. ft In 65540 BS Silicon reset is active high (RESET); in all following revisions reset is active low (RESET#). ( Reset / Setup / Test / Standby / Panel-Off Mode Summary > Revision 1.2 18 65540 / 545 M 2094116 OOLL74b 915Introduction / Overview CHIP ARCHITECTURE The 65540 / 545 integrates six major internal modules: Sequencer The Sequencer generates all CPU and display memory timing. It controls CPU access of display memory by inserting cycles dedicated to CPU access. It also contains mask registers which can prevent writes to individual display memory planes. CRT Controller The CRT Controller generates all the sync and timing signals for the display and also generates the multiplexed row and column addresses used for both display refresh and CPU access of display memory. Graphics Controller The Graphics Controller interfaces the 8, 16, or 32- bit CPU data bus to the 32-bit internal data bus used by the four planes (Maps) of display memory. It also latches and supplies display memory data to the Attribute Controller for use in refreshing the screen image. For text modes this data is supplied in parallel form (character generator data and attribute code); for graphics modes it is converted to serial form (one bit from each of four bytes form a single pixel). The Graphics Controller can also petform any one of several types of logical operations on data while reading it from or writing it to display memory or the CPU data bus. Attribute Controller The Attribute Controller generates the 4-bit-wide video data stream used to refresh the display. This is created in text modes from a font pattern and an attribute code which pass through a parallel to serial conversion. In graphics modes, the display memory contains the 4-bit pixel data. In text and 16 color graphic modes the 4-bit pixel data acts as an index into a set of 16 internal color look-up registers which generate a 6-bit color value. Two additional bits of color data are added to provide an 8-bit address to the VGA color palette. In 256-color modes, two 4-bit values may be passed through the color look-up registers and assembled into one 8-bit video data value. In high-resolution 256-color modes, an 8-bit video data value may be provided directly, bypassing the attribute controller color lookup registers. Text and cursor blink, underline and horizontal scrolling are also the responsibility of the Attribute Controller. VGA / Color Palette DAC The 65540 / 545 integrates a VGA compatible triple 6-bit Color Lookup Table (sometimes referred to as a "CLUT" or just "LUT") and high speed 6/8-bit DACs. Additionally true color bypass modes are supported displaying color depths of up to 24bpp (8-red, 8-green, 8-blue). The palette DAC can switch between true color data and LUT data on a pixel by pixel basis. Thus, video overlays may be any arbitrary shape and can lie on any pixel boundary. The hardware cursor is also a true color bitmap which may overlay on any pixel boundary. The internal palette DAC register I/O addresses and functionality are 100% compatible with the VGA standard. In all bus interfaces the palette DAC automatically controls accesses to its registers to avoid data overrun. This is handled by holding RDY in the ISA configuration and by delaying RDY# for VL-Bus and local bus interfaces. Extended RAMDAC display modes are selected in the Palette Control Register (XRO6). Two 16bpp formats are supported: 5-red, 5-green, 5-blue Targa format and 5-red, 6-green, 5-blue XGA format. The internal Palette / DAC may also be disabled via the Palette Control Register (XR06). [- > Red RGB5-6-5External Video >| 24 _ HighColorPixelData __ it Green L_ m > Blue LUTPixeData __8 _,| Tripl-hit 18 Color Palette / DAC Internal Block Diagram Revision 1.2 19 65540 / 545 mM 2096116 00117 47 65), =Introduction / Overview Clock Synthesizers Integrated clock synthesizers support all pixel clock (VCLK) and memory clock (MCLK) frequencies which may be required by the 65540 / 545. Each of the two clock synthesizers may be programmed to output frequencies ranging between 1MHz and the maximum specified operating frequency for that frequencies are set via a programmable 18-bit divisor value which contains fields for Phase Lock Loop (PLL), Voltage Controlled Oscillator (VCO) and Pre/Post Divide Control. A block diagram showing the clock synthesizer registers is included below. Refer to the Functional Description section clock in increments not exceeding 0.5%. The of this document for additional information. VCLkRegisterT able VGA CLKO = 25.175MHz VGA CLK1 = 28.322MHz 21 VCLK Synthesizer >| CLK2=Programmable Lt XR32:30- MCLKRegiste:Table MCLK = Programmable ay, > MCLK Synthesizer CLKSEL1:0 MISC Output Reg[3:2] ( Clock Synthesizer Register Diagram > Revision 1.2 20 65540 / 545 MH 2094116 0011748 798Introduction / Overview CONFIGURATION INPUTS The 65540 / 545 can read up to nine configuration bits. These signals are sampled on memory address bus AAO-AA8 on the trailing edge of Reset. The 65540 / 545 implements pull-up resistors on-chip on all configuration input pins. If the user wishes to force a certain option, then a 4.7K ohm resistor may be used to pull-down the desired configuration pin. 65540 / 545 Pin # Signal | Active Functionality 145 LB# | Low Bus Configuration 146 ISA# | Low Bus Configuration 147 2X# | Low 2xCPU Clock Select 148 | Low Reserved 149 | Low] Reserved (Do Not Use) 150 OS# | Low | External Oscillator Select 151 AD# | Low |ENABKL/ACTI=A26,A27 152 TS# | Low Test Mode Enable 153 LV# | Low Low Voltage Select 2X# ISA# LB# (AA2) | (AAI) | (AAO) Bus Functionality Pin 147 | Pin 146 | Pin 145 Low Low Low Reserved Low _| Low | High Reserved Low | High | Low Reserved Low | High | High [32-bit CPU Bus (2x clk) High | Low Low Reserved High | Low | High 16-bit ISA Bus High | High | Low | PCI Bus (65545 only) High | High | High | 32-bit VL-Bus (1x clk) AA2 determines the CPU clock rate for purposes of local bus implementation (0=2x CPU clock, 1=1x CPU clock). AA3 has no hardware function, but the status of the pin is latched in extension register 1 bit 3 on reset so it may be used to input system- specific information. AA4 is reserved and should be sampled high on reset. AAS5, if forced to 0, indicates that a reference frequency of 14.31818 MHz must be input on XTALI (pin 203). AA6 selects between ACTVYENABKL and A26-27 on pins 53-54 (default is ENABKL and ACTI). AA7, when forced low, enables clock test mode (VCLK and MCLK are output on A24-25 (pins 29-30). AA8, when forced low, selects 3.3V level of operation for the internal logic and the clock core. VIRTUAL SWITCH REGISTER The 65540 / 545 implements a virtual switch register. In 'EGA' mode, the sense bit of the Feature control register (3C2 bit 4) may be set up to read a selected bit from the virtual switch register (an extension register set up by BIOS at initialization time) instead of reading the state of the internal comparator output. LIGHT PEN REGISTERS In the CGA and Hercules modes, the contents of the Display Address counter are saved at the end of the frame before being reset. The saved value can be read in the CRT Controller Register space at indices 10h and 1ih. This allows simulation of a light pen hit in CGA and Hercules modes. BIOS ROM INTERFACE In typical ISA bus and VL-Bus applications, the 65540 / 545 is placed on the motherboard and the video BIOS is integrated with the system BIOS (in PCI Bus, the video BIOS is always inchided in the system BIOS). A separate signal (ROMCS#) is generated on the A24 pin for ISA bus or may be created external to the 65540 / 545 for imple- menting a separate external ROM BIOS. Typically, an 8-bit BIOS is implemented with one external ROM chip. A 16-bit dedicated video BIOS ROM could be implemented with the 65540 / 545 if required using two BIOS ROM chips, an external PAL, and a 74LS244 buffer. However, a higher- performance and lower-cost video system will result from implementation of the video BIOS as either an 8-bit dedicated video BIOS ROM or as part of the system BIOS and having the video BIOS be copied into system RAM by the system BIOS on startup. Chips and Technologies, Inc. supplies a video BIOS that is optimized for the 65540 / 545 hardware. The BIOS supports the extended functions of the 65540 / 545, such as switching between the flat panel and the CRT, SMARTMAP, Vertical Compensation, and palette load/save. The BIOS Modification Program (BMP) enables OEMs to tailor their feature set by programming the extended functions. CHIPS offers the BIOS as a standard production version, a customized version, or as source code. PACKAGE The 65540 / 545 is available in a EIAJ-standard 208-pin plastic flat pack with a 28 x 28 mm body size and 0.5 mm (19.7 mil) lead pitch. Revision 1.2 21 65540 / 545 MH 2098116 00117495 behAPPLICATION SCHEMATIC EXAMPLES This document includes application schematic examples of the following: 1. Bus Interface - 16-bit EISA/ISA Bus Bus Interface - 32-bit 486 Local Bus (1x Clock) Bus Interface - 32-bit VL-Bus (1x Clock) Bus Interface - 32-bit PCI Bus 2. Display Memory Interface 3. CRT / Panel Interface 4. PC Video Interface Introduction / Overview Revision 1.2 mM 2096116 0031750 346 me 22 65540 / 545Pin Diagram Sse 929 DRAM"B" DRAM'C" Beto N44 DisplayMemoryUpperS512KB FramBuffer or mPOP\OVWA TAN AS NNN in yin, prin, ma mereemOOoooCmmam ma SUOUUUUOUU poseccossssese re PC-Video a teak o 2 DRAM"A" 3% inst Benes ae BOT OO son sonst) 5 Interface DisplayMemory 25 BEB DEERE eee LowerS12KB 20 OOBMESSSSSS SESS SS SSS SS TRIAS ee pak hat commneRECAEN COTA Qe SOTA TO SSESS WEAH#) _ WEA# 57 : . WECL# VR6 CASCL#| ( > vee 38 Configuration Pins CAS VR7 CASCHA GAs. CASAH# 59 2X# =0 2XLCLK _ (WECH#) (PCL CH BAL#) CASAL # 60 OS# =0 External Oscillator (1=Xtal) KE 60 RASCH TSENA#) MADO o1 AD# =0 ENABKL & ACTI are A26,A27 20s 99 CAS CRENAS MADi 63 TS# =0 Enable Clock Test Mode 58 CAB AD 64 LV# =0 Input Threshold Level Control 97 CA7 MAD3 65 96 CA6 MAD4 66 95 CA5 MADS 67 94 CA4 MAD6 68 93 CA3 MAD7 69 92 CA2 MAD8 70 91 CAl MAD 71 90 CAO I MAD10 12 89 DGND MADI11 73 8 P15 MAD12 14 P14 MADI4 S179 bi} ADIs Hl 117 Flat Panel VGA Controller Pit STNDB # B Flo A3 80 P8 wee a 10/30/95 Fcc Me Be Interface 33) 7 IGND 84 Group 77 IGND A6 85 Pin names shown indicate VL-Bus connections (Default) 76 PS Bus Ag 88 Pin names in brackets <...> indicate ISA-Bus connections (ISA# = 0) 3 i Interface Ag 88 Pin names in parentheses indicate alternate functions 73 P2 Group AI) Ell iso FUE bo Al2 91 710 SHFCLK} Al3 92 r BE BLANKS 69 M Als el isd xe DEXBLANK#) SSB ELM Al6 ca{195 5S 66| fe DVCC Al? 96 z Se 65 HSYNC Als 97 5 Onl 64 VSYNC Al9 98 a ZO 63 GND A20 99 Ww > 62 ENAVD] Ax S s (ENABKT) O/B RED RePNa a 2 38 [E GREEN Clock rato HASADAAA ph AAAAA Zona d 3719 BLUE Group CVCCo oH i2hs SESEEEEE Se PoE er CS eee Ade 39| IE AGNP rit BESET HB 207 22028828 LE ge 7gRUS SARs S <5 34 || ENABEI |___CGND1 GV Go" GuvVeveNeveey vue 53) 9B AcTI AICS SPUN 00DN RIQIQNNQQUYIN Bus MOCK Ont Dstt Benno ote $e FF EHO Men pingestiun tenn oRaoclgeronstmaA OR SS ION A Zt et ett oe Interface BAAAAAAACERS ASA AaannnCanidaesemnananng pe ang Group man = me a ENABKL = (GPIO) (A27) (VB1) ACTI = (GPIO) (A26) (VBO) + In 2x clock mode, pin 23 becomes CRESET instead of RDYRTN# tt In Test mode, pin 29 becomes VCLKOUT and pin 30 becomes MCLKOUT ttt In 65540 ES Silicon reset_is active high (RESET); in all following revisions reset is active low (RESET#). Revision 1.2 23 65540 / 545 ME 205811b 001175) 282Pin Diagram DRAM"A" DisplayMemory Lower512KB (WEAH#) _ WEA# CASA#) CASAH# AL#) CASAL# MGNDA (ISENAG MADO (ICTENA#) MAD} MAD2 MAD3 MAD4 MADS5 MADI15 STNDBY# "reserved" A2 reserved A3 " ce reserved A4 "reserved" AS . GND reserved A6 "reserved" Al "reserved" Ag "reserved" AQ "reserved" AlQ reserved All "reserved" Al2 reserved Al3 ireserved" Al4 reserved Al5 ureserved" Al6 reserved Al7 "reserved" Al8 "reserved" Al9 "reserved" A20 reserved A2l Clock XTALI Group Gece CvVCC1 RESET# GND1 Bus Interface Group aaa a4 3 Rae es . DRAM'B' DRAM'C" ZO WAQ DisplayMemoryUpper512KB FramBuffer Begsnans RESSRSGESARSRT GP op REEL Per eOOOOOURMEMEA pra Bit OUOCCOCY SSS PC-Video nT Beo HE tnstemaco S 2 Interface AECAAPRERERR RS Rim SrA Ramm MRI BOSH OS mrmont nc ChnV BAZAAARAAgAaAR AAR a sRanAAAAAARRAagARACAAS Selle et eet eo MP Aenea ene AAEg mA AMM A FOO OOUOOOLOOUUF OO LLL LE LES po i ii NSE Cs a Daa BEBE RS NewWwY BARAR WW TMA Oqoor' S$ SDCOE\OU TON SOND OW TOON SON OWT MAAODWE ON WANN st St DTFOIAENCACHE MME EOANQNNOANNA Ste tt Stet Set SOOO REE CASClal Configuration Pins see CASCH: 2X# =0 2XLCLK Bese Ck WEG OS# =0 External Oscillator (1=Xtal) oS OECH AD# =0 ENABKL & ACTI are A26,A27 22 CAS TS# =0 Enable Clock Test Mode CA8 LV# = 0 Input Threshold Level Control Ga: CA5 CA4 CA3 9 CA2 CAL CAO J DGND P15 Pl4 P13 Flat Panel VGA Controller bit Panel bo ane 10/30/95 Iaantace BE Pb ce Group be Pin names shown indicate VL-Bus connections (Default) IGND Pin names in brackets <...> indicate ISA-Bus connections (ISA# = 0) P4 Pin names in quotes "... indicate PCI-Bus connections (LB# = 0) B Pin names in parentheses indicate alternate functions PI PO SHFCLK| he (RE BLANKH M Ae DE)(BLANK# by & 2e DYCC by oF HSYNC n mans 6 YSYNC ical ao GND & SS 62|[E ENAVD. ~ ~ (ENABKL) 60 RED an 4 8IIE GREEN AAAAAAAA AAAAA tt BBSSIUTs S88G828 0 58 8 Z| IE Ran EPPO EEE LER REN Mees Acs 5 EEUSTE38 22 Gpla Reeatece acs 4] E ENABKI oye vvuiy vivuvyvuvuVWY VV 3) JR AcTI SoNM TOE OADM TW NOr-wO* ICI SEIN NOI 0 CN Ht St tH I AIOIOIOQIAIOINIQIING) 200M t te BOO Os EEF OMe tintin tm GOR Qos onde MIAIACIA ANAS SS NZ nN nt ee at a ed ped a AARASS Ee ASAARAAAALAR BECO een EER ARO SARAARRARS as aan (=a) a ps ee Ss me a Qa mS mbobocine SQN Roo sotto} Hak a Se Soin macS Deo HM OINtMARO BRARAARA Re AaAAAAAAgSAan lohsniiatavalatatat ao eaqsecaaa Atta ae ASSESSES ES Fy Bn BASSSSS z = oie Ue Tes (e's TF = rp = Urey pT s TEAS s 3 ACTI = (GPIQ) (A26) (VBO} ENABKL = (GPIO) (A27) (VB1) + In 2x clock mode, pin 23 becomes CRESET instead of RDYRTN# tt In Test mode, pin 29 becomes VCLKOUT and pin 30 becomes MCLKOUT Revision 1.2 24 65540 / 545 MB 20594116 0011752 119Pin List Pin Name Pin # Dir Drive] |Pin Name Pin # Dir Drive} |Pin Name Pin # Dir Drive A2 179 In |}DO "ADO" 51 VO 8mA||MBD4 131 VO 2mA A3 180 In |}D1 ADI 50 VO 8mA||MBD5 132 VO 2mA A4 182 In ]}D2 "AD2" 49 I/O 8mA}|MBD6 133 VO 2mA AS 183 In |}D3 "AD3" 48 VO 8mA}|MBD7 134 VO 2mA A6 185 In ||D4 "AD4" 47 VO 8mA]|MBD8 135 VO 2mA A7 186 In |}D5 "ADS" 46 VO 8mA]|MBD9 136 VO 2mA A8 187 In ||D6 AD6" 45 VO 8mA]|MBDI10 137 VO 2mA Ad 188 In |}D7 "ADT" 44 VO 8mA]|MBD11 138 VO 2mA Al0O 189 In ]|ID8 "AD8 41 VO 8mA]|]MBD12 140 VO 2mA All 199 In |}D9 "ADO" 40 WO 8mA|/|MBD13 141 VO 2mA Al2 191 In }}D10 "ADIO" 38 VO 8mA]|MBD14 143. VO 2mA Al3 192 In ]/D1i1 "AD11" 37 VO 8mA}/|MBDI15 144 VO 2mA Al4 193 In |ID12 "AD12" 36 WO 8mA||MCDO (VB2) 106 VO 2mA Al5 194 In [}D13 "ADI3" 35 VO 8mA}|/MCD1_ (VB3) 107 VO 2mA Al6 195 In ]}D14 "AD14" 34. VO 8&mA]|]MCD2_ (VB4) 109 VO 2mA Al7 (LA17) 196 In |}DI5 "ADIS" 33 VO 8mA;|MCD3 (VB5) 110 VO 2mA Al8 (LA18) 197 In }f}D16 (ZWS#) "AD16" 20 WO 8mAI|MCD4 (VB6) 111 VO 2mA Al9 (LA19) 198 In #]D17. (MCSI16#) "AD17" 19 VO 8mA]|]MCD5 _ (VB7) 112 VO 2mA A20 (LA20) 199 In |/D18 (OCS16#) "AD18" 18 VO 8mAl|MCD6 = (VG2) 113. VO 2mA A21 (LA21) 200 In ]]{DI9 "AD19" 17 VO 8mA}]/MCD7 (VG3) 114. YO 2mA A22 (LA22) "CLK" 201 In |]D20 "AD20" 16 VO 8mAT]MCD8 (VG4) 115 VO 2mA A23 (LA23) 28 %In {]D21 "AD21" 18 VO 8mA}|MCD9 (VG5) 1146 VO 2mA A24 (ROMCS#) "PERR#" 29 VO 8mA]/D22 "AD22" 14 VO 8mA]|MCD10 (VG6) 117 VO 2mA A25 (RQ) "SERR# 30 VO 8mA]/D23 "AD23" 13. VO 8mA]|MCDi1 (VG7) 118 VO 2mA AAO (CFGO) (LB#) 145 VO 4mA{|/D24 ~ "AD24" 8 VO 8mA||MCD12 (VR2) 119 VO 2mA AAI (CFG1) (SA#) 146 VO 4mA]]D25 "AD25" 7 VO 8mA|]jJMCD13 (VR3) 120 VO 2mA AA2 (CFG2) (2X#) 147 VO 4mA|]D26 "AD26" 6 VO 8mA|}MCD14 (VR4) 121 VO 2mA AA3 (CFG3) 148 VO 4mA]|]D27 "AD27" 5 VO 8mA||MCDI5 (VRS) 122 YO 2mA AA4 (CFG4) 149 VO 4mA]]D28 "AD28" 4 YO &mA!/}MGNDA (Memory A) 1461 AAS (CFG5) (OS#) 150 TO 4mA]{D29 "AD29" 3 WO 8mA{|]MGNDB (Memory B) 139 AA6 (CFG6) (AD#) 151 VO 4mA]|D30 "AD30" 2 VO &mA]|MGNDC (Memory C) 105 AAT (CFG7) (TS#) 152 VO 4mA]{D31 "AD31" 1 VO 8mA||MAO# (AEN) "PAR" 31 VOt 4mA AA8 (CFG8) (LV#) 153. YO 4mA]}DGND (Display) 63 |JMVCCA (Memory A) 158 AA9 (32KHZ) (VRO) 154 VO 4mA]{DGND (Display) 89 |{MVCCB (Memory B) 142 ACTI (A26) (VBO) 53 VO 8mA]IDVCC (Display) 66 |JMVCCC (Memory C) 108 ADS# (ALE) "FRAME#" 22 In - |}ENABKL(A27) (VB1) 54 VO 8&mA|/OEAB# 155 Out 4mA AGND 56 |{IENAVDD 62 Out 8mA||OEC# (VR1) 100 VO 4mA AVCC 59 |}/ENAVEE(ENABKL) 61 Out 8mA]}PO 71 Out 8mA BEO# (AO) C/BEO#" 43 In ||FLM 67 Out 8mA}|Pl 72 Out 8mA BE1# (BHE#) "C/BE1#" 32 In ||GREEN 58 Out |/P2 73, Out 8mA BE2# (Al) "C/BE2#" 21 In |}HSYNC 65 Out 12mA}}P3 74 Out &mA BE3# (RFSH#) "C/BE3#" 10 In J]IGND (Internal Logic) 77 4)P4 75 Out 8mA BLUE 57 Out |}IGND (Internal Logic) 184 {]P5 76 Out 8mA BGND (Bus) 12 |{IVCC (internal Logic) 80 ||P6 78 Out 8mA BGND (Bus) 26 {]IVCC (internal Logic) 181 }|}P7 79 Out 8mA BGND (Bus) 39 ||LCLK (IORD#) "STOP#" 27 In ||P8 81 Out 8mA BGND (Bus) 52 ||LDEV# (IOWR#) "DEVSEL#" 25 T/O 12mA]|P9 82 Out 8mA BVCC (Bus) 9 |{LRDY# (RDY) "TRDY#" 24 Out 12mA/|/P10 83 Out 8mA BVCC (Bus) 42 ||LP (BLANK#)(DE) 68 Out 8mA|{P11 84 Out 8mA CAO (P16) 90 Out 4mA|[M (BLANK#)(DE) 69 Out 8mA|{P12 85 Out 8mA CAl (P17) 91 Out 4mA]{MADO (TSENA#) 162 VO 2mA}{P13 86 Out 8mA CA2 (P18) 92 Out 4mA||MAD1 (ICTENA#) 163 VO 2mA|}P14 87 Out 8mA CA3 (P19) 93. Out 4mA]{MAD2 164 VO 2mA}{P15 88 Out 8mA CA4 (P20) 94 Out 4mA]]MAD3 165 VO 2mA||RASA# 156 Out 4mA CAS (P21) 95 Out 4mA]|/MAD4 166 VO 2mA|{RASB# 123 Out 4mA CA6 (P22) 96 Out 4mA||MADS 167 VO 2mA|}RASC# (KEY) 101 VO 4mA CAT (P23) 97 Out 4mA!|MAD6 168 WO 2mA||RRTN#<MEMW#: "IRDY#" 23 In CA8 (VG1) 98 VO 4mA||MAD7 169 VO 2mA|/RED 60 Out CA9 (VGO) 99 VO 4mA}|MAD8 170 VO 2mA||RESET# (540 Rev 0=RESET) 207 In CASAH# (CASA#) 159 Out 4mA{|/MAD9 171 VO 2mA||/RSET 55 In CASAL# (WEAL#) 160 Out 4mA|)}MAD10 172 VO 2mA}|SHFCLK 70 Out 8mA CASBH# (CASB#) 125 Out 4mA}|/MAD11 173, YO 2mA}|STNDBY# 178 In CASBL# (WEBL#) 126 Out 4mA|}MAD12 174 VO 2mA||/VSYNC 64 Out 12mA CASCH# (CASC#) (VR7) 103 VO 4mA||MAD13 175 VO 2mA||WEA# (WEAH#) 157 Out 4mA CASCL# (WECL#(VR6) 104. YO 4mA||MAD14 176 VO 2mA||WEB# (WEBH#) 124 Out 4mA CGNDO (Clock) 202 -- |}MADI15 177, VO 2mA]|WEC# (WECH#(PCLK) 102 Out 4mA CGNDI1 (Clock) 208 |i{MBDO 127 VO 2mA]}W/R# (MEMR#)"IDSEL" 11 Ino CVCCO (Clock) 205 |/MBD1 128 WO 2mA]|XTALI 203 In CVCC1 (Clock) 206 |IMBD2 129 VO 2mA||XTALO 204 Out Note: Drive = 5V_ low drive and 3V_ high driv |MBD3 130 VO 2mA}}{ W/O in 65545 only for PCI, In for 65540 Revision 1.2 25 65540 / 545 Mi 2098116 0011753 055SHEESS SESE ESTEE, pIEEE ere Lr 5 r > Pin Lists PIN LIST-BUS INTERFACE 12.12. 150 Polo dilibebebitebibebeteb dol lo tobebol bibetibibed Pb debebibibibileliblat obo bibodetebebel bibetebitad PRC tb bbb bebe ob bbb batt C} + These two pins usually function as ACTI and ENABKL, but can be reconfigured as additional address msbs (for 386/486/VL-Bus only) via configuration bit-6 (see other tables and pin descriptions for more details) Tt} In internal clock synthesizer test mode, MCLK is output on A25 and VCLK is output on A24, LB# ISA# 2X# Buonfiguration 1 1 1 VL-Bus (1x clock) Pin-23 = RDYRTN# 1 1 0 CPU-Direct (2x clock) Pin-23 = CRESET 1 0 1 ISA Bus 1 0 0 -reserved- 0 1 1 PCI Bus (65545 only) 0 1 0 -reserved- 0 0 1 -reserved- 0 0 Q _-reserved- Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: IOL/IOH are specified in mA; Load is specified in pF Revision 1.2 26 65540 / 545 Me 20948116 0011754 TI,LArS> Pin Lists PIN LIST -BUS INTERFACE us Dus. Bus us us Us us us us us us us us us Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: IOL/IOH are specified in mA; Load is specified in pF Revision 1.2 27 65540 / 545 MB 2094116 0011755 7265Pin Lists I nN 50. AA7___ CEG?" VG1 MCD8 VG4 | N MCDI4 VR4 Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: IOL/IOH are specified in mA; Load is specified in pF Revision 1.2 28 65540 / 545 MH 2098116 0011756 664Crir>. Pin Lists PIN PIST-CRT INTERFACE PIN LIST- POWER & GROUND PIN PIST-PANEL INTERFACE Note: ITVCC must equal CVCC PIN LIST-POWER MANAGEMENT PIN LIST-CLOCK Note: CVCC must equal VCC Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: TOL/IOH are specified in mA; Load is specified in pF Revision 1.2 29 65540 / 545 WH 20948116 0011757 7TOVrir> fabesensesca os Pin Descriptions PIN DESCRIPTIONS ISA/CPU Direct/VL-Bus Interface Pin# Pin Name Type Active Description 207 RESET# In Low Reset. For VL-Bus interfaces, connect to RESET#. For direct CPU local bus interfaces, connect to the system reset generated by the motherboard system logic for all peripherals (not the RESET# pin of the processor). For ISA bus interfaces, RESET must be inverted before connection to this pin. 22 ADS# In Low Address Strobe. In VL-Bus and CPU local bus inter- (ALE) In High faces indicates valid address and control signal infor- mation is present. It is used for all decodes and to indicate the start of a bus cycle. 31 MAO# Th Both Memory/IO. In VL-Bus and CPU local bus interfaces (AEN) In High indicates memory or I/O cycle: 1 = memory, 0= I/O. 11 W/R# In Both Write / Read. This control signal indicates a write (MEMR#) In Low (high) or read (low) operation. It is sampled on the rising edge of the (internal) 1x CPU clock when ADS# is active. 23 RDYRTN# for ix clock config In Low Ready Return. Handshaking signal in VL-Bus interface CRESET for 2x clock config In High indicating synchronization of RDY# by the local bus (MEMW#) In Low master / controller to the processor. Upon receipt of this LCLK-synchronous signal the 65540 / 545 will stop driving the bus (if a read cycle was active) and terminate the current cycle. 24 LRDY# Out/OC (RDY) Ouv/OC Low High Local Ready. Driven low during VL-Bus and CPU local bus cycles to indicate the current cycle should be completed. This signal is driven high at the end of the cycle, then tri-stated. In ISA bus interfaces, this signal is active high and may be connected directly to the ISA bus RDY pin. 25 LDEV# Out (IOWR#) In Low Low Local Device. In VL-Bus and CPU local bus interfaces, this pin indicates that the 65540 / 545 owns the current cycle based on the memory or I/O address which has been broadcast. For VL-Bus, it is a direct output reflecting a straight address decode. 27 LCLK In (IORD#) In Both Low Local Clock. In VL-Bus this pin is connected to the CPU 1x clock. In CPU local bus interfaces it is connected to the CPU 1x or 2x clock. If the input is a 2x clock, the processor reset signal must be connected to CRESET (pin 23) for synchronization of the clock phase. Note: Pin names in parentheses (...) indicate alternate functions (in this case, ISA bus control) Revision 1.2 31 65540 / 545 MB 2098116 0011758 37CAirS Pin Descriptions PIN DESCRIPTIONS ISA/CPU Direct/VL-Bus Interface (continued) Pin# Pin Name Type Active Description 43 BEO# (AO) (BLE#) In Low Byte Enable 0. Indicates data transfer on D7:DO for the current cycle. AO address input in ISA interfaces. In 16-bit local bus interfaces indicates the low order byte at the current (16-bit) word address is being accessed. 32 BE1# (BHE#) In Low Byte Enable 1. Indicates data transfer on D15:D8 for the current cycle. In ISA, indicates high order byte at the current (16-bit) word address is being accessed. 21 BE2# (Al) In Low _ Byte Enable 2. Indicates data transfer on D23:D16 for the current cycle. Al address in ISA & 16-bit local bus. 10 BE3# (RFSH#) In Low Byte Enable 3. BE3# indicates that data is to be trans- ferred over the data bus on D31:24 during the current access. Refresh input in ISA interfaces. Disconnected in 16-bit local bus interfaces. 179 <A2 In High System Address Bus. In ISA, VL-Bus, and direct CPU 180 =A3 In High _ interfaces, the address pins are connected directly to the 182 A4 In High bus. In 386 SX local bus interfaces BE2# is address 183. AS In High input Al, BEO# is BLE#, and BE1# is BHE#. In ISA 185 <A6 In High _ bus interfaces BE2# is address Al, BEO# is address 186 A7 In High AO, BE1# is BHE#, Al7-23 are LA17-23, and A24 is 187 = A8 In High ROMCS# (indicates valid ROM access to memory 188 A9 In High address range OC0000-0C7FFFh). na n ich Address inputs through A23 are always available; A24- 191 Al2 In High 27 may be optionally used for other functions: 192 A13 In High In internal clock synthesizer test mode (TS#=0 at 193 Al4 In High Reset), A24 becomes VCLK out and A25 becomes 194 Al5 In High MCLK out. 195 Al6 In High . 196 Al17 (LAI7) In High A25 may alternately be used as a programmable polarity 197 A118 (LA18) In High IRQ output. Set when interrupt on VSYNC is enabled. 198 A19 (LA19) In High Cleared by reprogramming register 11h in the CRT 199 A20 (LA20) In High Controller. See also XR14 bit~7. 200 A21 (LA21) In High For 24-bit RGB Video input, A26-27 may be used as 201 A22 (LA22) In High the two Isbs of the Blue Video, Otherwise, A26 and 28 = A23 (LA23) In High 427 may be used as General Purpose I/O pins or as 29 A24 (ROMCS#) (VOUT) YO High Activity Indicatorand Enable Backlightrespectively (see 30 A25 (IRQ) (MOUT) YO High panel interface pin descriptions and XR5C and XR72 for more details). 53. A26 (ACTI) (VBO)(GPO) YO High 54 A27 (ENBKL)(VBI)(GP1) W/O High Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 32 65540 / 545 Mi 209861316 0011759 573seeeee sees se LY irs Pin Descriptions PIN DESCRIPTIONS ISA/CPU Direct/VL-Bus Interface (continued) Pin# Pin Name Type Active Description 51 DOO vo High System Data Bus. 29 bo? to Heh In 32-bit CPU Local Bus designs these data lines 48 D03 VO High connect directly to the processor data lines. On the VL- 47 D04 VO High Bus they connect to the corresponding buffered or 46 D0S5 VO High unbuffered data signal. a ee ho HHieh In ISA bus interfaces, D16-18 become outputs for the Zero Wait State, Memory Chip Select 16, and /O Chip 4] Dos YO High Select 16 respectively. In ISA bus interfaces D19-31 40 DO09 vO High are unused and should be left disconnected. 38 D10 vO High 37 Dil fe) High 36 ~=sD12 VO High 35 D13 vo High 34 ss D14 VO High 33 D15 VO High 20 =DI16 (ZWS#) VO High 19 DIi7 (MCS 16#) @) High 18 D18s (OCS 16#) VO High 17 DI9 VO High 16 D20 VO High 15 D21 VO High 14 D22 VO High 13 D23 VO High 8 D24 1/0 High 7 D25 VO High 6 D26 VO High 5 D27 VO High 4 D28 VO High 3 D29 VO High 2 D30 VO High 1 D31 Vo High Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 33 65540 / 545 Mi 20948116 0011760 215Pin Descriptions PIN DESCRIPTIONS PCI Bus Interface (65545 Only) Pin# Pin Name Type Active Description 207 RESET# In Reset. This input is used to bring signals and registers in the chip to a consistent state. All outputs from the chip are tri-stated or driven to an inactive state. 201 CLK In High Bus Clock. This input provides the timing reference for all bus transactions. All bus inputs except RESET# and INTA# are sampled on the rising edge of CLK. CLK may be any frequency from DC to 33MHz. 31 PAR YO High Parity. This signal is used to maintain even parity across ADO-31 and C/BE0-3#. PAR is stable and valid one clock after the address phase. For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase (i.e., PAR has the same timing as ADO-31 but delayed by one clock). The bus master drives PAR for address and write data phases; the target drives PAR for read data phases. 22 FRAME# In Low Cycle Frame. Driven by the current master to indicate the beginning and duration of an access. Assertion indicates a bus transaction is beginning (while asserted, data transfers continue); de-assertion indicates the transaction is in the final data phase. 23 IRDY# In Low Initiator Ready. Indicates the bus master's ability to complete the current data phase of the transaction. During a write, IRDY# indicates valid data is present on ADO-31; during a read it indicates the master is prepared to accept data. A data phase is completed on any clock when both IRDY# and TRDY# are sampled asserted (wait cycles are inserted until this occurs). 24 TRDY# S/TS Low Target Ready. Indicates the target's ability to complete the current data phase of the transaction. During a read, TRDY# indicates that valid data is present on ADO-31; during a write it indicates the target is prepared to accept data. A data phase is completed on any clock when both IRDY# and TRDY# are sampled asserted (wait cycles are inserted until this occurs). 27 STOP# S/TS Low Stop. Indicates the current target is requesting the master to stop the current transaction. 25 DEVSEL# S/TS Low Device Select. Indicates the current target has decoded its address as the target of the current access. Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before being released, and are not driven for at least one cycle after being released by the previous device. A pull-up provided by the bus controller is used to maintain an inactive level between transactions. Revision 1.2 34 65540 / 545 Mf 2094116 0011761 1c)PIN DESCRIPTIONS Pin Descriptions PCI Bus Interface (65545 Only) Pin# Pin Name Type Active Description 29 PERR# (VCLKOUT) S/TS Low Parity Error. This signal is for the reporting of data parity errors (except for Special Cycles where SERR# is used). The PERR# pin is Sustained Tri-state and is driven active by the agent receiving the data for two clocks following the data when a data parity error is detected. PERR# will be driven high for one clock before being tri-stated as with all sustained tri-state signals. PERR# will not be reported until the 65545 has claimed the access by asserting DEVSEL# and completing the data phase. 30 SERR# (MCLKOUT) OD Low System Error. Used to report system errors where the result will be catastrophic (address parity error, data parity errors for Special Cycle commands, etc.). This output is actively driven for a single PCI clock cycle synchronous to CLK and meets the same setup and hold time requirements as all other bused signals. SERR# is not driven high by the 65545 after being asserted; it is pulled high only by a weak pull-up provided by the system, so SERR# on the PCI bus may take two or three clock periods to fully return to an inactive state. 28 Reserved 179-180 Reserved 182-183 Reserved 185-200 Reserved n/a n/a n/a n/a n/a n/a n/a n/a These pins are reserved for future use and should not be connected. All the pins in this group are tri-stated at all times in PC] interface mode. Note: S/TS stands for "Sustained Tri-state". These signals are driven by only one device at a time, are driven high for one clock before being released, and are not driven for at least one cycle after being released by the previous device. A central pull-up provided by the bus controller is used to maintain an inactive level between transactions. Revision 1.2 35 65540 / 545 MH 2094116 00117b2 Ob6eactsne Spee seeaueosscas LaAir>S Pin Descriptions PIN DESCRIPTIONS PCI Bus Interface (65545 Only) Pin# Pin Name Type Active Description 51 ADOO VO High PCI Address / Data Bus 50 ADO1 VO High 49 ADO2 VO High Address and data are multiplexed on the same pins. A 48 ADO3 0) High bus transaction consists of an address phase followed 47 ADO04 vo High by one or more data phases (both read and write bursts 46 ADO5 vO High are allowed by the bus definition). 45 ADO06 0) High 44 ADO07 vO High The address phase is the clock cycle in which FRAME# . is asserted (ADO-31 contain a 32-bit physical address). 40 a LO ee For I/O, the address is a byte address, for memory and 38 ADIO V0 Hich configuration, the address is a DWORD address. 37 OAD II 10 Hich During data phases ADO-7 contain the LSB and 24-31 36 ADI2 vO Wich contain the MSB. Write data is stable and valid when 35 ADI3 VO eh IRDY# is asserted and read data is stable and valid 34 ADI4 vO Wich when TRDY# is asserted. Data is transferred during 33 CADIS VO Eich hose clocks when both IRDY# and TRDY# are 1gn asserted. 20 ADI6 VO High C/BE3-0 CommandType 65545 19 ADIT VO High 0000 InterruptAcknowledge 18 AD18 VO High 0001 SpecialCycle 17. ADI19 vo High 0010 ORead v 16 AD20 VO High 0011 WVOWrite Y 15 AD21 vo High 0100 = -reserved- 14 AD22 YO High oi neserved a Vv i emoryRea 13, AD23 YO High 0111 MemoryWrite Vv 8 AD24 vo High 1000 -reserved- 7 AD25 vo High 1001 = -reserved- 6 AD26 vo High 1010 ConfiguratiomRead Vv 5 AD27 vO High 1011 ConfiguratioiWrite Y 4 AD28 VO High 1100 MemoryReadMultiple 3 AD29 VO High 1101 Dual Address Cycle 2 DSO Vo tien | HHI Memon Reading 1 AD31 VO High emory Read & Invalidate 43 C/BEO# In Low Bus Command / Byte Enables. During the address 32 C/BE1# In Low phase of a bus transaction, these pins define the bus 21 C/BE2# In Low command (see list above). During the data phase, these 10 C/BE3# In Low pins are byte enables that determine which byte lanes cafry meaningful data: byte 0 corresponds to ADO-7, byte 1 to 8-15, byte 2 to 16-23, and byte 3 to 24-31. 11 IDSEL In High Initialization Device Select. Used as a chip select during configuration read and write transactions. Revision 1.2 36 65540 / 545 MH 2094116 0011763 TTYste Baretta LAPS Pin Descriptions PIN DESCRIPTIONS Display Memory Interface Pin# Pin Name Type Active Description 145 AAO (LB#) (CFGO) VO High Address bus forDRAMs A and B. 146 AAI. (SA#) (CFG1) YO High 147. AA2 (2X#) (CFG2) VO High Please see the configuration table in the Extended 148 = AA3 (Reserved)(CFG3) VO High Register description section for complete details on the 149 AA4 (Reserved)(CFG4) VO High configuration options (XRO1 and XR6C). 150 AAS (OS#) (CFG5) VO High 151 =AA6 (AD#) (CFG6) VO High 152 = AA7 (TS#) (CFG7) W/O High 153. AA8 (LV#) (CFG8) YO High 154. AAQ (32KHz) (VRO) YO High AAQ, alternately, becomes clock input for refresh of non-self-refresh DRAMs and panel power sequencing or video input red Isb. 90 CAO (P16) Out High Address bus for DRAM C. 91 CAI (P17) Out High 92 CA2 (P18) Out High 93 CA3 (P19) Out High 94 CA4 (P20) Out High 95 CA5 (P21) Out High 96 CA6 (P22) Out High 97 CA7 (P23) Out High 98 CA8 (VG1) YO High 99 CA9 (VGO0) YO High 156 RASA# Out Low Rowaddress strobe for DRAMA 123. RASB# Out Low Row address strobe for DRAM B 101 RASC# Out Low Rowaddress strobe for DRAM C (KEY) In High _ orcolorkey input from external video source 160 CASAL# (WEAL#) Out Low Columnaddress strobe for the DRAM A lower byte 159 CASAH#(CASA#) Out Low Columnaddress strobe for the DRAM A upper byte 126 CASBL# (WEBL#) Out Low Column address strobe for the DRAM B lower byte 125. CASBH# (CASB#) Out Low Column address strobe for the DRAM B upper byte 104 CASCL# (WECL#) (VR6) YO Both CAS forthe DRAM C lower byte or video in red bit-6 103. CASCH#(CASC#) (VR7) YO Both CAS forthe DRAM C upper byte or video in red bit-7 157 WEA# (WEAH#) Out Low WriteenableforDRAMA 124 WEB# (WEBH#) Out Low WriteenableforDRAMB 102 WEC# (WECH#)(PCLK) Out Both Write enable for DRAM C or video in port PCLK out 155 OEAB# Out Low Outputenable for DRAMs A andB 100 OEC# (VR1) YO Both Outputenable for DRAMC or video in red bit-1 Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 . 37 65540 / 545 ME 27094116 0011764 9130gRIE HE EEEe items LPP Pin Descriptions PIN DESCRIPTIONS Display Memory Interface (continued) Pin# Pin Name Type Active Description 162 MADO (TSENA#) Vo High Memory data bus for DRAM A (lower 512KB of 163 MADI (UCTENA#) VO High displaymemory) 164 MAD2 VO High 165 MAD3 VO High 166 MAD4 vO High 167 MADS VO High 168 MAD6 Vo High 169 MAD7 VO High 170 MAD8 Vo High 171 MAD9 vo High 172. MADIO vO High 173 MADI1 VO High 174 MAD12 VO High 175 MAD13 vo High 176 MAD14 1/0 High 177. MADIS YO High 127. MBDO vo High Memory data bus for DRAM B (upper 512KB) 128 MBDI1 Vo High 129. MBD2 VO High 130 MBD3 Vo High 131 MBD4 vO High 132. MBDS5 Vo High 133. MBD6 VO High 134. MBD7 YO High 135 MBD8 To High 136 MBD9 VO High 137 MBD10 vO High 138 MBD11 vo High 140 MBD12 vO High 141. MBD13 vo High 143. MBD14 VO High 144 MBD15 vo High 106 MCDO- (VB2) VO High Memory data bus for DRAM C (Frame Buffer) 107. MCD1 (VB3) 18) High 109 MCD2 - (VB4) VO High When a frame buffer DRAM is not required, this bus 110 MCD3 _ (VB5) vo High may optionally be used to input up to 24 bits of RGB 111 MCD4 ~~ (VB6) VO High data from an external PC-Video subsystem. For the 112, MCDS (VB7) VO High remaining pins of the 24-bit video input port see the pin 113. MCD6 (VG2) YO High descriptions of DRAM C address, DRAM C control, 114. MCD7 (VG3) VO High AA9, ACTI, and ENABKL. Note that this configu- 115 MCD8 = (VG4) VO High ration also provides for additional panel outputs so that 116 MCD9 = (VG5) Vo High a full 24-bit video input port may be implemented along 117. MCDI0 (VG6) VO High with a 24-bit true-color TFT panel (TFT panels never 118 MCDI11 (VG7) VO High needDRAMC). 119 MCD12 (VR2) YO High 120 MCDI13 (VR3) T/O High 121 MCDI14 (VR4) Vo High 122. MCDIi5 (VRS) vo High Note: Pin names in parentheses (...) indicate alternate functions. Note: If ICTENA# is low with RESET# low, a rising edge on XTALI will put the chip into In Circuit Test mode. In ICT mode, all digital signal pins become inputs which are part of a long path starting at ENAVDD (pin 62) and proceeding to lower pin numbers around the chip to pin 1 then to pin 208 and ending at VSYNC (pin 64). If all pins in the path are high, the VSYNC output will be high. If any pin is low, the VSYNC output will be low. Thus the chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a time and observing the effect on VSYNC. XTALI must be toggled last because rising edges on XTALI with ICTENA# high or RESET# high will exit ICT mode. As a side effect, ICT mode effectively 3-states all pins except VSYNC. If TSENA# is low with RESET # low, a rising edge on XTALI will 3-state_all pins. An XTALI rising edge without the enabling conditions exits 3-state. Revision 1.2 38 65540 / 545 mM 2098116 0011765 477Pin Descriptions PIN DESCRIPTIONS Flat Panel Display Interface Pin# Pin Name Type Active Description 71 PO Out High 8, 9, 12, or 16-bit flat panel data output. 18-bit and 24- 72 ~Pi Out High bit panel interfaces may also be supported (see CA0-7 73 P2 Out High for P16-23). Refer to the table below for configurations 74 B3 Out High for various panel types. 75 P4 Out High 76 PS Out High 78 P6 Out High 79 P7 Out High 81 P8 (SHFCLKU) Out High 82 P9 Out High 83 P10 Out High 84 Pll Out High 85 P12 Out High 86 P13 Out High 87 = P14 Out High 88 P15 Out High 70 SHFCLK (CL2) (SHFCLKL) Out High Shift Clock. Pixel clock for flat panel data. 67 FLM Out High First Line Marker. Flat Panel equivalent of VSYNC. 68 LP (CLI) (DE)(BLANK#) Out High Latch Pulse. Flat Panel equivalent of HSYNC. 69 M (DE) (BLANK#) Out High M signal for panel AC drive control (may also be called ACDCLK). May also be configured as BLANK# or as Display Enable (DE) for TFT Panels (see XR4F bit-6). 62 ENAVDD Out High Power sequencing controls for panel driver electronics 61 ENAVEE (ENABKL) Out High voltage Vppand panel LCD bias voltage VEE 53 ACTI (GP0)(VB0)(A26) I/O High Activity Indicator and Enable Backlight outputs. May 54 ENABKL (GP1)(VB1)(A27) VO High be configured for other functions (see Extension Registers XR5C and XR72 and pin descriptions of MCD0-15 and A26/A27 for more information). Mono Mono Mono Color Color Color ColorSTN Color Color Color 6554x 6554x SS DD DD TET TFT TFT HR STN SS_ STN SS STN DD STN DD Pin#f PinName 8-bit 8-bit 16-bit 9/12/16-bit 18/24-bit 18/24-bit 8-bit(X4bP) 16-bit(4bP) 8-bit(4bP) 16-bit(4bP) 71 PO - UD3 UD7 BO BO BOO Rl... RI... URI... URO... 72 Pl - UD2 UD6 Bi Bl BOl Bl... Gl... UGI... UGO... 73 P2 - UD1 UDS5 B2 B2 B02 G2... Bl... UBI... UBO... 74 P3 - UDO UD4 B3 B3 BO3 R3... R2... UR2... URI... 75 P4 - LD3 UD3 B4 B4 B10 B3... G2... IRI... LRO... 76 P5 - LD2 UD2 GO B5 Bll G4... B2.. LGl... LGO... 78 P6 - LDI UDI G1 B6 B12 RS... R3... LBI1... LBO... 79 P7 - LDO UbBO G2 B7 B13 B65... G3... LR2... LRI1... 81 P8 PO - LD7 G3 GO GOO SHFCLKU _ B3.. - UG... 82 P9 Pl - LD6 G4 Gl GO0l - R4.. - UBI1... 83 Pi0 P2 - LDS GS G2 G02 ~ G4... - UR2... 84 Pll P3 - LD4 RO G3 G03 - B4.. - UG2... 85 P12 P4 - LD3 R1 G4 Gi0 - RS.. - LG!1.. 86 P13 PS - LD2 R2 G5 Gil - GS... - LB1. 87 P14 P6 - LD1 R3 G6 G12 - BS.. - LR2?... 88 P15 P7 - LDO R4 G7 G13 - R6 - LG2... 90 P16 - - - - RO ROO - - - - 91 Pi7 - - - - RI RO1 - - - - 92 PI8 - - - - R2 RO2 - - - - 93 P19 - - - - R3 RO3 - - _ - 94 P20 - - - - R4 R10 - - - - 95 P21 - - - _ RS Ril - - - _~ 96 P22 - - - - R6 R12 - - - - 97 P23 - - - - R7 R13 - - - - 70 SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLK SHFCLKL SHFCLK SHFCLK SHFCLK Pixels / Clock: 8 8 16 1 1 2 2-2/3 -1/3 2-2/3 5-1/3 Revision 1.2 39 65540 / 545 ME 2098116 OOL17bb 703Pin Descriptions CRT and Clock Interface Description CRT Horizontal Sync (polarity is programmable) CRT Vertical Sync (polarity is programmable) CRT analog video outputs from the internal color palette DAC. Set point resistor for the internal color palette DAC. A 27002 1% resistor is required between RSET and AGND. Analog power and ground pins for noise isolation for the internal color palette DAC. AVCC should be isolated from digital VCC as described in the Functional- Description of the internal color palette DAC. AGND should be common with digital ground but must be tightly decoupled to AVCC. See the Functional Description of the internal color palette DAC for further information. Crystal In. When the internalclock synthesizer is used, this pin serves as either the series resonant crystal input or as the input for an external reference oscillator (usually 14.31818 MHz). Note that in test mode for the internal clock synthesizer, MCLK is output on A25 (pin 30) and VCLK is output on A24 (pin 29). Crystal Out. When the internal oscillator is used, this pin serves as the series resonant crystal output. When an external oscillator is used, this pin must be left disconnected. PINDESCRIPTIONS Pin# Pin Name Type Active 65 HSYNC Out Both 64 VSYNC Out Both 60 RED Out High 58 GREEN Out High 57 BLUE Out High 55 RSET In n/a 59 =AVCC vcc -- 56 AGND GND - 203 XTALI (MCLK) VO High 204 XTALO Out High 205 CVCCO vcc -- 202 CGNDO GND - 206 CVCC1 vcc -- 208 CGND1 GND - Analog power and ground pins for noise isolation for the internal clock synthesizer. Must be the same as VCC for internal logic. VCC/GND pair 0 and VCC/GND pair 1 pins must be carefully decoupled individually. Refer also to the section on clock ground Jayout in the Functional Description. Note that the CVCC voltage must be the same as the voltage for the internal logic (IVCC). Note: Pin names in parentheses (...) indicate alternate functions Revision 1.2 40 65540 / 545 M8 2098116 0011767 LOTsanen @ CAirs Pin Descriptions CRT/Panel Output Signal Status During Standby Mode 6554x Pin #: Signal Name Signal Status Signal Polarity 67 FLM Forced Low XR54 bit 7 68 LP Forced Low XR54 bit 6 70 SHFCLK Forced Low N/A 69 M Forced Low N/A 71 PO Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) a 72 _ Pil Forced Low __XR61 bit 7 (text); XR63 bit 7 (graphics) | 73 P2 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) TA P3 Forced Low XR6I bit 7 (text); XR63 bit 7 (graphics) 75 P4 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 76 PS Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 78 P6 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 79 PT. ForcedLow | XR61 bit 7 (text); XR63 bit 7 (graphics) 81 P8 Forced_Low XR61 bit 7 (text); KR63 bit 7 (graphics) 82 P9 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 83 P10 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 84 Pil Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 85 P12 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) oe BE P13 Forced Low XR61 bit 7 (text); XRO3 bit 7 (graphics) en P14 ForcedLow XRG bit 7 (text); XR63 bit 7 (graphics) 88 P15 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 90 P16/CAO Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 91 P17/CAI1 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 92 P18/CA2 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 93 P19/CA3 Forced Low XR6I bit 7 (text); XR63 bit 7 (graphics) 94" PRO/CA4 ForcedLow _-XR61 bit 7 (text); XR63 bit 7 (graphics) 95 P21/CA5 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 96 P22/CA6 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 97 P23/CA7 Forced Low XR61 bit 7 (text); XR63 bit 7 (graphics) 62 ENAVDD Forced Low N/A 61 ENAVEE Forced Low N/A 54 ENABKL/A27__ForcedLow N/A 65 HSYNC ForcedLow N/A 64 VSYNC _ ForcedLow N/A 53 ACTYV/A26 : ForcedLow N/A 60,58:57 RGB __ForcedLow N/A Display Memory Output Signal Status During Standby Mode 6554x Pin # Notes: 123 Name RASB# Status Driven Low see note see note see note see note see 1 These pins are inputs when using the video input port. These pins are driven as outputs when using a frame buffer DRAM. Revision 1.2 MBH 2098116 0011768 Sob 65540 / 545Pin Descriptions PIN DESCRIPTIONS Power/Ground and Standby Control Pin# Pin Name Type Active Description 178 STNDBY# In Low Standby Control Pin. Pulling this pin to ground places the 65540 / 545 in Standby Mode. 80 IVCC Vee - Power / Ground (Internal Logic). SV+10% or 3.3V 77 IGND Gnd - +0.3V. Note that this voltage must be the same as CVCC (voltage for internal clock synthesizer). 181 Ivcc Vec - 184. IGND Gnd - 9 BVCC Vec - Power / Ground (Bus Interface). 5V+10% or 3.3V 12 BGND Gnd - +0.3V. 26 BGND Gnd - 42 BVCC Vec - 39 BGND Gnd - 52 BGND Gnd - 66 DVCC Vcc - Power / Ground (Display Interface). 5V+10% or 3.3V 63 DGND Gnd - +0.3V. 89 DGND Gnd - 158 MVCCA Vec - Power / Ground (Memory Interface A). 5V+10% or 161 MGNDA Gnd - 3.3V +0.3V. 142 MVCCB Vee - Power / Ground (Memory Interface B). 5V+10% or 139 MGNDB Gnd - 3.3V +0.3V. 108 MVCCC Vee - Power / Ground (Memory Interface C). 5V+10% or 105 MGNDC Gnd - 3.3V +0.3V. Bus/ClockOutputSignalStatusDuringStandbyMode Signal Status 6554x Pin # SignalName VL-Bus ISA Bus 204 XTALO Driven (see note 1): Driven (see note 1) 29 ROMCS# / A24 N/A Driven High 30 IRQ / A25 N/A Tri-Stated 53 ACTI/ A26 (see previous page) N/A 54 ENABKL / A27 (see previous page) N/A 24 LRDY#/RDY Tri-Stated Tri-Stated 25 LDEV# Driven High N/A 51-44, 41-40,38-33 DO-15 Tri-Stated Tri-Stated 20 D16/ZWS# Tri-Stated Tri-Stated 19 D17 / MCS16# Tri-Stated Tri-Stated 18 D18 / IOCS16# Tri-Stated Tri-Stated 17-13, 8-1 D19-31 Tri-Stated Tri-Stated Notes: 1 The XTALO pin will always be driven except when XR33 bit-2 is set to 1. Revision 1.2 42 65540 / 545 m@ 2094116 0011769 4lieatsescs Sa 55 sussenatesse @ Lrirs T/OMap 1/O Map Portiddress Read Write [102 {Global Enable (ISA Bus Only) {Global Enable (ISA Bus Only) | 3B0 Reservedfor MDA/Hercules ReservedforMDA/Hercules z 3Bl Reserved for MDA/Hercules Reserved forMDA/Hercules Mono [| 3B2 ReservedforMDA/Hercules ReservedforMDA/Hercules Mode 3B3 Reservedfor MDA/Hercules ReservedforMDA/Hercules 3B4 CRTC Index CRTC Index 3B5 CRTCData CRTCData 3B6 ReservedforMDA/Hercules Reserved forMDA/Hercules 3B7 Reservedfor MDA/Hercules ReservedforMDA/Hercules 3B8 Hercules Mode Register(MODE) Hercules Mode Register(MODE) 3B9 -- Set Light Pen FF (ignored) 3BA Status Register (STAT) Feature Control Register (FCR) 3BB -- Clear Light Pen FF (ignored) 3BC r . { 3BD } Reserved for system parallel port i | 3BE 3BF Hercules Configuration Register(HCFG) _|Hercules Configuration Register (HCFG) 3CO Attribute Controller Index /Data Attribute ControllerIndex/Data 3Cl Attribute Controller Index/Data Attribute ControllerIndex /Data 3C2 Feature Read Register (FEAT) Miscellaneous Output Register (MSR) 3C3 Video Subsystem Enable (VSE)(LB Only) |Video Subsystem Enable (VSE)(LB Only) 3C4 Sequencer Index Sequencer Index 3C5 SequencerData SequencerData 3C6 Color Palette Mask Color Palette Mask 3C7 Color Palette State Color Palette Read Mode Index 3C8 Color Palette Write Mode Index Color Palette Write Mode Index 3C9 Color Palette Data ColorPalette Data 3CA Feature Control Register (FCR) - 3CB -- -~ 3CC Miscellaneous OutputRegister(MSR) -- 3CD -- -- 3CE Graphics Controller Index Graphics Controller Index 3CF Graphics Controller Data Graphics Controller Data n3D0+t 32-Bit DR Register Extensions (65545 only) |32-Bit DR Register Extensions (65545 only) n3D1f 32-Bit DR Register Extensions (65545 only) |32-Bit DR Register Extensions (65545 only) n3D2t 32-Bit DR Register Extensions (65545 only) |32-Bit DR Register Extensions (65545 only) n3D3 32-Bit DR Register Extensions (65545 only) |32-Bit DR Register Extensions (65545 only) 0Q3D4 CRTC Index CRTC Index Color L. 03D5 CRTCData CRTCData Mode 03D6 CHIPS Extensions Index CHIPS Extensions Index 03D7 CHIPS Extensions Data CHIPS Extensions Data 03D8 CGA Mode Register(MODE) CGA Mode Register(MODE) 03D9 CGA Color Register (COLOR) CGA Color Register (COLOR) 03DA Status Register (STAT) Feature Control Register (FCR) 03DB -- Clear Light Pen FF (ignored) 03DC ~ Set Light Pen FF (ignored) [46E8 I+ [Setup Control (ISA Bus Only) { 32-Bit register addresses are of the form 'bnnn nnlb bbbb bb00' where 'bbbbbbbb' is specified by /O base register XRO7 and 'nonnn' specifies 1 of 32 DRxx 32-bit registers Revision 1.2 43 65540 / 545 ME 2098116 0011770 134Register Summary | REGISTER SUMMARY -CGA, MDA, AND HERCULES MODEs Register Register Name Bits Access /OPort-MDA/Herc YV/OPort-CGA Comment STOO (STAT) Display Status 7 R 3BA 3DA CLPEN Clear Light Pen Flip Flop O Wi(n/a) 3BB(ignored) 3DB(ignored) ref only: no-light pen SLPEN Set Light Pen Flip Flop 0 Waa) 3B9(ignored) 3DC (ignored) _ ref only: no light pen MODE CGA/MDA/Hercules Mode Control 7 R/W 3B8 3D8 COLOR CGA Color Select 6 R/W n/a 3D9 R/W at XR7E also HCFG Hercules Configuration 2 WwW 3BF n/a R 3D6-3D7 index 14 na XR14 RX, RO-11 6845 Registers 0-8 R/W 3B4-3B5 3D4-3D5 XRX, XRO-7F Extension Registers 0-8 = R/W 3D6-3D7 3D6-3D7 | REGISTER SUMMARY-EGA MODE | . Register Register Name Bits Access YOPort-Mono T/OPort-Color Comment MSR Miscellaneous Output 7 Ww 3C2 3C2 FCR Feature Control 3 Ww 3BA 3DA STOO (FEAT) Feature Read (Input Status 0) 4 R 3C2 3C2 STO1 (STAT) Display Status (Input Status 1) 7 R 3BA 3DA CLPEN Clear Light Pen Flip Flop 0 Wava) 3BB(ignored) 3DB(ignored) ref only: no light pen SLPEN Set Light Pen Flip Flop 0 Wava) 3B9(ignored) 3DC (ignored) _ ref only: no light pen SRX, SRO-7 Sequencer 0-8 R/W 3C4-3C5 3C4-3C5 CRX, CRO-3F CRT Controller 0-8 R/W 3B4-3B5 3D4-3D5 GRX, GRO-8 Graphics Controller 0-8 R/W 3CE-3CF 3CE-3CF ARX, ARO-14 Attributes Controller 0-8 R/W 3C0-3C1 3C0-3C1 XRX, XRO-7F Extension Registers 0-8 R/W 3D6-3D7 3D6-3D7 | REGISTER SUMMARY-VGA MODE | Register Register Name Bits Access YOPort-Mono YOPort-Color Comment VSE Video Subsystem Enable 1 WwW 3C3 if LB 3C3 if LB Disabled by XR70 bit-7 SETUP Setup Control 2 Ww 46E8 if ISA 46E8 ifISA _ Disabled by XR70 bit-7 ENABLE Global Enable 1 R/W 102 if ISA 102 if ISA Setup Only in ISA Bus PRO-17 PCI Configuration 8, 16,32 R/W SystemDependent System Dependent PCI Bus Only MSR Miscellaneous Output 7 WwW 3C2 3C2 R 3CC 3CC FCR Feature Control 3 WwW 3BA 3DA R 3CA 3CA STOO (FEAT) Feature Read (Input Status 0) 4 R 3C2 3C2 STO1 (STAT) Display Status (Input Status 1) 6 R 3BA 3DA CLPEN Clear Light Pen Flip Flop 0 W(n/a) 3BB(ignored) 3DB(ignored) Ref only: No light pen SLPEN Set Light Pen Flip Flop 0 W(n/a) 3B9(ignored) 3DC(ignored) Ref only: No light pen DACMASK Color Palette Pixel Mask 8 R/W 3C6 3C6 DACSTATE Color Palette State 2 R 3C7 3C7 DACRX Color Palette Read-Mode Index 8 WwW 3C7 3C7 DACWX Color Palette Write-Mode Index 8 R/W 3C8 3C8 DACDATA Color Palette Data 0-FF 3x6 R/W 3C9 3C9 SRX, SRO-7 Sequencer 0-8 R/W 3C4-3C5 3C4-3C5 CRX, CRO-3F CRT Controller 0-8 R/W 3B4-3B5 3D4-3D5 GRX, GRO-8 Graphics Controller 0-8 R/W 3CE-3CF 3CE-3CF ARX, ARO-14 = Attributes Controller 0-8 R/W 3C0-3C1 3C0-3C1 XRX, XRO-7F Extension Registers 0-8 R/W 3D6-3D7 3D6-3D7 DROO-DROC 32-Bit Extension Registers 32 R/W n3D0-n3D3 n3D0-n3D3 = Programmable I/O address Revision 1.2 44 65540 / 545 M@@ 20598116 0011771 O70LaAIir> RegisterSummary | REGISTER SUMMARY-INDEXED REGISTERS (VGA) Register Register Name Bits RegisterType Access(VGA) AccessEGA) T/OPort SRX Sequencedndex 3 VGA/EGA R/W R/W 3C4 SRO Reset 2 VGA/EGA R/W R/W 3C5 SR1 Clocking Mode 6 VGA/EGA R/W R/W 3C5 SR2 Plane Mask 4 VGA/EGA R/W R/W 3C5 SR3 Character Map Select 6 WGA/EGA R/W R/W 3C5 SR4 Memory Mode 3 VGA/EGA R/W R/W 3C5 SR7 Reset Horizontal Character Counter 0 VGA WwW n/a 3C5 CRX CRTC Index 6 VGA/EGA R/W R/W 3B4 Mono, 3D4 Color CRO Horizontal Total 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CRI Horizontal Display End 8 VGA/SEGA R/W R/W 3B5 Mono, 3D5 Color CR2 Horizontal Blanking Start 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR3 Horizontal Blanking End 5+2+1 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR4 Horizontal Retrace Start 8 VGA/SEGA R/W R/W 3B5 Mono, 3D5 Color CR5 Horizontal Retrace End 5+2+1 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR6 Vertical Total 8 VGA/SEGA R/W R/W 3B5 Mono, 3D5 Color CR7 Overflow 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR8 Preset Row Scan 5+2 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR9 Character Cell Height 543. VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CRA Cursor Start 5+1 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CRB Cursor End 5+2 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CRC Start Address High 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CRD Start Address Low 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CRE Cursor Location High 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CRF Cursor Location Low 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color LPENH Light Pen High 8 VGA/EGA R R 3B5 Mono, 3D5 Color LPENL Light Pen Low 8 VGA/EGA R R 3B5 Mono, 3D5 Color CR10 Vertical Retrace Start 8 VGA/EGA R/W WwW 3B5 Mono, 3D5 Color CR11 Vertical Retrace End 444. VGA/EGA R/W Ww 3B5 Mono, 3D5 Color CR12 Vertical Display End 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR13 Offset 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR14 Underline Row Scan 5+2 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR15 Vertical Blanking Start 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR16 Vertical Blanking End 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR17 CRT Mode Control 7 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR18 Line Compare 8 VGA/EGA R/W R/W 3B5 Mono, 3D5 Color CR22 Graphics Controller Data Latches 8 VGA R n/a 3B5 Mono, 3D5 Color CR24 Attribute Controller Index/Data Latch 1 VGA R ia 3B5 Mono, 3D5 Color GRX Graphics Controller Index 4 VGA/EGA R/W R/W 3CE GRO Set/Reset 4 VGA/EGA R/W R/W 3CF GR1 Enable Set/Reset 4 VGA/EGA R/W R/W 3CF GR2 Color Compare 4 VGA/EGA R/W R/W 3CF GR3 Data Rotate 5 VGALEGA R/W R/W 3CF GR4 Read Map Select 2 VGA/EGA R/W R/W 3CF GRS Mode 6 VGA/IEGA R/W R/W 3CF GR6 Miscellaneous 4 VGA/EGA R/W R/W 3CF GR7 Color Don't Care 4 VGAIEGA R/W R/W 3CF GR8 Bit Mask 8 VGA/EGA R/W R/W 3CF ARX Attribute Controller Index 6 VGA/LEGA R/W R/W 3C0 (3C1) ARO-F Internal Palette Regs 0-15 6 VGA/EGA R/W R/W 3C0 BCl1) AR10 Mode Control 7 VGA/EGA R/W R/W 3C0 GBC1) AR11 Overscan Color 6 VGA/EGA R/W R/W 3C0 (3C1) AR12 Color Plane Enable 6 VGA/EGA R/W R/W 3C0 (3C1) AR13 Horizontal Pixel Panning 4 VGAIEGA R/W R/W 3C0 (3C1) ARI4 Color Select 4 VGA R/W n/a 3C0 GCI) Revision 1.2 45 65540 / 545 M@ 20598116 0011772 TO?Register Summary | EXTENSION REGISTER SUMMARY: 00-2F | CHIPS VGA Product Famil Reg Register Name Bits Access Port Reset 82C450 64300/310 65510 65530 65535 XRX_ Extension Index Register 7 RW 3D6 -XXXXXxXx ovo v v v v XROO Chip Version (65540: v=0; 65545: v=1) 8 R/O 3D7 110ivrrr Vv v v v v XRO1 Configuration 8 R/O 3D7 dddddddd V v v v v XRO2 CPU Interface Control 1 8 R/W 3D7 00000000 v v v v v XRO3 CPUInterfaceControl2 (ROM Intfc) 2 R/W 3D7J-i- - -- -- Ox . fv . . . XRO4 Memory Control 1 4 R/W 3D7 --0--000 Vv v v / / XRO5 Memory Control2 (Clock Control) 8 R/W 3D7 00000000 v : . v XRO6 Palette Control (DRAM Intfc) 8 R/W 3D7 00000000 vf v v v XRO7 VO Base (65545 Only ) 8 R/W 3D7 11110100 v . XRO8 Linear\ddressinase (LinearBaseL) 8 R/W 3D7 XXXXXXXX v / XRO9_ -reserved- (LinearBaseH) -- -- 3D7 v XROA -reserved- (XRAM Mode) -- -- 3D7 . v . . XROB CPU Paging 5 R/W 3D7 --00000 Vv v v v v XROC Start Address Top 2 R/W 3D7~ ------ xx wv / / v / XROD Auxiliary Offset 2 R/W 3D7-- - - - -- 00 v v v v v XROE Text Mode Control 6 R/W 3D7 O00000-- v v / v v XROF Software Flags 0 8 R/W 3D7 XXXXXXXX v v v v XR10 Single/Low Map 8 R/W 3D7 XXXXXKXXX oa / v v v XR11 High Map 8 R/W 3D7 XXXXXXXX vo v vf v v XR12_ -reserved- - -- 3D7 XRI3_ -reserved- -- -- 3D7 . . . . . XR14 Emulation Mode 8 R/W 3D7 0000hhOO Vv v / v v XRI15 WritProtect 8 R/W 3D7 00000000 v v v v XR16 Vertical Overflow 5 R/W 3D7 *00*000 / v XR17 Horizontal Overflow 7 RIW 3D7 0000000. v . . v XR18 Alternate H Disp End 8 R/W 3D7 XXXXXXXX wo v f dv v XR19 AlternateHSyncStart (Half-line) 8 R/W 3D7 XXXXXXXX Wo v v v v XRIA Alternate HSyne End 8 R/W 3D7 XXXXXKXX Wo / 7 v v XRIB Alternate H Total 8 R/W 3D7 XXXXXXxXx o vw J v v XRIC Alternate Blank Start/H PanelSize 8 R/W 3D7 XXXXXXXX ao v v v v XRID Alternate H Blank End 8 R/W 3D7 Oxxxxxxx ov v v v XRIE Alternate Offset 8 R/W 3D7 XXXXXXXxX wo v v v v XRIF Virtual EGA Switch Register 5 RIW 3D7 O---xxxx wo v / v XR20_ -reserved- -- = 3D7 . XR21_ -reserved- soe 3D7 v XR22 -reserved- owe 3D7 v XR23_ -reserved- -- -- 3D7 . . : v , XR24 FP AltMaxScanline 5 R/W 3D7 ee eXXXKX . . Jv / XR25 FP AltTxtHVirtPanel Size 8 R/W 3D7 XXXXXXXX v v XR26 AltHSyncStart 8 R/W 3D7 XXXXXXXXK v XR27_ -reserved- so 3D7 . . . . . XR28 Video Interface 5 RW 3D7 0000--0- Vv v 7 v v XR29 Half Line Compare 8 R/W 3D7 XXXXXXXX XR2A -reserved- -- -- 3D7 . . : . XR2B Software Flags 1 8 R/IW 3D7 00000000 v Jv v v v XR2C FLM Delay 8 R/IW 3D7 XXXXXXXX v v v XR2D LP Delay 8 R/W 3D7 XXXKXXKXX v v ? XR2E LP Delay 8 R/W 3D7 XXXKXXXX . . . v vf XR2F LP Width 8 R/W 3D7 XXXXXXXX . . v v v Reset Codes: x = Not changed by RESET (indeterminate on power-up) = Not implemented (always reads 0) d = Set from the corresponding data bus pin on falling edge of RESET = Reserved (read/write, reset to 0) h = Read-only Hercules Configuration Register Readback bits O/1 = Reset to 0/1 by trailing edge of reset r = Chip revision # (starting from 0000) Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 1.2 46 65540 / 545 = 2096116 OO1L773 543Poo ad a azancs @ Patel oe a6 ar RegisterSummary [EXTENSION REGISTER SUMMARY: 30-5F _| CHIPS VGA. Product Famil Reg Register Name Bits Access Port Reset 82450 64300/310 65510 65530 65535 XR30 Clock Divide Control 4 R/W 3D7 ooo eXxxXx v XR31 Clock M-Divisor 7 RIW 3D7 *XXXXXXX v v XR32. Clock N-Divisor 7 RIW 3D7 XXXKKXX / XR33_ Clock Control 7 RIW 3D7 0000000 v v XR34_-reserved- -- -- 3D7 XR35_-reserved- os 3D7 XR36= -reserved- - oo 3D7 XR37 = -reserved- -- -- 3D7 XR38_ -reserved- -- _ 3D7 XR39 = -reserved- woe 3D7 . XR3A Color Key 0 8 RW 3D7 XXXXXXXX v v XR3B Color Key 1 8 R/W 3D7 XKXXXXXX v 7 XR3C Color Key 2 8 R/W 3D7 XXXXXXXX v v XR3D Color Key Mask 0 8 RIW 3D7 XXXXXXXX / v XR3E Color Key Mask 1 8 R/W 3D7 XXXXXXXX v v XR3F Color Key Mask 2 8 R/W 3D7 XXXXXXXX v v XR40_ BitBLT Configuration (65545Only) 2 R/W 3D7- se - - - - xXx XR41_-reserved- so 3D7 XR42_-reserved- -- -- 3D7 XR43_=sCO-reserved- -- -- 3D7 . . . . . XR44 Software Flag Register 2 8 R/IW 3D7 XXXXXXXX . v v / v XR45 Software Flag Register 3 8 R/W 3D7 KXXXXXXX v XR46_-reserved- -- -- 3D7 XR47_-reserved- -- -- 3D7 XR48_-reserved- - -- 3D7 XR49_-reserved- -- -- 3D7 XR4A_-reserved- - - 3D7 XR4B -reserved- -- -- 3D7 XR4C_-reserved- -- - 3D7 XR4D -reserved- -- -- 3D7 XR4E_-reserved- -- - 3D7 : XR4F Panel Format 2 5 R/IW 3D7 XKX***XXX . . v XRSO Panel Format 1 8 R/iW 3D7 XXXXXXXKX v XR51_ Display Type 7 RIW 3D7 000+0000 . . v v v XR52 Power Down Control 8 R/W 3D7 00000001 . v v v v XR53_ Panel Format 3 7 RIW 3D7 *00000x0 v / v XR54_ PanelInterface 8 R/IW 3D7 XXXXXXXKX v v v XR55 H Compensation 6 R/W 3D7 XXXX**XX v v v XR56 H Centering 8 R/W 3D7 XXXXXXXX vf v v XR57_ V Compensation 8 R/W 3D7 XKXXXXXK v v v XR58 ~V~ Centering 8 R/W 3D7 XXXXXXXK v v v XR59 V Line Insertion 7 RIW 3D7 XXX *XXXX Jv v v XRSA V Line Replication 4 R/W 3D7 eee exxxXx v v v XRS5B Power Sequencing Delay 8 R/W 3D7 10000001 / v v XRSC_ Activity Indicator Control 7 RiW 3D7 Ox *xXxxxx v XR5D FP Diagnostic 8 R/W 3D7 00000000 . v XR5E ACDCLK (M) Control 8 R/W 3D7 XXXXXXXX v vw v XRS5F Power Down Mode Refresh 8 R/W 3D7 XXXXXXXX v cv Reset Codes: x = Not changed by RESET (indeterminate on power-up) = Not implemented (always reads 0) d = Set from the corresponding data bus pin on falling edge of RESET = Reserved (read/write, reset to 0) h = Read-only Hercules Configuration Register Readback bits O/1 = Reset to 0/1 by trailing edge of reset r = Chip revision # (starting from 0000) Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 1.2 47 65540 / 545 Me 2094116 0011774 &8TRegister Summary [EXTENSION REGISTER SUMMARY: 60-7F | CHIPS' VGA Product Famil Reg Register Name Bits Access Port Reset 82C450 64300/310 65510 65530 65535 XR60 Blink Rate Control 8 R/W 3D7 10000011 . v Jv vf v XR61 SmartMap Control 8 R/W 3D7 KXXXXXXX / v / XR62 SmartMap Shift Parameter 8 R/W 3D7 XXXXXXXKX v v XR63 SmartMapColorMappingControl 8 R/W = 3D7 KIXXXXXX v v vf XR64 FP Alternate Vertical Total 8 R/W 3D7 XXXXXXXX v v v XR65 FP Alternate Overflow 6 RW 3D7 XXX**XXX Jv v v XR66 FP Alternate Vertical Sync Start 8 R/W 3D7 XXXXXXXKX v / v XR67 FP Alternate Vertical Sync End 4 R/W 3D7 ooo exxxx v v v XR68 FP Vertical Panel Size 8 R/W 3D7 XXXXXXXX v v v XR69_-reserved- - 3D7 XRO6A -reserved- -- -- 3D7 XR6B -reserved- oe 3D7 . : . . . XR6C Programmable Output Drive 5 R/W 3D7 *0000d> . . v v v XR6D_ -reserved- - 3D7 . . . . XR6E Polynomial FRC Control 8 R/W 3D7 10111101 . . v vf / XR6F Frame Buffer Control 8 R/W 3D7 00000000 v v XR70 Setup/Disable Control 1 R/V 3D7 0------- v v v / v XR71_=-reserved- (GPIO Control) -- -- 3D7 vf . XR72_ ExternalDevicel/O (GPIOData) 7 RIW 3D7 0000000 v / XR73_ Miscellaneous Control 6 RW 3D7 00--0000 v v XR74_=-reserved- (Configuration2) -- -- 3D7 / XR75_-reserved- (Software Flags 3) -- -- 3D7 Jv XR76_-reserved- -- -- 3D7 XR77_-reserved- -- -- 3D7 XR78_ -reserved- -- -- 3D7 XR79_=-reserved- -- -- 3D7 XR7A_ -reserved- -- - 3D7 XR7B_ -reserved- -- -- 3D7 XR7C_ -reserved- -- -- 3D7 . XR7D_ Diagnostic 1 R/W 3D7 O0------ : . ov v XR7E CGA/Hercules Color Select 6 R/W 3D7 - -XXXXXX / v v Y ev XR7F Diagnostic 8 R/W 3D7 0Oxxxx00 v v v v Jv Reset Codes: x = Not changed by reset (indeterminate on power-up) ~ = Not implemented (always reads 0) d = Set from the corresponding data bus pin on trailing edge of reset = Reserved (read/write, reset to 0) h = Read-only Hercules Configuration Register Readback bits O/t = Reset to 0/1 by trailing edge of reset r = Chip revision # (starting from 0000) Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column Note: 82C450 & 64xxx VGAs drive CRTs only, 65xxx VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD) Revision 1.2 48 65540 / 545 Me 2098116 0011775 7lbRegister Summary | 32-BIT EXTENSION REGISTER SUMMARY | Reg DROO DRO1 DRO2 DRO3 DR04 DROS DRO06 DRO7 DRO8 DRO9 DROA DROB DROC Reset Codes: Group BitBLT BiuBLT BitBLT BitBLT BitBLT BitBLT BitBLT BitBLT Cursor Cursor Cursor Cursor Cursor S R soa x iow i Register Name Bits Access Port BitBLT Offset 16/32 BitBLT Pattern ROP 16/32 BitBLT BG Color 16/32 BitBLT FG Color 16/32 BitBLT Control 16/32 BitBLT Source 16/32 BitBLT Destination 16/32 BitBLT Command 16/32 Cursor Control 16/32 Cursor Color 0-1 16/32 Cursor Color 2-3 16/32 Cursor Position 16/32 CursorBase Address 16/32 83D0-3 87D0-3 8BD0-3 8FD0-3 93D0-3 97D0-3 9BDO-3 9FD0-3 A3D0-3 A7TD0-3 ABDO-3 AFDO-3 B3D0-3 Not changed by reset (indeterminate on power-up) et from configuration pin on trailing edge of reset ead-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) ~- ~~ XKKX XXXXXXXX KXXKXXKK XXXXXXXKX XXXXXXXX K----XXX Reset XXXXXXKK ---XXXXX XXXXXXKXX XXXXXXXX ---Oxxxx ---XXXXX ---XXXXX 00000000 XXXXXXXX XXXXXKXX XKXXXXKXXK 2-9 XXXX -- 7 XXKXK XXXXXXKK XXXXXKXK XXXXRXKXXX KXXXXXXXKX XXXXKXXKX XXXXAXXKX -- - -KXKX ee#29000 XXXXXXXX XXXXXKXXK X--- -XKX XKXXXKXK-- XXXKXXKX XXXXXXXX KKXXXXKX XXXXKXKXKX XXXXXXKX XAXAXXKKXX XXKKXXXX XXXXKAXKX 000***00 XXXXXXXX XXXXKXXX XXXXXXXX - = Not implemented (always reads 0) * = Not implemented (read/write, reset to 0) O/1 = Reset to 0/1 by trailing edge of reset Revision 1.2 Mi 2094116 0011776 49 b52 65540 / 545Register Summary [ PCI CONFIGURATION REGISTER SUMMARY | Reg Register Name Bits Access Offset Reset VENID VendorID 16 R 00h 00010000 00101100 DEVID DeviceID 16 R 02h 00000000 11011000 DEVCTL Device Control 16 R/W 04h ee 10 10000000 DEVSTAT Device Status 16 RC 06h 00000000 0------- REV Revision 8 R OB ee rrr PRG Programming Interface 8 R 09h 00000000 SUB Sub Class Code 8 R OAh 00000000 BASE Base Class Code 8 R OBh 00000011 MBASE MemoryBase Address 32 R/W 10h XXXXXXXK XXX----- tee ee eee ----0000 IOBASE J/OBaseAddress 32. R/IW 14h XXXAXXXXX XXXXXXXK KAXXXKXK-- cere 01 Note: R = Read, W = Write, C = Clear (1s written to specific bits will clear those bits) Revision 1.2 50 65540 / 545 M@ 2096116 0011777 5559Registers Registers GLOBAL CONTROL (SETUP) REGISTERS The Setup Control Register and Video Subsystem Enable registers are used to enable or disable the VGA. The Setup Control register is also used to place the VGA in normal or setup mode (the Global Enable Register is accessible only during Setup mode) The Setup Control register is used only in ISA bus interfaces; the Video Subsystem Enable register is used only in Local Bus configurations. The various internal disable bits OR together to provide multiple ways of disabling the chip; all disable bits must be off to enable access to the chip. When the chip is disabled in this fashion, only bus access is disabled; other functions remain operational (memory refresh, display refresh, etc.). Note: In setup mode in the IBM VGA, the Global Setup Register (defined as port address 102) actually occupies the entire I/O space . Only the lower 3 bits are used to decode and select this register. To avoid bus conflicts with other peripherals, reads should only be performed at the 10xh port addresses while in setup mode. To eliminate potential compatibility problems in widely varying PC systems, CHIPS' VGA controllers decode the Global Setup register at V/O port 102h only. PCI CONFIGURATION REGISTERS (65545) For PCI bus configuration in the 65545, ten 16-bit registers are implemented to allow identification of the chip, examination of various internal states, configuration of memory and I/O base addresses, and control of settings for various modes of operation. These registers are located at various offsets into the PCI configuration space which may be I/O or memory mapped depending on the system design. GENERAL CONTROL REGISTERS Two Input Status Registers read the SENSE function (Virtual Switch Register or internal RGB comparator output), pending CRT interrupt, display enable / horizontal sync output, and vertical retrace / video output. The Feature Control Register selects the vertical sync function while the Miscellaneous Output Register controls I/O address selection, clock selection, CPU access to display memory, display memory page selection, and horizontal and vertical sync polarity. CGA/HERCULES REGISTERS CGA Mode and Color Select registers are provided on-chip for emulation of CGA modes. Hercules Mode and Configuration registers are provided on- chip for emulation of Hercules mode. SEQUENCER REGISTERS The Sequencer Index Register contains a 3-bit index to the Sequencer Data Registers. The Reset Register forces an asynchronous or synchronous reset of the sequencer. The Sequencer Clocking Mode Register controls master clocking functions, video enable/disable and selects either an 8 or 9 dot character clock. A Plane/Map Mask Register enables the color plane and write protect. The Character Font Select Register handles video intensity and character generation and controls the display memory plane through the character generator select. The Sequencer Memory Mode Register handles all memory, giving access by the CPU to 4 / 16 / 32 KBytes, Odd / Even addresses (planes) and writing of data to display memory. CRT CONTROLLER REGISTERS The CRT Controller Index Register contains a 6-bit index to the CRT Controller Registers. Twenty one registers control various display functions: hori- zontal and vertical blanking and sync timing, panning and scrolling, cursor size and location, light pen, and text-mode underline. GRAPHICS CONTROLLER REGISTERS The Graphics Controller Index Register contains a 4- bit index to the Graphics Controller Registers. The Set/Reset Register controls the format of the CPU data to display memory. It also works with the Enable Set/Reset Register. Reducing 32 bits of display data to 8 bits of CPU data is accomplished by the Color Compare Register. Data Rotate Registers specify the CPU data bits to be rotated and subjected to logical operations. The Read Map Select Register reduces memory data for the CPU in the four plane (16 color) graphics mode. The Graphics Mode Register controls the write, read, and shift register modes. The Miscellaneous Register handles graphics/text, chaining of odd/even planes, and display memory mapping. Additional registers include Color Don't Care and Bit Mask. Revision 1.2 51 65540 / 545 Mi 2096116 0011778 425ATTRIBUTE CONTROLLER AND COLOR PALETTE REGISTERS The Attribute Controller Index Register contains a 5- bit index to the Attribute Controller Registers which consist of a 16-entry color lookup table with 6 bits per entry plus five additional control registers. A sixth index register bit is used to enable video. The Attribute Controller Registers handle color lookup table mapping, text/graphics mode control, overscan color selection, and color plane enabling. One register allows the display to be shifted left up to 8 pixels. Another register provides default values to extend the 6-bit lookup table values to 8 bits for modes providing less than 8 bits per pixel. The color palette registers control the interface to the on-chip color palette. This on-chip palette fully implements the functions of the VGA-standard palette Inmos IMSG176, Brooktree BT471/476, or equivalent functionality). The color palette primarily consists of a 256-entry color lookup table (also sometimes referred to as a CLUT), a mask register, index registers used to access the CLUT data, and triple 6 / 8-bit DACs used to drive analog RGB outputs to a CRT monitor. Each entry in the CLUT is 18 bits in length (6 bits each for red, green, and blue) so each CLUT data entry must be accessed sequentially as 3 separate bytes and each DAC output operates with 6 bits of resolution. In 24-bpp "True- Color modes, the CLUT is bypassed and each DAC operates with 8-bit resolution. EXTENSION REGISTERS The 65540 / 545 defines a set of extension registers (called "XR's") which are addressed with the 7-bit Extension Register Index. The I/O port address is fixed at 3D6-3D7h and read/write access is always enabled to improve software performance. The extension registers handle a variety of inter- facing, compatibility, and display functions as discussed below. They are grouped into the following logical groups for discussion purposes: 1. Miscellaneous Registers include the chip version/revision, configuration, and various interface control and diagnostic functions. 2. Mapping Registers include paging controls and base registers for relocation of /O and memory blocks. 3. Software Flags Registers provide locations for BIOS and driver software to store various temporary variable values on-chip Registers 4. Clock Registers control the operation of the on- chip clock synthesizer 5. MultimediaRegisters control the operation of the video input port color key and mask 6. BitBLTRegisters control the operation of the Bit- Block-Transfer (BitBLT) engine (65545 only) for graphicsacceleration. 7. Backwards Compatibility Registers control Hercules, MDA, and CGA emulation modes. Write Protect functions are provided to increase flexibility in providing backwardscompatibility. 8. AlternateHorizontalandVertical Registers handle all horizontal and vertical timing, including sync, blank and offset. These are used for backwards compatibility. 9. Flat Panel Registers handle all internal logic specific to driving of flat panel displays. 32-BIT REGISTERS The 65545 also implements a group of sixteen 32-bit doubleword extension registers (called "DR's"). These registers are used for control of the high performance BitBLT and Hardware Cursor subsystems and may be mapped anywhere in the /O and/or memory address space. For ISA and VL-Bus configurations, the 32-bit registers take up 32 doubleword locations in the 16- bit I/O address space (only the first 13 registers are defined; the remaining locations are reserved). An 8-bit extension register is provided to program the base address. The address is of the form bnnn nnlb bbbb bbxx (where b specifies the value programmed into the base register and 'n' selects one of the 32 register locations). The base register is typically programmed with '74h' to map the 32-bit registers to I/O addresses x3D0-x3D3h (unused ports in the standard VGA I/O address range). For PCI bus configurations, the 32-bit registers are mapped to both the memory and I/O address spaces. The PCI configuration registers contain an YO base register which defines a I1KB_ space (256 doublewords) which allows the 32-bit register space to start on any 1KB boundary in the I/O address space. In addition, the PCI memory base register specifies an 8MB memory address space; display memory is mapped into the lower 2 megabytes and the 32-bit registers are mapped into the upper 6 megabytes. Note: The state of most of the standard VGA registers is undefined at reset. The state at Reset of all registers specific to the 65540 / 545 (extension registers and 32-bit registers) is summarized in the register summary tables. Revision 1.2 65540 / 545 MH 2096116 0011779 3b]Global Control (Setup) Registers Global Control (Setup) Registers Register VO Mnemonic Register Name Index Access VO Address Page SETUP Setup Control - Ww 46E8h (ISA Bus Only) 53 VSE VideoSubsystemEnable - WwW 3C3h (Local Bus Only) 53 ENAB GlobalEnable - RW 102h (ISA Bus / Setup Mode Only) 54 SETUP CONTROL REGISTER (SETUP) Write only at I/O Address 46E8h [p7|D6 D5 p4[D3]D2[D1 [DO Reserved(0) VGA Enable VGA Setup } Reserved(0) This register is effective in ISA bus configuration only and is not used in local bus or PCI bus configurations. In ISA bus configuration, this regis- ter is ignored if XR70 bit-7 is set to 1 (the default is 0). In local bus configurations, the VGA may be enabled and disabled using register 3C3. In PCI bus configurations (65545), the VGA may be enabled and disabled via the PCI configuration registers. Setup mode is available only in ISA _ bus configuration via this register. This register is cleared by RESET. 2-0 Reserved (0) 3 VGA Enable Q VGA is disabled 1 VGAis enabled 4 Setup Mode 0 VGA is in Normal Mode 1 VGA is in Setup Mode 7-5 Reserved (0) VIDEOSUBSYSTEMENABLEREGISTER(VSE) Write Only at /O Address 3C3h (p7[D6|Ds5|[D4[D3 D2[D1|Do] L_ VGA Sleep Reserved(0) This register is accessible in Local Bus configurations only. It is ignored in ISA bus configurations (registers 102h and 46E8h are used in ISA bus configurations to control VGA enable and disable). Access to this register may be disabled by setting XR70 bit-7 to 1 (the default is 0). This register is cleared by RESET to disable the VGA. In this state, only register 3C3 is accessible (the other registers in the VGA I/O address range will be inaccessible and read or write accesses to VGA I/O addresses other than 3C3 will be ignored) until bit-0 of this register is set to 1. In PCI bus configurations, VGA enable and disable are controlled via the PCI configuration registers and this register is ignored. 0 VGA Sleep 0 VGAis disabled 1 VGAisenabled 7-1 Reserved (0) Revision 1.2 MM 2O9814b 53 65540 / 545 0011780 043Global Control (Setup) Registers GLOBAL ENABLE REGISTER (ENAB) Read/Write at 1/O Address 102h [D7[D6 DS p4[D3[D2|D1 [Do| [_ VGA Sleep Reserved(0) This register is accessible only in setup mode (46E8 bit-4 = 1). If the VGA is not in setup mode (46E8 bit-4 = 0), attempts to access this register are ignored. Bit-0 of this register is cleared by RESET in ISA bus configurations to disable the VGA (all VGA memory and I/O addresses except 102h and 46E8h are ignored). Bit-0 of this register is AND'ed with bit-3 of register 46E8: the VGA is enabled only if both bits are set. If the VGA is disabled, only register 46E8 is accessible. 0 VGA Sleep 0 VGA is disabled 1 VGAisenabled 7-1 Reserved (0) Revision 1.2 54 mM 20946116 0011751 T1T 65540 / 545PCI Configuration Registers PCI Configuration Registers Register Mnemonic Register Name Offset Access Reset State Page VENID VendorID 00h R 0001 0000 0010 1100 55 DEVID DeviceID 02h R 0000 0000 1101 1000 55 DEVCTL _ DeviceControl 04h 3 =R/W 0000 0010 1000 0000 56 DEVSTAT DeviceStatus 06h R/C 0000 0000 0000 0000 56 REV Revision 08h R 0000 0000 57 PRG ProgrammingInterface 09h R 0000 0000 57 SUB Sub Class Code OAh R 0000 0000 57 BASE Base Class Code OBh R 0000 0011 57 MBASE Memory Base Address 10h = =R/Wsxxxx xxxx xxx0 0000 0000 0000 0000 0000 58 IOBASE I/O Base Address 14h = R/WsXXxXxXx XXXX XXXX XXXxX Xxxx xx00 00000001 58 Note: 'Access' codes are R=Read, W=Wnite, and C=Clear (writing a 1 to a bit clears that bit) VENDOR ID REGISTER (VENID) Read/Only at PCI Configuration Offset 00h Byte or Word Accessible Accessible in PCI Bus Configuration Only fis Tr. - VendorID 15-0 Vendor ID Read-Only. Always returns 102Ch (4140d) DEVICE ID REGISTER (DEVID) Read/Only at PCI Configuration Offset 02h Byte or Word Accessible Accessible in PCI Bus Configuration Only (15 [rH r DeviceID 15-0 Device ID Read-Only. Always returns 0O0OD8h Revision 1.2 65540 / 545 M@ 2094116 0011782 156PCI Configuration Registers DEVICE CONTROL REGISTER (DEVCTL) Read/Write at PCI Configuration Offset 04h Byte or Word Accessible Accessible in PCI Bus Configuration Only {15 | L V/O Access Ena Mem Access Ena Always Read 0 Palette Snoop Ena PERR# Enable Always Reads 1 SERR# Enable Always Reads 1 Undefined(0) 0 WO Access Enable When set, the chip will respond to I/O cycles for addresses within the range specified by the IOBASE register. 1 Memory Access Enable When set, the chip will respond to memory cycles for addresses within the range specified by the MBASE register. Bus Master (Always Reads 0) Special Cycles ( Always Reads 0) Mem Write & Invalidate( Always Reads0) Palette Snoop Enable When set, the chip will not respond to VGA Palette Accesses. Reads will be ignored but writes will still update the internal palette. 6 PERR# Enable Set to enable PERR# response for detected data parity errors. 7 Wait Cycle Control (Always Reads 1) 8 SERR# Enable Set to enable SERR# response for detected address / command parity errors. The chip will also generate a Target Abort. 9 Fast Back-to-Back Enable for Masters (AlwaysReads0) 15-10 Undefined / Reserved (0) nak Ww DEVICE STATUS REGISTER (DEVSTAT) Read/Only at PCI Configuration Offset 06h Byte or Word Accessible Accessible in PCI Bus Configuration Only {15 ol LC Undefinec(0) Always Reads 1 Always Reads 0 DEVSEL# Timing (Always Reads 10) Target Abort Sig'd Always Reads 0 Always Reads 0 Sys Err Signaled 6-0 7 8 10-9 11 12 13 14 45 Parity Err Detected Undefined / Reserved (0) Fast Back-to-Back Capable (1) Data Parity Error Detect (0) Implemented by bus masters only. DEVSEL# Timing Always responds '10 (Slow) Target Abort Signaled Set whenever a Target Abort is generated on the bus. This can happen under the followingconditions: 1) Command/Address cycle parity error 2) Invalid byte enables received 3) VGA core unable to complete a cycle Received Target Abort (0) Implemented by bus masters only. Master Abort (0) Implemented by bus masters only. System Error Signaled Set whenever SERR# is asserted. Parity Error Detected Set when data parity error is detected even if PERR# response disabled (DEVCTL bit-6) Revision 1.2 56 65540 / 545 M@! 2094116 0011783 35PCI Configuration Registers REVISION REGISTER (REV) Read/Only at PCI Configuration Offset 08h ByteAccessible Accessiblein PCI Bus Configuration Only (p7[D6[Ds D4|D3 D2[D1 [Do] Chip Revision Code 2-0 Chip Revision Code These bits match XRO0O bits 2-0. Revision codes start at 0 and are incremented for each silicon revision. 7-3 Reserved (0) These bits are defined by the PCI 2.0 specification as additional revision code bits. They always read zero. PROGRAMMINGNTERFACREGISTERPRG) Read/Only at PCI Configuration Offset 09h ByteAccessible Accessable in PCI Bus Configuration Only [D7 D6[D5[D4[D3 [D2 D1|DO Programming Interface Code 7-0 Programming Interface Code This register always returns a value of 00h (no special register-level device-independent interface definition is defined). SUB CLASS CODE REGISTER (SUB) Read/Only at PCI Configuration Offset OAh ByteAccessible Accessablein PCI Bus Configuration Only [D7[D6]Ds p4]/D3|D2|D1 DO Sub-Class Code 7-0 Sub-Class Code This register always returns a value of OOh to indicate "VGA Compatible Controller". BASE CLASS CODE REGISTER (BASE) Read/Only at PCI Configuration Offset OBh ByteAccessible Accessable in PCI Bus Configuration Only [D7|D6 D5|D4[D3 D2[D1 [Do] Base Class Code 7-0 Base Class Code This register always returns a value of 03h to indicate base class "Display Controller. Revision 1.2 65540 / 545 Mi 2094116 0011784 725PCI Configuration Registers MEMORY BASE REGISTER (MBASE) Read/Write at PCI Configuration Offset 10h Byte, Word, or DoubleWord Accessible Accessable in PCI Bus Configuration Only Bl 23b2 443/21] 0} 0 (Memory Space) F 00 (32-bit Address) 0 (No Prefetching) r 0(Address Mask) (8MB Range) r Memory BaseAddress 0 Memory/IO Space (0) Always returns 0 to indicate memory space Memory Type (00) Always return 0 to indicate 32-bit address 3. ~~Prefetchable Memory (0) Always return 0 to prevent prefetching Address Mask (0) Always returns 0 to indicate an 8MB range 22-4 31-23 Memory Base Address R/W in bits 23 and above to indicate an 8MB address range. The lower 2MB is for video memory and the rest is for memory mapped IO. The actual value programmed in this field determines the start of the range in the 32-bit memory address space. For example: Value Programmed 0: 000000000b 8MB: 000000001b 16MB: 000000010b 24MB: 000000011b 32MB: 000000100b 40MB: 000000101b Memory Address Range IllegalSetting 00800000h - OOFFFFFFh 01000000h - 017FFFFFh 01800000h - 01 FFFFFFh 02000000h - 027FFFFFh 02800000h - O2FFFFFFh Note: XRO8 provides the same function for ISA/VL. It is ignored in PCI bus mode. VO BASE REGISTER (IOBASE) Read/Write at PCI Configuration Offset 14h Byte, Word, or DoubleWord Accessible Accessable in PCI Bus Configuration Only [34 10/9 2 1] 0} 1 (/O Space) O(Reserved) | O(Address Mask) (1KB Range) r 1/OBase Address 0 Memory/IO Space (1) Always returns | to indicate I/O space 1 Undefined/ Reserved (0) Address Mask (0) All bits in in this field return 0 to indicate a 1KB I/O address range 31-10 IYO Base Address R/W in bits 10 and above to indicate a 1KB address range for the 32-bit registers (DRxx registers). The actual value programmed in this field determines the start of the range in the 32-bit I/O address space. For example: Value Programmed 000000h 000001h 000002h 000003h 000004h V/O Address Range IlegalSetting 00000400h - 000007FFh 00000800h - OOOOOBFFh 00000C00h - OOOOOFFFh 00001000h - 000013FFh Note: XRO7 provides the same function for ISA/VL. It is ignored in PCI bus mode. In PCI bus configuration, the DR registers may also be memory mapped to the upper megabyte of the 2MB memory space (see MBASE). Note: Revision 1.2 58 65540 / 545 MM 2096116 0011785 &b5General Control Registers General Control & Status Registers Register Vo Protect Mnemonic RegisterName Index Access Address Group Page STOO Input Status 0 - R 3C2h - 59 STO1 Input Status 1 - R 3BAh/3DAh - 59 FCR Feature Control - WwW 3BAh/3DAh 5 60 R 3CAh MSR MiscellaneousOutput - W 3C2h 5 60 R 3CCh INPUT STATUS REGISTER 0 (ST00) Read only at I/O Address at 3C2h [D7|D6[Ds|[D4 D3[D2[D1 [DO Reserved(0) RGB Comparator / Sense Reserved(0) CRT Interrupt Pending INPUT STATUS REGISTER 1 (ST01) Read only at I/O Address 3BAh/3DAh D7 D6[D5[D4[D3 D2{D1 [Do] L_ DE/Hsync Output |_| Reserved(0) VerticalRetrace/Video | VideoFeedback Reserved(0) VSync Output 3-0 Reserved (0) 0 Display Enable/HSYNC Output The functionality of this bit is controlled by 4 RGB Comparator/Sense the Emulation Mode register (XR 14 bit-4). This bit returns the state of the output of the . er RGB output comparator or the output of the 0 Indicates DE or neYNG inactive Virtual Switch Register (XRIF bit 0, 1, 2, ndicates DE or active or 3) if enabled by XRIF bit-7. 2-1 Reserved (0) 6-5 Reserved (0) 3 Vertical Retrace/Video . The functionality of this bit is controlled by 7 CRT Interrupt Pending the Emulation Mode register (XR14 bit-5). 0 Indicates no CRT interruptis pending 0 Indicates VSYNC or video inactive 1 Indicates a CRT interrupt is waiting to 1 Indicates VSYNC or video active beserviced : 5-4 Video Feedback 1, 0 These are diagnostic video bits which are selected via the Color Plane Enable Register. 6 Reserved (0) 7 VSyne Output The functionality of this bit is controlled by the Emulation Mode register (XR14 bit-6). It reflects the active status of the VSYNC output: O=inactive, l=active. Revision 1.2 59 65540 / 545 MH 2096116 0011756 STLCAPS. General Control Registers FEATURE CONTROL REGISTER (FCR) MISCELLANEOUSOUTPUTREGISTER(MSR) Write at /O Address 3BAh/3DAh Write at I/O Address 3C2h Read at I/O Address 3CAh Read at I/O Address 3CCh Group 5 Protection Group 5 Protection (D7 [D D5[D4]D3[D2|D1 [Do] (D7/D6|[D5|D4]D3 D2|D1 [Do| L Feature Control L__ T/O Address Select - RAM Enable Reserved(0) VSync Control Clock Select Reserved(0) Page Select Reserved(0) HSync Polarity VSync Polarity 1-0 Feature Control This register is cleared by RESET. These bits are used internal to the chip in 0 VO Address Select conjunction with the Configuration Register (XRO1). When enabled by XRO1 bits 2-3 and Misc Output Register bits 3-2 = 10, these bits determine the pixel clock frequency typically as follows: FCR1:0 = 00 = 40.000 MHz FCR1:0 = 01 = 50.350 MHz 1 FCR1:0 = 10 = User defined FCR1:0 = 11 = 44.900 MHz This preserves compatibility with drivers developed for earlier generation Chips and 3-2 Technologies VGA controllers. 2 Reserved (0) 3 VSync Control This bit is cleared by RESET. 0 VSync output on the VSYNC pin 1 Logical 'OR' of VSync and Display Enable output on the VSYNC pin This capability is not typically very useful, but is provided for IBM compatibility. 7-4 Reserved (0) 4 CRT Display Syne Polarities 6 isplay req req >480Line Variable Variabld #7 200 Line 15.7 KHz 60 Hz 350 Line 21.8 KHz 60Hz 400 Line 31.5 KHz 70Hz 480 Line 31.5 KHz 60 Hz P P P P N P PN N_N This bit selects 3Bxh or 3Dxh as the I/O address for the CRT Controller registers, the Feature Control Register (FCR), and Input Status Register 1 (STO1). 0 Select 3BxhI/O address 1 Select 3Dxh I/O address RAM Enable O Prevent CPU access to display memory 1 Allow CPU access to display memory Clock Select. These bits usually select the dot clock source for the CRT interface: MSR3:2 = 00 = Select CLKO MSR3:2 = 01 = Select CLK1 MSR3:2 = 10 = Select CLK2 MSR3:2 = 11 = Select CLK3 See extension register XRO1 bits 2-3 (Configuration) and FCR bits 0-1 for variations of the above clock selection mapping. See also XR1F (Virtual Switch Register) for additional functionality potentially controlled by these bits. Reserved (0) Page Select. In Odd/Even Memory Map Mode 1 (GR6), this bit selects the upper or lower 64 KByte page in display memory for CPU access: O=select upper page; 1=select lower page. CRT HSync Polarity. O=pos, 1=neg CRT VSync Polarity. O=pos, 1=neg (Blank pin polarity can be controlled via the Video Interface Register, XR28). XR55 bits 6-7 are used to control H/V sync polarity instead of these bits if XR51 bit-2 = 1 (display type = flat panel). Revision 1.2 60 MB 2096116 001178? 65540 / 545 436gusesse fe CGA/Hercules Registers CGA/Hercules Registers Register Vo Protect Mnemonic RegisteiName Index Access Address Group Page MODE CGA/HerculesMode - R/W 3D8h - 61 COLOR CGA Color Select - R/W 3D9h - 62 HCFG HerculesConfiguration _ R/W 3BFh - 62 CGA/HERCULES MODE CONTROL REGISTER (MODE) Read/Write at /O Address 3B8h/3D8h [D7[D6 D5 p4[D3|D2 yi [__ HiRes Text (CGA only) GraphicsMode (0=Text) Monochrome (CGA only) VideoEnable HiRes Graphics (CGA only) Text Blink Enable Reserved(0) Page Select (Herc only) This register is effective only in CGA and Hercules modes. It is accessible if CGA or Hercules emulation mode is selected or the extension registers are enabled. If the extension registers are enabled, the address is determined by the address select in the Miscellaneous Outputs register. Otherwise the address is determined by the emulation mode. It is cleared by RESET. 0 CGA 80/40 Column Text Mode Q Select 40 column CGA text mode 1 Select 80 column CGA text mode 1 CGA/HerculesGraphics/Text Mode 0 Selecttextmode 1 Select graphics mode CGA Mono/Color Mode 0 Select CGA color mode 1 Select CGA monochrome mode CGA/Hercules Video Enable O Blankthe screen 1 Enable videooutput CGA High Resolution Mode 0 Select 320x200 graphics mode 1 Select 640x200 graphics mode CGA/Hercules Text Blink Enable 0 Disable character blink attribute (blink attribute bit-7 used to control back- groundintensity) 1 Enablecharacterblink attribute Reserved (0) Hercules Page Select 0 Select the lower part of memory (starting address BOOO0Oh) in Hercules Graphics Mode 1 Select the upper part of the memory (starting address B8000h) in Hercules Graphics Mode Revision 1.2 61 65540 / 545 MH 2098116 0011786 3745CGA COLOR SELECT REGISTER (COLOR) Read/Write at I/O Address 3D9h [D7|D6 D5[D4][D3[D2|D1 [DO [__ Color bit-0 (Blue) Color bit-1 (Green) Color bit-2 (Red) Color bit-3 (Intensity) Intensity Enable Color Set Select | Reserved(0) This register is effective only in CGA modes. It is accessible if CGA emulation mode is selected or the extension registers are enabled. This register may also be read or written as an Extension Register (XR7E). It is cleared by Reset. 3-0 Color 320x200 4-color: Background Color (color when the pixel value is 0) The foreground colors (colors when the pixel value is 1-3) are determined by bit-5 of this register. 640x200 2-color: Foreground Color (color when the pixel value is 1) The background color (color when the pixel value is 0) is black. 4 IntensityEnable TextMode: Enables intensified background colors 320x200 4-color: Enables intensified colors 0-3 640x200 2-color: Don't care 5 Color Set Select This bit selects one of two available CGA color palettes to be used in 320x200 graphics mode (it is ignored in all other modes) according to the following table: Pixel Color Set Color Set Value 0 1 0 0 Color per bits 0-3. Color per bits 0-3 01 Green Cyan 10 Red Magenta 11 Brown White 7-6 Reserved(0) CGA/Hercules Registers HERCULES CONFIGURATION REGISTER (HCFG) Write only at I/O Address 3BFh D7[D6|D5 D4[D3|[D2[D1 [Do] L_ Enable Graphics Mode Enable Memory Page 1 Reserved(0) This register is effective only in Hercules mode. It is accessible in Hercules emulation mode or if the extension registers are enabled. It may be read back through XR14 bits 2 & 3. It is cleared by Reset. 0 Enable Graphics Mode 0 Lock the chip in Hercules text mode. In this mode, the CPU has access only to memory address range BOOOOh- B7FFFh (in text mode the same area of display memory wraps around 8 times within this range such that BOOOO accesses the same display memory location as B1000, B2000, etc.). 1 Permit entry to Hercules Graphics mode 1 Enable Memory Page 1 0 Prevent setting of the Page Select bit (bit 7 of the Hercules Mode Control Register). This function also restricts memory usage to addresses BOOOOh- B7FFFh. 1 The Page Select bit can be set and the upper part of display memory (addresses B8000h - BFFFFh) is available. 7-2 Reserved (0) Revision 1.2 65540 / 545 M@@ 20598116 0011789 coSequencer Registers Sequencer Registers Register vO Protect Mnemonic Register Name Index Access Address Group Page SRX Sequencer Index - R/W 3C4h 1 63 SROO Reset 00h R/W 3C5h 1 63 SRO1 ClockingMode Olh R/W 3C5h 1 64 SRO2 Plane/MapMask 02h R/W 3CS5h 1 64 SRO3 CharacterFont 03h R/W 3C5h 1 65 SRO4 Memory Mode 04h R/W 3C5h 1 66 SRO7 Horizontal Character Counter Reset 07h WwW 3C5h - 66 SEQUENCER INDEX REGISTER (SRX) Read/Write at /O Address 3C4h D7(D6]/D5|D4/D3|[D2]D1 [Do] L Sequencerndex Reserved(0) This register is cleared by reset. SEQUENCER RESET REGISTER (SR00) Read/Write at I/O Address 3C5h Index 00h Group 1 Protection [D7|/D6 D5[D4]D3 D2[D1/D0 L_ Async Reset Sync Reset Reserved(0) Asynchronous Reset 2-0 Sequencer Index 0 Force asynchronous reset . . . 1 Normaloperation These bits contain a 3-bit Sequencer Index . . . value used to access sequencer data registers Display memory data will be corrupted if at indices 0 through 7. this bit is set to zero. 7-3 Reserved (0) 1 Synchronous Reset 0 Force synchronous reset 1 Normaloperation Display memory data is not corrupted if this bit is set to zero for a short period of time (a few tenths of a microsecond). See also XROE. 7-2 Reserved (0) Revision 1.2 63 65540 / 545 MB 2098116 0011790 TecSequencer Registers SEQUENCER CLOCKING MODE REGISTER (SRO01) Read/Write at I/O Address 3C5h Index O1h Group 1 Protection D7|D6[D5 D4[D3|D2 D1{Do] [__ 8/9 Dot Clocks Reserved(0) Shift Load Input Clock Divide Shift 4 Screen Off | Reserved(0) 8/9 Dot Clocks This bit determines whether a character clock is 8 or 9 dot clocks long. 0 Select9 dots/characterclock 1 Select8 dots/characterclock Reserved (0) Shift Load 0 Load video data shift registers every characterclock 1 Load video data shift registers every othercharacterclock Bit-4 of this register must be 0 for this bit to be effective. Input Clock Divide Q Sequencer master clock output on the PCLK pin (used for 640 (720) pixel modes) 1 Master clock divided by 2 output on the PCLK pin (used for 320 (360) pixel modes) Shift 4 0 Load video shift registers every 1 or 2 character clocks (depending on bit-2 of this register) 1 Load shift registers every 4th character clock. Screen Off 0 NormalOperation 1 Disable video output and assign all display memory bandwidth for CPU accesses 7-6 Reserved (0) SEQUENCER PLANE/MAP MASK REGISTER (SR02) Read/Write at /O Address 3C5h Index 02h Group 1 Protection [D7[D6 D5[D4[D3/D2|D1 Do| Color Plane Enable Reserved(0) 3-0 Color Plane Enable 0 Write protect corresponding color plane 1 Allow write to corresponding color plane. In Odd/Even and Quad modes, these bits still control access to the corresponding color plane. 7-4 Reserved (0) Revision 1.2 64 MB 2094116 0011791 5b9 65540 / 545SE EHH, tH CPPS Sequencer Registers CHARACTER FONT SELECT REGISTER (SR03) Read/Write at /O Address 3C5h Index 03h Group | Protection (D7/D6|Ds|D4[D3[D2|D1 [Do| | Font Select B bit-1 Font Select B bit-2 Font Select A bit-1 Font Select A bit-2 Font Select B bit-0 Font Select A bit-0 | Reserved(0) In text modes, bit-3 of the video data's attribute byte normally controls the foreground intensity. This bit may be redefined to control switching between char- acter sets. This latter function is enabled whenever there is a difference in the values of the Character Font Select A and the Character Font Select B bits. If the two values are the same, the character select function is disabled and attribute bit-3 controls the foreground intensity. SRO04 bit-1 must be 1 for the character font select function to be active. Otherwise, only character fonts 0 and 4 are available. 1-0 High order bits of Character Generator Select B 3-2 High order bits of Character Generator Select A 4 Low order bit of Character Generator Select B 5 Low order bit of Character Generator SelectA 7-6 Reserved (0) The following table shows the display memory plane selected by the Character Generator Select A and B bits. Code CharacterGeneratorTableLocation First 8K of Plane 2 Second 8K of Plane 2 Third 8K of Plane 2 Fourth 8K of Plane 2 Fifth 8K of Plane 2 Sixth 8K of Plane 2 Seventh 8K of Plane 2 Eighth 8K of Plane 2 where 'code' is: Character Generator Select A (bits 3, 2, 5) when bit-3 of the attribute byte is one. Character Generator Select B (bits 1, 0, 4) when bit-3 of the attribute byte is zero. SDN WN Revision 1.2 65 65540 / 545 Mi 27094116 0011792 6T5SEQUENCER MEMORY MODE REGISTER (SR04) Read/Write at I/O Address 3C5h Index 04h Group 1 Protection [D7 D6[D5|D4 D3 D2[D1|Do] L Reserved(0) ExtendedMemory Odd/EvenMode Quad Four Mode Reserved(0) 0 Reserved (0) 1 Extended Memory 0 Restrict CPU access to 4/ 16 / 32 KBytes 1 Allowcomplete access to memory This bit should normally be 1. 2 Odd/Even Mode 0 CPU accesses to Odd/Even addresses are directed to corresponding odd/even planes 1 All planes are accessed simultaneously (RGB color) Bit-3 of this register must be 0 for this bit to be effective. This bit affects only CPU write accesses to display memory. 3 Quad Four Mode 0 CPU addresses are mapped to display memory as defined by bit-2 of this register 1 CPU addresses are mapped to display memory modulo 4, The two low order CPU address bits select the display memory plane. This bit affects both CPU reads and writes to display memory. 7-4 Reserved (0) Sequencer Registers SEQUENCER HORIZONTAL CHARACTER COUNTER RESET (SR07) Read/Write at I/O Address 3C5h Index 07h [pD7[D6/Ds|[D4[D3[D2|D1 [Do] Don't Care Writing to SRO7 with any data will cause the horizontal character counter to be held reset (character counter output = 0) until a write to any other sequencer register with any data value. The write to any index in the range 0-6 clears the latch that is holding the reset condition on the character counter. The vertical line counter is clocked by a signal derived from horizontal display enable (which does not occur if the horizontal counter is held reset). Therefore, if the write to SRO7 occurs during vertical retrace, the horizontal and vertical counters will both be set to zero. A write to any other sequencer register may then be used to start both counters with reasonable synchronization to an external event via software control. This is a standard VGA register which was not documented by IBM. Revision 1.2 65540 / 545 Mf 20981146 0011793 731,CRT Controller Registers CRT Controller Registers Register VO Protect Mnemonic Register Name Index Access Address Group Page CRX CRTC Index - R/W 3B4h/3D4h - 68 CROO HorizontalTotal 00h R/W 3B5h/3D5h 0 68 CROI Horizontal Display Enable End Olh R/W 3B5h/3D5h 0 68 CRO2 Horizontal Blank Start 02h R/W 3B5h/3D5h 0 69 CRO3 Horizontal Blank End 03h R/W 3B5h/3D5h 0 69 CRO04 Horizontal Sync Start 04h R/W 3B5h/3D5h 0 70 CROS Horizontal Sync End 05h R/W 3B5h/3D5h 0 70 CRO6 VerticalTotal 06h R/W 3B5h/3D5h 0 71 CRO7 Overflow O7h R/W 3B5h/3D5h = (0/3 71 CRO8 Preset Row Scan 08h R/W 3B5h/3D5h 3 72 CRO9 Maximum Scan Line 09h R/W 3B5h/3D5h =s 2/4 72 CROA Cursor Start Scan Line OAh R/W 3B5h/3D5h 2 73 CROB Cursor End Scan Line OBh R/W 3B5h/3D5h 2 73 CROC Start Address High 0Ch R/W 3B5h/3D5h - 74 CROD Start Address Low ODh R/W 3B5h/3D5h 714 CROE Cursor Location High OEh . R/W 3B5h/3D5h - 74 CROF Cursor Location Low OFh R/W 3B5h/3DSh ~ 714 CR10 Vertical Sync Start (See Note 2) 10h WorR/W 3B5h/3D5h 4 75 CRil Vertical Sync End (See Note 2) lih WorR/W 3B5h/3D5h = 3/4 75 CR10 Lightpen High (See Note 2) 10h R 3B5h/3D5h - 75 CRII Lightpen Low (See Note 2) lh R 3B5h/3D5h - 75 CR12 Vertical Display EnableEnd 12h R/W 3B5h/3D5h 4 716 CR13 Offset 13h R/W 3B5h/3D5h 3 76 CR14 Underline Row 14h R/W 3B5h/3D5h 3 76 CRI5 Vertical Blank Start 15h R/W 3B5h/3D5h 4 77 CR16 VerticalBlankEnd 16h R/W 3B5h/3D5h 4 77 CR17 CRT Mode Control 17h R/W 3B5h/3D5h = 3/4 78 CR18 LineCompare 18h R/W 3B5h/3D5h 3 79 CR22 Memory DataLatches 22h R 3B5h/3D5h - 80 CR24 AttributeControllerToggle 24h R 3B5h/3D5h - 80 Note 1: When MDA or Hercules emulation is enabled, the CRTC YO address should be set to 3BOh-3B7h by setting the I/O address select bit in the Miscellaneous Output register (3C2h/3CCh bit-0) to zero. When CGA emulation is enabled, the CRTC I/O address should be set to 3D0h-3D7h by setting Misc Output Register bit-0 to 1. Note 2: In the EGA, all CRTC registers except the cursor (CROC-CROF) and light pen (CR10 and CR11) registers are write-only (i.e., no read back). In both the EGA and VGA, the light pen registers are at index locations conflicting with the vertical sync registers. This would normally prevent reads and writes from occurring at the same index. Since the light pen registers are not normally useful, the VGA provides software control (CRO3 bit-7) of whether the vertical sync or light pen registers are readable at indices 10-11. Revision 1.2 67 65540 / 545 me 2096116 0011794 75SEED GEHTS its LArS> CRT Controller Registers CRTC INDEX REGISTER (CRX) HORIZONTAL DISPLAY ENABLEEND Read/Write at /O Address 3B4h/3D4h REGISTER (CRO1) Read/Write at I/O Address 3B5h/3D5h Index Olh [p7[D6 DS [p4[D3 D2[D1 [Do| Group 0 Protection Ls D7|D6[D5|D4[D3 D2[D1[Do| CRTC Index L_ Horizontal Display Reserved(0) 5-0 CRTC Data Register Index 7-6 Reserved (0) This register is used for all VGA and EGA modes on CRTs. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. HORIZONTAL TOTAL REGISTER (CRO0) Read/Write at I/O Address 3B5h/3D5h Index 00h Number of Characters displayed per scan Group 0 Protection line - 1. [p7[De[Ds p4/D3|D2 Di {Do 7-0 Horizontal Display - Horizontal Total This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 Horizontal Total Total number of character clocks per line = contents of this register + 5. This register determines the horizontal sweep rate. Revision 1.2 68 65540 / 545 MB 2098116 0011795 504HORIZONTAL BLANK START REGISTER (CR02) Read/Write at I/O Address 3B5h/3D5h Index 02h Group 0 Protection {D71D6 D5 D4[D3[D2 D1|D0] H Blank Start This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 Horizontal Blank Start These bits specify the beginning of horizontal blank in terms of character clocks from the beginning of the display scan. The period between Horizontal Display Enable End and Horizontal Blank Start is the right side border on screen. CRT Controller Registers HORIZONTAL BLANK END REGISTER (CRO3) Read/Write at /O Address 3B5h/3D5h Index 03h Group 0 Protection {D7 ]D6]D5[D4/D3 D2]D1/D0] L_ H Blank End DE Skew Control Light Pen Register Enable This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 4-0 Horizontal Blank End These are the lower 5 bits of the character clock count used to define the end of horizontal blank. The interval between the end of horizontal blank and the beginning of the display (a count of 0) is the left side border on the screen. If the horizontal blank width desired is W clocks, the 5-bit value programmed in this register = [contents of CRO2 + W] and 1Fh. The most significant bit is programmed in CROS bit-7. This bit = [( CRO2 + W) and 20h]/20h. 6-5 Display Enable Skew Control Defines the number of character clocks that the Display Enable signal is delayed to compensate for internal pipeline delays. 7 ~~ Light Pen Register Enable This bit must be 1 for normal operation; when this bit is 0, CRTC registers CR10 and CR11 function as lightpen readback registers. Revision 1.2 Me 2098116 0011756 69 65540 / 545 yOuCRT Controller Registers HORIZONTAL SYNC START REGISTER (CR04) Read/Write at I/O Address 3B5h/3D5h Index 04h Group 0 Protection D7|D6|[D5|[D4/D3 [D2 D1[Do| Horizontal Sync Start This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MDA/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 7-0 Horizontal Sync Start These bits specify the beginning of HSync in terms of Character clocks from the beginning of the display scan. These bits also determine display centering on the screen. HORIZONTAL SYNC END REGISTER (CR05) Read/Write at /O Address 3B5h/3D5h Index 05h Group 0 Protection [D7/D6|D5 D4 D3]/D2|D1 [D0 Horizontal Sync End Horizontal Sync Delay H Blank End Bit 5 This register is used for all VGA and EGA modes. It is also used for 640 column CGA modes and MD/A/Hercules text mode. In all 320 column CGA modes and Hercules graphics mode, the alternate register is used. 4-0 Horizontal Sync End Lower 5 bits of the character clock count which specifies the end of Horizontal Sync. If the horizontal sync width desired is N clocks, then these bits = (N + contents of CRO04) and 1Fh. 6-5 Horizontal Sync Delay These bits specify the number of character clocks that the Horizontal Sync is delayed to compensate for internal pipeline delays. 7 ~~ Horizontal Blank End Bit 5 This bit is the sixth bit of the Horizontal Blank End Register (CRO3). Revision 1.2 65540 / 545 MS 2098iib 0011797 38? aCRT Controller Registers VERTICAL TOTAL REGISTER (CR06) Read/Write at I/O Address 3B5h/3D5h Index 06h Group 0 Protection [D7[D6 D5 p4{pD3[D2|D1 DO] LL V Total (Scan Lines) (Lower 8 Bits) This register is used in all modes. 7-0 Vertical Total These are the 8 low order bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow Register.. The Vertical Total value specifies the total number of scan lines (horizontal retrace periods) per frame. Programmed Count = Actual Count 2 OVERFLOW REGISTER (CR07) Read/Write at I/O Address 3B5h/3D5h Index 07h Group 0 Protection on bits 0-3 and bits 5-7 Group 3 Protection on bit 4 {b7[D6/D5|D4[D3|D2 D1[Do| LL V Total Bit & V DE End Bit 8 V Sync Start Bit 8 V Blank Start Bit 8 Line Compare Bit 8 V Total Bit 9 V DE End Bit 9 V Sync Start Bit 9 This register is used in all modes. 0 sna on he OO We Vertical Total Bit 8 Vertical Display Enable End Bit 8 Vertical Syne Start Bit 8 Vertical Blank Start Bit 8 Line Compare Bit 8 Vertical Total Bit 9 Vertical Display Enable End Bit 9 Vertical Sync Start Bit 9 Revision 1.2 71 65540 / 545 MB 2098116 0011798 213CRT Controller Registers PRESET ROW SCAN REGISTER (CRO8) Read/Write at I/O Address 3B5h/3D5h Index 08h Group 3 Protection [D7[D6|Ds|D4[D3|D2 D1[Do| LL Start Row Scan Count Byte Panning Control Reserved(0) 4-0 Start Row Scan Count These bits specify the starting row scan count after each vertical retrace. Every horizontal retrace increments the character row scan line counter. The horizontal row scan counter is cleared at maximum row scan count during active display. This register is used for soft scrolling in text modes. MAXIMUM SCAN LINE REGISTER (CR09) Read/Write at I/O Address 3B5h/3D5h Index 09h Group 2 Protection on bits 0-4 Group 4 Protection on bits 5-7 [D7 D6[D5/D4[D3]D2]D1 [Do] Scan Lines Per Row V Blank Start Bit 9 Line Compare Bit 9 Double Scan 4-0 Scan Lines Per Row These bits specify the number of scan lines in arow: Programmed Value = Actual Value 1 5 Vertical Blank Start Register Bit 9 6 Line Compare Register Bit 9 Double Scan 6-5 Byte Panning Control 0 NormalOperation These bits specify the lower order bits for 1 Enablescan line doubling the display start address. They are used for The vertical parameters in the CRT horizontal panning in Odd/Even and Quad Controller (even for a split screen) are not modes. affected, only the CRTC row scan counter 7 Reserved (0) (bits 0-4 of this register) and display memory addressing screen refresh are affected. Revision 1.2 72 65540 / 545 MB 2098116 0011799 157CURSOR START SCAN LINE REGISTER CROA) Read/Write at I/O Address 3B5h/3D5h Index OAh Group 2 Protection (D7|D6 D5 D4[D3[D2 D1{Do| 7-6 LL Cursor Start Scan Line Cursor off | Reserved(0) Cursor Start Scan Line These bits specify the scan line of the character row where the cursor display begins. Cursor Off 0 Text Cursor On 1 Text Cursor Off Reserved (0) CURSOR END SCAN CRT Controller Registers LINE REGISTER (CROB) Read/Write at I/O Address 3B5h/3D5h Index OBh Group 2 Protection D7|D6[D5|D4 D3[D2|D1 [Do] 6-5 7 LL Cursor End Scan Line Cursor Delay Reserved(0) Cursor End Scan Line These bits specify the scan line of a character row where the cursor display ends (i.e., last scan line for the block cursor): Programmed Value = Actual Value + 1 Cursor Delay These bits define the number of character clocks that the cursor is delayed to compensate for internal pipeline delay. Reserved (0) Note: If the Cursor Start Line is greater than the Cursor End Line, then no cursor is generated. Revision 1.2 73 65540 / 545 WS 2098116 0011800 7TLEEEHIGE. .IFaEs CRT Controller Registers START ADDRESS HIGH REGISTER (CROC) Read/Write at I/O Address 3B5h/3D5h Index OCh [b7/D6|[Ds|D4/D3[D2|D1 [Do] Display Start Address High (Upper 8 bits) 7-0 Display Start Address High This register contains the upper 8 bits of the display start address. In CGA / MDA / Hercules modes, this register wraps around at the 16K, 32K, and 64KByte boundaries respectively. START ADDRESS LOW REGISTER (CROD) Read/Write at I/O Address 3B5h/3D5h Index 0Dh [D7 D6[D5[D4[D3 D2[D1[Do] Display Start Address Low (Lower 8 bits) 7-0 Display Start Address Low This register contains the lower 8 bits of the display start address. The display start address points to the memory address corresponding to the top left corner of the screen. CURSORLOCATIONHIGHREGISTER(CROE) Read/Write at I/O Address 3B5h/3D5h Index OEh (D7 D6[D5[D4]D3 D2|D1|Do] Text Cursor Address (Upper 8 bits) 7-0 Text Cursor Location High This register contains the upper 8 bits of the memory address where the text cursor is active. In CGA / MDA / Hercules modes, this register wraps around at 16K, 32K, and 64KByte boundaries respectively. CURSORLOCATIONLOWREGISTERCROF) Read/Write at I/O Address 3B5h/3D5h Index OFh [D7 D6{D5{D4[D3[D2[D1|D0 Text Cursor Address (Lower 8 bits) 7-0 Text Cursor Location Low This register contains the lower 8 bits of the memory address where the text cursor is active. In CGA / MDA / Hercules modes, this register wraps around at 16K, 32K, and 64KByte boundaries respectively. Revision 1.2 74 65540 / 545 ' MM 2098116 0011801 635 aLIGHTPEN HIGH REGISTER (CR10) Read only at /O Address 3B5h/3D5h Index 10h Read-only Register loaded at line compare (the light pen flip-flop is not implemented). Effective only in MDA and Hercules modes or when CRO3 bit-7 = 0. LIGHTPEN LOW REGISTER (CR11) Read only at I/O Address 3B5h/3D5h Index 11h Read-only Register loaded at line compare (the light pen flip-flop is not implemented). Effective only in MDA and Hercules modes or when CRO3 bit-7 = 0. VERTICAL SYNC START REGISTER (CR10) Read/Write at /O Address 3B5h/3D5h Index 10h Group 4 Protection (D7[D6|[Ds p4[D3[D2|D1 Do] V Sync Start (Lower 8 bits) This register is used in all modes. This register is notreadable in (Line Compare bit-9) MDA/Hercules emulation or when CRO3 bit-7=1. 7-0 Vertical Sync Start The eight low order bits of a 10-bit register. The 9th and 10th bits are located in the CRTC Overflow Register. They define the scan line position at which Vertical Sync becomesactive. CRT Controller Registers VERTICAL SYNC END REGISTER (CR11) Read/Write at I/O Address 3B5h/3D5h Index 11h Group 3 Protection for bits 4 and 5 Group 4 Protection for bits 0-3, 6, and 7 (b7|D6|[Ds[D4[D3[D2 D1]Do] V Sync End V Interrupt Clear V Interrupt Enable Select Refresh Type Protect CRTC (Group 0) This register is used in all modes. This register is not readable in MDA/Hercules emulation or when CRO3 bit-7=1. 3-0 Vertical Sync End The lower 4 bits of the scan line count that defines the end of vertical sync. If the vertical sync width desired is N lines, then bits 3-0 of this register = (CR10 + N) AND OFh. 4 Vertical Interrupt Clear 0=Clear vertical interrupt generated on the IRQ output; 1=Normal operation. This bit is cleared by RESET. 5 Vertical Interrupt Enable 0 Enableverticalinterrupt(default) 1 Disableverticalinterrupt This bit is cleared by RESET. 6 Select Refresh Type ( Ignored ) 7 Group Protect 0 This bit is logically ORed with XR15 bit-6 to determine the protection for group 0 registers. This bit is cleared by RESET. 0 Enable writes to CROO-CRO7 1 Disable writes to CROO-CRO7 CRO7 bit-4 (Line Compare bit-9) is not affected by this bit. Revision 1.2 MH 20598116 0011402 75 65540 / 545 5cuVERTICAL DISPLAY ENABLE END REGISTER (CR12) Read/Write at /O Address 3B5h/3D5h Index 12h Group 4 Protection D7[D6[D5[D4[D3[D2|D1 [Do] L V Display Enable End (Lower 8 bits) 7-0 Vertical Display Enable End These are the eight low order bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow register. The actual count = Contents of this register + 1. OFFSET REGISTER (CR13) Read/Write at I/O Address 3B5h/3D5h Index 13h Group 3 Protection [D7[D6[D5]D4]D3|D2[D1 DO LL Display Buffer Width Display Buffer Width. The byte starting address of the next display row = Byte Start Address for current row + K* (CR13 + Z/2), where Z = bit defined in XROD, K = 2 in byte mode, and K = 4 in word mode. Byte, word and double word mode is selected by bit-6 of CR17 and bit-6 of CRI4. A less significant bit than bit-0 of this register is defined in the Auxiliary Offset register (XROD). This allows finer resolution of the bit map width. Byte, word and doubleword mode affects the translation of the logical display memory address to the physical display memory address. CRT Controller Registers UNDERLINE LOCATION REGISTER (CR14) Read/Write at /O Address 3B5h/3D5h Index 14h Group 3 Protection [p7/D6|Ds D4[D3[D2|D1|Do| 4-0 L Underline Position Count by 4 DoublewordMode Reserved(0) Underline Position These bits specify the underlines scan line position within a character row. Programmed Value = Actual scan line number 1 Count by 4 for Doubleword Mode O Frame Buffer Address is incremented by 1 or2 1 Frame Buffer Address is incremented by 4 or 2 See CR17 bit-3 for further details. Doubleword Mode O Frame Buffer Address is byte or word address 1 Frame Buffer Address is doubleword address This bit is used in conjunction with CR17 bit-6 to select the display memory addressing mode. Reserved (0) Revision 1.2 76 65540 / 545 M 2096116 00114803 400VERTICAL BLANK START REGISTER (CR15) Read/Write at I/O Address 3B5h/3D5h Index 15h Group 4 Protection [D7|D6[Ds D4[D3]D2 D1(Do] V Biank Start (Lower 8 bits) This register is used in all modes. 7-0 Vertical Blank Start These are the 8 low order bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow and Maximum Scan Line Registers respectively. Together these 10 bits define the scan line position where vertical blank begins. The interval between the end of the vertical display and the beginning of vertical blank is the bottom border on the screen. CRT Controller Registers VERTICAL BLANK END REGISTER (CR16) Read/Write at I/O Address 3B5h/3D5h Index 16h Group 4 Protection D7[D6|D5|D4[D3/D2|D1 [Do] V Blank End (Lower 8 bits) This register is used in all modes. 7-0 Vertical Blank End These are the 8 low order bits of the scan line count which specifies the end of Vertical Blank. If the vertical blank width desired is Z lines these bits = (Vertical Blank Start + Z) and OFFh. Revision 1.2 77 65540 / 545 Mi 2098116 00114604 347CRT MODE CONTROL REGISTER (CRI17) Read/Write at /O Address 3B5h/3D5h Index 17h Group 3 Protection for bits 0, 1, and 3-7 Group 4 Protection for bit 2 [D7|/D6 IDS [D4]D3 [D2[D1 [Do] L_ Compatibility Mode Select Row Scan Counter VSync Select Count by 2 Reserved(0) AddressWrap Word/ByteMode CRTC Reset 0 Compatibility Mode Support This bit allows compatibility with the IBM CGA two-bank graphics mode. 0 Character row scan line counter bit 0 is substituted for memory address bit 13 during active display time 1 Normal operation, no substitution takesplace 1 = Select Row Scan Counter This bit allows compatibility with Hercules graphics and with any other 4-bank graphics system. 0 Character row scan line counter bit 1 is substituted for memory address bit 14 during active display time 1 Normal operation, no substitution takesplace 2 ~=Vertical Sync Select This bit controls the vertical resolution of the CRT Controller by permitting selection of the clock rate input to the vertical counters. When set to 1, the vertical counters are clocked by the horizontal retrace clock divided by 2. CRT Controller Registers Count By Two 0 Memory address counter is incrementedeverycharacterclock 1 Memory address counter is incremented every two character clocks, used in conjunction with bit 5 of OFh. Note: This bit is used in conjunction with CR14 bit-5. The net effect is as follows: Increment CR14 CR17 ~~ Addressing Bit-5 Bit-3 Every 0 0 1 CCLK 0 1 2 CCLEK 1 0 4 CCLK 1 1 2 CCLEK Note: In Hercules graphics and Hi-res CGA modes, address increments every two clocks. Reserved (0) Addresirap (effective only in word mode) 0 Wrap display memory address at 16 KBytes. Used in IBM CGA mode. 1 Normal operation (extended mode). Word Mode or Byte Mode 0 Select Word Mode. In this mode the display memory address counter bits are shifted down by one, causing the most-significant bit of the counter to appear on the least-significant bit of the display memory address output 1 Select byte mode Note: This bit is used in conjunction with CR14 bit-6 to select byte, word, or double word memory addressing as follows: CR14 CRI17 Bit-6 _Bit-6 Addressing Mode 0 0 Word Mode 0 1 Byte Mode 1 0 Double Word Mode 1 1 Double Word Mode Display memory addresses are affected as shown in the table on the following page. CRTC Reset 0 Force HSYNC and VSYNC inactive. No other registers or outputs affected. 1 NormalOperation This bit is cleared by RESET. Revision 1.2 78 65540 / 545 M@ 2094116 0011605 233Display memory addresses are affected by CR17 bit 6 as shown in the table below: Logical Physical Memory Address Memory Byte Word DoubleWord Address Mode Mode Mode MAOO AO00 Note 1 Note 2 MAOI1 AOl A00 Note 3 MAO2 A02 AOl AOoo MA03 AO3 A02 AOI MA04 A04 A03 A02 MA05 AOS5 A04 A03 MA06 A06 A05 A04 MAO7 A07 A06 AOS MAO08 A08 A07 A06 MAO9 A09 A08 AQ7 MA10 Al0 A09 A08 MAI1I1 All Al0 A09 MAI12 Al12 All Al0 MA13 Al3 Al2 All MAI4 Al4 Al3 Al2 MAI15 Al5 Al4 Al3 Note 1 = Al3 * NOT CR17 bit 5 + A15 * CR17 bit 5 Note 2 = Al2 xor (A14 * XRO04 bit 2) Note 3 = A13 xor (A15 * XR04 bit 2) CRT Controller Registers LINE COMPARE REGISTER (CR18) Read/Write at I/O Address 3B5h/3D5h Index 18h Group 3 Protection (D7 D6[D5|D4[D3|D2[D1 [Do] L Line Compare Target (Lower 8 bits) Line Compare Target These are the low order 8 bits of a 10-bit register. The 9th and 10th bits are located in the CRT Controller Overflow and Maximum Scan Line Registers, respectively. This register is used to implement a split screen function. When the scan line counter value is equal to the contents of this register, the memory address counter is cleared to 0. The display memory address counter then sequentially addresses the display memory starting at address 0. Each subsequent row address is generated by the addition of the Offset Register contents. This register is not affected by the double scanning bit (CRO9 bit 7). Revision 1.2 79 65540 / 545 ME 20598116 0011806 117CRT Controller Registers MEMORY DATA LATCH REGISTER (CR22) Read only at /O Address 3B5h/3D5h Index 22h [D7 D6[D5[D4 [D3 D2 D1[Do] L_ Data Latch n Bit 7 Data Latch n Bit 6 Data Latch n Bit 5 Data Latch n Bit 4 Data Latch n Bit 3 Data Latch n Bit 2 Data Latch n Bit 1 Data Latch n Bit 0 This register may be used to read the state of Graphics Controller Memory Data Latch n', where n' is controlled by the Graphics Controller Read Map Select Register (GRO4 bits 0-1) and is in the range 0-3. Writes to this register are not decoded and will be ignored. This is a standard VGA register which was not documented by IBM. ATTRIBUTE CONTROLLER TOGGLE REGISTER (CR24) Read only at /O Address 3B5h/3D5h Index 24h [D7|D6[Ds D4[D3[D2|D1 [Do] Reserved(0) Index (0) / Data (1) 6-0 Reserved (0) 7 Index/Data This bit may be used to read back the state of the attribute controller index/data latch. This latch indicates whether the next write to the attribute controller at 3COh will be to the register index pointer or to an indexed register. 0 Next write is to the index 1 Next write is to an indexed register Writes to this register are not decoded and will be ignored. This is a standard VGA register which was not documented by IBM. Revision 1.2 80 65540 / 545 Mm 2094116 00114607 O56Graphics Controller Registers Graphics Controller Registers Register Vo Protect Mnemonic RegisterName Index Access Address Group Page GRX Graphics Index - R/W 3CEh 1 81 GROO Set/Reset 00h R/W 3CFh 1 81 GROl EnableSet/Reset Olh R/W 3CFh 1 82 GRO2 ColorCompare 02h R/W 3CFh 1 82 GRO3 DataRotate 03h R/W 3CFh 1 83 GRO4 Read Map Select 04h R/W 3CFh 1 83 GRO5 Graphics mode 05h R/W 3CFh 1 84 GR06 Miscellaneous 06h R/W 3CFh 1 86. GRO7 Color Don't Care 07h R/W 3CFh 1 86 GRO8 Bit Mask 08h R/W 3CFh 1 87 GRAPHICSCONTROLLER SET/RESET REGISTER (GR00) INDEX REGISTER (GRX) Write only at YO Address 3CEh Group 1| Protection D7|D6|Ds D4[D3 D2 D1[Do] Index to Graphics Controller Data Registers Reserved(0) 3-0 4-bitIndextoGraphicsControllerRegisters 7-4 Reserved (0) Read/Write at I/O Address 3CFh Index 00h Group | Protection [D7/D6|Ds|D4 D3[D2[D1|Do| | Set/Reset Bit 0 Set/Reset Bit 1 Set/Reset Bit 2 Set/Reset Bit 3 Reserved(0) The SET/RESET and ENABLE SET/RESET registers are used to expand 8 bits of CPU data to 32 bits of display memory. 3-0 Set/Reset Planes 3-0 When the Graphics Mode register selects Write Mode 0, all 8 bits of each display memory plane are set as specified in the corresponding bit in this register. The Enable Set/Reset register (GRO1) allows selection of some of the source of data to be written to individual planes. In Write Mode 3 (see GROS), these bits determine the color value. 7-4 Reserved (0) Revision 1.2 $1 65540 / 545 MB 2094116 0011408 TleGraphics Controller Registers ENABLE SET/RESET REGISTER (GRO1) Read/Write at I/O Address 3CFh Index O1h Group | Protection {p7|D6 D5[D4[D3/D2|D1 [DO Index 02h Group | Protection COLOR COMPARE REGISTER (GR02) Read/Write at I/O Address 3CFh [D7[D6]Ds D4]/D3]D2[D1 [Do] L Enable Set/Reset Bit 0 L_ Color Compare (Plane 0) Enable Set/Reset Bit 1 Color Compare (Plane 1) Enable Set/Reset Bit 2 Color Compare (Plane 2) Enable Set/Reset Bit 3 Color Compare (Plane 3) Reserved(0) Reserved(0) 3-0 Enable Set/Reset Planes 3-0 This register works in conjunction with the Set/Reset register (GROO). The Graphics Mode register must be programmed to Write Mode 0 in order for this register to have any effect. 0 The corresponding plane is written with the data from the CPU data bus 1 The corresponding plane is set to 0 or 1 as specified in the Set/Reset Register 7-4 Reserved (0) 3-0 Color Compare Planes 3-0 This register is used to reduce 32 bits of memory data to 8 bits for the CPU in 4- plane graphics mode. These bits provide a reference color value to compare to data read from display memory planes 0-3. The Color Don't Care register (GRO7) is used to affect the result. This register is active only if the Graphics Mode register (GROS5) is set to Read Mode 1. A match between the memory data and the Color Compare register (GRO2) (for the bits specified in the Color Don't Care register) causes a logical 1 to be placed on the CPU data bus for the corresponding data bit; a mis-match returns a logical 0. 7-4 Reserved (0) Revision 1.2 82 65540 / 545 M@ 20948116 0011805 929DATA ROTATE REGISTER (GR03) Read/Write at /O Address 3CFh Index 03h Group | Protection [D7|D6 DS D4]D3[D2]D1 [Do] L__ Rotate Count 0 Rotate Count 1 Rotate Count 2 Function Select Reserved(0) 2-0 Data Rotate Count 7-5 These bits specify the number of bits to rotate to the right the data being written by the CPU. The CPU data bits are first rotated, then subjected to the logical operation as specified in the Function Select bit field. The rotate function is active only if the Graphics Mode register is programmed for Write Mode 0. Function Select These Function Select bits specify the logical function performed on the contents of the processor latches (loaded on a previous CPU read cycle) before the data is written to display memory. These bits operate as follows: Bit4 Bit3 Result 0 0 No change to the Data 0 1 Logical AND' between Data and latched data i 0 Logical 'OR' between Data and latched data 1 1 Logical 'XOR' between Data and latched data Reserved (0) Graphics Controller Registers READ MAP SELECT REGISTER (GR04) Read/Write at I/O Address 3CFh Index 04h Group 1 Protection (D7 D6|D5|D4]D3|D2|D1 [Do] L_ Read Map Select 0 Read Map Select 1 Reserved(0) 1-0 Read Map Select This register is also used to 'reduce' 32 bits of memory data to 8 bits for the CPU in the 4-plane graphics mode. These bits select the memory plane from which the CPU reads data in Read Mode 0. In Odd/Even mode, bit-0 is ignored. In Quad mode, bits 0 and 1 are both ignored. The four memory maps are selected as follows: Bit1 BitO MapSelected 0 0 Plane 0 0 1 Plane 1 ] 0 Plane 2 1 1 Plane 3 7-2 Reserved (0) Revision 1.2 83 65540 / 545 Mf 2098116 0011810 L40Graphics Controller Registers GRAPHICS MODE REGISTER (GR05) Read/Write at I/O Address 3CFh Index 05h Group 1 Protection (D7 D6/D5{D4|[D3[D2|/D1 [Do] |] Write Mode Reserved(0) ReadMode Odd/EvenMode Shift Register Mode Reserved(0) 1-0 Write Mode For 16-bit writes, the operation is repeated on the lower and upper bytes of CPU data. 1 0 Write Mode 0 O Write mode 0. Each of the four display memory planes is written with the CPU data rotated by the number of counts in the Rotate Register, except when the Set/Reset Register is enabled for any of the four planes. When the Set/Reset Register is enabled, the corresponding plane is written with the data stored in the 2 Set/Reset Register. 3 0 1 Write mode 1. Each of the four display memory planes is written with the data previously loaded in the processor latches. These latches are loaded during all read operations. 1 OQ Writemode2. The CPU data bus data is treated as the color value for the addressed byte in planes 0-3. All eight pixels in the addressed byte are modified unless protected by the Bit Mask register setting. A logical 1 in the Bit Mask register sets the corresponding pixel in the addressed byte to the color specified on the data bus. A 0 in the Bit Mask register sets the corresponding pixel in the addressed byte to the corresponding pixel in_ the processor latches. The Set/Reset and Enable Set/Reset registers are ignored. The Function Select bits in the Data Rotate register are used. 1 Write mode 3. The CPU data is rotated then logically ANDed with the contents of the Bit Mask register (GRO8) and then treated as the addressed data's bit mask, while the contents of the Set/Reset register is treated as the color value. A '0' on the data bus (mask) causes the corresponding pixel in the addressed byte to be set to the corresponding pixel in the processor latches. A 'l' on the data bus (mask) causes the corresponding pixel in the addressed byte to be set to the color value specified in the Set/Resetregister. The Enable Set/Reset register is ignored. The Data Rotate is used. This write mode can be used to fill an area with a single color and pattern. Reserved (0) Read Mode Q The CPU reads data from one of the planes as selected in the Read Map Selectregister. The CPU reads the 8-bit result of the logical comparison between all eight pixels in the four display planes and the contents of the Color Compare and Color Don't Care registers. The CPU reads a logical 1 if a match occurs for each pixel and logical 0 if a mis-match occurs. In 16-bit read cycles, this Operation is repeated on the lower and upper bytes. (Continued on following page) Revision 1.2 84 65540 / 545 MH 2098116 0011811 587 omCrnir> Graphics Controller Registers 4 Odd/Even Mode 0 AllCPU addresses sequentially access all planes 1 Even CPU addresses access planes 0 and 2, while odd CPU addresses access planes 1 and 3. This option is useful for compatibility with the IBM CGA memory organization. 6-5 Shift Register Mode These two bits select the data shift pattern used when passing data from the four memory planes through the four video shift registers. If data bits 0-7 in memory planes 0-3 are represented as MODO-MOD7, M1D0-M1D7, M2D0-M2D7, and M3D0-M3D7 respectively, then the data in the serial shift registers is shifted out as follows: Last Bit 1st Bit Out- Shifted Shift Shifted put 65 Out Direction > Out to: 00: MODO MOD1 M0OD2 MO0D3 MO0OD4 MODS MOD6 MOD7 Bit 0 MIDO MiID1t MI1D2 M1D3 M1D4 MIDS MI1D6 MID7 Bit 1 M2D0 M2D1 M2D2 M2D3 M2D4 M2D5 M2D6 M2D7 Bit 2 M3D0 M3D1 M3D2 M3D3 M3D4 M3D5 M3D6 M3D7 Bit 3 O1: MIDO MI1D2 M1D4 M1D6 MODO MOD2 MOD4 MOD6 Bit 0 MIDI MI1D3 MID5 MI1D7 MOD1 MOD3 MODS MOD7 Bit 1 M3D0 M3D2 M3D4 M3D6 M2D0 M2D2 M2D4 M2D6 Bit 2 M3D1 M3D3 M3D5 M3D7 M2D1 M2D3 M2D5 M2D7 Bit 3 1x: M3D0 M3D4 M2D0 M2D4 MI1DO M1D4 MODO MOD4 Bit 0 M3D1 M3D5 M2D1 M2D5 MID1 MiD5 MOD1 MOD5 Bit 1 M3D2 M3D6 M2D2 M2D6 MID2 MiD6 MOD2 MOD6 Bit 2 M3D3 M3D7 M2D3 M2D7 MID3 M1D7 MOD3 MOD7 Bit 3 Note: If the Shift Register is not loaded every character clock (see SRO1 bits 2&4) then the four 8-bit shift registers are effectively chained with the output of shift register 1 becoming the input to shift register 0 and so on. This allows one to have a large monochrome (or 4 color) bit map and display one portion thereof. Note: If XR28 bit-4 is set (8-bit video path), GROS5 bit-6 must be set to 0: Ox and XR28 bit-4=1: M3D0 M2D0 MIDO MODO Bit 0 M3Di M2D1 MID! MOD1 Bit 1 M3D2 M2D2 MiD2 MO0OD2 Bit 2 M3D3 M2D3 M1D3 MOD3 Bit 3 M3D4 M2D4 MI1D4 MO0D4 Bit 4 M3D5 M2D5 M1D5 MOD5 Bit 5 M3D6 M2D6 MI1D6 MOD6 Bit 6 M3D7 M2D7 M1D7 MOD7 Bit 7 7 Reserved (0) Revision 1.2 85 65540 / 545 MB 2094116 0011812 413Crir> Graphics Controller Registers MISCELLANEOUS REGISTER (GR06) COLORDON'T CARE REGISTER (GR07) Read/Write at YO Address 3CFh Read/Write at /O Address 3CFh Index 06h Index 07h Group | Protection Group 1 Protection D7|D6|D5|[D4[D3 D2[D1[Do] (D7[D6 DS D4]/D3|D2[D1 Do] L__ Graphics/TextMode |__ Ignore Color Plane 0 Chain Odd/Even Planes Ignore Color Plane 1 Ignore Color Plane 2 Memory Map Mode -_____- Tgnore Color Plane 3 Reserved(0) -_________+- + Reserved(0) 0 Graphics/Text Mode 3-0 Ignore Color Plane (3-0) O TextMode 0 This causes the corresponding bit of 1 Graphics mode the Color Compare register to be a 1 Chain Odd/Even Planes don't care during a comparison. This mode can be used to double the address space into display memory. 1 The corresponding bit of the Color Compare register is enabled for color comparison. This register is active in 1 CPU address bit AO is replaced by a Read Mode J only. higher order address bit. The state of . AO determines which memory plane is 7-4 Reserved (0) tobe selected: A0O=0: select planes 0 and 2 AO=1: select planes 1 and 3 0 AOnotreplaced 3-2 Memory Map Mode These bits control the mapping of the display memory into the CPU address space as follows (also used in extended modes): Bit3 Bit2 CPU Address 0 0 A0000h-BFFFFh 0 1 A0000h-AFFFFh 1 0 BO000h-B7FFFh 1 1 B8000h-BFFFFh 7-4 Reserved (0) Revision 1.2 86 65540 / 545 MH 2098116 0011813 35TgTISEE FEED ETIE, gtttts BREESE geste Vnirs Graphics Controller Registers BIT MASK REGISTER (GR08) Read/Write at /O Address 3CFh Index O8h Group 1 Protection [D7[D6|Ds D4[D3]D2[Di [Do] L Bit Mask 0=Immune to change 1=Changepermitted 7-0 Bit Mask This bit mask is applicable to any data written by the CPU, including that subject to a rotate, logical function (AND, OR, XOR), Set/Reset, and No Change. In order to execute a proper read-modify-write cycle into displayed memory, each byte must first be read (and latched by the VGA), the Bit Mask register set, and the new data then written. The bit mask applies to all four planes simultaneously. 0 The corresponding bit in each of the four memory planes is written from the corresponding bit in the latches 1 Unrestricted manipulation of the corresponding data bit in each of the four memory planes is permitted Revision 1.2 MH 2094116 0011414 25b 37 65540 / 545Attribute Controller and Color Palette Registers Attribute Controller and VGA Color Palette Registers Register VO Protect Mnemonic Register Name Index Access Address Group Page ARX Attribute Index (for 3C0/3C 1h) - R/W 3CO0h J 89 AROO-AROF Attribute ControllerColor Data 00-OFh R/W 3C0Oh3Cih 1 90 AR10 Mode Control i0h R/W 3C0h3Clh 1 90 ARI11 OverscanColor 11h R/W 3C0h/3Cih =1 91 AR12 Color Plane Enable 12h R/W 3C0b/3Clh =] 91 ARI3 Horizontal Pixel Panning 13h R/W 3C0h/3Clh = 1 92 ARI4 Pixel Pad 14h R/W 3C0h/3Clh 1 92 DACMASK Color Palette Pixe] Mask - R/W 3C6h 6 93 DACSTATE Color Palette State - R 3C7h - 93 DACRX Color Palette Read-Mode Index - Ww 3C7h 6 94 DACX Color Palette Index (for 3C9h) - R/W 3C8h 6 94 DACDATA ColorPalette Data 00-FFh R/W 3C9h 6 94 In regular VGA mode, all Attribute Controller ATTRIBUTE INDEX registers are located at the same byte address (3COh) REGISTER (ARX) in the CPU I/O space. An internal flip-flop controls Read/Write at /O Address 3COh the selection of either the Attribute Index or Data Group 1 Protection Registers. To select the Index Register, an I/O Read is executed to address 3BAh/3DAh (Input Status [b7[D6]Ds|[b4]D3]b2|Di [Do] Register 1) to clear this flip-flop. After the Index D7|De|Ps [Days pap ips Register has been loaded by an I/O Write to address | 3COh, this flip-flop toggles, and the Data Register is Index to ready to be accessed. Every I/O Write to address Attribute Control 3COh toggles this flip-flop. The flip-flop does not tribute Controller have any effect on the reading of the Attribute Con- Data Registers troller registers. The Attribute Controller index reg- ister is always read back at address 3COh, the data Enable Video register is always read back at address 3C ih. | An option is provided to allow the Attribute Reserved(0) Controller Index register to be mapped to 3COh and the Data register to 3C Lh to allow word I/O accesses. Another option allows the Attribute Controller to be both read and written at either 3COh or 3Clh (EGA compatible mode). These optional mappings are selected by 'CPU Interface Register 1' (XR02[4-3]) and are not standard VGA capabilities. The VGA color palette is used to further modify the video color output following the attribute controller color registers. The color palette logic is contained on-chip; extension register XRO6 is provided to control various optional capabilities. DAC logic is provided on-chip to convert the final video output of the color palette to analog RGB outputs for use in driving a CRT display. Output comparator logic is also provided on-chip to duplicate the SENSE function (see Status Register 0 readable at 3C2h). 4-0 Attribute Controller Index These bits point to one of the intemal registers of the Attribute Controller. Enable Video 0 Disable video, allowing the Attribute Controller Color registers to be accessed by the CPU 1 Enable video, causing the Attribute Controller Color registers (AROO- AROF) to be inaccessible to the CPU Reserved (0) Revision 1.2 89 65540 / 545 MM 2094116 0011415 leeATTRIBUTE CONTROLLER COLOR REGISTERS (AR00-AROF) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 00-0Fh Group 1 Protection or XR63 bit-6 {D7[D6 D5 D4[D3/D2 DI [Do] Red SecondaryBlue SecondaryGreen SecondaryRed | Reserved(0) 5-0 Color Value These bits are the color value in the respective attribute controller color register as pointed to by the attribute index register. 7-6 Reserved (0) ATTRIBUTE CONTROLLER MODE CONTROL REGISTER (AR10) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 10h Group 1| Protection [D7[D6[Ds[D4[D3[D2[D1 DO] L_ Text/Graphics Mode Mono/Color Display Enable Line Graphics Select Background Reserved(0) Horizontal Split Screen 256 Color Video Output 4-5 Select Text/Graphics Mode 0 Selecttextmode 1 Select graphics mode Monochrome/Color Display 0 Selectcolordisplay attributes 1 Select monodisplay attributes Attribute Controller and Color Palette Registers Enable Line Graphics Character Codes This bit is dependent on bit 0 of the Override register. 0 Make the ninth pixel appear the same as the background 1 For special line graphics character codes (OCOh-ODFh), make the ninth pixel identical to the eighth pixel of the character. For other characters, the ninth pixel is the same as the background. Enable Blink/Select Background Intensity The blinking counter is clocked by the VSYNC signal. The Blink frequency is defined in the Blink Rate Control Register (XR60). 0. Disable Blinking and enable text mode backgroundintensity 1 Enable the blink attribute in text and graphics modes. Reserved (0) Split Screen Horizontal Panning Mode 0 Scroll both screens horizontally as specified in the Pixe] Panning register 1 Scroll horizontally only the top screen as specified in the Pixel panning register 256 Color Output Assembler 0 6-bits of video (translated from 4-bits by the internal color palette) are output every dot clock 1 Two 4-bit sets of video data are assembled to generate 8-bit video data at half the frequency of the internal dot clock (256 color mode). Video Output 5-4 Select 0 Video bits 4 and 5 are generated by the internal Attribute Controller color paletteregisters 1 Video bits 4 and 5 are the same as bits 0 and 1 in the Pixel Pad register (AR14) Revision 1.2 90 Mi 2094116 00114816 069 65540 / 545Attribute Controller and Color Palette Registers OVERSCAN COLOR REGISTER (ARI1) Read at 1/O Address 3C 1h Write at I/O Address 3C0/1h Index 11H Group 1 Protection [D7 D6[D5[D4|D3[D2[D1 [Do Overscan Color 7-0 Overscan Color These 8 bits define the overscan (border) color value. For monochrome displays, these bits should be zero. The border color is displayed in the interval after Display Enable End and before Blank Start (end of display area; i.e. right side and bottom of screen) and between Blank End and Display Enable Start (beginning of display area; i.e. left side and top of screen). COLOR PLANE ENABLE REGISTER (AR12) Read at I/O Address 3C1h Write at I/O Address 3C0/1h Index 12h Group 1 Protection D7[D6|[D5|[D4 D3(D2|D1 [Do L_ Color Plane 0 Enable Color Plane 1 Enable Color Plane 2 Enable Color Plane 3 Enable Display Status Select Reserved(0) 3-0 Color Plane (3-0) Enable 0 Force the corresponding color plane pixel bit to 0 before it addresses the colorpalette 1 Enable the plane data bit of the corresponding color plane to pass 5-4 Display Status Select These bits select two of the eight color outputs to be read back in the Input Status Register 1 (port 3BAh or 3DAh). The output color combinations available on the status bits are as follows: Status Register 1 Bit5 Bit4 Bit5 Bit4 0 0 P2 PO 0 1 P5 P4 1 0 P3 Pi 1 i P7 P6 7-6 Reserved (0) Revision 1.2 91 65540 / 545 MH 20948116 0011617 TTSAttribute Controller and Color Palette Registers ATTRIBUTE CONTROLLER HORIZONTAL PIXEL PANNING REGISTER (AR13) Read at I/O Address 3Cih Write At I/O Address 3C0/1h Index 13h Group 1 Protection [D7|D6[D5 D4 D3[D2]D1 [Do| Horizontal Pixel Panning Reserved(0) 3-0 Horizontal Pixel Panning These bits select the number of pixels to shift the display horizontally to the left. Pixel panning is available in both text and graphics modes. In 9 pixel/character text mode, the output can be shifted a maximum of 9 pixels. In 8 pixel/character text mode and all graphics modes a maximum shift of 8 pixels is possible. In 256-color mode (output assembler AR10 bit-6 = 1), bit O of this register must be 0 which results in only 4 panning positions per display byte. In Shift Load 2 and Shift Load 4 modes, register CRO08 provides single pixel resolution for panning. Panning is controlled as follows: Number of Pixels Shifted 9-dot $8-dot 256-color AR13 mode mode mode 0 1 0 0 1 2 1 -- 2 3 2 1 3 4 3 -- 4 5 4 2 5 6 5 -- 6 7 6 3 7 8 7 -- 8 0 -- -- 7-4 Reserved (0) ATTRIBUTE CONTROLLER PIXEL PAD REGISTER (AR14) Read at I/O Address 3C1h Write At I/O Address 3C0/th Index 14h Group 1 Protection [D7 D6|D5|D4 D3/D2|D1 DO L_ Video bit-4 if AR10 bit7=1 Video bit-5 if AR10 bit7=1 Video bit-6 if not 256-color Video bit-7 if not 256-color Reserved(0) 1-0 Video Bits 5-4 These bits are output as video bits 5 and 4 when AR1O bit-7 = 1. They are disabled in the 256 color mode. Video Bits 7-6 These bits are output as video bits 7 and 6 in all modes except 256-color mode. 7-4 Reserved (0) Revision 1.2 92 65540 / 545 MB 2098116 0011818 93]Attribute Controller and Color Palette Registers COLOR PALETTE PIXEL MASK REGISTER (DACMASK) Read/Write at I/O Address 3C6h Group 6 Protection (D7|D6 D5|D4[D3[D2|D1 DO | Pixel Mask Bit-0 Pixel Mask Bit-1! Pixel Mask Bit-2 Pixel Mask Bit-3 Pixel Mask Bit-4 Pixel Mask Bit-5 Pixel Mask Bit-6 Pixel Mask Bit-7 The contents of this register are logically ANDed with the 8 bits of video data coming into the color palette. Zero bits in this register therefore cause the corresponding address input to the color palette to be zero. For example, if this register is programmed with 7, only color palette registers 0-7 would be accessible; video output bits 3-7 would be ignored and all color values would map into the lower 8 locations in the color palette. COLOR PALETTE STATE REGISTER (DACSTATE) Read only at YO Address 3C7h [D7[D6 D5[D4[D3 D2[D1 [D0] [_ Palette State 0 Palette State | Reserved(0) 1-0 Palette State 1-0 Status bits indicate the I/O address of the last CPU write to the Color Palette: 00 The last write was to 3C8h (write mode) 11. The last write was to 3C7h (read mode) 7-2 Reserved (0) To allow saving and restoring the state of the video subsystem, this register is required since the color palette index register is automatically incremented differently depending on whether the index is written at 3C7h or 3C8h. Revision 1.2 93 65540 / 545 MM 2058116 0011819 675Attribute Controller and Color Palette Registers COLOR PALETTE READ-MODE INDEX REGISTER (DACRX) Write only at /O Address 3C7h Group 6 Protection COLOR PALETTE INDEX REGISTER (DACX) Read/Write at I/O Address 3C8h Group 6 Protection [D7[D6 D5[D4]D3 D2[D1/D0] L__ Color Palette Index 0 Color Palette Index 1 Color Palette Index 2 Color Palette Index 3 Color Palette Index 4 Color Palette Index 5 Color Palette Index 6 Color Palette Index 7 COLOR PALETTE DATA REGISTERS (DACDATA00-FF) Read/Write at I/O Address 3C9h Index 00h-FFh Group 6 Protection [D7][D6[D5[D4]/D3]D2|D1 [Do] Access Ast 2nd 3rd L_ RedQ GreenO Blue 0 Red1 Green1l Blue 1 Red2 Green2 Blue 2 Red3 Green 3 Blue 3 Red4 Green 4 Blue 4 pn nnn - Red5 Green5 Blue 5 |] Reserved (0) The palette index register is used to point to one of 256 palette data registers. Each data register is 18 bits in length (6 bits each for red, green, and blue), so the data values must be read as a sequence of 3 bytes. After writing the index register (8C7h or 3C8h), data values may be read from or written to the color palette data register port (3C9h) in sequence: first red, then green, then blue, then repeat for the next location if desired (the index is incrementedautomatically by the palette logic). The index may be written at 3C7h and may be read or written at 3C8h. When the index value is written to either port, it is written to both the index register and a 'save' register. The save register (not the index register) is used by the palette logic to point at the current data register. When the index value is written to 3C7h (readmode), it is written to both the index register and the save register, then the index register is automaticallyincremented When the index value is written to 3C8h (writemode), the automatic incrementing of the index register does not occur. After the third of the three sequential data reads from (or writes to) 3C9h is completed, the save and index registers are both automatically incremented by the palette logic. This allows the entire palette (or any subset) to be read (written) by writing the index of the first color in the set, then sequentially reading (writing) the values for each color, without having to reload the index every three bytes. The state of the RGB sequence is not saved; the user must access each three bytes in an uninterruptible sequence (or be assured that interrupt service routines will not access the palette index or data registers). When the index register is written (at either port), the RGB sequence is restarted. Data reads and writes may be intermixed; either reads or writes increment the palette logics RGB sequence counter. The palette's save register always contains a value one less than the readable index value if the last index write was to the 'read mode port. The state is saved of which port (3C7h or 3C8h) was last written; that information is returned on reads from 3C7h. Revision 1.2 94 65540 / 545 MB 2098116 0011820 S9TExtension Registers Extension Registers Register Register VO State After Mnemonic Group Extension Register Name Index Access Address Reset Page XRX -- Extension Index - R/W 3D6h -xXXXXXXX 97 XROO Misc Chip Version (65540: v=0; 65545: v=1) 00h RO 3D7h 110lvrrr 97 XROI Misc Configuration Olh RO 3D7h dddddddd 98 XRO02 Misc CPU Interface Control 1 02h R/W 3D7h 00000000 99 XRO3 Misc CPU Interface Control 2 03h R/W 3D7h ------ Ox 100 XRO4 Misc Memory Control 1 04h R/W 3D7h --0--000 101 XRO5 Misc Memory Control 2 05h R/W 3D7h 00000000 = 102 XRO06 Misc Palette Control 06h R/W 3D7h 00000000 103 XROE Misc Text Mode Control OEh R/W 3D7h OOOD000D-- 106 XR28 Misc Videolnterface 28h R/W 3D7h O000--0- 117 XR29 Misc Half Line Compare 29h R/W 3D7h xxxxxxxx = 117 XR70 Misc Setup / Disable Control 70h R/W 3D7h O------- 150 XR72 Misc External Device /O 72h R/W 3D7h 0000000* = 151 XR73 Misc DPMS Control 73h R/W 3D7h 00--0000 152 XR7D Misc Diagnostic (65545 Only) 7Dh R/W 3D7h O------- 152 XR7F Misc Diagnostic 7Fh R/W 3D7h OOxxxx00 ~~ 153 XRO7 Mapping V/O Base (65545 Only) 07h R/W 3D7h 11110100 = 104 XRO8 Mapping Linear Addressing Base 08h R/W 3D7h xxxxxxxx 104 XROB Mapping CPU Paging OBh R/W 3D7h --00000 = 105 XROC Mapping Start Address Top O0Ch R/W 3D7h ------ xx 105 XR10 Mapping Single/Low Map 10h R/W 3D7h xxxxxxxx 108 XR11 Mapping High Map lih R/W 3D7h xxxxxxxx 108 XROF Software Flags Software Flags 0 OFh R/W 3D7h xxxxxxxx 107 XR2B Software Flags Software Flags 1 2Bh R/W 3D7h 00000000 118 XR44 Software Flags Software Flags 2 44h R/W 3D7h xxxxxxxx = 127 XR45 Software Flags Software Flags 3 45h R/W 3D7h xxxxxxxx 127 XR14 Compatibility Emulation Mode 14h R/W 3D7h 0000hh00 ~~ 109 XR15 Compatibility Write Protect 15h R/W 3D7h 00000000 ~~ 110 XRIF Compatibility Virtual EGA Switch 1Fh R/W 3D7h O---xxxx II5 XR7E Compatibility CGA/Hercules Color Select 7Eh R/W 3D7h = --xxxxxx 153 XR30 Clock Clock Divide Control 30h R/W 3D7h seeexxxx = 121 XR31 Clock Clock M-Divisor 31h R/W 3D7h *xxxxxxx 122 XR32 Clock Clock N-Divisor 32h R/W 3D7h *xxxxxxx 122 XR33 Clock Clock Control 33h R/W 3D7h 0000+000 = 123 XR3A MultiMedia Color Key 0 3Ah R/W 3D7h xxxxxxxx = 124 XR3B MultiMedia Color Key 1 3Bh R/W 3D7h xxxxxxxx = 124 XR3C MultiMedia Color Key 2 3Ch R/W 3D7h xxxxxxxx = 125 XR3D MultiMedia Color Key Mask 0 3Dh R/W 3D7h xxxxxxxx 125 XR3E MultiMedia Color Key Mask 1 3Eh R/W 3D7h xXxxxxxxx 126 XR3F MultiMedia Color Key Mask 2 3Fh R/W 3D7h xxxxxxxx 126 XR40 BitBLT BitBLT Configuration (65545 Only) 40h R/W 3D7h ------ xx 127 Reset Codes: x = Not changed by reset (indeterminate on power-up) ~ = Not implemented (always reads 0) d = Set from the corresponding data bus pin on trailing edge of reset = Reserved (read/write, reset to 0) h = Read-only Hercules Configuration Register Readback bits 0/1 = Reset to 0 or | by trailing edge of reset r = Chip revision # (starting from 0000) Revision 1.2 95 65540 / 545 MH 2098116 00118c1 4ebExtension Registers Extension Registers (Continued) Register Register VO State After Mnemonic Group Extension Register Name Index Access Address Reset Page XROD Alternate Auxiliary Offset ODh R/W 3D7h ------ xx 106 XRI6 Alternate Vertical Overflow 16h R/W 3D7h =*0*0000 = 111 XR17 Altermate Horizontal Overflow 17h R/W 3D7h =8=*0000000 111 XR18 Alternate Alternate Horizontal Display End 18h R/W 3D7h Xxxxxxxx 112 XR19 Alternate Alternate Horizontal Sync Start 19h R/W 3D7h xxxxxxxx = 112 XRIA Alternate Alternate Horizontal Sync End 1Ah R/W 3D7h xxxxxxxx 113 XRIB Alternate Alternate Horizontal Total 1Bh R/W 3D7h xxxxxxxx = 113 XRIC Alternate Alternate H Blank Start / H Panel Size 1Ch R/W 3D7h xxxxxxxx 114 XRID Alternate Alternate Horizontal Blank End 1Dh R/W 3D7h Oxxxxxxx 114 XRIE Alternate Alternate Offset 1Eh R/W 3D7h xxxxxxxx 115 XR24 Alternate Alternate Maximum Scan Line 24h R/W 3D7h *e*xxxxx = 116 XR25 Alternate Alternate Text Mode / H Virtual Panel Size 25h R/W 3D7h xxxxxxxx 116 XR26 Alternate Alternate Horizontal Sync Start Register 26h R/W 3D7h xxxxxxxx 116 XR64 Alternate Alternate Vertical Total 64h R/W 3D7h xxXXXXxx 145 XR65 Alternate AlternateOverflow 65h R/W 3D7h xxxeexxx 145 XR66 Alternate Alternate Vertical Sync Start 66h R/W 3D7h xxxxxxxx 146 XR67 Alternate Alternate Vertical Sync End 67h R/W 3D7h seeexxxx 146 XR2C Flat Panel FLM Delay 2Ch R/W 3D7h xxxxxxxx 118 XR2D Flat Panel LP Delay (Comp Enabled) 2Dh R/W 3D7h xxxxXXxXxxx 119 XR2E Flat Panel LP Delay (Comp Disabled) 2Eh R/W 3D7h xxxxxxxx = 119 XR2F Flat Panel LP Width 2Fh R/W 3D7h xxxXXXXXX 120 XR4F Flat Panel Panel Format 2 4Fh R/W 3D7h xx**exxx 128 XRS5O Flat Panel Panel Format 1 50h R/W 3D7h xxxxxxxx 129 XR51 Flat Panel Display Type 51h R/W 3D7h 0000000 = 130 XR52 Flat Panel Power Down Control 52h R/W 3D7h 00000001 131 XR53 Flat Panel Panel Format 3 53h R/W 3D7h *00000x0 = 132 XR54 Flat Panel PanelInterface 54h R/W 3D7h xxxXXXXXX 133 XR55 Flat Panel Horizontal Compensation 55h R/W 3D7h xxxeexxx 134 XRS6 Flat Panel Horizontal Centering 56h R/W 3D7h xxxxxxxx 135 XR57 Flat Panel Vertical Compensation 57h R/W 3D7h xxxxxxxx 136 XRS58 Flat Panel Vertical Centering 58h R/W 3D7h xxxxxxxx = 137 XR59 Flat Panel Vertical Line Insertion 59h R/W 3D7Th xxx*xxxXx 137 XRSA Flat Panel Vertical Line Replication 5Ah R/W 3D7h seeexxxx 138 XRSB Flat Panel Panel Power Sequencing Delay SBh R/W 3D7h 10000001 138 XRS5C Flat Panel Activity Indicator Control 5Ch R/W 3D7h Oxexxxxx 139 XRSD Flat Panel FP Diagnostic 5Dh R/W 3D7h 00000000 140 XR5E Flat Panel M (ACDCLK) Control 5Eh R/W 3D7h xxxxxxxx = 141 XRSF Flat Panel Power Down Mode Refresh SFh R/W 3D7h xxxxxxxx 141 XR60 Flat Panel Blink Rate Control! 60h R/W 3D7h 10000011 142 XR61 Flat Panel SmartMap Control 61h R/W 3D7h xxxxxxxx = 143 XR62 Flat Panel SmartMap Shift Parameter 62h R/W 3D7h xxxxxxxx 144 XR63 Flat Panel SmartMap Color Mapping Control 63h R/W 3D7h xixxxxxx 144 XR68 Flat Panel Vertical Panel Size 68h R/W 3D7h xxxxxxxx 147 XR6C Flat Panel Programmable Output Drive 6Ch R/W 3D7h + *0000d+ = 147 XR6E Flat Panel Polynomial FRC Control 6Eh R/W 3D7h 10111101 148 XR6E Flat Panel Frame Buffer Control 6Fh R/W 3D7h 00000000 149 Reset Codes: x = Not changed by reset (indeterminate on power-up) = Not implemented (always reads 0) d = Set from the corresponding data bus pin on trailing edge of reset * = Reserved (read/write, reset to 0) h = Read-only Hercules Configuration Register Readback bits O/1 = Reset to 0 or 1 by trailing edge of reset r = Chip revision # (starting from 0000) Revision 1.2 96 65540 / 545 ME 20948116 0011822 3bEXTENSION INDEX REGISTER (XRX) Read/Write at I/O Address 3D6h [D7|D6|[D5[D4]D3 D2[D1 [Do] Index to Extension Registers Reserved(0) 6-0 Index value used to access the extension registers 7 Reserved (0) Extension Registers CHIPS VERSION REGISTER (XR00) Read only at /O Address 3D7h Index 00h [D7 [D6[Ds [D4[D3 [D2|[D1 [Do| Chip Revision 0=65540, 1=65545 Chip Type (1101) 7-0 Chip Version - 65540 Chip Versions start at DOh and are incremented for every silicon step. 65545 Chip Versions start at D8h and are incremented for every silicon step. Revision 1.2 97 65540 / 545 Me 20948116 0011423 2cToCHir> Extension Registers CONFIGURATION REGISTER (XR01) 5 CFG5-Oscillator Source Select Inde 01 if at VO Address 3D7h , 0 External Oscillator drives XTALI (pin ndex 203) 1 Internal Oscillator (series resonant (D7 [D6 [Ds D4|D3 [D2 [D1 [Do crystal connected to XTALI and L XTALO) CFG0/LB#: Bus Type CFG1 / ISA#: Bus Type 6 CFG 6-A26-A27 Enable CFG2 /2X#: Bus Type 0 Pin 53 is A26 (ignore for ISA & PCI) CFG3: Reserved Pin 54 is A27 (ignore for ISA & PCD CFG4: Reserved (do not use) 1 Pin 53 is ACTI CFGS / OS#: Osc Src Select Pin 54 is ENABKL CFG6 / AD#: A26-27 Ena CEG? / TS#: Clk Test Ena 7 CFG7-Internal Clock Test Mode 0 Enable internal clock test mode. These bits latch the state of memory address bus A Output MCLK on pin-30 (A25) and (AA bus) bits 0-7 on the rising edge of RESET#. VCLK on pin 29 (A24) The state of bits 0-7 after RESET# effect chip in- 1 Normal operation: ROMCS# ternal logic as indicated below. During RESET#, generated in ISA bus mode internal pullups are enabled for AA[7:0] and hence the status of these bits will be high if no external pull-down resistors are present on these pins. This register is not related to the Virtual EGA Switch register (XRIF). 2-0 CFG2:0-CPU Bus Type 2 1 0 2X# ISA# LB# Bus Type L L L_ Reserved L L H_ Reserved L H L. Reserved L H 4H Cpu Direct (2x LCLK) (pin-23=CRESET) H L L__ Reserved H L H_ ISA Bus H H_- L_ PCI Bus (65545 only) H H H_ VL-Bus (1x clk) (pin-23=RDYRTN#) 3 CFG3-Reserved The pin corresponding to this bit has no internal hardware function so may be used for sampling external conditions at reset. 4 CFG4-Reserved The pin corresponding to this bit must be sampled high on reset so this bit will always read back 1. Revision 1.2 98 65540 / 545 M 20948116 00114624 135Extension Registers CPU INTERFACE CTRL REGISTER 1(XR02) Read/Write at I/O Address 3D7h Index 02h (D7/D6|Ds[D4|D3 D2[D1|D9| [__ Enable 16-bit Mem Access Digital Monitor Mode Sim Disp CRT H Timing Attribute Controller Mapping 10-bit YO Address Decode 83C6-83C9 Palette Decode Attribute FF Status (R/O) 0 8/16-bit CPU Memory Access Q 8-bit CPU memory access (default) 1 16-bit CPU memory access 1 Digital Monitor Clock Mode 0 Normal (clk 0-1=25,28 MHz) (default) 1 Digital Monitor (clk 0-1=14,16MHz) 14MHz = 56MHz = 4 or 28MHz + 2 16MHz = 50MHz + 3 2 SimultaneousDisplayCRTHTimingSelect 0 Use XR19,1A,1B for H parameters 1 Use CR04,05,00 for H parameters 4-3 AttributeControllerMapping 00 Write Index and Data at 3COh. (8-bit access only) (default - VGA mapping) 01 Write Index at 3COh and Data at 3C1h (8-bit or 16-bit access). Attribute flip- flop (bit-7) is always reset in this mode (16-bit mapping) 10 Write Index and Data at 3COh/3C1h (8-bit access only) (EGA mapping) 11 Reserved 5 IO Address Decoding QO Decode all 16 bits of I/O address (default) 1 Decode only lower 10 bits of I/O address. This affects addresses 3B4- 3B5h, 3B8h, 3BAh, 3BFh, 3C0- 3C2h, 3C4-3C5h, 3CE-3CFh, 3D4- 3D5h, and 3D8-3DAh. 6 Palette Address Decoding 0 External palette registers can be accessed only at 3C6h-3C9h (default) 1 External palette regs can be accessed at 3C6h-3C9h & 83C6h-83C9h 7 Attribute Flip-Flop Status (readonly) 0 = Index, 1 = Data Revision 1.2 99 Me 2096116 00118e5 07, 65540 / 545Extension Registers CPU INTERFACE CTRL REGISTER 2 (XR03) Read/Write at I/O Address 3D7h Index 03h [D7 D6[Ds|D4 D3|D2|D1 [Do] 0 3-2 [__ Palette Write Shadow DR Access Ena (545 only) | Reserved(0) Palette RDY Response Diagnostic (Set to 0) Reserved(0) Palette Write Shadow 0 Chip responds normally to Palette Write accesses (LDEV# is returned for VL-Bus and DEVSEL+# is returned for PCI bus) 1 Palette write commands are executed internally but the chip does not respond externally (LDEV# is not returned for VL-Bus and DEVSEL# is not returned for PCI bus). This conforms to both VL-Bus and PCI bus "Palette Shadowing requirements as it forces the access to be passed on to the ISA bus where add-in cards may be shadowing the VGA color palette data. This bit should normally be set to 1. DR Register Access Enable Q 32-Bit DRxx register access Disabled (Default) 1 DRxx registers accessible at I/O port defined by XRO7. Reserved (0) ISA Bus Palette Access RDY Response 0 Hold off the CPU using RDY for palette accesses (read or write to 3C6- 3C9h). 1 Do not hold off the CPU using RDY for palette accesses (read or write to 3C6-3C9h) The internal RAMDAC has a minimum specification for time between accesses. A faster CPU is more likely to violate this specification, so it is normally required to add delay between accesses in software. 5 This bit may be set to 0 to effectively create a CPU-transparent delay, however this is not compatible with some systems: some systems ignore RDY for palette accesses, so for those systems, this bit must be set to 1. Diagnostic (R/W but should be set to 0) 7-6 Reserved (0) Revision 1.2 100 65540 / 545 M@ 2094116 00114826 TOS a2 esse Extension Registers MEMORY CONTROL REGISTER 1 (XR04) Read/Write at I/O Address 3D7h Index 04h (D7|D6|D5[D4 D3|D2[D1 [Do| =} Memory Configuration Memory Wraparound Ctrl Reserved(Q) Write Buffer Enable | Reserved(0) 1-0 Memory Configuration 00 32-bit memory data path, Memory data bus is on MAD15-0 & MBD15-0 (DRAMs A and B). If frame acceler- ation is enabled and embedded frame buffer is selected, the data will be stored in both DRAMs A and B. An external frame buffer can be enabled on DRAM C with this setting. 01 16-bit data path (DRAM A only). The memory data bus is on MAD15-0. If frame acceleration is enabled and embedded frame buffer is selected, the data will be restricted to storage in DRAM A only. An external frame buffer can be enabled on DRAM C with this setting. 10 32-bit memory data path. Memory data bus is on MAD15-0 & MCD15-0 (DRAMs A & C). DRAM C cannot be used as an external frame buffer with this setting, but programming can select between this setting and '01' to switch the function of DRAM C between use as display memory and use as an external frame buffer. 11 Reserved DRAM A must always be present and if that is the only DRAM present, setting 01 must be used. DRAM B may optionally be present and if it is, setting 00 may be used (either 00 or OL may be programmed with DRAMs A & B physically present). If all three DRAMs are present, setting 00 would normally be used (00, 01, and 10 are all allowable). Setting 10 would be used where only two DRAMs (A and C) are physically present (this field is set to 10 to use both 4-3 7-6 DRAMs as |MB of display memory and set to 01 to use DRAM A as 512KB of display memory and DRAM C as an external frame buffer). Memory Wraparound Control This bit enables bits 16-17 of the CRT Controller address counter (default = 0 on reset). 0 Disable CRTC addr counter bits 16-17 1 Enable CRTC addr counter bits 16-17 Reserved (0) CPU Memory Write Buffer Q Disable CPU memory write buffer (default) 1 Enable CPU memory write buffer Reserved (0) Revision 1.2 101 65540 / 545 M@ 2058116 0011427 944@ Extension Registers MEMORY CONTROL REGISTER 2 (XR05) Read/Write at I/O Address 3D7h Index 05h (D7 [D6 DS D4[D3[D2[D1 Do] ss = L_ Disable Long CPU Cycles CPU Access CAS# Ctrl Display Access CAS# Ctrl DRAM CAS# Address Memory CAS/WE Select Frame Buffr CAS/WE Slct PC Video Interface Enable PC Video Interface Width Disable Long CPU Cycles 0 Enable long CPU cycles (default on RESET). This puts as many CPU cycles as possible into one RAS cycle. 1 Disable long CPU cycles. CPU-MemAccessCAS#Cycle Ctrl (545) Display Mem AccessCAS#CycleCtrl (545) Bit-1 affects accesses to display memory initiated by the 65545 for display refresh. Bit-2 affects CPU accesses to display memory in the 65545. Both bits are defined as follows: 0 3-MCLK CAS# cycle (2 low, 1 high) for all read or write accesses (default) 1 4-MCLK CAS# cycle (3 low, 1 high) for all read accesses and for the first CAS# cycle of page-mode write accesses (following cycles are 2L/1H) These bits may be set to create looser memory timing (e.g., for 3.3V operation, to allow use of cheaper DRAMs, etc.). 4- MCLK CAS cycles are not supported in the 65540. Asymmetric Address for DRAMs A & B 0 Symmetric 256Kx16 DRAM is used (9-bit RAS/CAS addresses) (default) 1 Asymmetric 256Kx16 DRAM is used (10-bit RAS/8-bit CAS address) Asymmetric address DRAMs should not be used (and this bit should not be set to one) if AAG is used as a 32KHz clock input (see XR33 bit-6) or if 24-bit PC-Video interface is enabled (see bit-7 of this register), See also XR6F bit-2 (address symmetry control for DRAM C). CAS#/ WE# Select for DRAMs A&B Q 2-CAS# / 1-WE# 256Kx16 DRAM configurationis used (default) 1 1 CAS# and 2 WE# 256Kx16 DRAM configuration is used CAS#/WE# Select for DRAM C This bit is effective when XR6F[7]=1. 0 2 CAS# and 1 WE# configuration 256Kx16 DRAM is used (default) 1 1 CAS# and 2 WE# configuration 256Kx16 DRAM is used PC Video Interface Enable Q Disable PC Video Interface (default) 1 Enable PC Video interface on DRAM 'C pins (MCD15-0, RASC#, CASCH#, CASCL#, and WEC#). If bit-7 of this register is set to 1, OEC#H, AA9, ACTI, ENABKL, and CA8-9 also serve as PC Video Interface pins. An external frame buffer cannot be used in this configuration. PC Video Interface Control 0 18-bit PC Video interface 1 24-bitPC Video interface Note: When this bit is set to 1, AA9, ENABKL, ACTI pins are used for video inputs therefore they lose their alternate functions. When this bit is set to 1, a 24-bit panel interface is also available (CAO-7 become P16-23). This bit should not be set to 1 if the AD# (A26-27 enable) or EC# (external clock) configuration bits are asserted low at reset (since this enables ACTI and ENABKL to perform alternate functions). Revision 1.2 102 65540 / 545 Mi 20594116 0011424 440Extension Registers PALETTE CONTROL REGISTER (XR06) Read/Write at I/O Address 3D7h Index 06h (D7/D6|[Ds D4[D3]D2[D1 [Do] L_ Pixel Out Diagnostic Mode Internal DAC Disable Display Mode Color Depth PC Video Color Key Enble Bypass Internal Palette FP Color Reduction Select 0 Pixel Data Pin Diagnostic Output Mode 0 Normal operation. Pixel data (P15:0) pins output flat panel pixel data (default on Reset). 1 Output CRT pixel data on pixel data pins PO-7 and output various internal signals on pixel data pins P8-15 for diagnostic purposes. 1 Internal DAC Disable This bit affects the DAC analog outputs. Q Enable internal DAC (default on Reset). DAC analog outputs (R, G, B) will be active and HSYNC and VSYNC signals are driven (Default on reset). 1 Disable internal DAC. The DAC analog outputs (R, G, B) will be 3- stated. Setting this bit forces power down of the internal DAC. HSYNC and VSYNC are forced inactive if XRSD[6] is 0 and will be driven if XRS5D{6] is 1. 3-2 Display Mode Color Depth 00 4 or 8 bits-per-pixel (default on reset) 01 16 bpp (5-5-5) (Targa compatible) 10 24 bpp (true color) 11 16 bpp (5-6-5) (XGA compatible) 4 PCVideo Color Key Enable 0 Disable PC Video Overlay (default on reset) 1 Enable PC Video Overlay on color key Bypass Internal VGA Palette 0 Use internal VGA palette (Default on reset). 1 Bypass internal VGA palette which will be powered down if DAC is disabled. Color Reduction Select These bits are effective in flat panel mode. These bits select the algorithm used to reduce 24-bit or 18-bit color data to 8-bit or 6-bit color data for monochrome panels. 00 NTSC weighting algorithm (default on Teset) 01 Equivalentweightingalgorithm 10 Green only 11 Color (no reduction). This setting should be used when driving color panels. Revision 1.2 103 65540 / 545 MH 20948116 0011829 717Se a taEE Extension Registers VO BASE REGISTER (XR07) Read/Write at /O Address 3D7h Index 07h (D7|D6|Ds[D4|D3[D2 D1[D0| L- - 1/0 Base for 32-Bit Regs (65545 only) 7-0 VO Base for 32-Bit Registers (65545 only) In ISA and VL-Bus configuration, these bits determine the I/O range for the Doubleword Hardware Cursor & BitBLT registers (DRxx). The value programmed here is matched against CPU addresses A15 & A8- 2, Address A9 must equal 1 and Al4-10 select one of 32 DR registers. For example, a programmed value of 074h (011101 O0b) would result in this DR register mapping: DRxx: nxxx xx1n nnnn nn00b DROO: 03D0h = 0000 0011 1101 0000b DRO1: O7D0h = 0000 0111 1101 0000b DRO2: OBDOh = 0000 1011 1101 0000b DRO3: OFDOh = 0000 1111 1101 0000b DRO4: 13D0h = 0001 0011 1101 0000b DROS: 17D0h = 0001 0111 1101 0000b DRO6: 1BDO0h = 0001 1011 1101 0000b DRO7: 1FDOh = 0001 1111 1101 0000b DRO8: 23D0h = 00100011 1101 0000b DRO9: 27D0h = 0010 0111 1101 0000b DROA: 2BD0h = 0010 1011 1101 0000b DROB: 2FDOh = 0010 1111 1101 0000b DROC: 33D0h = 0011 0011 1101 0000b The DRxx registers are enabled for access by setting XRO3[1]. They are disabled following Reset. The programmer should write this register before enabling access to the DRxx registers. In PCI bus configuration, this register is ignored. The PCI Configuration IOBASE register is used to determine the base address for the 32-bit registers in the PCI I/O space. Note that for PCI bus configuration only, the 32-bit registers may also be memory mapped: MBASE defines a 2MB memory space with frame buffer memory mapped into the lower megabyte and the 32-bit registers mapped into the upper megabyte. LINEARADDRESSINGBASEREGISTER(XR08) Read/Write at I/O Address 3B7h/3D7h Index 08h [D7 [D6|[D5 [D4|D3 [D2/D1 [Do| L LinearAddressBase 7-0 Linear Address Base In VL-Bus_ configuration, if linear addressing is enabled (XROB[4]=1), these 8 bits are compared to A[27:20] to determine the base address of the 1MB of display memory in the 256MB VL-Bus address space (normally the VL address space is 4GB, but only 28 bits of address are de- coded by the chip). For example, if the video memory is to be placed at 12MB (0C00000-OCFFFFFh), this register should be programmed to '00001100b'. Note that as a result, programming this register to 0 is typically not useful. If A26-27 are not available (used for ACTI and ENABKL if Configuration Register XRO1 bit-6 = 1) then bits 6-7 of this register are ignored and only A20-25 are compared against bits 0-5 of this register to determine the base address for the linear frame buffer in the VL-Bus / 486 CPU memory space. Similarly, if A25 and/or A24 are not available (see configuration bits 3, 4, and 7), bits 5 and/or 4 are also ignored. In ISA bus configuration, address inputs A24-27 are never available, so bits 4-7 of this register are ignored and A20-23 are compared against bits 0-3 of this register to determine the base address for the linear frame buffer in the 16MB ISA memory space. In PCI bus configuration, this register is ignored. The PCI Configuration MBASE register is used to determine the base address for the linear frame buffer in the 4GB (full 32-bit address) PCI memory address space. Revision 1.2 104 65540 / 545 M 20948116 0011430 435Extension Registers CPU PAGING REGISTER (XROB) 4 _ Linear Addressing Enable 0 Standard VGA (A0000 - BFFFF) Read/Write at /O Address 3D7h Index OBh (D7 D6[D5|D4]D3 [D2[D1|Do| [__ Memory Mapping Mode Single/Dual Map CPU Address Divide by 4 Extended Text Mode (545) Linear Addressing Enable Reserved(0) Memory Mapping Mode 0 Normal Mode (VGA _ compatible) (default on Reset) 1 Extended Mode (mapping for > 256 KByte memory configurations) CPU Single/Dual Mapping 0 CPU uses only a single map to access the extended video memory space (default on Reset) 1 CPU uses two maps to access the extended video memory space. The base addresses for the two maps are defined in the Low Map Register (XR10) and High Map Register CXR11). CPU Address Divide by 4 0 Disable divide by 4 for CPU addresses (default on Reset) 1 Enable divide by 4 for CPU addresses. This allows the video memory to be accessed sequentially in mode 13. In addition, all video memory is available in mode 13 by setting this bit. Extended Text Mode (65545 only ) Set to enable text font scrambling in plane 2. Setting this bit improves text mode performancein single-DRAMconfigurations (with the proper BIOS support for font load/reload functions). This bit should be set in single DRAM configurations only. This bit is supported in the 65545 only; it should be programmed to 0 in the 65540. memory space decoded on-chip using A17-19 (default on Reset) 1 Linear Addressing Enabled. See XRO8 (Linear Addressing Base) for base address selection. Ignored in PCI bus configuration (see DEVCTL). 7-5 Reserved (0) START ADDRESS TOP REGISTER (XROC) Read/Write at I/O Address 3D7h Index OCh (D7|D6|D5[D4]D3|D2[D1 DO L Start Address Top Reserved(0) 1-0 Start Address Top These bits defines the high order bits for the Display Start Address when 512 KBytes or more of memory is used (see XRO4 bits 1-0). 7-2 Reserved (0) Revision 1.2 105 MH 2094116 0011431 375 65540 / 545Extension Registers AUXILIARY OFFSET REGISTER (XROD) Read/Write at YO Address 3D7h Index ODh (p7[D6|Ds[D4 D3{D2|D1 Do] TEXT MODE CONTROL REGISTER (XROE) Read/Write at I/O Address 3D7h Index OEh [D7{D6 D5|D4]/D3[D2]D1 [Do] [_ LSB of Offset (CR13) LSB of Alt Offset CCRIE) Reserved(0) Offset Register LSB This bit provides finer granularity to the display memory address offset when word and doubleword modes are used. This bit is used with the regular Offset register (CR 13). Alternate Offset Register LSB This bit provides finer granularity to the display memory address offset when word and doubleword modes are used. This bit is used with the Alternate Offset register (XRI1E). 7-2 Reserved (0) | Reserved(0) Cursor Blink Disable Cursor Style Alt Cursor Start (65545) Sync Reset Ignore This register is effective for both CRT and flat panel text modes. 1-0 2 6-4 Reserved (0) Cursor Mode 0 Blinking (default on Reset). 1 Non-blinking Cursor Style 0 Replace (default on Reset) 1 Exclusive-Or Alternate Cursor Start (65545 Only) When the alternate CRTC registers are active, this field may be set to specify the Cursor Start Scan Line instead of CROA bits 0-4 (this field specifies alternate bits 0-2 with bits 3-4 assumed to be 0). VGA software typically changes the shape of the cursor frequently between underline and block styles. This field allows the cursor style to be fixed (typically to 'block' for improved readability on panels). Synchronous Reset Ignore When this bit is set, the chip will ignore SROO bit-1 (Synchronous Reset) and will remain in normal operation. Synchronous reset is a holdover from the original VGA which is no longer required. VGA software, however, performs synchronous resets frequently, creating the possibility for display memory corruption if the chip is left in the synchronous reset state for too long. The 65540 / 545 display memory sequencer does not need to be periodically reset, so this bit is provided to prevent potential display memory corruption problems. For absolute VGA compatibility, this bit may be set to 0. Revision 1.2 106 65540 / 545 MB 2094116 0011432 201Extension Registers SOFTWARE FLAGS REGISTER 0 (XROF) Read/Write at I/O Address 3D7h Index OFh D7[D6|D5|D4|[D3[D2|D1 [Do] L. Memory Size Reserved(0) Hi / True Color Select Packed Pixel Dot Clock Interlace Select Text Compensation Enable This register contains eight read-write bits which have no internal hardware function. All bits are reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: 1-0 Memory Size 00 256KB 01 512KB ix 1MB 2-3. Reserved (0) 4 HiColor/True Color 0 Current mode is_not hi-/true-color mode 1 Current mode is hi-color / true-color mode 5 Packed-Pixel Mode Dot Clock 0 Use default dot clock in packed-pixel modes 1 Use 40MHz dot clock in packed-pixel modes This bit is used for high resolution panels in panel mode only. 6 = InterlaceSelect O Set mode 24h, 34h, 72h/75h or 7Eh interlaced 1 Set mode 24h, 34h, 72h/75h or 7Eh non-interlaced 7 Text Compensation Enable/Disable 0 Tall font disabled 1 Tall fontenabled See also XR2B, XR44, XR45 for definition of other software flags registers. Revision 1.2 107 Me 20598116 00114833 148 65540 / 545SINGLE/LOW MAP REGISTER (XR10) Read/Write at /O Address 3D7h Index 10h D7[D6[D5 p4[D3[D2|D1 DO LL Single or Lower Map Base Address Bits 17-10 This register effects CPU memory address mapping. 7-0 Single/Low Map Base Address Bits 17-10 These bits define the base address in single map mode (XROB bit-1 = 0), or the lower map base address in dual map mode (XROB bit-1 = 1). The memory map starts on a 1K boundary in planar modes and on a 4K boundary in packed pixel modes. In case of dual mapping, this register controls the CPU window into display memory based on the contents of GR06 bits 3-2 as follows: Extension Registers HIGH MAP REGISTER (XR11) Read/Write at /O Address 3D7h Index 1th (D7|D6[D5|D4[D3[D2[D1 Do] L Higher Map Base Address Bits 17-10 This register effects CPU memory address mapping. 7-0 High Map Base Address Bits 17-10 These bits define the Higher Map base address in dual map modes (XROB bit-1=1). The memory map starts on a 1K boundary in planar modes and on a 4K boundary in packed pixel modes. This register controls the CPU window into display memory based on the contents of GRO6 bits 3-2 as follows: GRO06 bits 3-2 High Map GR06 00 BO000-BFFFF Bits 3-2 Low Map Wo Deon AFEFP 00 A0000-AFFFF 1 Dent care 01 A0000-A7FFF ont care 10 BOO00-B7FFF Single mapping only 11 B&8000-BFFFF Single mapping only Revision 1.2 108 65540 / 545 Mi 2098116 00114634 0464Extension Registers EMULATION MODE REGISTER (XR14) 6 VSync Status Mode Read/Write at I/O Address 3D7h Index 14h [D7|D6[D5 [p4[D3 D2[D1 [Do| 1-0 Emulation Mode 00 VGA mode (default on Reset) 01 CGA mode 10 MDA/Herculesmode 11 EGAmode 3-2 Hercules Configuration Register (3BFh) readback (read only) 4 Display Enable Status Mode 0 Select DisplayEnable status to appear at bit O of Input Status register 1 (/O Address 3BAh/3DAh) (default on reset). Normally used for CGA, EGA, and VGA modes. 1 Select HSync status to appear at bit 0 of Input Status register 1 (I/O Address 3BAh/3DAh). Normally used for MDA/ Hercules mode. 5 - Vertical Retrace Status Mode 0 Select VerticalRetrace status to appear at bit 3 of Input Status register 1 (/O Address 3BAh/3DAh) (default on Reset). Normally used for CGA, EGA, and VGA modes. 1 Select Videoto appear at bit 3 of Input Status register 1 (V/O Address 3BAh/3DAh). Normally used for MDA/ Hercules mode. 0 Prevent VSync status from appearing at bit 7 of Input Status Register 1 (/O Address 3BAh/3DAh). Normally used for CGA, EGA, and VGA | modes. Emulation Mode Enable VSync status to appear as bit-7 of Input Status Register 1 (I/O Herc Config (read only) Address 3BAh/3DAh). Normally used for MDA/Hercules mode. DE Status Mode 7 Interrupt Output Function V Retrace Status Mode o, . . VSync Status Mode This bit controls the function of the interrupt Interrupt Polarity output pin (IRQ): InterruptState Bit-7=0 Bit-7=1 Disabled 3-state 3-state Enabled,Inactive 3-state Low Enabled, Active 3-state High Revision 1.2 109 65540 / 545 Me 2098116 0011835 T10 aExtension Registers WRITE PROTECT REGISTER (XR15) Read/Write at I/O Address 3D7h Index 15h [D7 D6|D5|D4 D3[D2|D1 Do] Wr Protect AR11 This register controls write protection for various groups of registers as shown. OQ = unprotected (default on Reset), 1= protected. 0 Write Protect Group 1 Registers This bit affects the Sequencer registers (SRO00-04), Graphics Controller registers (GROO-08), and Attribute Controller registers (AROO-14). Note that AR11 is also protected by bit-7 which is ORed with this bit. 1 Write Protect Group 2 Registers This bit affects CRO9 bits 0-4, CROA, and CROB. 2 Write Protect Group 3 Registers This bit affects CRO7 bit-4, CRO8, CR11 bits 5-4, CR13, CR14, CR17 bits 0-1 and bits 3-7, and CR18. 3. Write Protect Group 4 Registers This bit affects CRO9 bits 5-7, CR10, CR11 bits 0-3 and bits 6-7, CR12, CR15, CR16, and CR17 bit-2. 4 Write Protect Group 5 Registers This bit affects the Miscellaneous Output register (3C2h) and the Feature Control register(3BAh/3DAh). 5 Write Protect Group 6 Registers This bit affects the VGA color palette registers (3C6h-3C9h). If this bit is set, all VGA color palette registers are write protected. L__ Wr Protect Group 1 Regs Wr Protect Group 2 Regs Wr Protect Group 3 Regs Wr Protect Group 4 Regs Wr Protect Group 5 Regs Wr Protect Group 6 Regs Wr Protect Group 0 Regs Write Protect Group 0 Registers This bit affects CRO-7 (except CRO7 bit-4). This bit is logically ORed with CR11 bit-7. Write Protect AR11 This bit is ORed with bit-0, therefore writing to AR11 is possible only if both bit-O and bit-7 are 0. This feature is used for write protection of the overscan color. This is important in order to keep application software from changing the border color while still permitting the attribute controller to be changed for the addressable portion of the display. Overscan is increasingly becoming an ergonomics requirement and this bit will ensure software compatibility. Revision 1.2 110 65540 / 545 ME 2098116 00118356 157Extension Registers VERTICAL OVERFLOW REGISTER (XR16) Read/Write at /O Address 3D7h Index 16h D7|D6[D5[D4[D3 D2|D1 [Do] L_ Vertical Total Bit 10 Vertical Display End Bit 10 Vertical Sync Start Bit 10 Reserved(R/W) Vertical Blank Start Bit 10 Reserved(R/W) Line Compare Bit 10 Reserved(R/W) This register is used for both normal and alternate verticalparameters. 0 ~=- Vertical Total Bit-10 Vertical Display End Bit-10 Vertical Sync Start Bit-10 Reserved (R/W) Vertical Blank Start Bit-10 Reserved (R/W) Line Compare Bit-10 Reserved (R/W) SA oH & GS WN we HORIZONTALOVERFLOWREGISTER(XR17) Read/Write at I/O Address 3D7h Index 17h [D7 D6[D5|D4 D3/D2|D1 [Do] L Horizontal Total Bit 8 Horizontal Disp End Bit 8 Horizontal Sync Start Bit 8 Horizontal Sync End Bit 5 Horizontal Blank Strt Bit 8 Horizontal Blank End Bit 6 Line Compare Bit 10 Reserved(R/W) This register is used for both normal and alternate horizontalparameters. 0 Horizontal Total Bit-8 Horizontal Display End Bit-8 Horizontal Sync Start Bit-8 Horizontal Sync End Bit-5 Horizontal Blank Start Bit-8 Horizontal Blank End Bit-6 Line Compare Bit-10 Reserved (R/W) NSW mn & WwW NH Revision 1.2 111 65540 / 545 Mi 2094116 0011837? 493Crnir> Extension Registers ALTERNATEHORIZONTAL ALTERNATE HORIZONTAL SYNC START DISPLAY END REGISTER (XR18) REGISTER (XR19) Read/Write at 1/O Address 3D7h Read/Write at I/O Address 3D7h Index 18h Index 19h (D7|D6|Ds]D4 D3/D2[D1|Do| [D7|D6|Ds D4]D3|D2]D1|D0] Alternate H Display End | FP HSync Start This register is used in flat panel and CRT CGA text This register is used in all flat panel modes with and graphics modes, and Hercules graphics mode. horizontal compression disabled, to set the horizontal sync start. This register is also used in CRT CGA 7-0 Alternate Horizontal Display End text and graphics modes, and Hercules graphics This register specifies the number of mode. characters displayed per scan line, similar to 7-0 Alternate Horizontal Sync Start CRO1. These bits specify the beginning of the Programmed Value = Actual Value - 1 HSync in terms of character clocks from the beginning of the display scan. Similar to Note: This register is used in emulation modes only. CRO04. ete used in CRT or flat panel VGA Programmed Value = Actual Value1 Revision 1.2 112 65540 / 545 ' M@ 2098116 0011838 72TALTERNATE HORIZONTAL SYNC END REGISTER (XRIA) Read/Write at /O Address 3D7h Index 1Ah [p7/D6 Ds D4|D3/D2 D1{Do| FP H Sync End Alternate H Sync Delay _________--_ Reserved(0) This register is used in all flat panel modes with horizontal compression disabled, CRT CGA text and graphics modes, and Hercules graphics mode. 4-0 Alternate Horizontal Sync End Lower 5 bits of the character clock count which specifies the end of horizontal sync. Similar to CRO5. If the horizontal sync width desired is N clocks, then programmed valueis: (N + Contents of XR19) ANDed with 01F Hex 6-5 CRT Alternate Horizontal Sync Delay See CRO5 for description 7 ~ Reserved (0) Extension Registers ALTERNATEHORIZONTALTOTAIREGISTER (XRIB) Read/Write at /O Address 3D7h Index 1Bh [D7 D6[D5|[D4[D3/D2 D1[D0] FP H Total This register is used in all flat panel modes with horizontal compression disabled, CRT CGA text and graphics modes, and Hercules graphics mode. 7-0 Alternate Horizontal Total This register contents are the total number of character clocks per line. Similar to CROO. Programmed Value = Actual Value5 Revision 1.2 113 65540 / 545 ME 2098116 0011435 bbbALTERNATE HORIZONTAL BLANK START/ HORIZONTALPANELSIZEREGISTER(XRIC) Read/Write at /O Address 3D7h Index 1Ch [D7/D6|Ds p4[D3/D2 D1{Do| H Blank Start (Horizontal Panel Size) The value in this register is the Horizontal Panel Size in all Flat Panel Modes. In CRT mode, it is used for CGA text and graphics and Hercules graphics modes. 7-0 FP Horizontal Panel Size Horizontal panel size is programmed in terms of number of 8-bit (graphics/text) or 9-bit (text) characters. For double drive flat panels the actual horizontal panel size must be a multiple of two character clocks. Programmed Value = Actual Value-1 or 7-0 CRT Alternate Horizontal Blank Start See CRO2 for description Programmed Value = Actual Value 1 Extension Registers ALTERNATE HORIZONTAL BLANK END REGISTER (XR1D) Read/Write at I/O Address 3D7h Index 1Dh (D7[D6/D5[D4[D3/D2|[D1 [Do] H Blank End DE Skew Control Split Screen Enhance Bits 0-6 of this register are used in CRT CGA text and graphics modes and CRT Hercules graphics mode. Bit 7 of this register is used for all CRT and flat panel modes. 4-0 CRT Alternate Horizontal Blank Start See CRO3 for description 6-5 CRTAlternateDisplayEnableSkewControl See CRO3 for description 7 Line Compare Fix This bit affects all CRT and FP text modes. This bit is 0 on reset. 0 Internal Line Compare (split screen) flag is not delayed so that the Vertical Row Counter is reset too early which in text mode causes the first scanline of the first character row following split screen to be skipped (not dis- played). This is IBM VGA com- patible. 1 Internal Line Compare (split screen) flag is delayed so that the Vertical Row Counter is reset properly which in text mode causes the first scanline of the first character row following split screen to be displayed Note: This register is used in emulation modes only. It is not used in CRT or flat panel VGA modes. Revision 1.2 114 65540 / 545 MH 2098116 0011840 346abscas aay canons annbes Cnirs Extension Registers ALTERNATE OFFSET REGISTER (XRIE) Read/Write at I/O Address 3D7h Index 1Eh D7 D6[D5|D4[D3 [D2 D1 [Do] Alternate Display Buffer Width This register is used in all flat panel modes, CRT CGA text and graphics modes and Hercules graphics mode. 7-0 Alternate Offset See CR13 for description Programmed Value = Actual Value1 VIRTUAL EGA SWITCH REGISTER (XRIF) Read/Write at I/O Address 3D7h Index 1Fh D7|D6]D5 p4[D3[D2[D1 DO Virtual EGA Switches Reserved(0) Sense Select 3-0 Virtual Switch Register If bit-7 is 'l', then one of these four bits is read back in Input Status Register 0 (3C2h) bit 4. The selected bit is determined by Miscellaneous Output Register (3C2h) bits 3-2 as follows: Misc 3-2. XRIFBit Selected 00 bit-3 01 bit-2 10 bit-1 11 bit-0 6-4 Reserved (0) 7 Sense Select 0 Select the output of the internal RGB comparator (Sense) for readback in Input Status Register 0 bit-4 (default on Reset). 1 Select one of bits 3-0 for readback in Input Status Register 0 bit-4. Revision 1.2 65540 / 545 ME 2098116 0011441 214Extension Registers ALTERNATE MAXIMUM SCANLINE REGISTER (XR24) Read/Write at 1/O Address 3D7h Index 24h (D7|D6]Ds|D4 D3 D2/D1{Do] Alternate Max Scanlines Reserved(R/W) This register is used in flat panel text mode when TallFont is enabled during vertical compensation. 4-0 Alternate Maximum Scanlines (AMS) Programmed Value = number of scanlines minus one per character row of TallFont Double scanned lines, inserted lines, and replicated lines are not counted. 7-5 Reserved (R/W) ALTERNATE TEXT MODE/HORIZONTAL VIRTUAL PANEL SIZE REGISTER (XR25) Read/Write at I/O Address 3D7h Index 25h [D7|D6 D5[D4]D3|[D2 D1 [Do| AltText Mode H Virtual Panel Size This register is used in flat panel 9-dot text modes. 7-0 Alternate Text Mode Horizontal Virtual Panel Size Programmed Value = 9/8 [XRIC + 1]-1 ALTERNATE HORIZONTAL SYNC START OFFSET REGISTER (XR26) Read/Write at I/O Address 3D7h Index 26h (D7|De6]Ds D4]D3|D2]D1 Do] Alt H Sync Start Offset This register is used in flat panel mode. 7-0 Horizontal Sync Start Offset This value is added to CRO4 ( Horizontal Sync Start) when XRO2 bit 2 is set to I. Revision 1.2 116 65540 / 545 MB 2098116 0011442 150Extension Registers VIDEO INTERFACE REGISTER (XR28) Read/Write at I/O Address 3D7h Index 28h (D7|D6 D5(D4[D3|[D2[D1 Do] 3-2 | Reserved(0) Blank#/DE Select Reserved(0) 256-Color Video Path InterlaceMode 8-Bit Video Pixel Panning Tall Font Replication Reserved (0) Blank/Display Enable Select This bit is effective in CRT mode only. In flat panel mode, XR54 bit-1 controls BLANK# functionality. 0 BLANK# controls color palette blanking (default on reset) 1 Display Enable controls color palette blanking Note: This bit also controls the functionality of pins 68 or 69 when BLANK# / DE is selected for output instead of the default function (M is normally output on pin 69 and LP is normally output on pin 68 but this can be changed by XR4F bits 6 and 7 respectively). See also XR54 bits 0 and 1. Reserved (0) 256-Color Video Path This bit is effective for both CRT and flat panel in 256-color modes other than mode 13 (.e., Super VGA modes). 0 4-bit video data path (default on reset) 1 &-bit video data path (horizontal pixel panning is controlled by bit-6) Note: GRO5 bit-5 must be 0 if this bit is set Interlace Video This bit is effective only for CRT graphics mode. This bit should be programmed to 0 for flat panel. In interlace mode XR29 holds the half-line positioning of VSync for odd rames. Q Non-interlaced video (default on reset) 1 Interlacedvideo 6 8-Bit Video Pixel Panning This bit is effective for both CRT and flat panel when the 8-bit video data path is selected (bit-4 = 1). 0 AR13 bits 2-1 are used to control pixel panning (default on Reset) 1 AR13 bits 2-0 are used to control pixel panning 7 ~~ Tall Font Replication 0 Tall font replicates lines 1, 9 and 12 1 Tall font replicates line 0 twice and line 15 once HALF LINE COMPARE REGISTER (XR29) Read/Write at I/O Address 3D7h Index 29h (p7[D6|Ds|D4 D3[D2|D1 Do| Half-Line Compare In Interlaced mode CRT operation, this register is used to generate the Half Line Compare Signal. 7-0 CRT Half-Line Value In CRT interlaced video mode this value is used to generate the half-line compare signal that controls the positioning of the VSync for odd frames. Revision 1.2 117 65540 / 545 MB 2098116 0011843 097Extension Registers SOFTWARE FLAGS REGISTER 1 (XR2B) Read/Write at I/O Address 3D7h Index 2Bh (D7[D6]D5|[D4[D3]p2|D1 Do] Flag 0 Flag 1 Flag 2 Flag 3 Flag 4 Flag 5 Flag 6 Flag 7 This register contains eight read-write bits which have no internal hardware function. All bits are reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: 7-0 Display Mode These bits are used by the BIOS to store the current display mode number. See also XROF, XR44, XR45 for definition of other software flags registers. FLM DELAY REGISTER (XR2C) Read/Write at 1/O Address 3D7h Index 2Ch [p7|D6 D5[D4]D3[D2[D1 [Do] FLM Delay This register is used only in flat panel mode when XR2F bit-7=0. The First Line Marker (FLM) signal is generated from an internal FP VSync active edge with a delay specified by this register. The FLM pulse width is always one line for SS panels and two lines for DD panels. 7-0 FLM Delay (VDelay) These bits define the number of HSyncs between the internal VSync and the rising edge of FLM. Revision 1.2 118 65540 / 545 MM 2098116 00114844 T23Extension Registers LEDELAY REGISTEKCMPRENABLEDYXR2D) Read/Write at /O Address 3D7h Index 2Dh (p7/D6|[Ds|D4 D3[D2|D1 Do] LP Delay (graphics mode horizontal compression enabled This register is used only in flat panel mode when XR2F bit-6 = 0 and graphics mode horizontal compression is enabled The LP output is generated from the FP Blank inactive edge with a delay specified by XR2F bit-5 and the value in this register. The LP pulse width is specified in register XR2F. 7-0 LP Delay These bits define the number of character clocks between the FP Blank inactive edge and the rising edge of the LP output in flat panel mode with 9-dot text mode forced to 8-dot text. The msb (bit 8) of this parameter is XR2F bit-5. Programmed Value = Actual Value1 Note: For DD panels without frame acceleration, the programmed value should be doubled. LBELAYREGISTER (CMPRDISABLED{XR2E) Read/Write at I/O Address 3D7hIndex 2Eh D7|D6|D5|D4 D3[D2|Di [Do| LP Delay (graphics mode horizontal compression disabled This register is used only in flat panel mode when XR2F bit-6 = 0 and 9-dot text mode is used. The LP output is generated from the FP Blank inactive edge with a delay specified by XR2F bit-4 and the value in this register. The LP pulse width is specified in register XR2F. 7-0 LP Delay These bits define the number of character clocks between the FP Blank inactive edge and the rising edge of the LP output in flat panel 9-dot text modes. The msb (bit 8) of this parameter is XR2F bit-4. Programmed Value = Actual Value 1 Note: For DD panels without frame acceleration, the programmed value should be doubled. Revision 1.2 119 65540 / 545 MM 2094116 00113445 SbTr FEET. sTEEIE Extension Registers LP WIDTH REGISTER (XR2F) Read/Write at I/O Address 3D7h Index 2Fh (D7/D6|Ds p4][D3]D2[D1 Do| L LP Width LP Delay (XR2E) Bit-8 LP Delay (XR2D) Bit-8 LP Delay Disable FLM Delay Disable This register is used only in flat panel mode. This register together with XR2D or XR2E defines the LP output pulse in flat panel mode. 3-0 LP Width (HWidth) These bits define the width of LP output pulse in terms of number of character (8-dot only) clocks in flat panel mode. Programmed Value = Actual Value1 LP Delay (XR2E) Bit 8 This bit is the msb of the LP Delay parameter for 9-dot text modes. LP Delay (XR2D) Bit 8 This bit is the msb of the LP Delay parameter for graphics mode with horizontal compression disabled. LP Delay Disable 0 LP Delay Enable: XR2D and XR2F bit-5 (or XR2E and XR2F bit-4) are used to delay the LP active edge with respect to the FP Blank inactive edge. 1 LP Delay Disable: LP active edge will coincide with the FP Blank inactive edge. FLM Delay Disable 0 KLM Delay Enable: XR2C is used to delay the external FLM active edge with respect to the internal FP VSync active edge. 1 FLM Delay Disable: the external FLM active edge will coincide with the in- ternal FLM active edge. Revision 1.2 Me 20946116 0011446 ST 120 65540 / 545Extension Registers CLOCK DIVIDE CONTROL REGISTER(XR30) Read/Write at I/O Address 3D7h Index 30h [b7/D6[pDs[D4[D3 [D2 D1 [Do| [__ Reference Divisor Select VCO Post Divide Reserved(R/W) The three clock data registers (XR30-XR32) are programmed with the loop parameters to be loaded into the clock synthesizer. The Memory and Video clock VCO's both have programmable registers. Which of the VCO's is currently selected for programming is determined by the Clock Register Program Pointer (XR33[5]). The data written to this register is calculated based on the reference frequency, the desired output frequency, and characteristic VCO constraints as described in the Functional Description. Data is written to registers XR30, and XR31 followed by a write to XR32. The completion of the write to XR32 causes data from all three registers is transferred to the VCO register file simultaneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence. 0 Reference Divisor Select Selects the reference pre-scale factor: 0 Divide by 4 1 Divideby 1 3-1 Post Divisor Select Selects the post-divide factor: 000 Divideby 1 001 Divide by 2 010 Divideby4 011 Divideby 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 7-4 Reserved (R/W) Revision 1.2 WE 2094116 0011447? 732 121 65540 / 545CLOCK M-DIVISOR REGISTER (XR31) Read/Write at I/O Address 3D7h Index 3th [p7|De|Ds D4[D3[D2|D1 [Do| M-Divisor Value Reserved(R/W) The three clock data registers (XR30-XR32) are programmed with the loop parameters to be loaded into the clock synthesizer. The Memory and Video clock VCO's both have programmable registers. Which of the VCO's is currently selected for programming is determined by the Clock Register Program Pointer (XR33[5]). The data written to this register is calculated based on the reference frequency, the desired output frequency, and characteristic VCO constraints as described in the Functional Description. Data is written to registers XR30, and XR31 followed by a write to XR32. The completion of the write to XR32 causes data from all three registers is transferred to the VCO register file simultaneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence. 6-0 VCO M-Divisor M-Divisor value calculated for the desired output frequency. 7 Reserved (R/W) Extension Registers CLOCK N-DIVISOR REGISTER (XR32) Read/Write at 1/O Address 3D7h Index 32h [D7[D6|Ds|[D4[D3 [D2 D1|D0] N-Divisor Reserved(R/W) The three clock data registers (XR30-XR32) are programmed with the loop parameters to be loaded into the clock synthesizer. The Memory and Video clock VCO's both have programmable registers. Which of the VCO's is currently selected for programming is determined by the Clock Register Program Pointer (XR33[5]). The data written to this register is calculated based on the reference frequency, the desired output frequency, and characteristic VCO constraints as described in the Functional Description. Data is written to registers XR30, and XR31 followed by a write to XR32. The completion of the write to XR32 causes data from all three registers is transferred to the VCO register file simultaneously. This prevents wild fluctuations in the VCO output during intermediate stages of a clock programming sequence. 6-0 VCO N-Divisor N-Divisor value calculated for the desired output frequency. 7 Reserved (R/W) Revision 1.2 122 65540 / 545 MB 2098116 0011446 675agnen | zanas eae Extension Registers CLOCK CONTROL REGISTER (XR33) Read/Write at /O Address 3D7h Index 33h D7|D6|[D5|D4 D3{D2[D1 DO] [__ VCLK VCO Powerdown MCLK VCO Powerdown Oscillator Powerdown Reserved(R/W) Video Clock Select CLK Reg Program Pointer Power Sequencing Clock Clock Mode Control 0 VCLK VCO Powerdown 0 VCLK VCO Enabled (default) 1 VCLK VCO Disabled This bit is only effective if XRO1[4] = 1. 1 MCLK VCO Powerdown 0 MCLK VCOEnabled (default) 1 MCLKVCODisabled This bit is only effective if XRO1[4] = 1. 2 ~~ Oscillator Powerdown Q OSCEnabled (default) 1 OSCDisabled This bit is only effective if XRO1[5] = 1 and XR33[6] = 1. 3. ~Reserved (R/W) 4 Video Clock Select 0 If XRO1[4] = 1 (internal clock source), use output of VCLK VCO as video clock otherwise if XRO4[4] = 0, use RCLK input as video clock (default). 1 If XRO1[4] = 1 (internal clock source), use output of MCLK VCO divided by 2 as the video clock; otherwise if XRO1[4]=0, then use MCLK input divided by 2 as the video clock. 5 Clock Register Program Pointer This bit determines which of the VCO's is being programmed. Following a write to XR32 the data contained in XR32:30 is synchronously transferred to the appropriate VCO counter latch. 0 VCLKVCOselected 1 MCLKVCOselected 6 Power Sequencing Reference Clock 0 Use RCLK (reference clock) divided by 384 as panel power sequencing reference clock and Standby Mode display memory refreshes. For RCLK=14.31818 MHz, panel power sequencing clock would be 37.5 KHz (default). 1 Use AAQ pin as 32 KHz clock input for panel power sequencing reference clock and Standby Mode display memory refreshes. Asymmetric DRAM option (XRO5[3]=1) should not be enabled in this case. 7 ~~ Clock Mode Control 0 Clock 0 and Clock I default to 25.175 and 28.322 MHz respectively. 1 Clock 0 and Clock 1 default to 31.5 MHz and 35.5 MHz. Revision 1.2 123 65540 / 545 Me 2096116 0013845 505 meCOLOR KEY REGISTER 0 (XR3A) Read/Write at 1/O Address 3D7h Index 3Ah Extension Registers [D7|D6|D5[pD4[D3 D2|/D1|D0 COLOR KEY REGISTER 1 (XR3B) Read/Write at I/O Address 3D7h Index 3Bh (D7|D6[Ds[D4[D3/D2]D1 [Do] LL Color Compare Data 0 7-0 Color Compare Data 0 These bits are compared to the least signif- icant 8 bits of the background video stream. If a match occurs on all enabled bits (see Color Compare Mask Register XR3D) and the key is enabled (XR06[4]), external video is sent to the screen. External video is input on the MCD15:0, CASCH# and CASCL# pins (and CA8-9, ACTI, ENABKL, AA9, and OEC# if 24-bit external video input is enabled (XRO5[7]=1)). The logical masking and compare operations are described in the functionaldescription. The color comparison occurs before the RAMDAC. In 4BPP and 8BPP modes using palette LUT data, the LUT index is used in the comparison, not the 18BPP LUT data. L Color Compare Data 1 7-0 Color Compare Data 1 These bits are compared to bits 15:8 of the background video stream. If a match occurs on all enabled bits (see Color Compare Mask Register XR3D) and the key is enabled (XRO6[4]), external video is sent to the screen. External video is input on the MCD15:0, CASCH# and CASCL# pins (and CA8-9, ACTI, ENABKL, AA9, and OEC# if 24-bit external video input is enabled (XRO05[7]=1)). The logical masking and compare operations are described in the functional description. This register should be masked from participating in the comparison in 4BPP and 8BPP modes. This is accomplished by setting Color Mask Register 1 (XR3E) = OFFh. Revision 1.2 124 65540 / 545 mM 20948116 0011450 2c?COLOR KEY REGISTER 2 (XR3C) Read/Write at /O Address 3D7h Index 3Ch (D7 D6[D5[D4/D3|D2 D1 Do] LL Color Compare Data 2 7-0 Color Compare Data 2 These bits are compared to bits 23:16 of the background video stream. If a match occurs on all enabled bits (see Color Compare Mask Register XR3D) and the key is enabled (XR06[4]), external video is sent to the screen. External video is input on the MCD15:0, CASCH# and CASCL# pins (and CA8-9, ACTI, ENABKL, AA9, and OEC# if 24-bit external video input is enabled (XRO5[7]=1)). The logical masking and compare operations are described in the functional description. This register should be masked from participating in the comparison in 4BPP, 8BPP and 16BPP modes. It should only be used in 24BPP modes. This is accomplished by setting Color Mask Register 2 (XR3F) = OFFh. Extension Registers COLOR KEY MASK REGISTER 0 (XR3D) Read/Write at /O Address 3D7h Index 3Dh [D7 [D6 [D5 [D4 D3[D2|D1 [Do] L Color Compare Mask 0 7-0 Color Compare Mask 0 This register is used to select which bits of the background video data stream are used in the comparison with the Color Compare Data 23:0. This register controls bits 7:0. 0 Data does participate in compare operation 1 Data does not participate in compare operation(masked) Revision 1.2 125 65540 / 545 MB 2098116 0011851 163Extension Registers COLOR KEY MASK REGISTER 1 (XR3E) COLOR KEY MASK REGISTER 2 (XR3F) Read/Write at I/O Address 3D7h Read/Write at /O Address 3D7h Index 3Eh Index 3Fh (D7 D6[D5{D4 D3[D2[D1 [Do] [p7|D6|Ds D4[D3/D2 D1[D0| Color Compare Mask 1 -___ -. Color Compare Mask 2 7-0 Color Compare Mask 1 7-0 Color Compare Mask 2 This register is used to select which bits of This register is used to select which bits of the background video data stream are used in the background video data stream are used in the comparison with the Color Compare Data the comparison with the Color Compare Data 23:0. This register controls bits 7:0. 23:0. This register controls bits 7:0. 0 Data does participate in compare 0 Data does participate in compare operation operation 1 Data does not participate in compare 1 Data does not participate in compare operation(masked) operation(masked) Revision 1.2 126 65540 / 545 MB 2094116 0011452 OTTcnir>. Extension Registers BitBLTCONFIGREGISTER(CKR40) (655450nly) 3-0 Set Panel Type (40K BIOS Only ) Read/Write at I/O Address 3D7h 00 Panel #1 Index 40h ane 01 Panel #2 02 ~= Panel #3 PPrbslps[bapps|HaIB oo] 03 Panel #4 L 04 ~=Panel #5 BitBLT Draw Mode 05 = Panel #6 06 = Panel #7 07 ~=s- Panel #8 08-OF Reserved Reserved(0) 4 Optimal Compensation Enable 0 Disableoptimalcompensation 1 Enableoptimalcompensation 7-5 Reserved (0) 1-0 BitBLT Draw Mode (65545 only ) See also XROF, XR2B, XR45 for definition of other The 65545 supports two color depths in its software flags registers. drawing engine: 00 Reserved 01 8BPP 10 16BPP SOFTWARE FLAGS REGISTER 3 (XR45) 11 Reserved Read/Write at I/O Address 3D7h Index 45h Note: 24BPP is handled in 8BPP mode. There is no nibble mode access for 4BPP modes. D7|D6]D5]D4/D3[D2[D1 [po] | _ 7-2 Reserved (0) ree , Flag 2 |} Flag 3 SOFTWARE FLAGS REGISTER 2 (XR44) ee Read/Write at I/O Address 3D7h Flas 5 Index 44h 6 Flag 6 Flag 7 (D7 D6 D5|D4 D3(D2[D1 Do| | This register contains eight read-write bits which have no internal hardware function. All bits are Set Panel Type reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: Optimal Compensation Ena 7-0 Flags (Reserved ) See also XROF, XR2B, XR44 for definition of other Reserved(0) software flags registers. This register contains eight read-write bits which have no internal hardware function. All bits are reserved for use by BIOS and driver software. For reference, the functions of the bits of this register are currently defined as follows: Revision 1.2 127 65540 / 545 Me 20598116 0011453 T3bPANEL FORMAT REGISTER 2 (XR4F) Read/Write at I/O Address 3D7h Index 4Fh [pD7|D6 D5/D4[D3(D2|D1 [Do] L Bits Per Pixel Reserved(R/W) M Functionality Select LP Functionality Select This register is used only in flat panel mode. 2-0 Bits Per Pixel Selection The value in this field, along with the dither and FRC settings, determines gray / color levels produced: No FRC # of msbs Gray / Gray / Used Color Color to Generate Levels Levels Gray/Color without with Levels Dithering Dithering 001 1 2 5 010 2 4 13 011 3 8 29 100 4 16 61 101 5 32 125 110 6 64 253 111 8 256 n/a 2-Frame FRC (Color TFT or Monochrome Panels) # of msbs Gray / Gray / Used Color Color to Generate Levels Levels 3-5 Gray/Color without with evels Dithering Dithering 6 010 I 3 9 011 2 5 25 100 3 15 57 101 4 31 121 7 Extension Registers 16-Frame FRC (Color or Monochrome STN Panels) # of msbs Gray / Gray / Used Color Color to Generate Levels Levels Gray/Color without with vels Dithering Dithering 001 1 2 5 010 2 4 13 011 3 8 29 100 4 16 61 The setting programmed into this field deter- mines how many most-significant color-bits / pixel are used to generate flat panel video data. In general, 8 bits of monochrome data or 8 bits/color of RGB color data enter the flat panel logic for every dot clock. Not all of these bits, however, are used to generate output colors / gray scales, depending on the type of panel used, graphics / text mode, and the gray-scaling algorithm chosen (the actual number of bits used is indicated in the table above). If the VGA palette is used then a maximum of 6 bits/pixel (bits 7-2) (setting '110') should be used. If the VGA palette is bypassed then a maximum of 8 bits/pixel (bits 7-0) (setting '111) may be used. With 2-frame and 16-frame FRC, settings not listed in the tables above are undefined. Also note that settings which achieve higher gray / color levels may not necessarily produce acceptable display quality on some (or any) currently available panels. This document contains recommended settings for various popular panels that Chips & Technologies has found to produce acceptable results with those panels. Customers may modify these settings to achieve a better match with their require- ments. Reserved (R/W) M Pin Select 0 M signal goes to the M pin (default on reset 1 FP Display Enable (FP Blank#) signal goes to the M pin. Polarity is controlled by XR54([0]. LP Pin Select 0 FP HSync (LP) signal goes to the LP in. Polarity is controlled by R54[6] (default on reset). 1 FP Display Enable (FP Blank#) signal goes to the LP pr Polarity is controlled by XR54[0] Revision 1.2 128 65540 / 545 MB 2096116 00113854 172PANEL FORMAT REGISTER 1 (XR50) Read/Write at I/O Address 3D7h Index 50h (D7|D6[Ds [D4 D3 D2|D1 [Do] L Frame Rate Control Dither Enable Clock Divide TFT Panel Data Width This register is used only in flat panel mode. 1-0 3-2 Frame Rate Control (FRC) FRC is gray scale simulation on a frame-by- frame basis to generate shades of gray or color on panels that do not support gener- ation of gray / color levels internally. 00 No FRC. This setting may be used with all panels, especially for panels which can generate shades of gray / colorinternally. 01 16-frame FRC. This setting may be used for Color STN or Monochrome panels. One to four bits/pixel output to the panel are possible and therefore this setting is used only with panels which do not support internal gray scaling. This setting is used to simulate 16 gray / color levels per pixel, The bits per pixel are specified y XR4F[2-0]; valid values are 001, 010, 011, and 100. 10 2-frame FRC. This setting may be used for Color TFT or Monochrome panels. One to four bits/pixel output to the panel are possible and therefore this setting can also be used with panels that support internal gray scaling. Number of input bits used (specified in XR4F[2-0]) are one more than the number of output bits. Therefore, valid values for XR4F[2-0] are 010, 011, 100, and 101. 1] Reserved Dither Enable 00 Disabledithering 01 Enable dithering for 256-color modes (AR10 bit-6 = 1 or XR28 bit 4 = 1) 10 Enable dithering for all modes 11 Reserved Extension Registers 6-4 Clock Divide (CD) These bits specify the frequency ratio between the dot clock and the flat panel shift clock (SHFCLK) signal. 000 Shift Clock Freq = Dot Clock Freq. This setting is used to output 1 pixel er shift clock with a maximum of 8 pp (bits/pixel) for single drive monochrome panels. For double drive color panels, this setting is used to output 2 2/3 4-bit pack pixels. FRC and dithering may be enabled. 001 Shift Clk Freq = 1/2 Dot Clock Freq. This setting is used to output 2 pixels er shift clock with a maximum of 8 its/pixel for single drive monochrome panels and 4 bpp for single drive color panels. For double drive color panels, this setting is used to output 5-1/3 4- bit pack pixels. FRC and dithering can be enabled. 010 Shift Clk Freq = 1/4 Dot Clock Freq. This setting is used to output 4 pixels er shift clock with a maximum of 4 PP for single drive mono panels and 2 bits/pixel for single drive color panels. For single drive color panels this setting is used to output 5-1/3 4- bit pack pixels. For double drive monochrome panels, this setting is used to output 8 pixels per shift clock with 1 bit/pixel. FRC and dithering can be enabled. 011 Shift Clk Freq = 1/8 Dot Clock Freq. This setting is used to output 8 pixels pet shift clock with a maximum of 2 pp for single drive mono panels and 1 bit/pixel for single drive color panels. For double drive mono panels, this setting is also used to output 16 pixels per shift clock with 1 bit/pixel. FRC and dithering can be enabled. 100 Shift Clk Freq = 1/16 Dot Clock Freq. This setting is used to output 16 pixels er shift clock with maximum of 1 it/pixel for single drive monochrome panels. Dithering can also be enabled. TET Panel Data Width This bit is effective only when TFT (active matrix) panels are used (XR50 bits 1-O=10). 0 16-bit color TFT interface (565 RGB) 1 24-bit color TFT interface (888 RGB) Revision 1.2 129 65540 / 545 MH 2098116 0011455 605eHSEEEG G2 35 EETED. gintzs Extension Registers DISPLAY TYPE REGISTER (XR51) Read/Write at I/O Address 3D7h Index 51h {D7|D6 D5[D4[D3[D2|D1 DO 1-0 Panel Type (PT) These bits are effective for flat panel only. 00 Single Panel Single Drive (SS) 01 Reserved 10 Reserved 11 DualPanel DoubleDrive (DD) 2 Display Type (DT) This bit is effective for CRT and flat panel. This bit also controls the BLANK# output. 0 CRT display (default on reset) BLANK# outputs CRT Blank 1 FP (Flat Panel) display BLANK# outputs FP Blank Note: There is no pin dedicated to output of BLANK#. Therefore this bit is ignored if BLANK# is not selected to be output on either the M or LP output pins. 3 Shift Clock Divide This bit is effective for flat panel only. 0 Shift Clock to Dot Clock relationship expressed by XRSO[6-4]. 1 In this mode, the Shift Clock is further divided by 2 and different video data is valid on the rising and falling edges of Shift Clock. 4 Reserved (R/W) I} Panel Type Display Type Shift Clock Divide Reserved(R/W) Shift Clock Mask Enable FP Compensation LP During V Blank Shift Clock Mask (SM) This bit is effective for flat panel only. 0 Allow shift clock output to toggle outside the display enable interval 1 Force the shift clock output low outside the display enable interval Enable FP Compensation (EFCP) This bit is effective for flat panel only. It enables flat panel horizontal and vertical compensation depending on panel size, current display mode, and contents of the compensationregisters. 0 Disable FP compensation 1 Enable FP compensation LP During Vertical Blank This bit should be set only for SS panels which require FP HSync (LP) to be active during vertical blank time when XR54 bit-1 = 0 (e.g., Plasma / EL panels). This bit should be reset when using non-SS panels or when XR454 bit-1 = 1. O FP HSync (LP) is generated from internal FP Blank inactive edge 1 FP HSync (LP) is generated from internal FP Horizontal Blank inactive edge Revision 1.2 65540 / 545 M@@ 20946116 00114856 745Extension Registers POWER DOWN CONTROL REGISTER(XR52) Read/Write at I/O Address 3D7h Index 52h [D7|D6|D5[D4|D3[D2|D1 DO Normal Refresh Count Panel Off Mode Software Standby Mode Standby/Panel Off Control Standby Refresh Control CRT Mode Control 2-0 FP Normal Refresh Count These bits specify the number of memory re- fresh cycles to be performed per scanline. A minimum value of 1 should be programmed in this register. 3 Panel Off Mode This bit provides a software alternative to enter Panel Off mode. Note that Panel Off mode will be effective in both CRT and flat panel modes of operation. 0 Normal mode (default on reset) 1 Panel Off mode In Panel Off mode, the CRT / FP display memory interface is inactive but CPU interface and display memory refresh are still active. The internal RAMDAC is also inactive. 4 Software Standby Mode This bit provides an alternative way to enter the Standby mode. When this bit is set, the chip enters Standby mode. To exit Standby mode, when this bit is set, the STNDBY# pin must be asserted and then reasserted. This bit will also be reset when the STNDBY# pin goes active (low). 0 Normal Mode (default on reset) 1 Standby Mode Standby and Panel Off Control This bit is effective in Flat Panel Mode during Standby and Panel Off modes (XR52[3] = 1 or (XR52[4] = 1 or STNDBY#, pin 178 is active (low)). 0 Video data and/or flat panel control signals are driven inactive (default on reset). 1 Video data and flat panel control signals pins are tri-stated with a weak internal pull-down. Note: XR61 bit-7 controls the inactive level for video data in text mode; XR63 bit-7 controls the inactive level for video data in graphics mode: 0 = low when inactive 1 = high when inactive Note: This bit does not affect the HSYNC and VSYNC pins. In Standby and Panel Off modes, HSYNC and VSYNC will be driven low. Standby Refresh Control This bit is effective only in Standby mode (STNDBY# pin low). Standby mode is effective for both CRT and flat panel modes. In Standby mode, CPU interface to display memory and internal registers is inactive. The CRT / FP display memory interface, video data and timing signals, and internal RAMDAC are inactive (all CRT and flat panel video control and data pins are 3- stated). | Display memory refresh is controlled by this bit. 0 Self-Refresh DRAM support. 1 Display memory refresh frequency is derived from the 32KHz input or RCLK (14.31818MHz _ Reference Clock) divided per the value in XR5F. CRT Mode Control This bit is effective in CRT mode only (non- simultaneous CRT and flat panel) (XR51 bit-2 = 0). 0 Video data and flat panel control signals are 3-stated with weak internal pull-down (default on reset). 1 Video data and flat panel control signals are inactive. Revision 1.2 131 65540 / 545 MB 2094116 0011457 641Extension Registers PANEL FORMAT REGISTER 3 (XR53) Read/Write at I/O Address 3D7h Index 53h [D7/D6[D5[D4 D3/D2|D1 [Do [ Disable AR10 bit-2 Alt Line Gr Char Code Ctrl FRC Option 1! FRC Option 2 Color STN Pixel Packing FRC Option 3 Reserved(R/W) 0 Disable AR10 Bit-2 QO Use ARI1O bit-2 for Line Graphics control (default on Reset). 1 Use XR53 bit-1 instead of AR10 bit-2 for Line Graphics control 1 AlternateLineGraphicsCharacterControl This bit is effective only if bit-0 = 1. 0 Ninth pixel of line graphics character is set to the backgroundcolor 1 Ninth pixel of line graphics character is identical to the eighthpixel 2 FRC Option 1 (always program to 1) 3 FRC Option 2 (always program to 1) Color STN Pixel Packing This field determines the type of pixel packing (the RGB pixel output sequence) for color STN panels. These bits should be programmed only when color STN panels are used. These bits must be programmed to 00 for monochrome panels or color TFT panels. 00 3-bit Pack. XR50 bits 6-4 can be 000, 001, or 010. Ol 4-bit Pack. For SS Color STN panels, XR50 bits 6-4 can be 000, 001, or 010. For DD panels, XR50 bits 6-4 may be set to 000 or 001. 10 Reserved 11 Extended 4-bit Pack. XR50 bits 6-4 must be programmed to 001. This setting may be used for 8-bit interface Color STN SS panels only. ~] FRC Option 3 This bit affects 2-frame FRC only 0 FRC data changes every frame 1 FRC data changes every other frame Reserved (R/W) Revision 1.2 132 65540 / 545 Mi 2098116 00113454 5156PANEL INTERFACE REGISTER (XRS54) Read/Write at /O Address 3D7h Index 54h {D7 [D6|Ds [D4[D3 [D2|D1 [Do| L__ FP Blank Polarity + FP Blank Select FP Clock Select FP Feature Control FP LP Polarity FP FLM Polarity This register is used only in flat panel modes. 0 FP Blank Polarity This bit controls the polarity of the BLANK# pin in flat panel mode. In CRT mode, XR28 bit-0 controls polarity of the BLANK# pin. 0 Positivepolarity 1 Negativepolarity FP Blank Select This bit controls the BLANK# pin output in flat panel mode. In CRT mode, XR28 bit-1 controls the BLANK# output. This bit also affects operation of the flat panel video logic, generation of the FP HSync (LP) pulse signals, and masking of the Shift Clock. 0 The BLANK# pin outputs both FP Vertical and Horizontal Blank. In 480-line DD panels, this option will generate exactly 240 FP HSync (LP) pulses. 1 The BLANK# pin outputs only FP HorizontalBlank. During FP Vertical Blank, the flat panel video logic will be active, the FP HSync (LP) pulse will be generated, and Shift Clock can not be masked. Note however that Shift Clock can still be masked during FP Horizontal Blank. Note: The signal polarity selected by bit-0 is applicable for either selection. Extension Registers 3-2 FP Clock Select Bits 1-0 Select flat panel dot clock source. These bits are used instead of Miscellaneous Output Register (MSR) bits 3-2 in flat panel mode. See description of MSR bits 3-2. FP Feature Control Bits 1-0 Select flat panel dot clock source. These bits are used instead of Feature Control Register (FCR) bits 1-0 in flat panel mode. See des- cription of FCR bits 1-0. FP HSync (LP) Polarity This bit controls the polarity of the flat panel HSync (LP) pin. 0 Positivepolarity 1 Negativepolarity FP VSyne (FLM) Polarity This bit controls the polarity of the flat panel VSync (FLM) pin. 0 Positivepolarity 1 Negativepolarity Revision 1.2 133 65540 / 545 Mf 2098116 0011859 454HORIZONTAL COMPENSATION REGISTER 4-3 (XR55) Read/Write at /O Address 3D7h 5 Index 55h D7|D6|D5 D4]/D3|D2[D1[Do] | Ena H Compensation Ena H Auto Centering Ena H Compression | Reserved(R/W) Ena Auto H Doubling Alternate HSync Polarity Alternate VSync Polarity This register is used only in flat panel modes when flat pane] compensation is enabled (XR51 bit-6 = 1). 0 EnableHorizontalCompensation(EHCP) 6 0 Disablehorizontalcompensation 1 Enablehorizontalcompensation 1 Enable Automatic Horizontal Centering (EAHC) (effective only if bit-0 is 1) 0 Enable non-automatic horizontal cen- tering. The Horizontal Centering Register is used to specify the left border. If no centering is desired then the Horizontal Centering Register can be programmed to 0. 1 Enable automatic horizontal centering. Horizontal left and right borders will becomputedautomatically. 2 EnableTextModeHorizontalCompression (ETHCX this bit is effective only if bit-0 is 1 in flat panel text mode). Setting this bit will turn on text mode horizontal compression re- gardless of horizontal display width or horizontal panel size. 0 Textmode horizontal compression off 1 Text mode horizontal compression on. 8-dot text mode is forced when 9-dot text mode is specified (SRO1 bit-0 = 0 or Hercules text). Note: This bit affects the horizontal pixel panning logic. When text mode horizontal compression is active, programming 9-bit panning will result in 8-bit panning. Extension Registers Reserved (R/W) Enable Automatic Horizontal Doubling (EAHD\ this bit is effective if bit-0 is 1) 0 Disable Automatic Horizontal Dou- bling. Horizontal doubling will only be performed for flat paneis when SRO1 bit-3 = 1 in any emulation mode or when 3B8/3D8 bit-0 & 3B8/3D8 bit-4 = 0 in CGA emulation. 1 Enable Automatic Horizontal Dou- bling. Horizontal doubling will be performed for flat panels when SRO1 bit-3 = 1 in any emulation mode or when 3B8/3D8 bit-0 & 3B8/3D8 bit-4 = 0 in CGA emulation or when the Horizontal Display width (CRO1) is equal to or less than half of the Horizontal Panel Size (XR18). Alternate CRT HSync Polarity 0 Positive 1 Negative Alternate CRT VSync Polarity 0 Positive 1 Negative Note: bits 6 and 7 above are used in flat panel mode (XR51 bit-2 = 1) instead of MSR bits 6 and 7). This is primarily used for simultaneous CRT / Flat Panel display. Revision 1.2 134 65540 / 545 MH 20596116 00131860 17bCrnir> Extension Registers HORIZONTALCENTERINGREGISTER(XR56) Read/Write at I/O Address 3D7h Index 56h [D7[D6 D5[D4]D3[D2 D1 [Do] LeftBorder This register is used only in flat panel modes when non-automatichorizontal centering is enabled. 7-0 Horizontal Left Border (HLB) | Programmed Value (in characterclocks) = Width of Left Border 1 Revision 1.2 135 65540 / 545 Mi 2096116 0011861 OO mmVERTICAICOMPENSATIORREGISTERXRS7) Read/Write at I/O Address 3D7h Index 57h D7[D6|D5 D4[D3[D2|D1 Do| Enable V Compensation Enable Auto V Centering Enable Text V Stretching | Text V Stretch Method Enable Gr V Stretching Gr V Stretch Method Disable Fast Centering This register is used only in flat panel modes when flat panel compensation is enabled. 0 Enable Vertical Compensation (EVCP) 0 Disableverticalcompensation 1 Enableverticalcompensation 1 Enable Automatic Vertical Centering (EAVC) This bit is effective only if bit-O is 1. 0 Enable non-automatic vertical centering. The Vertical Centering Register is used to specify the top border. If no centering is desired then the Vertical Centering Register can be programmed to 0. 1 Enable automatic vertical centering. Vertical top and bottom borders will becomputedautomatically. 2 Enable Text Mode Vertical Stretching (ETVS) This bit is effective only if bit-0 is 1. 0 Disable text mode vertical stretching; graphics mode vertical stretching is used if enabled. 1 Enabletextmode vertical stretching Extension Registers 4-3 Text Mode Vertical Stretching (TVS1-0) These bits are effective if bits 2 and 0 are 1. 00 Double Scanning (DS) and Line Insertion (LI) with the following priority: DS+LI, DS, LI. 01 Double Scanning (DS) and Line Insertion (LI) with the following priority: DS+LI, LI, DS. 10 Double Scanning (DS) and TallFont (TF) with the following priority: DS+TF, DS, TF. 11 Double Scanning (DS) and TallFont (TF) with the following priority: DS+TF, TF, DS. 5 Enable Vertical Stretching (EVS) This bit is effective only if bit-0 is 1. 0 Disableverticalstretching 1 Enableverticalstretching 6 Vertical Stretching (VS) Vertical Stretching can be enabled in both text and graphics modes. This bit is effective only if bits 5 and 0 are 1. 0 Double Scanning (DS) and Line Replication (LR) with the following priority: DS+LR, DS, LR. 1 Double Scanning (DS) and Line Replication (LR) with the following priority: DS+LR, LR, DS. 7 Disable Fast Centering This bit is effective only if XR58[1-0] = 11. 0 Enable Fast Centering 1 Disable Fast Centering Revision 1.2 65540 / 545 MB 2098116 00114b2 T45zitess Extension Registers VERTICAL CENTERING REGISTER (XR58) Read/Write at I/O Address 3D7h Index 58h [D7|[D6 D5[D4/D3[D2/D1 [Do| Top Border LSBs This register is used only in flat panel modes when non-automatic vertical centeringis enabled. 7-0 Vertical Top Border LSBs (VTB7-0) Programmedvalue: Top Border Height (in scan lines) - 1 This register contains the eight least signif- icant bits of the programmed value of the Vertical Top Border (VTB). The two most significant bits are in the Vertical Line Insertion Register (XR59). VERTICALLINEINSERTIONREGISTER(XRS59) Read/Write at /O Address 3D7h Index 59h D7|D6|D5|D4]|D3|D2]D1 Do| V Line Insertion Height Reserved(0) Top Border Bits 8-9 Hardware Line Replication This register is used only in flat panel text mode when vertical line insertion is enabled. 3-0 Vertical Line Insertion Height (VLIH3-0) ProgrammedValue: Number of Insertion Lines 1 The value programmed in this register - 1 is the number of lines to be inserted between the rows. Insertion lines are never double scanned even if double scanning is enabled. Insertion lines use the background color. 4 Reserved (0) 6-5 Vertical Top Border MSBs (VTB9-8) This register contains the two most signif- icant bits of the programmed value of the Vertical Top Border (VTB). The eight least significant bits are in the Vertical Centering Register (XR58). 7 Hardware Line Replication This bit is effective in text mode when Line Replication is selected (XR57[2] = 1). Hardware line replication, when enabled, replicates lines to display a 19-line character from a 16-line font as specified in XR28 bit- 7. 0 Normaltext modeline replication 1 Hardware line replication is enabled Revision 1.2 137 65540 / 545 Mi 2098116 0011463 965VERTICAL LINE REPLICATION REGISTER (XR5A) Read/Write at /O Address 3D7h Index 5Ah [D7 D6|D5|D4[D3|D2[D1|Do] Line Replication Height Reserved(R/W) This register is used only in flat panel text or graphics modes when vertical line replication is enabled. 3-0 Vertical Line Replication Height (VLRH) Programmed Value = Number of Lines Between Replicated Lines 1 Double scanned lines are also counted. In other words, if this field is programmed with '7', every 8th line will be replicated. 7-4 Reserved (R/W) Extension Registers PANEL POWER SEQUENCING DELAY REGISTER (XR5B) Read/Write at I/O Address 3D7h Index 5Bh [D7|D6[Ds [D4 D3/D2|D1 Do| Delay on Power Down Delay on Power Up This register is used only in flat panel modes. The generation of the clock for panel power sequencing logic is controlled by XR33[6]. The delay intervals below assume a 37.5 KHz clock generated by the internal clock synthesizer. If the 32KHz input is used, the delay intervals should be scaled accord- ingly. 3-0 Power Down Delay Programmable value of panel power- sequencing during power down. This value can be programmed up to 459 milliseconds in increments of 29 milliseconds. A value of 0 is undefined. Power Up Delay Programmable value of panel power sequencing during power up. This value can be programmed up to 54 milliseconds in increments of 3.4 milliseconds. A value of 0 is undefined. Revision 1.2 138 65540 / $45 MH 2094116 0011864 811ACTIVITYITIMERCONTROIREGISTERXRSC) Read/Write at I/O Address 3D7h Index 5Ch [p7[D6 D5[D4]/D3[D2/[D1 Do| Activity Timer Count Reserved(R/W) Activity Timer Action Enable Activity Timer This register is used to control Activity timer functionality. The activity timer is an internal counter that starts counting from a _ value programmed into this register (see bits 0-4 below) and is reset back to that count by read or write accesses to graphics memory or I/O. If no accesses occur, the counter counts till the end of its programmed interval and activates either the ENABKL pin or Panel Off mode (as selected by bit- 6 below). The timer count does not have to be reloaded once programmed and the timer enabled: any access to the chip with the timer timed out (ENABKL active or Panel Off mode active) will reset the timer and the ENABKL pin de-activated (or Panel Off mode exited, whichever is selected). The activity timer uses the same clock as power sequencing which is controlled by XR33[6]. The delay intervals below assume a 35.7 KHz clock, if an external 32KHz input is used, the delay is scaled accordingly. 4-0 Activity Timer Count For a 35.7 KHz clock the counter granularity is approximately 25.6 seconds. The minimum programmed value of 1} results in 25.6 second delay and the maximum count of 32 results in a delay of 13.7 minutes. If the clock input on pin 154 (AA9) is other than 32 KHz, the delay should be scaled accordingly. 5 Reserved (R/W) Extension Registers 6 Activity Timer Action O When the activity timer count is reached, the ENABKL pin is activated (driven low to turn the backlight off) 1 When the activity timer count is reached, Panel Off mode is entered. 7 Enable Activity Timer 0 Disableactivity timer (default on reset) 1 Enableactivitytimer See also XRSD bit-2. Revision 1.2 139 65540 / 545 MB 2098116 OO118b5 755Crhir> FP DIAGNOSTIC REGISTER (XR5D) Read/Write at I/O Address 3D7h Index 5Dh [D7 D6[D5[D4 D3[D2|D1 [Do | Enable Palette Powerdown Enable Access in PNLOFF Enable Activity Timer Test Force 16-bit Local Bus Disable Vertical Comp 18-bit Color Test Mode HSync/VSync Deactivation Enable Palette Powerdown EnablePanel-OffVGAPalettePowerdown 0 Disable VGA Palette powerdown in Panel Off Mode (default on reset) 1 Enable VGA Palette powerdown in Panel Off mode Enable Panel-Off VGA Palette Access This bit is effective when bit O=1 or bit 7=1. 0 Disable CPU access to VGA Palette in Panel Off Mode (default on reset) 1 Enable CPU access to VGA Palette in Panel Off Mode Enable Activity Timer Test 0 Disable Activity Timer test mode (default on reset) 1 Enable Activity Timertest mode Force 16-Bit Local Bus This bit is effective when 32-bit local bus and 16-bit memory interface are used during font load. 0 Do not force 16-bit local bus when loading font (default on reset) 1 Force 16-bit local bus when loading font Disable Vertical Compensation 0 Vertical compensation can be enabled in all cases (default on reset) 1 Disable vertical compensation if Vertical Display Enable End equals Vertical Panel Size. Extension Registers 18-bit Color TFT Test Mode 0 Disable 18-bit color TFT test mode (default on reset) 1 Enable 18-bit color TFT test mode PreventHSYNCand VSYNC Deactivation 0 Allow HSYNC and VSYNC to be deactivated when XRO6[1] = 1 (default on reset) 1 Prevents HSYNC and VSYNC from being deactivated when XRO6[1] = 1. EnablePalettePowerdowninBypassMode 0 Disable VGA palette powerdown when XR06[5]=1 1 Enable VGA palette powerdown when XRO06[5]=1 and XRO6{1]=1 Revision 1.2 140 65540 / 545 MB 2094116 0011466 694Gueesnseusse son ence Extension Registers M(ACDCLK) CONTROL REGISTER (XR5E) Read/Write at I/O Address 3D7h Index 5Eh [D7/D6|Ds[D4[D3 [D2 D1{Do| POWER DOWN REFRESH REGISTER (XRSF) Read/Write at /O Address 3D7h Index 5Fh D7[D6|D5|D4[D3[D2|D1 [Do LL M (ACDCLEK) Count M (ACDCLK) Control This register is used only in flat panel mode. 6-0 M(ACDCLK) Count(ACDCNT) These bits define the number of HSyncs between adjacent phase changes on the M (ACDCLK) output. These bits are effective only when bit 7 = 0 and the contents of this register are greater than 2. Programmed Value = Actual Value -2 7 M(ACDCLK) Control 0 The M (ACDCLK) phase changes depending on bits 0-6 of this register 1 The M (ACDCLK) phase changes every frame if the frame accelerator is not used. If the frame accelerator is used, the M (ACDCLK) phase changes every other frame. If XR4F bit-6 is programmed to one to enable flat panel DE / BLANK# to be output on the M (ACDCLK) pin, the contents of this register will be ignored. L_ Power Down Refresh Freq 7-0 Power Down Refresh Frequency These bits define the frequency of memory refresh cycles in power down (standby) mode (STNDBY# pin low). CAS-Before- RAS (CBR) refresh cycles are performed. If XR52 bit-6 = 1, the interval between two refresh cycles is determined by bits 0-3 of this register per the table below. Bits 4-7 of this register are reserved for future use in this mode (and should be programmed to 0). 3210 ApproximateRefresh Interval 0000 16 usec / cycle 0001 47 usec / cycle 0010 63 usec / cycle 0011 78 usec / cycle 0100 94 usec / cycle 0101 109 usec / cycle 0110 125 usec / cycle 0111 141 usec/ cycle 1000 156 usec / cycle These refresh intervals assume a 32 KHz clock. If the internal clock is used, the refresh interval is scaled accordingly. If XR52 bit-6 = 0, a value of 0 causes no refresh to be performed. Self-Refresh DRAMs should be used in this case. Revision 1.2 141 65540 / 545 MM 20598116 0011867 520BLINK RATE CONTROL REGISTER (XR60) Read/Write at /O Address 3D7h Index 60h [D7|D6 D5 p4[D3]b2|D1 [Do] L Cursor Blink Rate Char Blink Duty Cycle This register is used in all modes. 5-0 Cursor Blink Rate These bits specify the cursor blink period in terms of number of VSyncs (50% duty cycle). In text mode, the character blink period and duty cycle is controlled by bits 7- 6 of this register. These bits default to 000011 (decimal 3) on reset which corresponds to eight VSyncs per cursor blink period per the following formula (four VSyncs on and four VSynes off): Programmed Value = (Actual Value) /2-1 Note: In graphics mode, the pixel blink period is fixed at 32 VSyncs per cursor blink period with 50% duty cycle (16 on and 16 off). Character Blink Duty Cycle These bits specify the character blink (also called attribute blink) duty cycle in text mode. CharacterBlink Duty Cycle 50% 25% 50% (default on Reset) 15% For setting 00, the character blink period is equal to the cursor blink period. For all other settings, the character blink period is twice the cursor blink period (character blink is twice as slow as cursor blink). =r OO Sa Oe CIN Extension Registers Revision 1.2 142 Mf 2096116 0011868 447 me 65540 / 545Extension Registers Note: This bit does not affect CRT text / graphics mode or flat panel graphics mode; i.e.: the color lookup table is always used, and similarly the internal RAMDAC palette is used if enabled. SMARTMAP CONTROL REGISTER (XR61) 4-1. SmartMap Threshold Read/Write at /O Address 3D7h . : Index 61h These bits are used only in flat panel text mode when SmartMap is enabled (bit-0 = 1). They define the minimum difference (D7|De[Ds p4]/D3|D2|D1 [Do| between the foreground and background | colors. If the difference is less than this SmartMap Enable threshold, the colors are separated by adding L__. and subtracting the shift values (XR62) to the foreground and background colors. SmartMapThreshold However, if the foreground and background color values are the same, then the color . values are not adjusted. SmartMap Saturation Text Enhancement 5 SmartMap Saturation Text Video Output Polarity This bit is used only in flat panel text mode . . oo. . when SmartMap is enabled (bit-0 = 1). It This register is used in flat panel text mode only. selects the clamping level after the color SmartMap Enable addition/subtraction. . 0 The color result is clamped to the 0 iookup Sara ce nt maximum and minimum values (OFh RAMDAC palette if enabled (XRO6 and 00h respectively) bit-2 = 1). 1 The color result is computed modulo 1 Enable SmartMap, bypass both 16 (no clamping) color lookup table and _ internal RAMDAC palette in flat panel text 6 Text Enhancement mode. Although color lookup table is This bit is used only in flat panel text mode. bypassed, translation of 4 bits/pixel 0 Normaltext data to 6 bits/pixel data is still : : 1 Text attribute O7h and OFh are performed depending on ARIO bit-1 reversed to maximize the brightness of (monochrome / color display) as the normal DOS prompt follows: Promp a oy Note: This bit should be set to 0 if XR63[6] Output ABIO bit} =0 ARIO DIE =1 is set to 1. Conversely, if this bit is Outl Inl Inl set to 1, XR63[6] should be set to 0. Out2 In2 In2 . . Out3 In3 In0+In14In2+In3 7 Text Video Output Polarity (TVP) Out4 In3 In3 This bit is effective for flat panel text mode Out5 In3 In3 only. Q Normalpolarity 1 Invertedpolarity Note: Graphics video output polarity is controlled by XR63 bit-7 (GVP). Revision 1.2 143 65540 / 545 M@! 2098116 0011869 373SMARTMAP SHIFT PARAMETER REGISTER (XR62) Read/Write at I/O Address 3D7h Index 62h {p7[D6[Ds|D4 D3 D2|D1/D0] Extension Registers SMARTMAPCOLORMAPPING@CONTROL REGISTERXR63) Read/Write at /O Address 3D7h Index 63h [D7|D6[Ds[D4[D3 D2|D1 [DO LL Foreground Shift Background Shift This register is used in flat panel text mode when SmartMap is enabled (XR61 bit-0 = 1). 3-0 7-4 Foreground Shift These bits define the number of levels that the foreground color is shifted when the foreground and background colors are closer than the SmartMap Threshold (XR61 bits 1-4). If the foreground color is "greater" than the background color, then this field is added to the foreground color. If the foreground color is "smaller" than the background color, then this field is sub- tracted from the foreground color. Background Shift These bits define the number of levels that the background color is shifted when the foreground and background colors are closer than the SmartMap Threshold (XR61 bits 1-4). If the background color is "greater" than the foreground color, then this field is added to the background color. If the background color is "smaller" than the foreground color, then this field is sub- tracted from the background color. L Color Threshold New Text Enhancement Gr Video Output Polarity 5-0 Color Threshold These bits are effective for monochrome (XR51 bit-5 = 1) single/double drive flat panel with 1 bit/pixel (XR50 bits 4-5 = 11) without FRC (XR50 bits 0-1 = 11). They specify the color threshold used to reduce 6- bit video to 1-bit video color. Color values equal to or greater than the threshold are mapped to 1 and color values less than the threshold are mapped to 0. New Text Enhancement If set this bit enables new text enhancement that does not affect the CRT display. If this bit is set to 1, the old text enhancement bit (XR61[6]) must be set to 0. Conversely, if XR61[6] is 1 then this bit should be set to 0. Reset defaults this bit to 1. Graphics Video Output Polarity (GVP) This bit is effective for CRT and flat panel graphics mode only. 0 Normalpolarity 1 Invertedpolarity Note: Text video output polarity is controlled by XR61 bit-7 (TVP). Revision 1.2 65540 / 545 MB 2094116 0011470 015Extension Registers FP ALTERNATE VERTICAL TOTAL REGISTER (XR64) Read/Write at /O Address 3D7h Index 64h [D7|D6 D5|D4]D3 [D2 D1 [Do| This register is used in all flat panel modes. 7-0 FP Alternate Vertical Total The contents of this register are 8 low order FP Alternate V Total bits of a 10-bit value. Bits 9 and 10 are defined in XR65. The vertical total value specifies the total number of scan lines per frame. Similar to CRO6. Programmed Value= Actual Value 2 FP ALTERNATE OVERFLOW REGISTER (XR65) Read/Write at /O Address 3D7h Index 65h D7|D6|D5|D4[D3 D2|D1 [Do] L_ FP Alt V Total Bit-8 FP V Panel Size Bit-8 FP Alt VSync Start Bit-8 Reserved (R/W) Reserved (R/W) FP Alt V Total Bit-9 FP Alt Panel Size Bit-9 FP Alt VSync Start Bit-9 This register is used in all flat panel modes. SN nA un hk OD N = FP Alternate Vertical Total Bit-8 FP Vertical Panel Size Bit-8 FP Alternate Vertical Syne Start Bit-8 Reserved (R/W) Reserved (R/W) FP Alternate Vertical Total Bit-9 FP Vertical Panel Size Bit-9 FP Alternate Vertical Sync Start Bit-9 Revision 1.2 145 65540 / 545 MH 2098116 0011871 TS)FP ALTERNATE VERTICAL SYNC START REGISTER (XR66) Read/Write at I/O Address 3D7h Index 66h (D7 [D6|D5[D4]D3 D2[D1[Do] REGISTER (XR67) Read/Write at I/O Address 3D7h Index 67h D7 D6[D5/D4]D3/D2|D1 [Do] L Extension Registers FP ALTERNATE VERTICAL SYNC END FP Alt VSync End FP Alternate VSync Start This register is used in all flat panel modes. 7-0 FP Alternate Vertical Sync Start The contents of this register are the 8 low order bits of a 10-bit value. Bits 9 and 10 are defined in XR65. This value defines the scan line position at which vertical sync becomes active. Similar to CR10. Reserved(R/W) This register is used in all flat panel modes. 3-0 FP Alternate Vertical Sync End The lower 4 bits of the scan line count that defines the end of vertical sync. Similar to CRI11. If the vertical sync width desired is N lines, the programmed value is: (contents of XR66 + N) ANDed with OFH Programmed Value = Actual Value1 7-4 Reserved (R/W) Revision 1.2 146 Mi 2094116 0011872 998 65540 / 545VERTICAL PANEL SIZE REGISTER (XR68) Read/Write at /O Address 3B7h/3D7h Index 68h (D7/D6[Ds[D4]D3 D2{D1 [Do| (XR6C) Extension Registers PROGRAMMABLEOUTPUTDRIVEREGISTER Read/Write at /O Address 3B7h/3D7h Index 6Ch (D7[D6|[D5[D4 D3[D2[D1 [Do] L Vertical Panel Size This register is used in all flat panel modes. 7-0 Vertical Panel Size The contents of this register define the number of scan lines per frame. Programmed Value= Actual Value1 Panel size bits 8-9 are defined in overflow register XR65. L_ Reserved(R/W) CFG8/LV#: Vcc Select Flat Panel Output Drive Bus Interface Output Drive Mem Intfc A&B Out Drive Mem Intfc C Out Drive 1 Reserved(R/W) This register is used to control the output drive of the bus, video, and memory interface pins. 0 1 Note: Programming lower drive for 3.3V __> operation results in lower than rated output drive. Programming higher output drive for SV operation results in higher than rated output drive. Reserved (R/W) CFG8/LV#- Internal Logic Vcc Selection This bit determines pad input threshold. On the trailing edge of reset, this bit will latch the state of AA8 pin (CFG8). 0 Vcc for internal logic IVCC) is 3.3V 1 Vec for internal logic (IVCC) is 5V (Default) Flat Panel Interface Output Drive Select 0 Lower drive (Default) (Use for DVCC=5V) 1 Higher drive (Use for DVCC=3.3V) Bus Interface Output Drive Select 0 Higher drive (Default) (Use for BVCC=3.3V) 1 Lower drive (Use for BVCC=5V) MemorylinterfaceA & BOutputDriveSelect This bit affects memory interface groups A & B control pins: RASB#, CASBH#, CASBL#, WEB#, OEB#, MAD[15:0] and MBD([15:0] 0 Lower drive (Default) (Use for MVCCA/B=5V) 1 Higher drive MVCCA/B=3.3V) Memory Interface C Output Drive Select This bit affects memory interface group C control pins: RASC#, CASCH#, CASCL#, WEC#, OEC#, and MCD15:0. O Lower drive (Default) (Use for MVCCC=5V) 1 Higher drive (Use for MVCCC=3.3V) Reserved (R/W) (Use for Revision 1.2 147 65540 / 545 MH 2098116 0011873 624 oeCAir>S Extension Registers POLYNOMIAL FRC CONTROL REGISTER (XR6E) Read/Write at I/O Address 3D7h Index 6Eh (D7|D6 D5[D4[D3[D2|D1 Do| Polynomial 'N' Value Polynomial 'M Value This register is effective in flat panel mode when polynomial FRC is enabled (see XR50 bits 0-1). It is used to control the FRC polynomial counters. The values in the counters determine the offset in rows and columns of the FRC count. These values are usually determined by trial and error. 3-0 Polynomial 'N' value 7-4 Polynomial 'M value This register defaults to '10111101' on reset. Revision 1.2 148 65540 / 545 MS 2094116 0011474 760 aFRAMEBUFFERCONTROLREGISTER(XR6F) Read/Write at /O Address 3D7h Index 6Fh (D7 D6|D5[D4|D3 D2[D1[D0] L Frame Buffer Enable Frame Accelerator Enable DRAM C Asym addr select - Frame Buffer Refrsh Count Frame Buffer Lines/Page Frame Buffer Method This register is effective in flat panel mode only. 0 Frame Buffer Enable This bit is used to enable frame buffer operation (external or embedded). Frame buffering is required for DD panel operation. For SS panel operation (LCD, Plasma or EL), frame buffering is not required so this bit should be set to 0. 0 Disable frame buffer (default) 1 Enable frame buffer Since the 65540 and 65545 have the ability to embed frame buffer data in display memory, enabling frame buffering does not mean that an external DRAM frame buffer chip is required (see bit-7 of this register to set the frame buffer method). Frame Accelerator Enable Frame acceleration may be used for panels with vertical refresh rate specifications above 110 Hz to reduce the dot clock rate. For panels with vertical refresh rate specifica- tions below 110 Hz, Frame Acceleration will violate panel specifications and should not be used. This bit should be programmed to 0 when the Frame Buffer is disabled (bit-O of this register set to 0) or for non-DD panels. If this bit is set to 1, bit-O of this register must be set to 1 and a DD panel must be used (XR51[1-0], Panel Type, must be set to 11). 0 Disableframeaccelerator(default) 1 Enableframeaccelerator Extension Registers Asymmetric Address for DRAM C 0 64Kx16 DRAM (8-bit RAS and CAS address) 1 Symmetric or Asymmetric 256Kx16 DRAM (9-bit RAS and CAS address or 10 bit RAS and 8 bit CAS addresses) This bit is effective only if bit 7=1. Either Symmetric or Asymmetric DRAMs may be used. Frame Buffer Refresh Count These bits are effective only if bit 7=1. Frame Buffer Lines/ Page 0 1 line per DRAM page 1 2lines per DRAM page This bit is effective only if bit 7=1. Note: 65540 only, should be programmed with 0 in the 65545. Frame Buffer Method 0 Embedded Frame Buffer. Frame buffer data is stored in display memory (DRAM A or DRAMs A & B depending on the setting of XR04 bits 0-1) 1 Extermal Frame Buffer. DRAM "C" is used exclusively for frame buffer data. Note: This bit can be set to 1 only when XRO04[1-0] (Memory Configuration) is set to either 00 (Display Memory in DRAMs A & B) or 01 (Display Memory in DRAM A). Revision 1.2 149 65540 / 545 MB 2094116 0011875 &bT? fmCAair> Extension Registers SETUP/DISABLECONTROLREGISTER(XR70) Read/Write at I/O Address 3D7h Index 70h [D7/D6|D5|D4]D3/D2]D1 DO Reserved(0) 3C3/46E8 Register Disable 6-0 Reserved (0) 7 3C3/46E8 Register Disable 0 In local bus configuration, port 3C3h works as defined to provide control of VGA disable. In ISA bus config- uration, port 46E8h works as defined to provide control of VGA disable and setup mode. 1 In local bus configuration, writes to VO port 3C3 have no effect. In ISA bus configuration, writes to I/O port 46E8h have no effect (the VGA remains enabled and will not go into setup mode). Note: Writes to register 46E8 are only effective in ISA bus configurations (46E8 is ignored in local bus configurations independent of the state of this bit). Writes to 3C3 are only effective in local bus config- urations (3C3 is ignored in ISA bus config- urations independent of the state of this bit). In PCI bus configuration (65545), this register has no effect; the chip comes up disabled except for the PCI configuration registers and the PCI configuration registers control VGA access. Reads from ports 3C3 and 46E8h have no effect independent of the programming of this register (both 3C3 and 46E8h are write-only registers). This register is cleared by reset. Revision 1.2 150 65540 / 545 M@@ 20948116 0011876 533Po eee ee Extension Registers EXTERNAL DEVICE I/O REGISTER(XR72) Read/Write at I/O Address 3D7h Index 72h D7[D6|D5{D4]D3(D2[D1 DO L Reserved(R/W) ENAVEE Pin Control GPIOO (ACTI Data GPIOO (ACTI) Pin Control GPIO1 (ENABKL) Data 0 Reserved (R/W) 1 ENAVEE Pin Control O Pin 61 is used as Enable VEE (ENA VEE) output (default on reset) 1 Pin 61 is used as Enable Backlight (ENABKL) output 2 GPIOO (ACTI) Data This bit always reads back the state of the ACTI pin (pin 53). When ACTI is configured as general purpose output (XR72[4-3]=11) this bit determines the data output on ACTI pin. 4-3 GPIOO (ACTI) Pin Control This bit is effective only when XRO1[4]=1, XR50[7]=0, and XROS{7-6]#1 1. 00 Pin 53 is ACTI output (default on reset). ACTI goes high during valid VGA memory or J/O read or write operations that are recognized by the chip. 01 Reserved 10 Pin 53 is general purpose input 0 GPIO1 (ENABKL) Pin Ctrl 5 GPIO1 (ENABKL) Data This bit always reads back the status of the ENABKL pin (pin 54). When ENABKL is configured as general purpose output (XR72[7-6]=1 1), this bit determines the data output on the ENABKL pin. 7-6 GPIO1 (ENABKL) Pin Control This bit is effective only when XRO1[4]=1, XR50[7]=0, and XRO5[7-6}411. 00 Pin 54 is used to output ENABKL (enable backlight) (default on reset) 01 Reserved 10 Pin 54 is general purpose input 1 (GPIO1) 11 Pin 54 is general purpose output 1 (GPIO1) See also XR5C "Activity Timer Control Register". The activity timer may be used to activate ENABKL or to evoke Panel Off mode after a specified time interval. (GPIOO) 11 Pin 53 is general purpose output 0 (GPIOO) Revision 1.2 151 65540 / 545 MB 2098116 0011877 eTDPMS CONTROL REGISTER (XR73) Read/Write at 1/O Address 3D7h Index 73h D7[D6|D5[D4]D3 D2|D1 [DO [| HSYNC Data HSYNC Control VSYNC Data VSYNC Control Reserved(0) This register is provided to allow the controller to independently shut down either or both of the HSYNC and VSYNC outputs. This capability allows the controller to signal a CRT monitor to enter power-saving states per the VESA DPMS (Display Power Management Signaling) Standard. The DPMS states are: H Nv Power ManagementState Active Active NormalOperation Inactive Active Active Inactive Inactive Inactive Standby (Quick Recovery) Opt Suspend (Max Power Savings) Off (Autorecovery is optional) 0 HSYNC Data If bit-1 of this register is programmed to 1, the state of this bit (XR73[0]) will be output on HSYNC (pin 65). 1 HSYNC Control Determines whether bit-0 of this register or internal CRTC horizontal sync information is output on HSYNC (pin 65). 0 CRTC HSYNC is output (Default) 1 XR73[0] is output 2 VSYNC Data If bit-3 of this register is programmed to 1, the state of this bit (XR73[2]) will be output on VSYNC (pin 64). 3. VSYNC Control Determines whether bit-2 of this register or internal CRTC vertical sync information is output on VSYNC (pin 64). 0 CRTC VSYNC is output (Default) 1 XR73[2] is output 7-4 Reserved (0) Extension Registers DIAGNOSTIC REGISTER (XR7D) (65545 Only) Read/Only at I/O Address 3D7h Index 72h [D7[D6 D5[D4][D3[D2 D1 [Do] Reserved(0) BitBLT Clock Control 6-0 Reserved (0) 7 BitBLT Clock Control (65545 Only ) 0 BitBLT logic receives a continuous running memory clock 1 The clock to the BitBLT logic is shut off Revision 1.2 152 65540 / 545 MH 2098116 00114878 30bCGA/HERCCOLORSELECTREGISTER(XR7E) Read/Write at I/O Address 3D7h Index 7Eh (D7[D6|Ds[D4 D3[D2[D1 [DO L_ Color Bit-0 (Blue) Color Bit-1 (Green) Color Bit-2 (Red) Color Bit-3 (Intensity) Intensity Enable Color Set Select l Reserved(0) This I/O address is mapped to the same register as TY/O address 3D9h. This alternate mapping effec- tively provides a color select register for Hercules mode. Writes to this register will change the copy at 3D9h. The copy at 3D9h is visible only in CGA emulation or when the extension registers are enabled. The copy at XR7E is visible when the extension registers are enabled. 5-0 See Register 3D9 7-6 Reserved (0) Extension Registers DIAGNOSTIC REGISTER (XR7F) Read/Write at I/O Address 3D7h Index 7Fh D7|D6|D5 D4]/D3|D2[D1 [Do 3-State Control Test Function Test Function Enable Special Test Function 0 3-State Control Bit 0 0 Normal outputs (default on reset) 1 3-state system bus and display output pins: HSYNC, VSYNC, FLM, LP, M, SHFCLK, P0-15, LDEV#, and LRDY#. 1 3-State Control Bit 1 0 Normal outputs (default on reset) 1 3-state memory output pins: RASA#, RASB#, RASC4#, CASAL#, CASAH#, CASBL#, CASBH#, CASCL#, CASCH#, WEA#, WEB#, WEC#, OEAB#, OEC#, AAO-9, and CAO0-9. 5-2. Test Function These bits are used for internal testing of the chip when bit-6 = 1. 6 Test Function Enable This bit enables bits 5-2 for internal testing. 0 Disabletest function bits (default) 1 Enable test function bits 7 ~~ Special Test Function This bit is used for internal testing and should be set to 0 (default to 0 on reset) for normal operation. Revision 1.2 65540 / 545 M! 2094116 00114679 242cnir>. Extension Registers PAGE(S) INTENTIONALLY BLANK Revision 1.2 154 65540 / 545 M@! 20594116 0012880 To4 om32-Bit Registers 32-Bit Registers (65545 Only ) Register Register Extension vO State After MnemonicGroup _Registet(Name Access __Type_ Address Reset Page DROO BitBLT BitBLT Offset 16/32-bit R/W 83D0-3 ----xXXXX XXXXXXXX ----XXXX XXXXXKXXX 156 DROt BitBLT BitBLT Pattem ROP 16/32-bit R/W 87D0-3 -------- ~--XXXXX XXXXXXXX XXXXXXXX 156 DRO2 BitBLT BitBLT BG Color 16/32-bit R/W 8BD0-3 xxxxxxxxX XXXXXXXX XXXXXXXK XXXXXXXX 157 DRO3 BitBLT BitBLTFGColor 16/32-bit R/W 8FD0-3 xxxxxxXX XXXXXXXX XXXXXKXAX KXXXXXXK 157 DRO4 BitBLT BitBLT Control 16/32-bit R/W 93D0-3 -------- ~--OXXXX XXXXXXKK XXKXXXXX 158 DRO5 BurBLT BitBLT Source 16/32-bit R/W 97D0-3 -------- ---XXXXX XXXXXXXK XXXXXXKX 159 DRO06 BitBLT BitBLT Destination 16/32-bit R/W 9BDO-3 - ------- -=-XXXXX XXXXXXXKX XXXXXXXX 159 DRO7 BiiBLT BitBLTCommand 16/32-bit R/W 9FDO-3 ----0000 00000000 ----xxxx xxxxxxxx 160 DRO8 Cursor Cursor Control 16/32-bit R/W A3D0-3 -------- -------- *e29000 000**+00 161 DRO Cursor Cursor Color 0-1 16/32-bit R/W A7DO-3 xxxxxXXXX XXXXXXXX XXXXXXXX XXXXXXXX 162 DROA Cursor Cursor Color 2-3 16/32-bit R/W ABDO-3 xxxxxXxXXX XXXXXXXX XXXXXKXX XXXXXXXKX 162 DROB Cursor Cursor Position 16/32-bit R/W AFDO-3 x----xXxXxX XXXXXXXK K+---XXX XXXKXXXX 163 DROC Cursor CursorBaseAddress 16/32-bit R/W B3D0-3 -------- ----XXXXK XXXXKX-- -------- 164 Reset Codes: Not changed by RESET (indeterminate on power-up) = Not implemented (always reads 0) Set from the corresponding pin on falling edge of RESET Read-only Hercules Configuration Register Readback bits Chip revision # (starting from 0000) = Not implemented (read/write, reset to 0) 0/1 = Reset to 0 or 1 by falling edge of RESET Revision 1.2 MH 2096116 0011851 155 65540 / 545 [TO32-Bit Registers BitBLT OFFSET REGISTER (DRO00) Write at I/O Address 83D083D3h Read at I/O Address 83D0-83D3h Word or Double Word Accessible 13128|27 16]1512|11 r Source Offset Tr + Reserved(0) - Destination Offset F Reserved(0) 11-0 Source Offset This value is added to the start address of the Source BitBLT to calculate the starting position for the next line. 15-12 Reserved (0) 27-16 Destination Offset This value is added to the start address of the Destination BitBLT to calculate the starting position for the next line. 31-28 Reserved (0) BitBLT PATTERN ROP REGISTER (DRO1) Write at I/O Address 87D0-87D3h Read at I/O Address 87D0-87D3h Word or Double Word Accessible Bi 21/20 Tr r Pattern Pointer r Reserved(0) 20-0 Pattern Pointer Address of Pattern Size - aligned 8 Pixel x 8 line pattern. For an 8BPP pattern (occupying 8 bits / pixel * 8 pixels / line * 8 lines / pattern) the pattern must be aligned on a 64 byte (16 DWord) boundary. For a 16BPP pattern (occupying 1 6bits / pixel * 8 pixels / line * 8 lines / pattern) the pattern must be aligned on a 128byte (32 DWord) boundary. For monochrome patterns (1 Bit / pixel * 8 pixels / line * 8 lines / pattern) the pattern must be aligned on an 8 byte (2 DWord) boundary. The lower bits of the Pattern Pointer are read/write, however the Drawing Engine forces them to zero for drawing operations. 3121 Reserved (0) Warning: Do not readt his egister while a BitBLT is active. Revision 1.2 65540 / 545 Mi 270596116 0011482 43732-Bit Registers BitBLT BACKGROUND COLOR REGISTER (DR02) Write at /O Address 8BD0-8BD3h Read at /O Address 8BD0O-8BD3h Word or Double Word Accessible Bi | rt | BackgroundColor 15-) Background Color This register contains the background color data used during opaque mono-color expan- sions. All 16 bits must be written regardless of pixel depth. If the drawing engine is operating at 8BPP, then the same data should be duplicated in bits 31:24, 23:16, 15:8, and 7:0. For 16BPP the data is dupli- cated twice. 31-16 Duplicate of 15-0 BitBLT FOREGROUND COLOR REGISTER (DR03) Write at I/O Address 8FD0-8FD3h Read at YO Address 8FDO-8FD3h Word or DoubleWord Accessible Bi TT. t Foreground Color 15-0 Foreground/Solid Color This register contains the color data used during solid paint operations. It also is used as the foreground color during mono-color expansions. All 16 bits must be written regardless of pixel depth. If the drawing engine is operating at 8BPP, then the same data should be duplicated in bits 31:24, 23:16, 15:8, and 7:0. For 16BPP the data is dupli- cated twice. 31-16 Duplicate of 15-0 Warning: Only bits 15-0 are used. They are duplicated in bits 31-16 when this register is read back by the CPU. Warning: Only bits 15-0 are used. They are duplicated in bits 31-16 when this register is read back by the CPU. Revision 1.2 65540 / 545 Mi 2094116 0011883 77332-Bit Registers BitBLT CONTROL REGISTER (DR04) Write at I/O Address 93D0-93D3h Read at I/O Address 93D0-93D3h Word or DoubleWord Accessible 131272320 1916]15 87 ROP TT. INC_X, INC_Y Source Data Source Depth Pattern Depth Background BitBLT Sre/Dst Pattern Seed Solid Pattern BitBLT Status Reserved(0) Buffer Status 7-0 10 11 Reserved(0) ROP Raster Operation as defined by Microsoft Windows. All logical operations of Source, Pattern, and Destination Data are supported. INC_Y DeterminesBitBLTY-direction: 0 Decrement(Bottomto Top) 1 Increment (Top to Bottom) INC_X DeterminesBitBLTX-direction: 0 Decrement(Rightto Left) 1 Increment (Left to Right) Source Data Selects variable data or color register data: 1 Source is FG Color Reg (DRO3) 0 Source data selected by DRO4[14] Source Depth Selects between monochrome and color source data. This allows BitBLTs to either transfer source data directly to the screen or perform a font expansion INC_X=1 only): 0 Source is Color 1 Source is Mono (Font expansion) 12 13 15-14 18-16 19 20 23-21 27-24 31-25 Pattern Depth Selects between monochrome and color pattern data. This allows the pattern register to operate either as a full pixel depth 8x8 pattern for use by the ROP, or as an 8x8 monochromepattern: 0 Pattern is Color 1 Patternis Monochrome Background The 65540 / 545 supports both transparent and opaque backgrounds for monochrome patterns and font expansion: 0 BGis Opaque (BG Color Reg DRO2) 1 BGis Transparent (Unchanged) BitBLT Source/Destination The 65540 / 545 only supports its local display memory as the destination for BitBLT operations. The source may be either display memory or system memory (CPU): 15 14 BitBLT Source> Dest 0 0 Screen > Screen (Dest) 0 1 System > Screen (Dest) 1 O- Reserved 1 1 Reserved Pattern Seed Determines the starting row of the 8x8 pattern for the current BitBLT. A pattern is typically required to be destination aligned. The 65540 / 545 can determine the x- alignment from the destination address however the y-alignment must be generated by the programmer. These three bits determine which row of the pattern is output on the first line of the BitBLT. Incrementing and decrementing are controlled by bit DRO4[8]. Solid Pattern 1 = Solid Pattern (Brush) 0 = BitmapPattern BitBLT Status (Read Only ) 0 BitBLTEngineldle 1 BitBLT Active - do not write BitBLT regs Reserved (0) Buffer Status # of DWords that can be written to the chip: 0000 Buffer Full 0001 1 Space available in the queue 1111 15 Spaces available in the queue Reserved (0) Revision 1.2 158 65540 / 545 Me 2094116 0011884 LOT32-BifRegisters BitBLT SOURCE REGISTER (DR05) BitBLT DESTINATION REGISTER (DR06) Write at /O Address 97D0-97D3h Write at I/O Address 9BDO-9BD3h Read at I/O Address 97D0-97D3h Read at /O Address 9BDO-9BD3h Word or Double Word Accessible Word or Double Word Accessible Bi 21/20 o| Bi 2120 ol LE Li - SourceAddress f Destination Addr r Reserved(0) r Reserved(0) 20-0 Source Address 20-0 DestinationAddress Address of Byte aligned source block. Address of Byte aligned destination block. 31-21 Reserved (0) 31-21 Reserved (0) Warning: Donotreadthis register Warning: Donotreadthis register while a BitBLT is active. while a BitBLT is active. Revision 1.2 159 65540 / 545 MB 2098116 0011885 Sub32-Bit Registers BitBLT COMMAND REGISTER (DR07) Write at I/O Address 9FD0-9FD3h Read at YO Address 9FDO0-9FD3h Word or DoubleWord Accessible (3128|27 16/1512|11 r Bytes per Line Tt fb Reserved(0) r Lines per Block E Reserved(0) 11-0 Bytes Per Line Number of bytes to be transferred per line 15-12 Reserved (0) 27-16 Lines Per Block Height in lines of the block to be transferred 31-28 Reserved (0) Warning: Do not attempt to perform a CPU read/write to display memory while a BitBLT is active. Revision 1.2 M 2096116 0011486 44e 160 65540 / 54532-Bit Registers CURSOR/POP-UFCONTROIREGISTERDR08) Write at I/O Address A3D0-A3D3h Read at I/O Address A3D0-A3D3h Word or DoubleWord Accessible B1 16]1512/1 110 9] 8i7 6] 5l4_ 21 ol Cursor Enable Resrvd (must be 0) ULC Select Test Pop-up Width X Zoom Y Zoom Auto Zoom Reserved(R/W) Reserved(0) 1-0 42 Cursor/Pop-Up Menu Enable This bit enables the hardware cursor. The cursor will be enabled/disabled in the frame following the current active frame (synchronized to vertical blank). 00 BothDisabled 01 32x32 Cursor Enable 10 64x64 Cursor Enable 11 Pop-Up Menu Enable Reserved (R/W) Must be programmed to 0. Upper Left Corner (ULC) Select The cursor is set relative to either the Upper Left Corner (ULC) of the active display or of the overscan region. When set relative to the active display (BLANK#) the cursor will not be visible in the overscan area. When relative to Display Enable, the cursor may appear in the overscan region. All x,y positioning is relative to the selected ULC. 0 ULC is BLANK# (x=0, y=0 corre- sponds to the top left of the panel) 1 ULC is Display Enable (x=0, y=0 corresponds to the top left of the image) 7-6 11 Test Pop-Up Menu Width 0 One bpp. Menu width = 128 pixels. This also forces a height of 128 lines. CCO and CCl (DRO9) determine menu colors. 1 Two bpp. Menu width = 64 pixels. CCO0-3 (DRO9 and DROA) determine menu colors. X Zoom (Manual) 0 Nopixel replication. 1 Replicate pixels in the horizontal direction. No pixel replication takes place in CRT interlace mode and for 32x32 cursor. Y Zoom (Manual) 0 Nopixelreplication. 1 Replicate pixels in the vertical direction. No pixel replication takes place in CRT mode and for 32x32 cursor. Auto Zoom 0 Autozoom off 1 Replicate pixels in high resolution modes. No pixel replication takes place in CRT interlace mode and for 32x32 cursor. 15-12 Reserved (R/W) 31-16 Reserved (0) Refer to the Functional Description section of this Revision 1.2 document for additional information on programming of the Hardware Cursor feature. 65540 / 545 161 Mi 2094116 0011687 319CHiFS 32-Bit Registers CURSOR/POP-UPCOLOR0-IREGISTER(DRO9) CURSOR/POP-UPCOLOR2-3REGISTER(DROA) Write at /O Address A7DOA7D3h Write at /O Address ABDO-ABD3h Readat I/O Address A7D0-A7D3h Read at YO Address ABDO-ABD3h Word or DoubleWord Accessible Word or Double Word Accessible Bi 2726 2120 16[15 11/10 54 | Bi 27p6 2120 1615 11]10 5/4 o| 4 E + CCO - Blue | CC2 - Blue f CCO- Green J CC2 - Green t CCO - Red = F CC2 - Red r CCI - Blue oo PF CC - Blue r CC1 - Green o P_ CC3 - Green r CCI - Red r CC3 - Red A 4 Cursor Colors 0 and 1 are 16-bit high color values Cursor Colors 2 and 3 are 16-bit high color values consisting of 5 bits of Red, 6 bits of Green, and 5 consisting of 5 bits of Red, 6 bits of Green, and 5 bits of Blue. Colors 0 and 1 may be accessed either bits of Blue. Colors 2 and 3 may be accessed either as two 16-bit registers or as a single 32-bit register. as two 16-bit registers or as a single 32-bit register. A write to this register immediately affects the cursor Colors 2 and 3 are only used when the Cursor is in color displayed. Pop-Up Mode. A write to this register immediately affects the cursor color displayed. 4-0 CC0-Blue Cursor Color 0 Blue value 40 CC2-Blue Cursor Color 2 Blue value 10-5 CCO0-Green Cursor Color 0 Green value 10-5 CC2-Green Cursor Color 2 Green value 15-11 CC0-Red Cursor Color 0 Red value 15-11 CC2-Red Cursor Color 2 Red value 20-16 CC1-Blue Cursor Color 1 Blue value 26-21 CC1-Green Cursor Color 1 Green value 31-27 CC1-Red Cursor Color 1 Red value 20-16 CC3-Blue Cursor Color 3 Blue value 26-21 CC3-Green Cursor Color 3 Green value 31-27 CC3-Red Cursor Color 3 Red value Revision 1.2 162 65540 / 545 Mi 2094116 0011488 25532-Bit Registers CURSOR/POP-UFPPOSITIONREGISTERDROB) Write at I/O Address AFDO-AFD3h Read at I/O Address AFDO-AFD3h Word or DoubleWord Accessible 180 2726 1615/14 11/10 | ' r X Offset r Reserved(0) X SIGN r Y Offset F Reserved(0) Y SIGN 10-0 14-11 15 X Offset Cursor X-position. The cursor position is calculated as the signed offset (in pixels) between the Upper Left Corner (ULC) of the screen (as defined by BLANK#) and the Upper Left Corner of the cursor. X Offset is the magnitude portion of the signed offset of the cursor position in the horizontal axis. This magnitude in combination with the X SIGN bit (15) form the signed offset of the cursor in the X direction. The X OFFSET and X SIGN may be written as a 16-bit quantity with bits 14-11 ignored. The range for the ULC of the cursor is: 2047 <= X-Position <= 2047 Reserved (0) X Sign Sign associated with the X OFFSET magnitude which together form the signed offset of the cursor in the X direction. 26-16 30-27 31 Y Offset Cursor Y-position. The cursor position is calculated as the signed offset (in pixels) between the Upper Left Corner (ULC) of the screen (as defined by BLANK#) and the Upper Left Corner of the cursor. Y Offset is the magnitude portion of the signed offset of the cursor position in the vertical axis. This magnitude in combination with the Y SIGN bit (31) form the signed offset of the cursor in the Y direction. The Y OFFSET and Y SIGN may be written as a 16-bit quantity with bits 30-27 ignored. The range for the ULC of the cursor is: ~2047 <= Y-Position <= 2047 Reserved (0) Y Sign Sign associated with the Y OFFSET magnitude which together form the signed offset of the cursor in the Y direction. In pop-up menu mode negative values are not supported. Revision 1.2 163 65540 / 545 MH 20986116 0011689 15)CHIFS 32-Bit Registers CURSOR/POP-UP BASE ADDRESS (DROC) Write at I/O Address B3D0-B3D3h Read at YO Address B3D0-B3D3h Word or DoubleWord Accessible 1 20]19 10/9 - Reserved(0) lr | BaseAddress r Reserved(0) 9-0 Reserved (0) 19-10 Base Address Base address for cursor / pop-up data in display memory. Bit 10 (address Isb) should be programmed to 0 when the 128x128 pop-up menu is being displayed. Defines a byte address in display memory as seen by the CPU. 31-20 Reserved (0) Refer to the Functional Description section of this document for additional information on programming of the Hardware Cursor feature. Revision 1.2 164 65540 / 545 Mi 2094116 0011490 503Functional Description System Interface Functional Blocks The 65540 / 545 contains 5 major functional blocks including the standard VGA core (Sequencer, Attribute controller, Graphics Controller, and CRT Controller), a BitBLT engine (65545 only), Hardware Cursor (65545 only), Palette DAC, and Clock Synthesizer. There are also other subsystems such as the bus and memory interfaces which are transparent to both the user and software programmer. While in standard VGA modes only the VGA core, Palette DAC, and clock synthesizer are active. Bus Interface Two major buses are directly supported by the 65540 and 65545: Industry Standard Architecture (ISA), and VESA Local Bus (VL-Bus); the 65545 also supports the PCI Bus. Direct interfaces to popular 80486DX, 80486DX2, 80486SX, and 80386DX processors are supported by both chips. Connection to 16-bit PI bus and other 32-bit system buses such as EISA and Micro Channel (MC) are possible with external logic but are not inherently supported. ISA Interface The 65540 / 545 operates as a 16-bit slave device on the ISA bus. It maps its display memory into the standard VGA address range (OA0000-OBFFFFh). The VGA BIOS ROM is decoded in the 32KByte space at 0CO000-0C7FFFh (an output is available on the ROMCS# pin for ROM chip selection). Address lines LA23:17 are required for decoding MEMCS 16# hence these addresses are latched internally by ALE. The remaining addresses (SA16:0) are accepted from the system without internal latching. The 65540 / 545 supports 16-bit memory and I/O cycles. Whenever possible the 65540 / 545 executes zero wait state memory cycles by asserting ZWS#. It does not generate MEMCS16# or ZWS# on ROM accesses. Memory may be mapped as a single linear frame buffer anywhere in the 16 MByte ISA memory space on a 512K/1MByte boundary (depending on the amount of display memory installed - see XROB[4]). The 16-bit bus extension signals MEMR# and MEMWi# are used for memory control since mapping above the 1MByte boundary is permitted. For ISA compatibility the IRQ pin operates as an active high level-triggered interrupt. VL-BusInterface The 65540 / 545 operates as a 32-bit target on the VL-Bus. It has an optimized direct pin-to-pin connection for all VL-Bus signals to eliminate external components. Up to 28 bits of the 32-bit VL- Bus address may be decoded on-chip permitting location of the linear frame buffer anywhere in a 256MByte address space. Optionally, the upper 4 address bits may be decoded externally to support the full 32-bit, 4GB VL-Bus address space. Zero wait state read accesses are not permitted, however, the 65540 / 545 will terminate a read cycle in the second T2 if the data is available. Burst cycles are not supported Direct ProcessorInterface The 65540 / 545 can interface directly to all 32-bit x86-architecture processors. Its full non-multiplexed 28-bit address makes it simple to connect to the CPU. On valid 65540 / 545 accesses it will generate LDEV# which is monitored by the system logic controller. This interface is essentially the same as the VL-Bus interface with the exception that both 1x and 2x CPU clocks are acceptable. When using a 2x clock the CPU Reset must be connected to the 65540 / 545 CRESET input for phase coherency. The 65540 / 545 does not support pipelined mode in its 386 processor interface. PCI Interface The 65545 also supports a full 32-bit PCI bus interface as defined by PCI Interface Specification Revision 2.0. All features required of a non-bus- master target device are implemented on-chip with no external glue logic required. Read/Write cycles are supported for Memory, I/O, and Configuration address spaces. Burst accesses are not supported. Interrupt capability is provided for vertical interrupts. Refer to the PCI Pin Descriptions and Configuration Registers sections for further information. Revision 1.2 165 65540 / 545 Mi 2094116 0011891 647Functional Description Display Memory Interface Memory Architecture The 65540 / 545 supports both 512K and IMB configurations for display memory plus an additional 512K for an optional external frame buffer. Frame buffering is required for support of simultaneous display on CRTs and DD panels, however, the 65540 / 545 has the ability to embed frame buffer data in display memory. Since this uses some of the available memory bandwidth, the 65540 / 545 also supports an additional DRAM for use as an external frame buffer for improved performance. The 65540 / 545 implements a 32-bit wide data bus for display memory and 16-bit for the optional external frame buffer. The memory data buses are named 'A', 'B', and 'C in groups of 16 bits. A holds the lower 512K of display memory, B' normally holds the upper 512K of display memory in 1MB configurations and 'C is normally used for the external frame buffer (if used). The chip may, however, be optionally programmed to put the upper half of display memory in DRAM 'C' instead (..e., 'C' may be programmed to hold either display memory or external frame buffer data). When an external frame buffer is not required, 'C may also be used as an input port for external video data (to implement overlay of live video over VGA output for example) and to provide additional panel interface data bits beyond the basic 16 (for TFT panels with 18-bit or 24-bit data interfaces since TFT panels are single panels and never require frame buffering). There are separate groups of RAS, CAS, and WE pins for each of the three DRAMs (A, B, and C). There are only two OE pins and two address buses however, one for A and B and another for C. Configuration initialization data is latched from memory address pins AAOQ-8 (the address bus for DRAMs A and B) at the end of reset. These bits are readable in XRO1[0-7] and XR6C[1] respectively. The 65540 and 65545 support all VGA text and graphics modes (planar, packed pixel, odd/even chain modes, etc.) but the storage locations of the data (i.e., the locations and bit positions in the DRAMs) does not correspond to the original VGA which implemented 256KB of display memory as 4 physical planes of 64KB (using two 64Kx4 DRAMs to implement each plane with separate address buses for planes 0-1 and 2-3). In other words, no assumptions should be made regarding the correspondence of the data pins on the display memory data bus of the 65540 / 545 to traditional VGA 'plane' concepts. For example, text data is still stored in plane 0, attribute data in plane 1, and font data in plane 2, but due to the extensive use of page-mode cycles and the use of a single address bus for display memory data, where those planes are physically located in the DRAMs is much different. In addition, the 65540 / 545 make extensive use of internal FIFOs to improve performance. As a result the read / write activity on the DRAM interface pins at any point in time corresponds only approximately to system bus and CRT / panel output activity at that time. Memory Chip Requirements The 65540 / 545 is designed to use 256K x 4 or 256K x 16 DRAMs. Fast-page-mode capability is required. Either 'CAS-Before-RAS' or Self- Refresh DRAMs may be used. Both dual-CAS# (default) and dual-WE# types of 256Kx16 DRAMs are supported. DRAMs with symmetrical address inputs (A0-8) are supported by default, but the chip can be configured to support asymmetrical address (A0-9) DRAMs. The BIOS can test the DRAMs to detect the type of DRAM used and program the chip accordingly. The 65540 / 545 can generate Page Mode Read, Page Mode Write, and Page Mode Read-Modify-Write cycles. CAS-before-RAS Refresh and Self-Refresh cycles are also supported. The memory interface is optimized for 40ns page mode cycles but is flexible and can be tuned for any speed DRAM. The 65540 / 545 supports various DRAM speeds. The maximum frequency of the 65540 / 545 is 75 MHz. The recommended maximum memory clock frequency for various DRAM based on commonly available DRAM specifications is as follows: DRAMSpeed Memory Clock Frequency* 100 ns 50.000 MHz 80 ns 57.000 MHz 70 ns 65.000 MHz * DRAM AC timing parameters varies among different DRAM manufacturers therefore please check with DRAM specifications and 65540 / 545 memory timing. Revision 1.2 166 65540 / 545 MB 20548116 0011852 78Functional Description Clock Synthesizer An integrated clock synthesizer supports all pixel clock (VCLK) and memory clock (MCLK) frequencies which may be required by the 65540 / 545. Each of the two clock synthesizer phase lock loops may be programmed to output frequencies ranging between 1MHz and the maximum specified operating frequency for that clock in increments not exceeding 0.5%. The frequencies are generated by an 18-bit divisor word. This value contains divisor fields for the Phase Lock Loop (PLL), Voltage Controlled Oscillator (VCO) and Pre/Post Divide Control blocks. The divisor word for both synthesizers is programmable via Clock Control Registers XR30-32. MCLK Operation Normal operational frequencies for MCLK are between SOMHz and 68MHz. Refer to the Electrical Specifications for maximum frequencies at 3.3V and 5V (the maximum frequency at 3.3V will be slightly lower). Normal MCLK operational frequencies are defined by the display memory sequencer parameters described in the Memory Timing section. The frequency selected is also dependent upon the AC characteristics of the display memories connected to the 65540/545. A typical match is between industry standard 70ns access memories and a 65MHz MCLK. The MCLK output defaults to 60MHz on reset and is fully programmable. This initial value is conservative enough not to violate slow DRAM parameters but not so slow as to cause a system timeout on CPU accesses. The MCLK frequency must always equal or exceed the host clock (CCLK) frequency. VCLkRegisterTable VGA CLKO = 25.175MHz VGA CLK] = 28.322MHz 21 VCLK Synthesizer >| CLK2 = Programmable Ln XR32:30 MCLKERegisterT able >| MCLK=Programmable 2), MCLK Synthesizer CLKSEL1:0 MISC Output Reg[3:2] ( Clock Synthesizer Register Structure > XR30(0] Reference 1 [ PSN] j >| Phase Charge | A ->P CLK XR32[6:0] hi > +N p| Detector Pump ] >) VCO m) +2 : i Cs ' Internal ' i Loop Filter : XR31[6:0] <2 | Mf ; XR30[3:1] post-VCO divider select a 1 Phase-LockedLoop Oscillator (| Clock Synthesizer PLL Block Diagram Revision 1.2 167 65540 / 545 MH 2094116 0011493 bicFunctional Description VCLK Operation The VCLK output typically ranges between 19MHz and 65MHz. VCLK has a table of three frequencies from which to select a frequency. This is required for VGA compatibility. CLKO and CLK] are fixed at the VGA compatible frequencies of 25.175MHz and 28.322MHz respectively. These values can not be changed unlike CLK2 which is fully program- mable. The active frequency is chosen by clock select bits MSR[3:2]. Programming the Clock Synthesizer The desired output frequency is defined by an 18-bit value programmed in XR30-32. The 65540 / 545 has two programmable clock synthesizers; one for memory (MCLK) and one for video (VCLK). They are both programmed by writing the divisor values to XR30-32. The clock to be programmed is selected by the Clock Register Program Pointer XR33[5]. The output frequency of each of the clock synthe- sizers is based on the reference frequency (FReF) and the 4 programmed fields: Field # Bits PrescaleN(PSN) XR30[0] (+1 or +4) Mcounter(M') XR31[6:0] (M=M - 2) Ncounter (N) XR32[6:0] (N'=N - 2) PostDivisor(P) XR30[3:1] (+2P;0<P<5) Frer * 4* M Four = pon * N *2P The frequency of the Voltage Controlled Oscillator (Fvco) is determined by these fields as follows: where FREF = Reference frequency (between 4 MHz - 20 MHz; typically 14.31818 MHz) Note: If a reference frequency other than 14.31818 MHz is used, then the frequencies loaded on RESET will not be correct. P Post Divisor 000 1 001 2 010 4 011 8 100 16 101 32 Programming Constraints There are five primary programming constraints the programmer must be aware of: 4 MHz < Frer < 20 MHz 150 KHz < Frer/(PSN * N) < 2 MHz 48 MHz < Fvco < 220 MHz 3<M<127 3<SN <127 The constraints have to do with trade-offs between optimum speed with lowest noise, VCO stability, and factors affecting the loop equation. The value of Fvco must remain between 48 MHz and 220 MHz inclusive. Therefore, for output frequencies below 48 MHz, Fvco must be brought into range by using the post-VCO Divisor. To avoid crosstalk between the VCO's, the VCO frequencies should not be within 0.5% of each other nor should their harmonics be within 0.5% of the other's fundamental frequency. The 65540 / 545 clock synthesizers will seek the new frequency as soon as it is loaded following a write to XR32. Any change in the post-divisor will take affect immediately. There is a possibility that the output may glitch during this transition of post divide values. Because of this, the programmer may wish to hold the post-divisor value constant across a range of frequencies (eg. changing MCLK from the reset value of 5SOMHz to 72MHz). There is also the consideration of changing from a low frequency VCO value with a post-divide +1 (eg. SOMHz) to a high frequency +4 (eg. 220MHz). Although the beginning and ending frequencies are close together, the intermediate frequencies may cause the 65540 / 545 to fail in some environments. In this example there will be a short-lived time frame during which the output frequency will be in the neighborhood of 12.5MHz. The bus interface may not function correctly if the MCLK frequency falls below a certain value. Register and memory accesses which are synchronized to MCLK may be so slow as to violate bus timing and cause a watchdog timer error. Programmers should time-out the system (CPU) for approximately 10ms after writing XR32 before accessing the VGA again. This will ensure that accesses do not occur to the VGA while the clocks are in an indeterminate state. Note: On reset the MCLK is initialized to a 60MHz output with a post divisor = 2 (Fvco= 120MHz). Revision 1.2 168 65540 / 545 MB 2098116 0011894 555Programming Example The following is an example of the calculations which are performed: Derive the proper programming word for a 25.175 MHz output frequency using a 14.31818 MHz refer- encefrequency: Since 25.175 MHz < 48 MHz, double it to 50.350 MHz to get Fvco in its valid range. Set the post divide field (P) to 001. Prescaling PSN = 4 Theresult: Fvco = 50.350 = (14.31818 x 4x M/4x N) MIN = 3.51655 Several choices for M and N are available: M N Fvco Error 109 31 50.344 -0.00300 102 29 50.360 +0.00500 Choose (M, N) = (109,31) for best accuracy. Prescaling PSN = 1 Theresult: Fvco = 50.350 = (14.31818 x 4.x M/1 x N) MIN = 0.879127 M N 80 91 Fvco $0.349 Error -0.00050 FREF/(PSN x N) = 157.3KHz Therefore M/N = 80/91 with PSN = 1 is even better than with PSN = 4. XR30 = 0000010b (02h) XR31 = 80 - 2 = 78 (4Eh) XR32 = 91 - 2 = 89 (59h) [er] NOTE: Do not connect Vcc here. } vec Force the trace through the Designator Value | decoupling C1,C3,C4,C6,C7 | 0.1 HF cap pad. C2,C5 A47TpF R1LR2 102 Functional Description PCB Layout Considerations Clock synthesizers, like most analog components, must be isolated from the digital noise which exists on a PCB power plane. Care must be taken not to route any high frequency digital signals in close proximity to the analog sections. Inside the 65540/545, the clocks are physically located in the lower left corner of the chip surrounded by low frequency imput and output pins. This helps minimize both internally and externally coupled noise. The memory clock and video clock power pins on the 65540/545 each require similar RC filtering to isolate the synthesizers from the VCC plane and from each other. The filter circuit for each CVCCn / CGNDn pair is shown below: +5V t 10Q pVA CvCCn _[LO.1pF 47pF | _| 0.1pF 7~ an AN CGNDn GND The suggested method for layout assumes a multi- layer board including VCC and GND planes. All ground connections should be made as close to the pin / component as possible. The CVCC trace should route from the 65540/545 throughthepads of the filter components. The trace should NOT be connected to the filter components by a stub. All components (particularly the initial 0.1p4F capacitor) should be placed as close as possible to the 65540/545. we a: " on GND Cc) a2 a c a2 CGNDO = GND ("7 xTALl Cc XxTALo cvcco CVCC1 CY] RESET# Gl Always pass the Vcc trace through the decoupling cap pad. Do not leave a stub as shown here. Revision 1.2 169 65540 / 545 MM 2098116 00113895 4955Functional Description VGA Color Palette DAC The 65540 / 545 integrates a VGA compatible triple 6-bit lookup table (LUT) and high speed 6/8-bit DACs. Additionally the internal color palette DAC supports true-color bypass modes displaying color depths up to 24bpp (8-8-8). The palette DAC can switch between true-color data and LUT data on a pixel by pixel basis. Thus, video overlays may be any arbitrary shape and can lie on any pixel boundary. The hardware cursor is also a true-color bitmap which may overlay both video and graphics on any pixel boundary. The internal palette DAC register I/O addresses and functionality are 100% compatible with the VGA standard. In all bus interfaces the palette DAC automatically controls accesses to its registers to avoid data overrun. This is accomplished by holding RDY in the ISA configuration and by delaying LRDY# for VL-Bus and direct processor interfaces. For compatibility with the VL-Bus Specification the 65540 / 545 may be disabled from responding to palette writes (although it will perform them) so that an adapter card on a slow (ISA) bus which is shadowing the palette LUT may see the access. The 65540 / 545 always responds to palette read accesses so it is still possible for the shadowing adapter to become out of phase with the internal modulo-3 RGB pointer. It is presumed that this will not be a problem with well-behaved software. Extended display modes may be selected in the Palette Control Register (XR06). Two l6bpp formats are supported: 5-5-5 Targa format and 5-6-5 XGA format. HighColorPixelData | ~~ + Red 24 : Hardwarursor _ > Triple ExternaIRGBVideo } _ > 6/8-bit | > Green (565, 666, or 888) DAC | Blue LUTPixeData __8-___) TMPI@bit | 18 VGA Color Palette DAC Data Flow Revision 1.2 170 65540 / 545 Mi 2094116 0011856 32]BESET EEEE HEED gbtzaz CAPS Functional Description BitBLT Engine (65545 only ) Bit Block Transfer The 65545 integrates a Bit Block Transfer (BitBLT) Engine which is optimized for operation in a Microsoft Windows environment. The BitBLT engine supports system-to-screen and screen-to- screen memory data transfers. It handles monochrome to color data expansion using either system or screen data sources. Color depths of 8 and 16bpp are supported in the expansion logic. Integrated with the screen and system BitBLT data streams is a 3-operand raster-op (ROP) block. This ROP block includes an independent 8x8 pixel (mono or color) pattern. Color depths of 8 and 16bpp are supported by the pattern array. All possible logical combinations of Source (system or screen data), Destination (screen data), and Pattern data are available. The BitBLT and ROP subsystems have been archi- tected for compatibility with the standard Microsoft Windows BitBLT parameter block. The source and destination screen widths are independently program- mable. This permits expansion of a compressed off- screen bitmap transparent to the software driver. The BitBLT Control Register (DRO4) uses the same raster-op format as the Microsoft Windows ROP so no translation is required. All 256 Windows defined ROPs are available. All possible overlaps of source and destination data are handled by controlling the direction of the BitBLT im the x and y directions. As shown below there are eight possible directions for a screen-to- screen BitBLT (no change in position is a subset of all eight). Software must determine the overlap, if any, and set the INC_X and INC_Y bits accord- ingly. This is only critical if the source and desti- nation actually overlap. For most BitBLTs this will not be the case. In BitBLTs where INC_X is a don't care it should be set to 1 (proceed from left to right). This will increase the performance in some cases. Source Source Source Dest Dest Dest INC_X = X; INC_Y =0 Source Dest INC_X = 0; INC_Y =X INC_X = X; INC_LY =0 Arrowsindicate appropriatedirection for BitBLT progression so thatdestinationoverlap does not corrupt data. INC_X = X; INC_LY =0 Dest Source INC_X = 1; INC_LY =X Dest Dest Dest Source Source Source INC_X = X; INC_LY =1 INC_X = X; INC_LY =1 INC_X = X; INC_LY =1 ( Possible BitBLT Orientations With Overlap > Revision 1.2 171 65540 / 545 Me 2096116 0011497 choSample Screen-to-Screen Transfer Below is an example of how a screen-to-screen BitBLT operation is traditionally performed. The source and destination blocks both appear on the visible region of the screen and have the same dimensions. The BitBLT is to be a straight source copy with no raster operation. The memory address space is 2MBytes and display resolution is 1024 x 768. The size of the block to be transferred is 276 horizontal x 82 vertical pixels (114h x 52h). The coordinates of the upper left corner (ULC) of the source block is 25h,30h. The ULC coordinates of the destination block are 157h,153h. Because the source and destination blocks do not overlap, the INC_X and INC_Y BitBLT direction bits are not important. We will assume that INC_X = 1, INC_Y = 0, and the BitBLT will proceed one scan line at a time from the lower left corner of the source moving to the right and then from the bottom to the top. The source and destination offsets are both the same as the screen width (400h): BitBLT Offset Register (DROO) = 04000400h }-_ 400h (1024) _+ * [25h,30h 114h 52h Source 138h,8th 300h 157h,153h (768 Destination 26Ah, 1A4h 1024 x 768 x 8BPP Functional Description The Pattern ROP Register does not need to be programmed since there is no pattern involved. Neither the Foreground Color nor Background Color Register has to be programmed since this does not involve a color expansion or rectangle solid color paint. The BitBLT Control Register contains the most individual fields to be set: ROP = Source Copy = 0CCh INC_Y =0 (Bottom to Top) INC_X = 1 (Left to Right) Source Data = Variable Data = 0 Source Depth = Source is Color =0 Pattern Depth = Don't Care = 0 Background = Don't Care = 0 BitBLT = Screen-to-Screen = 00 Pattern Seed = Don't Care = 000 BitBLT Control Register (DR04) =002CCh Since the BitBLT will be starting in the lower left corner (LLC) of the source rectangle, the start address for the source data is calculated as: 1 020538h FEFFFh Line 52h rl Off-Screen 020425h 0C000Ch -____ | _ 06926Ah Dest 054D57h F 020538h 00c938h Soure Line 3 00C025h 00C825h 000000h 00C538h Line 2 00C425h 00C138h Line 1 00C025h ( Screen-to-Screen BitBLT > Revision 1.2 65540 / 545 M@ 2098116 0011898 174gescces suse nescapesccss HOHE lel HH ULnirs Functional Description (81h * 400h) + 25h = 020425h BitBLT Source Register (DRO5) = 020425h Similarly, the LLC of the destination register calcu- latedas: (1A4h * 400H) + 157h = 069157h BitBLT Destination Register (DR06) = 069157h To begin any BitBLT the Command Register must be written. This register contains key information about the size of the current BitBLT which must be written for all BitBLT operations: Lines per Block = 52h Bytes per line = 114h (Current example 8bpp) Command Register (DRO7) = 00520114h After the Command Register (XRO7) is written the BitBLT engine performs the requested operation. The status of the BitBLT operation may be read in DRO04[20] (read only bit). This is necessary to determine when the BitBLT is finished so that another BitBLT may be issued. No reads or writes of the display memory by the CPU are permitted while the BitBLT engine is active. In the present example the BitBLT source and desti- nation blocks have the same width as the display. As can be seen below each scan line is transferred from source to destination. Alignment is handled by the BitBLT engine without assistance from software. Compressed Screen-to-Screen Transfer Next we consider an example of how a screen-to- screen BitBLT operation is performed when the source and destination blocks have different widths (pitch). This type of BitBLT is commonly used to store bitmaps efficiently in offscreen memory or when recovering a saved bitmap from offscreen memory. The 65545 display memory consists of a single linear frame buffer. The number of bytes per scan line and lines displayed changes with resolution and pixel depth. For simplification, the concepts of pixels, 1FFFFFh 020538h 06926Ah J Line 52h] | Line 52h 020425h 069157h 0C0000h ( (a dL or 069269h Dest 054D57h 020538h 00C938h 05566Ah Source Line 3 | | Line 3 00C025h 00C825h 055557h 000000h . 00C538h 05526Ah Line 2. | ----_ | Line 2 00C425h 055157h 00C138h 054E6Ah Line 1. | > | Line 1 00C025h 054D57h ( BitBLT Data Transfer Revision 1.2 173 MB 2098116 00114899 030 65540 / 545ste atttes @ Functional Description lines, and columns are foreign to the BitBLT engine. Instead, the 65545 operates on groups of bytes (rows) which are separated by the width of the screen. The 65545 permits separation between the row lengths to be different for source and destination bitmaps. For efficient use of offscreen memory we may assume that the "width" of the screen is the same as the width of the data. Below is an example of how a screen-to-screen BitBLT operation is performed with the destination data efficiently compressed into the offscreen area. The reverse operation is also valid to recreate the original block on the visible screen. Once again the BitBLT is to be a straight source copy with the source block in the same location as the previous example. The destination block is to be located beginning at the first byte of off-screen memory. Because the source and destination blocks do not overlap the INC_X and INC_Y BitBLT direction bits are not important. We will assume that INC_X = 1, INC_Y = 1 and the BitBLT will proceed one scan line at a time from the upper left corner of the source 1FFFFFh 020538h | Line 52h} [ 020425h Off-Scree Memory (i ore 020538h 00C938h Line 3 00C025h 00C825h 000000h 00C538h Line2 | + 00C425h 00C138h Line 1 | "+ 00C025h Source moving to the right and then from the top to the bottom. The source offset is the same as the screen width (400h) and the destination offset is the same as the source block width (1 14h): BitBLT Offset Register (DROO) = 01140400h The Pattern ROP Register does not need to be programmed since there is no pattern involved. Neither the Foreground Color nor Background Color Register has to be programmed since there is no color expansion. The BitBLT Control Register contains the following bit fields: ROP = Source Copy = 0CCh INC_Y = 1 (Top to Bottom) INC_X = 1 (Left to Right) Source Data = Variable Data=0 Source Depth = Source is Color = 0 Pattern Depth = Don't Care = 0 Background = Don't Care = 0 BitBLT = Screen --> Screen = 00 1FFFFFh Off-Screen Memory 0C5867h Line 52h 0C5754h faa L- L Dest __| Ar | oco000n 0C0336h 920538h Line 3 ource QC0227h . Line 2 0CO114h 000000h 0C0113h : oe | Line 1 0C0000h Destination ( Differential Pitch BitBLT Data Transfer Revision 1.2 65540 / 545 MZ 2094116 0011900 b82Pattern Seed = Don't Care = 000 BitBLT Control Register (DR04) =003CCh Since the BitBLT will be beginning in the ULC of the source rectangle, the start address for the source datais calculated as: (30h * 400h) + 25h = OC025h BitBLT Source Register (DRO5) = OC025h Similarly, the ULC of the destination register calcu- lated as (Number of scan lines * Bytes per scan line): 300h * 400h = OCO000h BitBLT Destination Register (DRO6) = OCO000h As in the previous example the Command Register must be written to begin the BitBLT. This register contains the size of the current BitBLT which must be written for all BitBLT operations: Lines per Block = 52h Bytes per line = 114h (Current example 8bpp) Command Register (DRO7) = 005201 14h System-to-Screen BitBLTs When performing a system-to-screen BitBLT the source rotation information is passed in the BitBLT Source Address and Source Offset registers. The 2 LSbits of the Source Address register indicate the alignment. For example if the system data resides at system address 0413456h then the processor pointer should be set to 0413454h (doubleword aligned) and the Source address register is written with xxxxx2h. When the end of the scan line is reached (the number of bytes programmed in the Command Register have been written) any remaining bytes in the last doubleword written to the 65545 are discarded. The 2 LSbits of the Source Offset Register are then added to the 2 LSbits of the Source Address Register to determine the starting byte alignment for the first doubleword of the next scanline. This process is continued until all scanlines are completed. The most common case will be a doubleword aligned bitmap in system memory in which case the 2 Lbits of the Source Address Register are zero. It is also common for bitmaps to be stored with each scanline doubleword aligned (Source Offset Register = xxxxxOh). Once the Command Register is written and the BitBLT operation has begun the 65545 will wait for data to be sent to its memory address space. Any write to a valid 65545 memory address, either in the VGA space or linear address space if enabled, Functional Description will be recognized as BitBLT source data and will be routed to the correct address by the BitBLT engine. This enabies the programmer to set up a destination pointer into the video address window (doubleword aligned) and simply perform a REP MOVSD. Any unused data in the last word/doubleword write will be discarded by the BitBLT Engine. For system-to-screen monochrome (font) expansions the data is handled on a scanline by scanline basis. As with the system-to-screen BitBLT with ROP, this type of transfer uses the 2 LSbits of the source address register to determine the beginning byte index into the first doubleword. On subsequent scanlines the source offset register is added to the current scanline byte index to determine the indexing for the start of the next scan line. Monochrome data is taken from bit 7 through bit 0, byte 0 through 3 and expanded left to right in video memory (NOTE: monochrome source only supports left to night operation). At the end of the first scanline any remaining data in the active doubleword is flushed and the byte pointer for the starting byte in the next doubleword (for the next scanline) is calculated by adding 2 LSbits of the source offset to the starting byte position in the previous scanline. Monochrome expansion then continues bit 7 through 0 incre- menting byte (after byte 3 bit 0 a new doubleword begins at byte 0: bit 7) until the scanline is complete. Note that the number of bytes programmed into the Command register references the number of expanded bytes written; not the number of bytes to be expanded. Revision 1.2 175 65540 / 545 mM 20946116 0011901 515CnirsS. Functional Description Revision 1.2 176 65540 / 545 ME 2098116 0011902 455Functional Description Hardware Cursor (65545 only ) The 65545 supports four types of cursors: 32x32 x2bpp (and/xor) 64x64 x2bpp (and/xor) 64x64 x2bpp (4-color) 128x128 x Ibpp (2-color) The first two hardware cursor types indicated as 'and/xor' above follow the MS Windows AND/XOR cursor data plane structure which provides for two colors plus transparent! (background color) and inverted (background color inverted). The last two types in the list above are also referred to as Pop-Ups because they are typically used to implement pop-up menu capabilities. Hardware cursor / pop-up data is stored in display memory, allowing multiple cursor values to be stored and selected rapidly. The two or four colors specified by the values in the hardware cursor data arrays are stored in on-chip registers as high- color (5-6-5) values independent of the on-chip color lookup tables (i.e., Attribute Controller and VGA Color Palette). The hardware cursor can overlay either graphics or video data on a pixel by pixel basis. It may be positioned anywhere within screen resolutions up to 2048x2048 pixels. 64x64 and/xor' cursors may also be optionally doubled in size to 128 pixels either horizontally and/or vertically by pixel replication. Hardware cursor screen position, type, color, and base address of the cursor data array in display memory may be controlled via the 32-bit 'DR' extension registers. Hardware Cursor Programming Once the 32-bit extension registers are enabled (XRO3[1]=1), the cursor registers (DRO8-DROC) may be accessed. DRO8 controls the cursor type and X/Y zoom (H/V pixel replication). It also enables the hardware cursor to appear on the screen. DRO9 and DROA specify up to four 16-bit RGB (5-6-5) cursor color values. DROB specifies the cursor position on screen in X-Y coordinates (number of pixels from the left and top edges of the addressable portion of the display). DROC specifies the address in display memory where the cursor data array is stored. A 10- bit base address may be specified allowing cursor data patterns to be stored in any of 1024 different locations in the maximum 1MB of display memory. Each cursor storage area takes up 1024 bytes of display memory which is exactly large enough to hold a 64x64x2 cursor pattern. Cursor Data Array Format and Layout Cursor data is stored in display memory as shown: 32x32 2bpp Cursor Offset Line PlaneOQ Planet Plane? Plane 3 000h O A7-0 X7-0 Al15-8 X15-8 004h O A23-16 X23-16 A31-24 X31-24 o08h 1 A7-0 X7-0 Al5-8 X15-8 00OCh 1 A23-16 X23-16 A31-24 X31-24 OFCh 31 A23-16 X23-16 A31-24 X31-24 64x64 2bpp Cursor / Pop-Up Offset Line PlaneO Plane1 Plane2 Plane 3 000h O A7-0 X7-0 Al5-8 X15-8 004h O A23-16 X23-16 A31-24 X31-24 O08h O A39-32 X39-32 A47-40 X47-40 00Ch 0 A55-48 X55-48 <A63-56 X63-56 010h 1 A7-0 X7-0 Al5-8 X15-8 014h 1 A23-16 X23-16 A31-24 X31-24 3FCh 63 A55-48 X55-48 A63-56 X63-56 128x128 lbpp Pop-Up Offset Line PlaneQ Plane1 Plane2 Plane3 000h O- P7-0 P15-8 P23-16 P31-24 004h O P39-32 P47-40 P55-48 P63-56 008h O P71-64 P79-72 P87-80 P95-88 00Ch O P103-96 P111-104 P119-112P127-120 010h 1 P7-0 P15-8 P23-16 P31-24 014h 1 P39-32 P47-40 P55-48 P63-56 7FCh 127 P103-96 P111-104 P119-112P127-120 A7/X7 is the left-most pixel of the cursor pattern displayed on the screen for all cursor types. Note that 32x32 cursors take up 256 bytes each (the upper 3/4 of the 1KB space allocated for each cursor storage location in display memory is unused). 128x128 cursors (pop-ups) take up 2KB each, so require A10 of the base address to be set to 0. Cursor data array elements map as follows: Ann Xnn And/XorType 4-Color Type 0 0 Color 0 Color 0 0 1 Color 1 Color 1 1 0 Transparent Color 2 1 1 Inverted Color 3 where colors 0 and 1 are defined by DRO9 and colors 2 and 3 are defined by DROA. Each pixel in 2-color (1bpp) cursors (pop-ups) may be either color 0 or color 1. Revision 1.2 177 65540 / 545 Mi 2098116 0011903 351 m=Display Memory Base Address Formation The address bits in the cursor base address register DROC are aligned so they are in the proper position corresponding to the CPU address required to write to display memory. However, there are two methods of addressing display memory, VGA-style and 'Linear Frame Buffer style, so the actual CPU address for loading a cursor data array must be constructed differently depending on the addressing method used. If VGA addressing is used, the lower 16-bits of DROC may be used as an offset into the 64KB VGA address space (starting at either OA0000h or OBOO00O0h depending on whether the VGA is set for text mode or graphics mode). DROC bits 16-19 would then be used to control the VGA's paging mechanism to set the 64KB CPU aperture into display memory to the correct location for storing the cursor pattern (see XROB, XRIO, and XR11). If linear frame buffer addressing is used, the entire 1MB of display memory can be accessed directly and the base value in DROC may be used directly as a 24-bit offset into a programmable 1MB space in system memory (specified in the Linear Addressing Base register XRO8). VGA Controller Programming In order to copy the cursor data pattern to the controller, the VGA controller must be properly programmed for 32-bit direct access to all 4 planes. Proper programming for the controller consists of putting the controller in either 'text' or graphics' mode and then setting the following registers as indicated: SRO04 =0Eh Sequencer Memory Mode SRO2 =0Fh Sequencer Plane Mask GR05 =00h Graphics Controller Mode GR06 =04h (text mode) Graphics Controller Misc =05h (gr mode} Graphics Controller Misc XROB=x5h Paging Control This sets up the VGA controller to allow 32-bit direct access to all 4 planes of all 1MB of display memory in a linear fashion. It also sets the VGA memory aperture to a 64KB space at 0A0000h independent of initial graphics or text mode settings. Copying Cursor Data to Display Memory Once the base address for the cursor data pattern in display memory has been determined and the VGA has been properly programmed, the cursor data pattern may be copied from system memory to display memory. The following program sequence shows an example of one method which may be used: es:edi = display memory base address for cursor ds:si = address of AND array in system memory ds:bx = address of XOR array in system memory MOV AL, [SI+1] MOV AH, [BX+1] SHL FAX, 16 MOV AL, [STI] MOV AH, [BX] STOSD Setting the Cursor Position, Type, and Base Address Following storage of the cursor data array in display memory, the location of the cursor in display memory is set via the Cursor Base Address register (DROC) and the X-Y coordinates for positioning the cursor are written to the Cursor Position Register (DROB). The cursor type and X/Y zoom (H/V pixel replication) factors are then set and the cursor enabled via the Cursor Control Register (DRO8). To update the cursor position, a 32-bit write (or two 16-bit writes) are performed to the Cursor Position Register (DROB). This new position will take effect on the next frame (synchronized to VSync). When the cursor changes shape, it should normally be disabled, reprogrammed as described above, and then re-enabled. Alternately, a new shape may be stored in a different location in display memory, the cursor screen XY location updated (via DROB), then the new cursor selected as the active cursor (by reprogramming the base register DROC). Cursor base register changes are also synchronized to VSync to avoid glitching of the cursor on the display. Revision 1.2 178 65540 / 545 MM 20598116 00119504 ecsFlat Panel Timing Flat Panel Timing Overview A number of extension registers in the 65540 / 545 control the panel interface, including the functions of the interface pins and the timing sequences produced for compatibility with various types of panels. Some key registers of interest for panel interfacing are: XRIC H Panel Size (# of characters 1) XR68 V Panel Size (# of scan lines 1) bits 0-7 (XR65[1]=Vsize bit-8, XR65(6]=bit-9) XR4F Panel Format 2 (Bits/pixel,M/LP function) XR50 Panel Format 1 (FRC,dither,clkdiv, VAM) XR51 Display Type (Panel type,cik/LP control) XR53_ Panel Format 3 (FRC opt,pixel packing) XR54 Panel Interface (FLM/LP Control) XRSE M(ACDCLK) Control XR6F Frame Buffer Control This section summarizes the function of the various fields of the above registers as they pertain to panel interfacing. Detailed timing diagrams are shown for output of data and control sequences to a variety of panel types. The 65540 / 545 highly configurable controllers can interface to virtually all existing monochrome LCD, EL, and Plasma panels and all color LCD STN and TFT panels. The panel types supported are: Single panel-Single drive (SS) Monochrome 1 pixel/clock, 8 bits/pixel 2 pixels/clock, 8 bits/pixel 4 pixels/clock, 4 bits/pixel 8 pixels/clock, 2 bit/pixel 16 pixels/clock, 1 bit/pixel Dual panel-Doubledrive (DD) Monochrome 8 pixels/clock, 1 bit/pixel 16 pixels/clock, 1 bit/pixel Single panel-Single drive (SS) Color TFT 1 pixel/clock, 16 bit/pixel 5-6-5 RGB 1 pixel/clock, 24 bit/pixel 8-8-8 RGB 2 pixels/clock, 12 bit/pixel 4-4-4 RGB Single panel-Single drive (SS) Color STN 2 2/3 pixels/clock, 3 bit/pixel 1-1-1 RGB 5 1/3 pixels/clock, 3 bit/pixel 1-1-1 RGB Dual panel-Doubledrive (DD) Color STN 2 2/3 pixels/clock, 3 bit/pixel 1-1-1 RGB 5 1/3 pixels/clock, 3 bit/pixel 1-1-1 RGB Panel Size The horizontal panel size register (XR1C) is an 8-bit register programmed with panel width (minus one) in units of 8-pixel characters (e.g., a 640x480 panel is 80 characters wide so XRIC would be programmed with 79 decimal). The vertical panel size register is programmed with the panel height (minus one) in scan lines (independent of single or dual panel type). The programmed value is 10 bits in size with the 8 Isbs in XR68 and the overflow in XR65 bits 1 and 6. The maximum panel resolution supported is 2048 x 1024. Panel Type The panel type (PT) is determined by XR51 bits 1-0: 00 Single panel-Single drive (SS) 11 Dualpanel-Doubledrive(DD) For DD panels, XR6F bit-O (Frame Buffer Enable) and/or bit-1 (Frame Accelerator Enable) must also be set (either external or embedded may be used). TFT Panel Data Width XR50 bit-7 controls output width for TFT panels: 0 16-bit color TFT panel interface (565 RGB) 1 24-bit color TFT panel interface (888 RGB) Revision 1.2 179 65540 / 545 ME 2096116 0011905 165Display Quality Settings Frame Rate Control (FRC The 65540 / 545 provides 2 and 16 level FRC to generate multiple gray / color levels. FRC selection is determined by XR50 bits 1-0: 00 NoFRC 01 16-frame FRC (color or mono STN panels) 10 2-frame FRC (color TFT or mono panels) Three options are provided for FRC control: FRC option 1 (XR53[2]) (always set to 1) FRC option 2 (XR53[3]) (always set to 1) FRC option 3 (XR53[6]) (for 2-frame FRC only): 0 FRC data changes every frame 1 FRC data changes every other frame A setting of 0 typically results in better display quality, but panels with an internal 'M' signal typically recommend this bit be set to 1 for longer panel life. XR6E is also provided for FRC polynomial control. The values of the 'm' and 'n' parameters are typically set by trial and error (recommended settings are given elsewhere in this manuals for selected panels as derived by Chips and Technologies). Dither The 65540 / 545 also provides Dither capability to generate multiple gray / color levels. Ditherselection is determined by XR50 bits 3-2: 00 NoDither 01 Enable Dither for 256-color modes only 10 Enable Dither for all modes M Signal Timing Register XR5E (M/ACDCLK Control) is provided to control the timing of the M (sometimes called ACDCLEK) signal. XRS5E bit-7 selects between two types of timing control: 0 Use XRSE bits 0-6 to determine M signal timing (bits 0-6 are programmed with the number of HSYNCs between phase changes minus 2) 1 M phase changes every frame if the frame buffer is used, otherwise the phase changes every other frame XR4F bit-6 controls the M pin output. If set, the M pin will output flat panel BLANK# / Display Enable (DE) instead of the normal M signal (and XR5E will be ignored). Flat Panel Timing Gray / Color Levels Gray / color levels are selected via XR4F bits 2-0 (somewhat misleading called "Bits Per Pixel): No FRC # of msbs Used Gray/ Gray / Color to Generate Color Levels with Gray/ColorLevels Levels Dithering 001 1 2 5 010 2 4 13 011 3 8 29 100 4 16 61 101 5 32 125 110 6 64 253 111 8 256 n/a 2-Frame FRC (Color TFT or Monochrome Panels) #ofmsbs Used Gray/ Gray/ Color to Generate Color Levels with Gray/ColorLevels Levels Dithering 010 1 9 011 2 5 25 100 3 15 57 101 4 31 121 16-Frame FRC (Color or Monochrome STN Panels) # of msbs Used Gray/ Gray / Color to Generate Color Levels with Gray/ColorLevels Levels Dithering 001 ] 5 010 2 4 13 011 3 8 29 100 4 16 61 The setting programmed into XR4F bits 0-2 above determines how many most-significant color-bits / pixel are used to generate flat panel video data. In general, 8 bits of monochrome data or 8 bits/color of RGB color data enter the flat panel logic for every dot clock. Not all of these bits, however, are used to generate output colors / gray scales, depending on the type of panel used, graphics / text mode, and the gray-scaling algorithm chosen (the actual number of bits used is indicated in the table above). Also note that settings which achieve higher gray / color levels may not necessarily produce acceptable display quality on some (or any) currently available panels. This document contains recommended settings for various popular panels that Chips & Technologies has found to produce acceptable results with those panels. Customers may modify these settings to achieve a better match with their requirements. Revision 1.2 180 65540 / 545 mi 620948116 0011906 OTOCHiFS. Pixels Per Shift Clock The 65540 / 545 can be programmed to output 1, 2, 4, 8, or 16 pixels per shift clock. This is achieved by programming the frequency ratio between the dot clock and the shift clock. The shift clock divide (CD) is set by XR5O bits 6-4. For monochrome Flat Panel Timing The number of bits per pixel is determined as follows: ibpp: Bits/Pixel=000 or 001 or 16-Frame FRC or 2-Frame FRC with Bits/Pixel=010 panels, the valid settings are: 2bpp: Not lbpp and CD=011 (8 Pixels/Clock) Pixels P Pixels P. 4bpp: Not lbpp and CD=010 (4 Pixels/Clock) ixels Per ixels Per . Shift ShiftClock Shift Clock BOPP a eee a aT Pe tC Clock withoutFrm Acc with Frm Acc ot [bpp and CD=000 (1 Pixels/Clock) 000 = Dotclk 2 ValidColor TFT panel shift clock divide settings are: 001) Delk/2 2 4 Pixels O10 Delk/4 4 8 er TFT TFT BO-n" "GO-n" "RO-n" 011 Dclk/8 8 16 : 100 6 hift Output Output Panel Delk/1 16 n/a Clock Width Format Outputs Outputs Outputs Pixels 8-Bit Valid 16-Bit Valid 000 1 16 =5-6-5 PO-4 P5-10 P11-15 Per Shift Panel Outputs Panel Outputs 001 2 4 eee rae Pe Fi6-23 Clock Interface (8-bit) Interface (16-bit) aa ~ ~ - 1 Sbpp P8-15 8bpp P8-15 P4-7 Pi2-15 P20-23 2 4bpp P8-15 (8-11 Ist) 8bpp PO-15 For 2 pixels/shift clock, the first pixel output is on 4 2bpp _P8-15 (8-9 lst) 4bpp PO-15 PO-3, 8-11, and 16-19. 8 bpp P1,3,5,... (1 Ist) 2bpp PO-15 16 n/a n/a lbpp PO-15 For Color STN, valid shift clock divide settings are: The pixel on the lowest numbered output pin is Pixels Per Clock _ Pixels Per Clock always the first pixel output (the pixel shown first on without with the left side of the screen). For example, for 8 pixels FrameAcceleration FrameAcceleration per clock, ibpp on an 8-bit interface, P1 is the first 000 SS or DP Panels DD Panels Only pixel, P3 is the second, etc. For 16 pixels per clock, 001 3 4 {bpp on a 16-bit interface, PO is the first pixel, P1 is 010 4 n/a the second, etc. For 4 pixels per clock, 2bpp on an 8-bit interface, P8-9 is the first pixel, P10-11 is the second, etc. For Color STN data, pixel output sequences are controlled by the 'Color STN Pixel Packing bits (XR53[5-4]) described on the following page ait Dit I6bix Sin Ibis K_ISo Eg may be selected ag S-Bit Pack EB Pink: 1 9 1 1 2 4 8 Pack, or 'Extended 4-Bit Pack sometimes referred CD: 000 001 000 000 O01 O10 O11 to in this document as 3bP, {bP and XtOP au _ cases in the above table can use 3-Bit Pack or 4-Bit OT Bn Ben BSn - eon ea eon Pack. Extended 4-Bit Pack is only used for the P2 | B2n| Bon | BSn | - | G2n [G4n+i/G6n+1 single case of 2 pixels per shift clock without frame P3 | B3n |_B7n | B6n | - | G3n |G5n+1/G7n+1 acceleration. ixel Packing is not used for P4 | B4n [B4n+1|_ B7n | GOnt |GOn+1|G4n+2)/G6n+2 EL/Pliasma, Monochrome DD, or Color TFT panels ee Bon Bont! ean Cont intl GSnt2 ints so the pixel packing bits should be set to 00 for all in Nn: n n Th Nt N: P7 B7n_|B7n+!| G4n | G3nt |G3n+1]G5n+3}G7n+3 panels excep tcolor STN. P8 GOn | G4n | G5n | GOn | G4n } G6n |G6n+4 Shift Clock Divide P9 Gln | G5n | G6n | Gln | G5Sn |_G7n |G7n+4 ivi CTD) bi ; Pio | Gon | Gn | Gin | Gan | Gon (Goat Gons3 dhe above clock divide (CD") bits (XR50 bits a Pit. | G3n | Gin | R3n | G3n | Gin |G7n+1/G7n4s affect both shift clock and data out. XR51([3] (Shift P12 | Gan [Gnel] R4n | G4n [G4n+1]G6n+2/Gon+6 Clock Divide or SD) may be set so that only the shift P13 | G5n |G5n41| R5n | G5n |G5n+1|G7n+2|G7n+6 clock (and not the video data) is further divided by P14 | Gn |G6nt+1| R6n | Gn |G6n+1}G6n+3|Gont7 two beyond the setting of XR50 bits 6-4. This has PIS |_G7n |G7n+1| R7n | G7n [G7n+1]G7n+3|G7n+7 the effect of causing a new pixel to be output on P16 | ROn | R4n [ ~ = = every clock edge (i.e., both rising and falling) in- P17 | Rin| R5n |] - - - - - stead of just every falling clock edge (the first pixel et Ren Ren - - - - - output on every scan line will be on the rising edge). n n - - - - - P20 | R4n [R4n+]] - - - ~ - Extended 4-Bit Pack for Color STN panels requires P21 | RSn /R5nt+i} - - - ~ that the SD bit (XR51[3]) be set to i In all other P22 | R6n [R6n+t] - - - - - cases in the Color STN table above, either setting P23. | R7n jR7n+1] - - - - - may be used. + For information only, not recommended for panel connections Revision 1.2 181 65540 / 545 MH 2098116 0011907? 137Color STN Pixel Packing (Pixel Output Order) For color STN panes, pixel packing must be selected via XR53 bits 5-4: Packing CDSettings Allowable 00 3-Bit Pack SS: 000, 001, or 010 DD: 000, 001 (010 w/o FA) SS: 000, 001, or 010 DD: 000, 001 (010 w/o FA) 11 Ext'd 4-Bit Pack SS: 001 (8bit panels only) These settings are valid for color STN panels only (these bits must be set to 00 for monochrome and color TFT panels). 01 4-Bit Pack Pixel output order for 3-Bit Pack STN-SS panels withoutframeacceleration: CD=000 (Ip/clk) CD=001 (2p/clk) CD=010 (4p/clk) ShfCik Edge Shift Clock Edge Shift Clock Edge Ast 2nd 3rd 4th = Ast 2nd 3rd 4th = Ist 2nd 3rd 4th PO - 7 7 Pi [RI]R2]R3|.. [RIJR31R5|... [RITR5|R9] ... P2 |G1]G2}G3] .... |G1}G3]G5].... |Gi]Gs}G9] ... P3 [B1|B2/B3|.... [B1}B3|B5|..._ | B1|B5|B9| ... P0- -~ - - PS - - EK R2/R4/R6|.. [R2]R6]RI10 ... PO - - - G2}G4|G6|... | G2|G61GI0 ... Py - B2|B4/B6]... |B2|B6|Bid ... PE - | - - = 7 PO = = KH - - - R3/R7 R11 ... PIO - - - - - - G3|G7|G1] ... Pll - - - - oe B3| B7 (Bill ... PI2- - - - = = = = = PI3 - - - - - - R4/RSIRIQ Pi4- - ~ = - G4/G8|G22 ... PIS - - - - - - B4| B8|B1Q ... 4b Pack, CD=001 Ext'd 4b Pack, CD=001 Shift Clock Edge Shift Clock Edge Ist 2nd 3rd 4th Ist 2nd 3rd 4th Sth 6th 7th PO 7 Pl P2 P3 P4 P5 P6 P7 The pixel sequence for 3-bit Pack repeats with either 1, 2, or 4 pixels every shift clock edge depending on the setting of the clock divide (CD) field. The pixel sequence for 4-bit Pack repeats with 8 pixels every 3 shift clock edges. The sequence for Extended 4-Bit Pack repeats with 16 pixels every 6 shift clock edges. Extended 4-bit Pack is used only for 8-bit color STN-SS panels. It is not used for color STN DD panels or for 16-bit color STN interfaces. Flat Panel Timing Pixel output order for 4-Bit Pack 8-bit STN DD panels: Shift Clock Edge Ast 2nd 3rd 4th R2]G3|B4_. The pixel sequence repeats with 8 pixels (4 for each of the upper and lower panels) every 3 shift clock edges. Clock divide must be set to 000 with Frame Acceleration and 001 without Frame Acceleration. Pixel output order for 16-bit STN panels (4bit Pack): STN-SS Panels STN-DD Panels Shift Clock Edge Shift Clock Edge Ast 2nd 3rd 4th Ist 2nd 3rd 4th PO R1{G6|B11 Upper: __ P1 {Gi PO [RI] B3| Gol... P2 {BI Pi |G1/R4|B}... P3 [R2 P2 [B1|G4/R7L... P4 |G2 P3) [R21 B4/G71... RO Be Pgs |G2)R5|B7I... p7 (1G PO [B2/G5/R8 |... ps |B3 P10 [R3|B5| G81... po srg Pll |G3{R6[B8)... P10 |G4 Lower:__ __ Pll |B4 P4 [Ri] B3| G6... P12 |R5 P5 G1] R41 B6]... P13 |G5 Po =[ Bi} G4/R7L... P14 [BS | P7 | R2|B4| G7... PIS |R6 P12 |G2/R5/ B71... P13 | B2}G5/R8 1... Pi4 [R3/B5|G8I... P15 |G3]R6[B8]... For STN-SS panels the pixel sequence repeats with 16 pixels every 3 shift clock edges (5-1/3 pixels per shift clock edge). Clock divide must be set to 010. For STN-DD panels the pixel sequence repeats with 16 pixels (8 for each of the upper and lower panels) every 3 shift clock edges (2-2/3 pixels per shift clock edge per panel). Clock divide must be set to 001 with Frame Acceleration and 010 without Frame Acceleration. Revision 1.2 65540 / 545 M@@ 2096116 0011908 573Output Signal Timing LP Signal Timing LP output polarity is controlled by XR54([6] (O=positive, l=negative). Setting XR4F bit-7, however, causes the LP pin to output flat panel BLANK#/ DE instead of the normal LP signal (and all other LP timing control parameters will be ignored). Some panels (e.g., Plasma and EL) require LP to be active during vertical blank time. XR51[7] may be set to enable this. Otherwise LP pulses are not generated during vertical blank. FLM Output Signal Timing FLM signal output polarity is controlled by XR54[7] (O=positive, 1=negative). BLANK#/ DE Output Signal Timing The polarity of the BLANK#/ DE output (if selected for output on M, LP, or FLM as indicated above) may be controlled by XR54[0] (O=positive, l=negative). XR54[1] selects whether BLANK# / DE outputs both H and V (0) or just H (1). XRS51[2] selects whether BLANK#/ DE is generated from CRT Blank or Flat Panel Blank. SHFCLK Output Signal Timing XR51[5] (Shift Clock Mask or SM) may be set to force the shift clock output low outside the display enableinterval. Flat Panel Timing Pixel Timing Diagrams Pixel output timing sequences are shown for the following panel configurations: 1) SS Monochrome Plasma/EL Single Panel-Single Drive (Panel Type = 00) Plasma/EL Panel 2 pixels/shift clock, 4 bits/pixel (CD = 001) 2) DD Monochrome LCD Dual Panel-Double Drive (Panel Type = 11) MonochromeLCD Panel 8 pixels/shiftclk, 1bit/pixel, CD =011 (010 with FB) 16 pixels/shiftclk, 1 bit/pixel, CD = 100 (011 with FB) 3) SS_Color TFT LCD Single Panel-Single Drive (Panel Type = 00) Color TFT LCD Panel 4/5/6/8 bits/color/pixel (12/16/18/24 bits total) 1 pixel/shift clock, 16-bit 5-6-5 RGB, CD=000 1 pixel/shift clock, 24-bit 8-8-8 RGB, CD=000 2 pixels/shift clock, 24-bit 4-4-4 RGB, CD=001 4) SS Color STN LCD Single Panel-Single Drive (Panel Type = 00) Color STN LCD Panel 1 bit/color/pixel (3 bits total) 1-1-1 RGB 1 pixel/shiftclk (3bit), CD=000 2 pixels/shiftclk (6bit), CD=001 2-2/3 pixels/shift clock (8bit), CD=010 5-1/3 pixels/shift clock (8bit), CD=010, SD=1 5-1/3 pixels/shift clock (16bit), CD=010 5) DD Color STN LCD Dual Panel-Dual Drive (Panel Type = 11) Color STN LCD Panel All timings = 1 bit/color/pixel (3 bits total) RGB 2-2/3 pixels/shift clock (8-bit), CD=001 5-1/3 pixels/shift clock (16-bit), CD=010 Revision 1.2 65540 / 545 ME 2098116 0011909 40TCRIPPS Flat Panel Timing Lp \_/ \_/ IVS BLANK# Sf NINN SHFCLK PULAU SUL UL... JUL SU. + 320 Clks /H >| 320 Clks /H >| + 320 Clks /H | FLM \ y / P8-15 (1,1)...640,1) | (1,2)...(640,2) _____________ 480 Data Transfer Cycles / YV _______________>| SHFCLK e e (EL +) L a ; C8 -1 -1 -1 -1 4 4, -1 -1 2 2 2 2 4, 4, -8 -8 y -8 8 4, 4, -8 -8 -1 -1 -1 -1 ZL A -1 -1 ESAS y 6 SLI LS (Plasma) A JL P Ce SX SX re P10 SX Ss Le Tee, LD 2 2 4, 2 -2 4 4 ~2 ~2 P14 (2,1) (4,1) (638,1) (640,1) -4 4 Yj -4 ~4 4 4 4 -4 -8 -8 a -8 -8 Lf -8 -8 + EL panels use the rising edge of SHFCLK to clock in panel data, so the SHFCLK output from the 65540 / 545 must be inverted prior to driving the panel ( Panel Timing - Monochrome 16-Gray-Level EL/Plasma 8-Bit Interface > Revision 1.2 184 65540 / 545 MB 20948116 0011910 52]LAIrS Flat Panel Timing Panel Output Timing - 640 x 480 Monochrome DD 8-Bit (1 Bit/ Pixel, 8 Pixels/ Shift Clock) MT LP \ / \ /f \ /f \ f BLANK# / \ / \ LI / \ sHrceK JU UL JUL JUL S$... JUL JUU$ f~ 160 Clks/H > it 160 Clks /H > 160 Clks/H (640 x 480) (640 x 480) (640 x 480) FLM \ PO-7 (1,1)...(640,1) (1,2)...(640,2) (1,240)...(640,240) 1,241)...(640,241 (1,242)...(640,242) (1,480)...(640,480) |}______________ 240 Data Transfer Cycles / V _-- (640 x 480) Panel OutputPixel Order-640x480 (NoOFAYDCLK JUINIUITUIIUIIUIUIAL UU (SHECLE x 8) SUT SUPA SULLA JULIA APL (FA) DCLK (SHECLK x 4) SHFCLK J LS LS F LS LS fe es (UD3) PO XG XD X03.) C7. XK y (UD2) P1 XD XG) X34. X38 XK , (UD1) P2 X BD YX GD YX Cs Xe (UDO) P3 7X (36.1) X40.) X (LD3) P4 (A GB.2ADX CTA y (LD2) P5 7X4 2ADX 638,24 X_ 7 Z (LD1) P6 7X C52ADX (39.2407 (LD0) P7 X24) X24 XK 7X (63624 DX 404K FA=Frame Accelerator (Imbedded or External) ( Panel Timing - Monochrome LCD DD 8-Bit Interface Revision 1.2 185 65540 / 545 MB 2094116 00115911 445CRir>S Flat Panel Timing Panel Output Timing - 1024x768 Monochrome DD 16-Bit (1 Bit / Pixel, 16 Pixels / Shift Clock) Ml LP \ / \ /f \ \ f BLANK# / \ / \ fi / \ SHFCLK JUULASJUUL.JUU LULL. FUL. 256 Clks /H 256 Clks / H 256 Clks / H (1024 x 768) (1024 x 768) (1024 x 768) FLM \ (,)...(1024,1) (,2)...024,2) | - (1,384)...(1024,384) | PO-15 | (1,385)..(1024,385) _ (1,386)...(1024,386), (1,768)...(1024,768) }+_____________ 384 Data Transfer Cycles / V (1024 x 768) Pixel Output Pixel Order- 1024x768 (No FA) DCLK JUIN (SHECLK 3 16) SU SUT LN ss (SIFCLK x8) UO U$e (FA) DCLK ( Ope rd SHFCLK _J~ SO LT fT (UD7) PO _xX (cD) X_GD T0538) (UD6) P1 _xX (2.1) xT . __Oro384y (UD5) P2_xX GD XA) C 0 101,384 (UD4) P3_xX GI) <_a21) ib . ora 384) (UD3) P4_X GD xT 0X 003384) (UD2) P5 __X GD XE, X<_ 01384) (UD1) P6_X 71D <_5,1) 4 1015,384 (UDO) P7 _X @D <6 0 38) (LD7) P8 _xX (1,385) X= G7385) X00 768) (LD6) P9 _X (2,385) <3) XX _010,768) (LDS) P10 _X (3,385) <_(11,385)_ 7 7 ___0T,768)_ (LD4) Pll X (4,385) <_12,385)_ 7, 6X 768) (LD3) P12 _X 6,385) X71137385) Xorg 78) (LD2) P13 __X (6,385) X_14,385) Kur 768) (LD1) P14 __X (7,385) 7157385) <_U01s 768) (LDO) P15 _X (8,385) x 16385) (X06 768) (016,768) FA =Frame Accelerator (Embedded or External) ( Panel Timing - Monochrome LCD DD 16-Bit Interface > Revision 1.2 186 65540 / 545 MB 2098116 0011912 3T4CAair> Flat Panel Timing pax [| [LJ TLPLE LP Ld suck _ | | _[ |_ ee ee PO X_BOO) X Bi) X k BO(O) k B2(0) k Pl X Bod) X Bid) X Xx BO) X B2(1) xX P2 X_BO@) X B12) X k BO(2) k B2(2) k P3 X_ BOG) X BiG) X k B1(0) k B3(0) X P4 X_BOd) X Bi4) X x B1(1) X B3(1) kK P5 X_G0) X_G1(0)_ X x Bi(2) X B3(2) k P6 X God) X Gld) X x G0(0) X G2(0) x P7 k_GO2) X G12) X X GOQ) X G2) x P8 X_G0G3) X G1G) x k G0) k G2(2) k P9 k_G0(4)_X Gi(4) x x G1(0) k G3(0) x P10 X_GOG) X Gi(5) X X G1Q) x G3() x Pll X_ ROO) X_ Ri) X X GIQ) X G3(2) X Pi2 Xx ROG) X Rid) X x ROO) k R2(0) k P13 X_ RO@) X_RI@) X k ROG) X R20) k P14 X_ROG) X_RIG) X k R1(0) X R3(0) k P15 k_ROM) X RIG) X k R1@) k R3() k CD: 000 (1 Pixel / Clock) 001 (2 Pixels / Clock) FRC: 10 (2 Frame) 10 (2-Frame) Bits / Pixel: 110 (6 bits/pixel) 011 G bits/pixel) Pixel Format: 5-6-5 RGB 2-3-3 RGB DataWidth: 16-Bit 7 16-Bit f ft Panels with 9 or 12-bit data interfaces would use this setting and only connect to the msbs of each color ( Panel Timing - Color LCD TFT 9/12/16-Bit Interface > Revision 1.2 187 65540 / 545 Mi 2096116 0033913 230Lrr> Flat Panel Timing PO k_BOO) X Bl) X k BO(0) k B2(0) k Pl X_ BOG) X Bid) X k Bod) X B20) k P2 X_BO@) X Bi) k k BO) X B2Q) x P3 k_BoG3) X BIG) k k BO(3) X B2(3) k P4 k_BOG) X_Bi(4)_ } k B1(0) k B3(0) k P5 k_BOG) X BiG) X X B1Q) X B3Q) k P6 k_ BO) X BiG) X k B12) k B32) k P7 k_BO7) X Bi) X k B1(3) k B3(3) k P8 k__GO(O) X G10) x k G00) k G2(0) k P9 X_GOd) X Gidl) X x G0Q) k G2(1) k P10 k_GO@) X_ G12) X x G02) k G2(2) k Pll X_GO3) X GiG) X x G0@) k G2(3) k P12 k_GO(4) X G14) X x G1(0) k G3(0) X P13 X_GOG) X G1G) X X G10) k G3(1) X P14 X_GO6) X GIO) X k G1(2) x G3(2) k P15 k_ GO) X GIG) X k G13) x G3(3) x P16 k_ROW) X_R1O) X k RO(O) x R2(0) k P17 X_ROG) X_RICG) X x ROG) k R24) x P18 X_RO2) X RIC) X k ROQ) k R2(2) k P19 X_ ROG) X_ RIG) X k ROG) k R2(3) k P20 k_RO) X_RI4) X k R1(0) k R3(0) k P21 X_ROG) X_RIG) X X R1d) X R30) x P22 -X ROG) XY RIG) X X R1Q) X R3(2) X P23 X_ROM) X RIM) X k RIG) k R33) K CD: 000 (1 Pixel / Clock) 001 (2 Pixels / Clock) FRC: 00 (no FRC) 10 (2-Frame) Bits / Pixel: 111(8bits/pixel) 100/101 (4 or 5 bits/pixel) Pixel Format: 8-8-8 RGB 4-4-4 RGB DataWidth: 24-Bit + 24-Bit + t Panels with 18-bit data interfaces would use this setting and only connect to the msbs of each color ( Panel Timing - Color LCD TFT 18/24-Bit Interface > Revision 1.2 188 65540 / 545 M@ 20594116 0031914 177peek FLO LL ALLALeLLLLL Flat Panel Timing meuke TfL SHFCLKU ~ 1) fF (Pin 70) Y L_| SHFCLKL [ q PY ;)SCt (Pin 81) yds t Po X Rl X Gl ) ce | Bo X__~&BI XY R12 Pi X Bl X R2 X R7 X G7 X G12 XY B12 p2 X G2 X B2 X B77. YX R8 X R13 XY G13 P3 X R3 X G3 XY cs X B8 X__B13 XY R14 p4 X B3 X R4 X Co | G9 X_Gi4 XY B14 ps X G4 X B4 X Bo X R10. X R15 X_ G15 P6 X RS X Gs YX Gio X Blo. _X__BI5 Xi RI6 P7 X BS X R6 XY Ri YX Gli -X__-Gi6 XY B16 PT: 00 (SS Panel) CD: 010 (5-1/3 Pixels / Clock) 16 Pixels are FRC: 01 (16-Frame) transferred Pixel Packing: 11 (Extended 4-Bit Pack) every 16 dot clocks Bits / Pixel: 100 (4 bits / pixel) (6 shift clock edges) Frame Buffer/ Acceleration: Disabled/ Disabled ( Panel Timing - Color LCD STN 8-Bit (Extended 4-Bit Pack) Interface > Revision 1.2 189 65540 / 545 M 2098116 0011915 003Flat Panel Timing SHFCLK (IDCLK/2) PO Pl P2 P3 P4 P5 P6 P7 P8 P9 P10 Pil P12 P13 P14 P15 r__| ~ | we | ww vy | w_ X RI X G6 X Bi X Ri7 -X G22 XY B27 X Gl X B6 YX Riz X Gi7__X__B22 X__R28 X Bi X R7 XX Gi2 X B17 X__-R23 X__G28 X R2 X G7 XY _Bi2 X Rigs X G23 X B28 X G2 X B7 ) a | Gis X B23 YX R29 X B2 X R8 X G3 X Bis X R24 G29 X R3 X G8 YX Bis_ Xx R19 YX G24 X__B29 X G3 X B8 X R44 X Gi9_X_=&B24 YX R30 X B3 X R9 X Gia X B19 -X__ R25 X G30 X R4 X G9 X Bia X R20. X G25 X__B30 X G4 X B9 YX Ris X G20. -X__B25 YX R31 X B4 X_RIO X Gis X B20. YX R26 X_G3l X R5 X Gio YX Bis X R21 -X_ G26 X31 X G5 X Bio XC RI6 CX G21 -X_~&B26 X_R32 X B5 X Rli X Gis X B21. X R27 X_G32 X R6 X Gili =X Bie X R22. X_ G27 XY B32 PT: 00 (SS Panel) CD: 010 (5-1/3 Pixels / Clock) FRC: 01 (16-Frame) Pixel Packing: 01 (4-Bit Pack) Bits / Pixel: 100 (4 bits / pixel) Frame Buffer/ Acceleration: Disabled/Disabled ( Panel Pixel Timing - Color LCD STN 16-Bit (4-Bit Pack) Interface > Revision 1.2 190 mM 2094116 0011916 TUT 65540 / 545rete Be Geaberesieens . LAPS Flat Panel Timing pik [| L_f| LJ LJ LJ LEJ LEf Lo [ SHFCLK (IDCLK) _| v | | v | v | v po X RGD XY G21) YX BG.) XRG) X G61) X Pl Y Gd) Y BOD X CD) X_GG6,1) XB) X P2_X Ba.) X RGD X G(4,1) XY BG) XY R,1) YX P3_X RD X GG) X B(4,1) XY R61) XY GOD YX p4__ X R241) X_G@,241) X B(3,241) YX _R(5,241) X__G(6,241) XY pS __X Gd.241) Y_B,241) X R(4,241) X_GG,24 XY BG6,241) X P6 YX _BG,241) XY_RG.241) X G(4,241) XY B(5,241) X__R(7,241) XY P7__ X R@,241) XY GG,241) X B(4,241) X_ RG,241) __G(7,241) X PT: 11 (DD Panel) CD: 000 (2-2/3 Pixels / Clock) FRC: 01 (16-Frame) Bits / Pixel: 100 (4 bits/pixel) Pixel Packing: 01 (4-Bit Pack) FrameBuffer/Acceleration: Enabled/Enabled 8 Pixels (4 each for the upper and lower panels) are transferred every 4 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing - Color LCD STN-DD8-Bit (4-Bit Pack) Interface - With Frame Acceleration Revision 1.2 191 65540 / 545 MB 2098116 0011917 186Crir>. Flat Panel Timing DCLK IDCLK pck | _l . Fe fey : Po _X Rd.) X G(2,1) X B(3,1) XRG) YX G(6,1) XY Pi_X Gab) X BQ) YX RGD YX G6D X BEN X_ pP2_X Ba.) X RG,1) X G(4,1) XY BGO. X R(7,1) XY PX R@Y XY GGD YX Ba) YX RG@D XY GD YX pa X ROU,241) YX G@241) OX BG.241) ~X_ RG 241 X GO241 X_ PSX G0,241) X_BG.241) XX OR4241) ~SX_- GG.241) XiBY6.241) YX Po X Bd,241) XRG 241) XY GG241I) XX BG 24D YX RO24D OX P7_ X R241) X -GG.241) XX BY4.241) ~~ X_ RG} 241 X GO.241) XY _ PT: 11 (DD Panel) CD: 001 (2-2/3 Pixels / Clock) FRC: 01 (16-Frame) Bits / Pixel: 100 (4 bits/pixel) Pixel Packing: 01 (4-Bit Pack) FrameBuffer/Acceleration: Enabled/Disabled 8 Pixels (4 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing - Color LCD STN-DD 8-Bit (4-Bit Pack) Interface - Without Frame Acceleration Revision 1.2 192 65540 / 545 ME 2098116 0011918 81CHiFS Flat Panel Timing vprk =JLI LIU UU UU UU LU UL wak tJLI LIL ILI Lilt JU UL IU! SHFCLK | v v | POX Rd) X BG,1) X G(6,1) X ROD XX BaLD YX Pi_X Gai XY RGD YX BED YX Gon XY Raz YX p2_ X BO X G(4,1) XY R(7,1) X BOD X Gd2pD YX _ P3 YX RI) X BD XY G@D X_RGO1) XY B21) YX p4 _ X RO,241) X BG.241I) XG 6,241) X_RO.241) X_BG1241 YX P5 _ X G0,241) XY R4241) XX BG241) XX G24) XRU2,241) YX P6 _ X BC,241) XY G(4.241) XO RO.241) X_ B.241) YX GA2,241) XX P7 _ X R241) X_BG241) XX G7,241) XY RGO.241)X_B2,.241) YX Ps X GQ) X R61) X B71) X_ G00) X_ RG3.1) XX po YX B21 XY GOD YX RGD Y Bao XY Ga31 YX _ P10 X RG.) X BG,1) X G(8,1) X Rd) XX Bd3,1) XX Pll YX G@G1) X R61) X B(8,1) XY Gant X. RG4) YX _ Pi2 _ X G@.241) XY RG.241) XX B7.241) XY G0.24N YX RG3.241) YX P13 _ X BO,241) XY GG.241) XO R(B.241) XX BCO,24NX_-G3.241) XY P14 _ X RG.241) YX BG 241) YX G8.241) XY RG1,24 YX BG3,241) YX PIS _ X GG,241) XY RG241) YX B(8.241) YX GU1,24N YX RG4,241) YX PT: 11 (DD Panel) CD: 001 (5-1/3 Pixels / Clock) FRC: 01 (16-Frame) Pixel Packing: 01 (4-Bit Pack) Bits / Pixel: 100 (4 bits / pixel) Frame Buffer/ Acceleration: Enabled/ Enabled 16 Pixels (8 each for the upper and lower panels) are transferred every 8 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing-Color LCD STN-DD 16-Bit (4-BitPack) Interface - With Frame Acceleration Revision 1.2 193 65540 / 545 MH 2098116 0011919 755aReneGs Gn Ss sauce aseces CFir> Flat Panel Timing pax ILI LILI LE LLU Lu UU UL mrk JLIU LIU ULSI uU UU UU IDCLK /2 tL] | [| [| fo UL ances) wae ne | RG,1) X BG.1) XY GD a | G,1) X RG) X___B@,1) p2_ X B(1,1) X G(4,1) YX RGD p3 Xx R21) X B41) XY Ga.) pa _X R241) X B(3,241) k__G@,241) ps X G(,241) XY R(4,241) X___B6,241) P6 YX B(,241) X G(4,241) XY RC7,241) p7_ Xx R(2,241) X B(4,241) YX G24) a G2,1) X RGD XB. a | B(2,1) X G6,D XY RD P10 X RG) Y BG,1) Y GED Pll _ X GG.) X RG) Y__ BED P12 _X G(2,241) Y RG,241) YX B7,241) P13 _ X B(2,241) X G(65,241) K__R(8,241) Pi4_ X RG,241) Y B(5,241) XY _G8,241) PIs X GG,241) X R(6,241) YX B(8,241) PT: 11 (DD Panel) CD: 010 (5-1/3 Pixels / Clock) FRC: 01 (16-Frame) Pixel Packing: 01 (4-Bit Pack) Bits / Pixel: 100 (4 bits / pixel) FrameBuffer/Acceleration: Enabled/Disabled 16 Pixels (8 each for the upper and lower panels) are transferred every 16 Dot Clocks (3 Shift Clock Edges) Panel Pixel Timing-Color LCD STN-DD 16-Bit (4-Bit Pack) Interface- Without Frame Acceleration Revision 1.2 194 65540 / 545 Me 2096116 00115920 470Programming Programming and Parameters GENERAL PROGRAMMING HINTS The values presented in this section make certain assumptions about the operating environment. The flat panel clock (dot clock) is assumed to be generated by the internal clock synthesizer. The values programmed into the SmartMap control registers (XR61 and XR62) give a threshold of 3 with foreground and background shift of 3 but SmartMap is turned off. To enable it, set XR61 bit-O = I. The 65540 and 65545 provide programmability of the gray scaling algorithm by adjusting 'm and 'n' polynomial values in extended register 6E. The horizontal parameter values presented here are the minimum required for each panel type. For high resolution panels, these parameters may be changed to suit the panel size. The horizontal values equal the number of characters clocks output per line. In dual drive panels this value includes both panels. Therefore, the horizontal values are double those expected. Due to pipelining of the horizontal counters, certain sync or blank values may result in no display. Generally, the horizontal blank start must equal the display end and the blank end must equal the horizontal total. The horizontal sync start and end values have a wide range of acceptable values. The 65540 / 545 also has the versatility to program an LP delay to aid in interfacing to panels with a wide variety of timing requirements. In order to program the 65540 / 545 for simulta- neous display, two FLM signals are required. The first shorter FLM will match the normal FLM frequency as the data is displayed on the first half of the CRT display data. The second FLM will be longer to allow for the CRT blank time. The FLM delay is programmed in XR2C and should be equal to the CRT blank time FLM front porch FLM width. For flat panel types and sizes not presented here, start with the parameters for a pane] that most closely resembles the target panel. Adjust the flat panel configuration registers as needed and adjust the horizontal and vertical parameters as needed. Adaption to a non-standard panel is usually a trial and error process. These parameters are recommended by Chips and Technologies, Inc. for the 65540 / 545. They have been tested on several different flat panel displays. Customers should feel free to test other register values to improve the screen appearance or to customize the 65540 / 545 for other flat panel displays. Revision 1.2 195 65540 / 545 M@@ 20948116 0011%9e1 307C ri r> Programming EXTENSION REGISTER VALUES The 65540 / 545 controller can be programmed for a wide variety of flat panels, compensation techniques and backwards compatibility. The following pages provide the following 65540 / 545 Extension Register Value tables: Extension Table Registers Display Type Description Panels #1 Minimum Parameters for Initial Boot (Analog CRT VGA Mode) #2 Additional Parameters for Emulation Modes #3 Additional 640x480 Monochrome LCD-DD (Panel Mode Onlly).............. Epson EG-9005F-LS Citizen G6481L-FF Sharp LM64P80 Sanyo LCM-6494-24NTK Hitachi LMG5364XUFC #4 Additional 640x480 Monochrome LCD-DD (Simultaneous Mode Display) #5 Additional 640x480 Color TFT LCD (Panel Mode Only)............ccccsese Hitachi TX26D02VC2AA Sharp LQ9DO011 Toshiba LTM-09C015-1 #6 Additional 640x480 Color TFT LCD (Simultaneous Mode Display) #7 ~=Additional 640x480 Color STN-SS LCD - 4-Bit Pack ooo... eee Sanyo LM-CK53-22NEZ (Panel Mode & Simultaneous Mode Display) Sanyo LCM5327-24NAK Sanyo LCM5330 #8 Additional 640x480 Color STN-SS LCD - Extended 4-Bit Pack............... Sharp LM64C031 #9 Additional 640x480 Color STN-DD LCD - 16-Bit Interface... Sharp LM64C08P (Panel & Simultaneous Mode Display) Sanyo LCM5331-22NTK Hitachi LMG9721XUFC Toshiba TLX-8062S-C3X Optrex DMF-5035 1NC-FW #10 Additional 640x480 16 Internal Gray Scale Plasma..........ccccssseseeeeerees Matsushita S804 #11 Additional 640x480 16 Internal Gray Scale EL... eee eeeeeeeeeneeenaees Sharp LJ64ZU50 Table #1 specifies the minimum Extension Register values required for the 65540 / 545 to boot to VGA Table #2 Tables #3-11 mode on an analog CRT monitor. specifies the additional Extension Register values required for emulation of EGA, CGA, MDA and Hercules backwards compatibility modes. The registers in Table #2 should be used in conjunction with the registers specified in Table #1. For registers listed in both tables, use the values in Table #2 (shown in bold text). specify the additional Extension Register values required to support various panels. The registers in Tables #3-11 should be used in conjunction with the registers specified in Table #1 (and optionally Table #2). For registers listed in more than one table, use the values in Tables #3-11 (shown in bold text). Revision 1.2 196 65540 / 545 MM 20948116 O01159e2 243Crhir> Programming Table #1- Parameters for Initial Boot Initial Boot-Up Extension Register Values for VGA Display on an Analog CRT Monitor Register Value (in Hex) Register Comments XRO2 01 CPU Interface Control 1 XRO4 Al Memory Control 1 Note 1 XRO5 00 Memory Control 2 XRO06 00 Palette Control XRO8 00 Linear Addressing Base XROB 00 CPU Paging XROC 00 Start Address Top XROD 00 Auxiliary Offset XROE 80 Text Mode Control XROF 10 Software Flags 0 Note 2 XRI1O 00 Single/Low Map XR11 00 High Map XR14 00 Emulation Mode XRI5 00 Write Protect XR16 00 Vertical Overflow XR17 00 Horizontal Overflow XRIE 00 Alternate Offset XRIF 00 Virtual EGA Switch XR24 12 Alternate Max Scanline XR25 59 Horizontal Virtual Panel Size XR28 80 Video Interface XR29 4C Half Line Compare XR2B 00 Software Flags 1 Note 2 XR30 03 Clock Divide Control (Initialize Memory Clock) XR31 6B Clock M-Divisor (Initialize Memory Clock) XR32 3C Clock N-Divisor (nitialize Memory Clock) XR33 20 Clock Control (Initialize Memory Clock) XR30 03 Clock Divide Control (Initialize Clock 2) XR31 4E Clock M-Divisor (Initialize Clock 2) XR32 59 Clock N-Divisor (Initialize Clock 2) XR33 00 Clock Control (Initialize Clock 2) XR44 10 Software Flags 2 Note 2 XR45 00 Software Flags 3 Note 2 XRS1 63 Display Type XR52 40 Power Down Control XR53 00 Panel Format 3 XR54 32 Panel Interface XRSF 06 Power Down Mode Refresh XR60 88 Blink Rate Control XR61 2E SmartMap Control XR62 07 SmartMap Shift Parameter XR63 41 SmartMap Color Mapping Control XR70 80 Setup / Disable Control XR72 24 External Device I/O Note: 1) Memory Control Register 1 is automatically re-programmed with the proper display memory configuration by the BIOS 2) The Software Flag Registers are used by the BIOS and should not be re-programmed Revision 1.2 197 65540 / 545 MH 2098116 0011923 187annsess Sass scene scenes LeaIrS Programming Table #2-Parameters for Emulation Modes Extension Register Values for CRT-Only, Panel-Only, & Simultaneous CRT / Panel Display Register Value (in Hex) Register Comments XR14 00 Emulation Mode EGA Emulation XRI5 18 Write Protect EGA Emulation Register Value (in Hex) Register Comments XR14 01 Emulation Mode CGA Emulation XR15 0D Write Protect CGA Emulation XR18 27 Alternate Horizontal Display Enable End CGA Emulation XR19 2B Alternate Horizontal Retrace Start CGA Emulation XRIA AO Alternate Horizontal Retrace End CGA Emulation XR1IB 2D Alternate Horizontal Total CGA Emulation XR1C 28 Alternate Horizontal Blanking Start CGA Emulation XR1D 10 Alternate Horizontal Blanking End CGA Emulation XRIE 14 Alternate Offset CGA Emulation XR7E 30 CGA / Hercules Color Select CGA Emulation Register Value (in Hex) Register Comments XR14 52 Emulation Mode MDA Emulation XRI15 oD Write Protect MDA Emulation XR7E OF CGA / Hercules Color Select MDA Emulation Register Value (in Hex) Register Comments XROD 02 Auxiliary Offset Hercules Emulation XR14 52 Emulation Mode Hercules Emulation XRI5 oD Write Protect Hercules Emulation XR18 59 Alternate Horizontal Display Enable End Hercules Emulation XR19 60 Alternate Horizontal Retrace Start Hercules Emulation XRIA 8F Alternate Horizontal Retrace End Hercules Emulation XRIB 6E Alternate Horizontal Total Hercules Emulation XRIC 5C Alternate Horizontal Blanking Start Hercules Emulation XR1ID 31 Alternate Horizontal Blanking End Hercules Emulation XRIE 16 Alternate Offset Hercules Emulation XR7E OF CGA / Hercules Color Select Hercules Emulation Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 198 65540 / 545 ME 2098116 0012924 O16 aProgramming Table #3-Parameters for 640x480 Monochrome LCD-DD Panels (Panel Mode Only) Extension Register Values for Epson EG9005F-LS Citizen G6481L-FF Sharp LM64P80 Sanyo LCM-6494-24NTK Hitachi LMG5364XUFC Register Value (in Hex) Register XRO06 XR19 XRIA XRIB XRIC XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XR53 XR54 XRS55 XR56 XRS7 XR58 XR59 XR5A XR5B XR5D XRS5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F Note: 1) Bold text indicates registers with values different from those shown in Table #1 02 57 19 59 4F 04 50 50 00 44 25 67 41 0c 3A Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Altermate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 2 Panel Format 1 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLEK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Register Frame Buffer Control Comments Disable Internal DAC Optimize for best display quality 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 199 M@ 2098116 0011925 TSe 65540 / 545Programming Table #4-Parameters for 640x480 Monochrome LCD-DD Panels (Simultaneous Mode Display) Extension Register Values for Epson EG9005F-LS Citizen G6481L-FF Sharp LM64P80 Sanyo LCM-6494-24NTK Hitachi LMG5364XUFC Register Value (in Hex) Register Comments XR19 55 Alternate Horizontal Sync Start XRIA 00 Alternate Horizontal Sync End XRIB 5F Alternate Horizontal Total XRIC 4F Horizontal Panel Size XR2C 21 FLM Delay XR2D 50 LP Delay (CMPR enabled) XR2E 50 LP Delay (CMPR disabled) XR2F 00 LP Width XR4F 44 Panel Format 2 XRS50 25 Panel Format 1 XR51 67 Display Type XR52 41 Power Down Control XRS53 0c Panel Format 3 XRS54 3A Panel Interface XR55 E5 Horizontal Compensation XR56 00 Horizontal Centering XR57 1B Vertical Compensation XR58 00 Vertical Centering XR59 84 Vertical Line Insertion XRS5SA 00 Vertical Line Replication XRS5B 8F Power Sequencing Delay XR5D 10 FP Diagnostic XRSE 80 M (ACDCLK) Control XR64 OB Alternate Vertical Total XR65 26 Alternate Overflow XR66 EA Alternate Vertical Sync Start XR67 0c Alternate Vertical Sync End XR68 DF Vertical Panel Size XR6C 02 Programmable Output Drive XR6E 26 Polynomial FRC Control Register Optimize For LCD XR6F 1B Frame Buffer Control Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 200 Mm 2098116 0011926 195 65540 / 545CHIE S Programming Table #5- Parameters for 640x480 Color TFT Panels (Panel Mode Only) Extension Register Values for Hitachi TX26D02VC2AA Sharp LQ9D011 (set to accommodate the DE signal) Toshiba LTM-09C015-1 Register Valne (in Hex) Register Comments XRO06 C2 Palette Control Color Reduction XR19 56 Alternate Horizontal Sync Start XRIA 13 Alternate Horizontal Sync End XRIB 5F Alternate Horizontal Total XRIC 4F Horizontal Panel Size XR2C 04 FLM Delay XR2D AFP LP Delay (CMPR enabled) XR2E 4F LP Delay (CMPR disabled) XR2F OF LP Width XR4F 44 Panel Format 1 XR50 02 Panel Format 2 XRS1 C4 Display Type XR52 41 Power Down Control XR53 0c Panel Format 3 XR54 FA Panel Interface Set to F9 for Toshiba color panels XRS55 E5 Horizontal Compensation XR56 00 Horizontal Centering XR57 1B Vertical Compensation XR58 00 Vertical Centering XR59 84 Vertical Line Insertion XRS5A 00 Vertical Line Replication XR5B 8F Power Sequencing Delay XRSD 10 FP Diagnostic XRSE 80 M(ACDCLK) Control XR64 01 Alternate Vertical Total XR65 26 Alternate Overflow XR66 DF Alternate Vertical Sync Start XR67 0c Alternate Vertical Sync End XR68 DF Vertical Panel Size XR6C 02 Programmable Output Drive XR6E BD Polynomial FRC Control Optimize for best display quality XR6F 00 Frame Buffer Control Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 201 65540 / 545 MB 2094116 0011927? 425gESS32 5252 ISTE, gTset . Lrirs Programming Table #6-Parameters for 640x480 Color TFT Panels (Simultaneous Mode Display) Extension Register Values for Hitachi TX26D02VC2AA Sharp LQ9D01 1 (set to accommodate the DE signal) Toshiba LTM-09C015-1 Register Value _(in Hex) Register Comments XRO06 co Palette Control Color Reduction XRI9 55 Alternate Horizontal Sync Start XRIA 00 Alternate Horizontal Sync End XR1B 5F Alternate Horizontal Total XRIC 4F Horizontal Panel Size XR2C 00 FLM Delay XR2D 4F LP Delay (CMPR enabled) XR2E 4F LP Delay (CMPR disabled) XR2F OF LP Width XR4F 44 Panel Format 2 XR50 02 Panel Format 1 XRS51 C4 Display Type XRS52 41 Power Down Control XR53 0c Panel Format 3 XR54 FA Panel Interface Set to F9 for Toshiba color panels XR55 ES Horizontal Compensation XR56 00 Horizontal Centering XR57 1B Vertical Compensation XR58 00 Vertical Centering XR59 84 Vertical Line Insertion XRSA 00 Vertical Line Replication XR5B 8F Power Sequencing Delay XRS5D 10 FP Diagnostic XRS5E 80 M (ACDCLK) Control XR64 0c Alternate Vertical Total XR65 26 Alternate Overflow XR66 EA Alternate Vertical Sync Start XR67 0c Alternate Vertical Sync End XR68 DF Vertical Panel Size XR6C 02 Programmable Output Drive XR6E BD Polynomial FRC Control Optimize for best display quality XR6F 00 Frame Buffer Control Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-boid text indicates additional registers (not included in Table #1) Revision 1.2 202 65540 / 545 MB 20598116 0011928 7b1onsen Re atenss Airs Programming Table #7 - Parameters for 640x480 Color STN-SS Panels with 16-Bit Interface 4-Bit Pack (Panel & Simultaneous Mode Display) Extension Register Values for Sanyo LM-CK53-22NEZ Sanyo LCM5327-24NAK Sanyo LCM5330 Register Value _(in Hex) Register Comments XRO06 C2 Palette Control CO for Simultaneous Display XR19 56 Alternate Horizontal Sync Start 55 for Simultaneous Display XRIA 19 Alternate Horizontal Sync End 00 for Simultaneous Display XRIB 59 Alternate Horizontal Total 5F for Simultaneous Display XRIC 4F Horizontal Panel Size XR2C 04 FLM Delay 22 for Simultaneous Display XR2D 5C LP Delay (CMPR enabled) 62 for Simultaneous Display XR2E 5C LP Delay (CMPR disabled) 62 for Simultaneous Display XR2F 5C LP Width 60 for Simultaneous Display XR4F 44 Panel Format 1 XR50 25 Panel Format 2 XR51 C4 Display Type XR52 41 Power Down Control XRS53 1C Panel Format 3 XRS54 3A Panel Interface XR55 E5 Horizontal Compensation XR56 00 Horizontal Centering XR57 1B Vertical Compensation XR58 00 Vertical Centering XR59 84 Vertical Line Insertion XR5A 00 Vertical Line Replication XRSB 8F Power Sequencing Delay XRSO 10 Panel Format 1 XRS5E 80 M (ACDCLEK) Control XR64 E4 Alternate Vertical Total OB for Simultaneous Display XR65 07 Alternate Overflow 26 for Simultaneous Display XR66 El Alternate Vertical Sync Start EA for Simultaneous Display XR67 02 Alternate Vertical Sync End OC for Simultaneous Display XR68 DF Vertical Panel Size XR6C 02 Programmable Output Drive XR6E 6] Polynomial FRC Control Optimize for best display quality XR6F 00 Frame Buffer Control Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 203 65540 / 545 Mm 2094116 0011929 67hProgramming Table #8 - Parameters for 640x480 Color STN-SS Panels with 8-Bit Interface (Extended 4-Bit Pack) Extension Register Values for Sharp LM64C031 Register Value (in Hex) Register XR06 XRI9 XRIA XR1B XRIC XR2C XR2D XR2E XR2F XR4F XR50 XRS51 XR52 XR53 XR54 XR55 XR56 XR57 XR58 XR59 XRSA XRS5B XR5D XRSE XR64 XR65 XR66 XR67 XR68 XR6C XRG6E XR6F C2 56 00 59 4F 02 50 50 00 44 15 6C 41 3C Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 2 Panel Format 1 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Insertion Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control Comments CO simultaneous mode 55 simultaneous mode 5F simultaneous mode 2B simultaneous mode 15 simultaneous mode 26 simultaneous mode EA simultaneous mode OC simultaneous mode Optimize for best display quality Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 204 65540 / 545 MB 2098116 00119350 317Programming Table #9 - Parameters for 640x480 Color STN-DD Panels with 16-Bit Interface with Frame Acceleration (Panel & Simultaneous Mode Display) Extension Register Values for Sharp LM64C08P Sanyo LCM5331-22NTK Hitachi LMG9721XUFC Toshiba TLX-8062S-C3X Optrex DMF-50351NC-FW Register Value (in Hex) Register XRO06 XR19 XRIA XR1B XRIC XR2C XR2D XR2E XR2F XR4F XR50 XR51 XR52 XRS53 XR54 XR55 XR56 XR57 XR58 XR59 XRSA XR5B XR5D XRS5E XR64 XR65 XR66 XR67 XR68 XR6C XR6E XR6F C2 37 19 59 4F 15 50 50 00 04 25 67 41 1C 3A Palette Control Alternate Horizontal Sync Start Alternate Horizontal Sync End Alternate Horizontal Total Horizontal Panel Size FLM Delay LP Delay (CMPR enabled) LP Delay (CMPR disabled) LP Width Panel Format 1 Panel Format 2 Display Type Power Down Control Panel Format 3 Panel Interface Horizontal Compensation Horizontal Centering Vertical Compensation Vertical Centering Vertical Line Replication Vertical Line Replication Power Sequencing Delay FP Diagnostic M (ACDCLK) Control Alternate Vertical Total Alternate Overflow Alternate Vertical Sync Start Alternate Vertical Sync End Vertical Panel Size Programmable Output Drive Polynomial FRC Control Frame Buffer Control Comments 22 for no frame acceleration OF for no frame acceleration 35 for no frame acceleration Optimize for best display quality. SF for external frame buffer with frame acceleration. 99 for external frame buffer without frame acceleration. Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 205 65540 / 545 M@@ 2098116 0011951 2cSbhHE SPST ISZ, asests Unir> Programming Table #10-Parameters for 640x480 Plasma Panels with 16 Internal Gray Levels Extension Register Values for Matsushita $804 Register Value (in Hex) Register Comments XRI19 60 Alternate Horizontal Sync Start XRIA 00 Alternate Horizontal Sync End XRIB 60 Alternate Horizontal Total XRIC 4F Horizontal Panel Size XR2C 04 FLM Delay XR2D 62 LP Delay (CMPR enabled) XR2E 6D LP Delay (CMPR disabled) XR2F 08 LP Width XR4F 04 Panel Format 1 XR50 17 Panel Format 2 XR51 C4 Display Type XR52 41 Power Down Control XR53 0c Panel Format 3 XR54 39 Panel Interface XR55 E5 Horizontal Compensation XR56 00 Horizontal Centering XR57 1B Vertical Compensation XR58 00 Vertical Centering XR59 84 Vertical Line Insertion XRS5A 00 Vertical Line Replication XR5B 8F Power Sequencing Delay XRSD 10 FP Diagnostic XRS5E 80 M (ACDCLK) Control XR64 OD Alternate Vertical Total XR65 26 Alternate Overflow XR66 E8 Alternate Vertical Sync Start XR67 0A Alternate Vertical Sync End XR68 DF Vertical Panel Size XR6C 02 Programmable Output Drive XR6E 0D Polynomial FRC Control XR6F 00 Frame Buffer Control Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Optimize for best display quality Revision 1.2 206 Me 2094116 0011932 15 65540 / 545ansnege Sas0 fosccecseses LaAirsS Programming Table # 11- Parameters for 640x480 EL Panels with 16 Internal Gray Levels Extension Register Values for Sharp LJ64ZU50 Register Value (in Hex) Register Comments XR19 52 Alternate Horizontal Sync Start XRIA 15 Alternate Horizontal Sync End XRI1B 54 Alternate Horizontal Total XRIC 4F Horizontal Panel Size XR2C 0c FLM Delay XR2D 4F LP Delay (CMPR enabled) XR2E 4E LP Delay (CMPR disabled) XR2F 81 LP Width XR4F 04 Panel Format 1 XRS5O 17 Panel Format 2 XR51 44 Display Type XR52 41 Power Down Control XR53 0c Panel Format 3 XR54 F9 Panel Interface XRS55 E5 Horizontal Compensation XR56 00 Horizontal Centering XR57 1B Vertical Compensation XR58 00 Vertical Centering XR59 84 Vertical Line Insertion XRSA 00 Vertical Line Replication XRS5B 8F Power Sequencing Delay XRS5D 10 FP Diagnostic XRSE 80 M (ACDCLK) Control XR64 FO Alternate Vertical Total XR65 07 Alternate Overflow XR66 E5 Alternate Vertical Sync Start XR67 05 Alternate Vertical Sync End XR68 DF Vertical Panel Size XR6C 02 Programmable Output Drive XR6E 9D Polynomial FRC Control Optimize for best display quality XR6F 00 Frame Buffer Control Note: 1) Bold text indicates registers with values different from those shown in Table #1 2) Non-bold text indicates additional registers (not included in Table #1) Revision 1.2 207 65540 / 545 MB 20948116 0011933 025Cries. Application Schematic Examples Application Schematic Examples This section includes schematic examples showing various 65540 / 65545 interfaces. The schematics are divided into into three main groups: 1) System Bus Interface ISA (PC/AT) Bus (16-bit) VL-Bus/ 486 CPU-Direct Local Bus (1x Clock) (32-bit) PCI Local Bus (32-bit) 2) Display Memory Interface 3) CRT/Panel/Video Interface To design a system around the 65540 or 65545, one schematic page would be selected from each of the groups above. Selection of a bus interface for the VGA controller is generally dictated by the type of bus and CPU available in the system. If performance is a concern, however, and a 386 or 486 CPU is being used, a local bus interface should be considered and linear addressing support should be implemented. Linear addressing improves performance in GUI environments such as Windows by allowing the software used to access display memory (typically the Windows Driver) to be more efficient. Clock connections are shown as part of the bus interface diagrams. A 14.31818 MHz reference crystal is shown, although if a clean source of 14.31818 MHz is available in the system, it may be input on XTALI and the crystal would then not be required. Generally, 256Kx16 DRAMs would be used for display memory, although, if desired, the memory interface may be designed to use 256Kx4's instead. 256Kx16 DRAMs come in two types: one write enable (WE#) with two CAS# inputs (one for the high byte and one for the low byte) or one CAS# input with two write enables (one for the high byte and one for the low byte). Either variety of DRAM may be used (default is to the 2-CAS variety with a programming option in the 65540/ 545 to change the memory control outputs for compatibility with either type). CHIPS' BIOS is able to detect which type is connected and program the controller accordingly. It is also possible to lay out a PCB to allow either type to be used. The memory interface diagram also shows how to interface the 6554x to CHIPS' PC-Video products to provide live video overlay capability. An interface diagram is included showing connections to a standard CRT display. Panel interfaces, however, are not as standardized (generally every panel interface is different). To show how to interface to a wide variety of commonly available panels, the interface diagram in this section shows the connections used on CHIPS' DK (Development Kit) Printed Circuit Board from the 6554x chip to connectors defined by CHIPS on that board. In the following section of this document, examples are included showing connections from those DK board connectors to a number of typical panels. The DK board connectors are used to simplify evaluation of the 6554x with various panels; a real system would not typically use the connectors shown, but would instead interface directly to the connector(s) used by the panel manufacturer. Revision 1.2 209 65540 / 545 ME 20594116 00115934 TLSApplication Schematic Examples 505-~)RESET_33 ohm S07 RESET# Tt 14,31818 Cor {XTALI (65545 Only) ALE 0.01uF 7S MHz 53-| XTALO ISABus_ _PCI Bus AEN =e 3144 ADS# <ALE> "FRAME#" MEMR# 119 Mi10# <AEN> PAR TORD# a7 W/R# <MEMR#> "IDSEL , RDY 74 LCLK (2XCLK)<IORD#> "STOP# j OWR# ie LRDY# <RDY> "TRDY# , MEMW# 734 LDEV# <IOWR#> "DEVSEL# 544 RRTN# (CRST) <MEMW#> IRDY# Use as ENABKL 53 A27 (ENABKL) , IROO Use as ACTI 30 1 426 (ACTI) 7 ; 39 A25 <IRQ> "SERR#" LA23 Use as ROMCS# if required 37 A24 <ROMCS#> "PERR#" LA22 01 A23 <LA23> "Reserved" LA2I 200 034 ee Ron ved" > eserve: LALO 1924420 65540 <ra20> Reserved AIB 197 Al9 or <LA19> "Reserved" AlT 196 Al8 <LA18> Reserved" Alb 195 Al7 6554 <LAI7> "Reserved" AIS 194 Al6 <Al6> "Reserved" Ald 193 Al5_ Bus <Al5> "Reserved" ALB 192 Al4 Interface <Al4> Reserved Al? 191 Al3 <Al13> "Reserved" All 90 [412 = Default = <A12> "Reserved" Al0 139 [411 Names <Al1> Reserved" AQ 88 Al0 Indicate <Al0> "Reserved" A8 187 A9 VL-Bus <A9> "Reserved" AT : 186198 9 or Ixfx <A8> Reserved Ab 185147 4s6cpu <A7> Reserved AS 183 A6 Direct <A6> "Reserved" "Ad 182 AS Local Bus <AS> "Reserved" AB 180 A4 <A4> "Reserved" AD 179 A3 <A3> "Reserved" RESH# 10,1 A2 <A2> "Reserved" Al a1 BE3# <RFSH#> "C/BE3#" BHE# 300 BE2# <Al> "C/BE2#" AO 43 BE1# <BHE#> "C/BE1#" Great anole pte anew SBE +5V =B3, B29. DI6 Ircult Example [21 <Reserv " " , | D30 <Reserved> "AD30" GND = Bl, B10,B31,D18 6554x ISA Bus Interface 3 D29 <Reserved> "AD29" - , . 5 D28 <Reserved> "AD28" NOTE: Additional data output drive may be enabled by programming 6 D27 <Reserved> "AD27" XR6C bit 3=0. 7 D26 <Reserved> "AD26" NOTE: The 6554x may be configured for ISA operation by connecting pin ce 8 pb <Reserved> ae 146 (AA1ASA#) to GND via a 4.7K resistor. a 7 D3 <Reserved> "AD23" NOTE: Can use external 14.31818MHz oscillator into XTALI (with XTALO 15 D22 <Reserved> "AD22" not connected) by connecting pin 150 (AAS/OC#) to GND via a 16 1D21 <Reserved> "AD21" 4.7K resistor. 1 pie <Reserved> a <Reserved> {OCS 168 15] D18 <IOCS16#> "AD18" 7WS# 30 DI? <MCS 16#> "ADI?" Dis 33 D16 <ZWS#> "ADI6" Di4 34 D15 <Di5> "ADI5" D3 35 D14 <D14> "AD14 12 36 D113 <D1i3> AD13" DTI 37 D12 <D12> "AD12" NTO 38 D11 <DI1> "ADI1" D09 40 D10 <D10> "ADI0" DOs Al D9 <D9> "ADO" DO7 44 Ds <D8> "AD8" DOG 45 D7 <D7> "ADT" DOS 46 D6 <D6> "AD6" Dod 47 D5 <D5> "ADS" Do3 48 D4 <D4> "AD4" D02 49 D3 <D3> "AD3" Dot 50 D2 <D2> "AD2" D00 51 D1 <DI> "ADI" DO <D0> "ADO" Revision 1.2 210 65540 / 545 MB 2098116 00119455 7)Application Schematic Examples : RESET# __207-SRESET# ee en en ve HEF XTAL IsABus PCIBus : . i. us aK Pw I96pinPOEP Cx#B6S/S2 rey apse il "aqxTato ZALE> _ "FRAME#" in 2 AD VL-A45 -aifigg 319 <AEN> "PAR" CPU-145 CPU-SIT MIO# VLB4d") Ma ve iq MiLO# SMEMR#> IDSEL" CPU-1i1 )}{CPU- W/R# VL-B45 Chic 27 LK)<IORD#> = ""STOP#" CPU-120 CPU-NI7.) GpucLK VL-BS63-L 74{LCLK (2XCLK) TRDY#" PU-123 )-{CPU-C3 AAR" LRDY# LRDY# <RDY> " Ps CPUS CPU Fig) RDYE WEARS LDEVE 25 Rev <IOWR#> "DEVSEL EUs To Local Bus Control Logic| vA RDYRINS 23 aN NOBKD) IRDY# A27 or ENABKL VL-B24 53 | A27 CPU-9 {CPU 456 of ACTI VE-A23_)-A28 301436 ACT) RO SERRA CPU-8 ePU-?? 2725 VL-B25 )~A54 29) 54 <ROMCS#> "PERR# CPU-7 CPU-7? Ad VL-A25 9-453 28 <LA23> "Reserved" CPU-S CPU-?? 3 = b A23 nOren C S75 A2 VL-B26 459 201 14459 <LA22> "CLK CPU4 CPU- ss ADD VL-A26 )~4 5} 200 [51 <LA2I1> "Reserved" CPU3 CPU- 55 A2I VL-B27 450 199 150 65540 aA20> "Reserved" CPU-2 CPU- 37) A20 VL-A28 A719 198 | A t9 <LAI9> s "Reserved" CPU-193 CPU-O Al9 VL-B28 Dag 197 Or aaAig> "Reserved" CPU-191 Y{CPU-04 S75 [-A29> Al8 "Reserved" PU-R5 VL-A29 9 Al7 196 Al7 <LA17> Rese (CPU-189 CPU- Al? VL-B30 195 65545 Al6> "Reserved" 183 _}<CPU-O3 Al6 }A16 < , " CPU- Al6 VL-A30)-A45 194 <Al5> Reserved U-181 CPU-09 AIS Bus 0" a" CP AIS VL-B31 "A 14 193 [444 <Al4> Reserve CPU-180_}-{CPU-R7_ A 17 VL-A31 192 Interface =, 135 "Reserved" CPU-178 CPU-S5 Al3 bA13 < F r PU-17 19) AB VL-B33 2A19 191 {415 <Al2> Reserved CPU-176 CPU- Al2 VL-A32-S55 190 Default cAlIo "Reserved" CPU-174 )-{CPU-S7 ui - pA] Names " d" C Ri? A VL-B34 Al0 189 VA10 t <A10> Reserve . CPU-172 CPU- Al0 VL-A33 09 188 Indicate <A9> "Reserved CPU-165-){CPU-S13 = -A9-VL-Bus : . CP =PULOTI A9 VL-B35 A08 187 | A8 <A8> Reserve CPU-163 CPU-O AS VL-A34 AT 186 or 1x/2x <AT> "Reserved" CPU-161 CPU-R13 AT VL-B36 185 TAT 486 CPU "Reserved" CPU-159-){CPU-O13.)-42 VL-A36-)-408 183 {AS Direct </A6> "Reserved" CPU-158 CPU-S15 A5 VL-B37 182 TAS Local Bus Ad> "Reserved" ePU1S4 CPU-O12 A04 + A4 < " * CPU-15 . 167y-Ad VL-A37 JA 93 180 |'.3 <A3> Reserved CPU-152 CPU-S AB VL-B39 495 179 V'A5 <A2> "Reserved" CPU-150_ 9 CPU-RI5_ -A5 VL-B40 aH 10 <RFESH#> "C/BE3#" CPU- 146 )-{CPU-O14 Rigg VE-Ad4-)-BE3# 21d Bay <Al>"C/BE2#" Sports 3 feeb) Beat BET 324 BEM <BHE#> "C/BEI#" CPU-115 94 CPU-JIS Brig VL-A41 Bog 43 <A> "C/BEO#" CPU-1 16 CPU-J16 . ______( BEO# " " C BEO# VL-A39 D31 1 <Reserved> "AD31 -117 CPU-K15 (D311 CPU: BS D31 VL-A20 D30 2 LD30 <Reserved> "AD30 CPU-74 CPU-BS D30 VL-B19)-559 3 lh59 <Reserved> "AD29" CPU-71 ep D29 VL-Al9 )-538 4598 <Reserved> "AD28" CPU-69 pone D28 VL-B18 557 5139 <Reserved> "AD27" CPU-67 CPU- e521 VL-Al8 56 6 | 556 <Reserved> "AD26" CPU-65 ECs D26 VL-BI7 555 T1h95 <Reserved> "AD25" CPU-63 pt D25 VL-A16 94 acy <Reserved> "AD24" CPU-61 CPU-B D24 VL-B16 13 Reserved> "AD23" Sor CPU-A6 D23 }D23 < " " CPU-5S9 _ iT Ad D23 VL-Al15 D2? 14 p22 <Reserved> "AD22 CPU-55 Ey a5-$_D22 VL-B15 553 IS Hot <Reserved> "AD21" CPU-53 a 5 D21 VL-Al4 {D200 16 D20 <Reserved> "AD20" CPU-51 = PU-AL D20 VL-B13 {D19 17 D19 <Reserved> "AD19 CPU-47 cP a5 ~_DI18 VL-B12 117 19 lH <MCS16#> "AD17" CPU-46 ne D7 VL-All) Hi6 20 1H 16 <ZWS#>""ADIO" CPU-45 alae D16 VL-BIL Yrs 33.1515 <D15> "ADI5" CPU-44 CPU- DIS VL-A09) 517 34 D14> "AD14" -42 CPU-F3 D1 D4 < . 1 CPU-41 os D13 VL-A08 YH 15 36 119 D123 "AD12" + PU-39 ere Di2 VL-BO8 14 31 1n11( Circuit ERainple Dil" CPU-38 UCD VL-A07 > Hi0 Fe [D10| 6554x VI<BAGY 486 ADIO CPU-37 CPU- Di0 VL-BOT 99 40 <)> AD9" CPU-35_{CPU-E3 2-59 VE-A06-)- R02 41 [D9 | CPU DireQP>Local AD? -PU-32 J $CPU-DI_ 03 VL-B0S 97 44{P8 Bus Ipgyiace py CPU-31 CPU-F 34 DO7 VL-A05 ) 596 45 he : AD6" CPU-29 eS D06 VL-B04 505 46 [55 <D5> "ADS" CPU-27 CPU-L DOS VL-A04 )-Ho4 47 Da <D4> "AD4" CPU-26 CPU Dod VL-B03-)- 204 ag|D4 Dae *AD3" CPU-25 ee Ms D03 VL-A02 599 49 | 55 <D2> "AD2 EU 23 YA EPUH? o2 VL-B02)-7 0; 50 |p <Di> "ADI" CPU-20 CPU-N DOI VL-A0L 500 5] <D0> "ADO" CPU-18_~}-{CPU-N2 9-599 VL-BOI> DO CPU-17 CPU-P1 11 65540 / 545 Revision 1.2Application Schematic Examples REO# le ENTE RESET# n/c 14.318 MHz H[]F-55y-] XTALI we REQ64# rXTALO ISA Bus PCI Bus n/c ACK64# ADS# <ALE> "FRAME#" M/IO# <AEN> "PAR" W/R# <MEMR#> "IDSEL" we InTBE 6 PCEAIS ILCLK (2XCLK)<IORD#> = ""STOP#" n/c INTC# PCI-B07 LRDY# <RDY> "TRDY#" nc INTD# PCI-A07_) LDEV# <IOWR#> "DEVSEL#" nfc SSE PCI-B08_) RRTN# (CRST) <MEMW#> "IRDY#" A27 (ENABKL) PRSNT1# 2244 A26 (ACTD ve PRSNT2# PCI-B42_)- SERRE 301 25 <IRQ>_"SERR#" nie Reserved PCI-B40 8 A24 <ROMCS#> "PERR#" CLK 301 A23 <LA23> "Reserved" PCI-B16 00 A22 <LA22> "CLK" 199 A2l <LA21> "Reserved" LOCK# 198 A20 <LA20> "Reserved" Spor We 197 [419 65545 <LA19> Reserved SDONE n/c 196 A18 <LA18> "Reserved" We 1951417 Bus <LAI7> "Reserved" 194 Al6 Interface <Al6> "Reserved" 193 Al5 <Al5> "Reserved" 192 |414 Defauk 49 <A 14> "Reserved" 191 Al3 Names <A13> Reserved 190 Al2 Indicate <A12> "Reserved" 189 All vepys <All> "Reserved" ez tA10 or 1x2x <ALO> Reserved AQ 486 CPU <A9> "Reserved" PCIA6 Direct <A8> "Reserved" PCLBOI Local Bus <A7> "Reserved" PCI-A6? <A6> Reserved <A5> "Reserved" <A4> "Reserved" <A3> "Reserved" <A2> "Reserved" <RFSH#> = "C/BE3#" <AlI> "C/BE2#" <BHE#> "C/BE1#" <A0> "C/BEO#" <Reserved> "AD31" <Reserved> "AD30" <Reserved> "AD29" <Reserved> "AD28" <Reserved> "AD27" <Reserved> "AD26" : <Reserved> "AD25" +12V <Reserved> "AD24" <Reserved> "AD23" _+* PCI-B01_) <Reserved> "AD22" <Reserved> "AD21" NOTE: Can use external PCI-BO3 SReserved> A 14.31818MHz PCI-BI5 | " ete PCLBI7 ADIT 19 <IOCS16#> "AD18 oscillator into PCLAI8 ADI6 20 1D17 <MCS16#> "AD17" XTALI (with PCLB22 ADIS5 33 | D16 <ZWS#> =""ADI6" XTALO not PCILA24 ADI|4 34 [DIS <DI5> "ADIS5" connected)b PCI-B28 ADI3 35,|D14 <Di4>TADIA" ey 1D13 <D13> "ADI3" connecting pin PCTA30 PCLB47)- 4012 36.119 <D12> "AD12" PCI-B34 AD11 37 150 (AA5/OC#) PCL_A35) PCI-A47_) ADIO 38 Dil <DII> "AD11" to GND viaa PCLA37 9 PCI-B48 ADO 40 D10 <D10> "AD10" 4.7K resistor. PCLB38 PCI-A49 ADOS Al D9 <D9> "ADO" PCI-A42 ADOT ag [De <D8> ADs" . . PCI-B. : <D7> "ADT" CircuitExample PCL-B46 AUG 43 1h <D6> "ADS" 65545 Interface to PCEBAO PCI-BSS A Dod a7 1D5 <D5> "ADS" PCI Local Bus PCEAS6,) $-ECEASS.2Ap03 4g [D4 <D4> ecedh PCI-BS7 PCI-B56 ADO? 49 D3 <D3> "AD3" PCI-A57 ADOL 50 + D2 <D2> "AD2" 7 PCI-B58 ADOO 51 D1 <D1i> "ADI" PCI-A58 (DO <D0> "ADO" Revision 1.2 212 65540 / 545 MB 2098116 0011937 774 aApplication Schematic Examples DRAM "C" Not Installed 16/18 / 24-Bit PC-Viceo 16 / 18 / 24-Bit TFT Panels J3 DK PCB No ACTI feature w/24-bit The following bits effect the Panel No ENABKL feature w/24-bit DRAM / PC-Video interface: Connector 26-bit VL-Bus ackress range Display Int Ext with 18 / 24-bit PC-Video Mem. FB OEB (up to 28-bit w/16-bit video) XRO4[1-0] 00 A&B A&B Opt - ol oA A Opt 10 A&C A nla 11 ---- Reserved ---- n/c XR6F[7] 0=FB in DRAMs A/B 1=FB in DRAM C XR6F[2] 0=Sym Addr (C) ves 1=Asym Addr (C) XRO5[3] 0=SymAddr(A/B) giz 32 DK PCB 1=Asym Addr(A/B) ATR? PC-Video VA Connector XRO5[4] 0=2C/1W (APB) 1=1C/2W(A/B) var XRO5[5] 0=2C/1W (C) AGe 1=1C/2W (C) LAIGS XRO5[6] PC-Video Port Enable VeGs XROS[7] 0=18-bit PC-Video VAIG2. 1=24-bit PC-Video / XR6C[4] 2x Output Drive (A/B) VBT XR6C[5]_ 2x Output Drive (C) AV B6 AVBS /VB4 65 YVB3 HSYNC |e /VB2 VSYNC Faq 4 (VRO) AAI 5 (VGO) CA9 FG (VB1) (A27)(GPIOI)ENABKL}33 (VBO) (A26)(GPIOO) ACTI (VR5-2,VG7-2,VB7-2)MCD15-0 > D15:0 Used for improving performance Ey Rasce lol ase DRAM With color DD STN panels (VR7) (CASC#) CASCH# D7 a3 dcu asek eu in simultaneous display mode (VR6) (WECL#) CASCL# D365 OcL DRAM Optional PC-Video port not available & (PCLK) (WECH#) WEC#O 100 O WE panel interface limited to 16-bit (VR1) OEC# O-+______#0 0E when DRAM "C" is used) MBD15-0 15: 65540 / 545 a 380. DAC . we RASB# D153 - ORAS nec | DRAM provides additional 512KB embedded (CASB#) CASBH# O75-F-_Qcu 7 "B frame buffer & displ (WEBL#) CASBL# O15, f-CCL prany| Optional Duier & cisplay memory (WEBL#) WEB#O-*__ WE -Q OE Circuit Example MAD15-0 D15:0 Display Memory/PC-Video Circuit (CFG8-0) AAB-0 pares . A8:0 RASA# O422--_O] RAS (CASA#) CASAH# D122-dcy 256K | DRAM Provides base 512KB embedied (WEAL#) CASAL# Os. oO CL DRAM A frame buffer & display memory (WEAH#) WEA#073s_}-C WE OEAB# 0-4 0E Revision 1.2 213 65540 / 545 MH 20946116 0011938 00 meApplication Schematic Examples J3 =DK PCB 50-Pin Connector J5 =DK PCB 26-Pin Connector 70 SHECLK SHFCLK (BLANK#) (DE) M183 BLANKA (DE) LP (BLANK#) (DE)_LP 25 TM j FLM 1 J 6 DE 178 From System Power Control Circuitry STNDBY#0O-~ (Tie high if not used) 62 eR SAFE 56D (PION (A27) ENABKL 24 Control Circuitry I2VSAFE $7353 IDVSAFE 35-15 53 (GPIOO)** (A26) ACTI | _ 8 0 ENABRL_ 33-5 _)ENABEL. To System Power Control Circuitry (Leave unconnected if not used) (P23) CA7 {34 eS (P22) CAG [Se Pi (P21) CAS fog P20 (P20) CA4 fo, P19 (P19) CA3 55 Pig (P18) CA2| 65 Pry (P17) CA1 }5G Pie (P16) CAO} ge pis P15 pia [82 Pi4 p13 [88 P13 p12 [85 Pi2 pr [84 Pll 65540 510 83 P10 or po 8S 8 P8 65545 p7 {2 Fi 76 128 P6 FlaPanel P5 76 PS VGAController = 4}25 P4 p34 P3 PLB P2 pi 22 PI po Ll PO 60 6 [38 B LZ 59 AVCC 55 Rset 1% 225% ae Ant 7 oH RSET [56] uF | 0.1{ 0.047 2002 ae HSYNC [3 (DDCICLK)VSYNC } Rset= 5.4* Rload Rload = RL* 75 Note: DDC2CLK* 5V | Digital Ground DDCDAT** RL+75 ~ For RL=75: Rset=202Q * Lb Analog Ground 15K | (MS1)ACTI**;"_T1-12 -) For RL=150: Rset=2702 (MS0) n/c {_Ji-11_ > ( 65540/545 CRT/Panel Interface Circuit Revision 1.2 214 65540 / 545 M@ 209816 00119399 Su?Panel Interface Examples Panel Interface Examples This section includes schematic examples showing how to connect the 65540 / 545 to various flat panel displays. Plasma/EL Panels Panel Panel Panel Panel Panel PanelData Gray Mfr Part Number Resolution Technology Drive Interface _ Transfer Levels Page 1) Matsushita $804 640x480 Plasma SS 8-bit 2 Pixels/Clk 16 9217 2) Sharp LJ64ZU50 640x480 EL SS 8-bit 2 Pixels/Clk 16 8218 Monochrome LCD Panels Panel Panel Panel Panel Panel PanelData Gray Mfr Part Number Resolution Technology Drive Interface Transfer Levels Page 3) Epson EG-9005F-LS 640x480 LCD DD _ 8-bit 8 Pixels/Clk 2 219 4) Citizen G6481L-FF 640x480 LCD DD _ 8-bit 8 Pixels/Clk 2 220 5) Sharp LM64P80 640x480 LCD DD _ 8-bit 8 Pixels/Clk 2 221 6) Sanyo LCM-6494-24NTK 640x480 LCD DD _ 8-bit 8 Pixels/Clk 2 222 7) Hitachi LMG5364XUFC 640x480 LCD DD _ 8-bit 8 Pixels/Clk 2 223 8) Sanyo LCM-5491-24NAK = 1024x768 LCD DD 16-bit ~- 16 Pixels/Clk 2 224 9) Epson ECM-A9071 1024x768 LCD DD 16-bit 16 Pixels/Clk 2 225 Active Color Panels Panel Panel Panel Panel PanelData Panel Mfr Part Number Resolution Technology Drive Interface Transfer Colors Page 10) Hitachi TM26D50VC2AA 640x480 TFILCD SS 9-bit 1 Pixel/Clk $12 226 11) Sharp LQ9D011 640x480 TFITLCD SS 9-bit 1 Pixel/Clk $12. 227 12) Toshiba LTM-09C015-1 640x480 TFILCD SS 9-bit 1 Pixel/Clk 512 228 13) Sharp LQ10D311 640x480 TFTLCD SS 18-bit 1Pixel/Clk 256K 229 14) Sharp LQ10DX01 1024x768 TFTLCD SS 18-bit 2 Pixels/Clk 512 230 Passive Color Panels Panel Panel Panel Panel PanelData Panel Mfr Part Number Resolution Technology Drive Interface _ Transfer _-~%Colors Page 15) Sanyo LM-CK53-22NEZ 640x480 STNLCD SS 16-bit 5-1/3Pixels/Clk 8 231 16) Sanyo LCM5327-24NAK 640x480 STNLCD SS 16-bit 5-1/3Pixels/Clk 8 232 17) Sharp LM64C031 640x480 STNLCD SS 8-bit 2-2/3Pixels/Clk 8 233 18) Kyocera KCL6448 640x480 STNLCD DD 8-bit 2-2/3Pixels/Clk 8 234 19) Hitachi LMG9720XUFC 640x480 STNLCD DD 8-bit 2-2/3Pixels/Clk 8 235 20) Sharp LM64C08P 640x480 STNLCD DD 16-bit 5-1/3Pixels/Clk 8 236 21) Sanyo LCM5331-22NTK 640x480 STNLCD DD _ = 16-bit 5-1/3Pixels/Clk 8 237 22) Hitachi LMG9721XUFC 640x480 STNLCD DD _ 16-bit 5-1/3Pixels/Clk 8 238 23) Toshiba TLX-8062S-C3X 640x480 STNLCD DD = 16-bit 5-1/3Pixels/Clk 8 239 24) Optrex DMF-50351INC-FW 640x480 STNLCD DD _ = 16-bit 5-1/3Pixels/Clk 8 240 Glossary: SS = Single Panel Single Scan DD =Dual Panel Dual Scan TFY = Thin Film Transistor (Active Matrix) STN = Super Twist Nematic (Passive Matrix) Revision 1.2 215 65540 / 545 ME 2094116 0011940 265Panel Interface Examples DEVELOPMENT KIT (DK) PRINTED CIRCUIT BOARD CONNECTOR SUMMARY =DK6554x, DK6554x_ | Mono | Mono | Mono Color Color Color | Color Color Color . Color 6554x 6554x26-Pin | 50-Pin SS DD DD TFT TFT TFTHiRes STN SIN |'STNDD STNDD Pin# Pin Name Connector Connector | 8-bit 8-bit | 16-bit 9/12/16-bit 18/24-bit -18/24-bit | 8-bit | 16-bit 8-bit / 16-bit Pixels Transferred Per Shift Clock: ~ 8 8 16 to ai 2: 228) 5-18 2-23 5-18 - UD3 UD7 BO BO BOO Ri. Ri... URI... . URI... = Ub2"* UD6 Bi Bi Boi Bi. Gl... UGI... - UGi... = UDI | UD5 B2 B2 B02 G2... Bl... UBI... . UBI... = UDO = UD4 B3 B3 B03 R3... R2.. | UR2... UR2... = LD3_ | UD3 B4 B4 B10 B3... G2... LRi... - LRI... = Lb2 UD2 GO BS Bil G4...) B2. GI... LG... - LDi |" UDi Gl B6 Bi2 RS... R3.... LBi..._LBi... = LDO UD6 G2 B7 Bi3 BS... G3... | LR2.. TR? PO ~ LD7 G3 GO G00 SHFCLKU B3... | _: UG2... Pi = LD6 G4 Gl G01 - R4.. ~_UB2... P2 ~ LD5 G5 G2 G02 - G4... UR3... P3 - LbD4 RO = B4.. "UG3... P4 LD3 Ri - R5.. - 12... PS = Lb R2 = G5. LB... P6 - LDi R3 = BS. TRS... P7 - LDO R4 ~ R6 "L63 54/61 ENABKL 4 5 ENABKLENABKLENABKL ENABKL ENABKL ENABKL ENABKL:ENABKLENABKLENABKI 70 | SHFCLK 9 13 SHFCLK SHFCLK SHFCLK SHFCLK | SHFCLK: SHFCLK SHFCLKISHFCLK SHFCLK SHFCLK! 69 M 1 7 M M M M M M M M M M 68 Lp 5 10 LP LP LP LP LP LP LP LP Lp LP 67. FLM 3 11 FLM__FLM__FLM FLM FLM FLM FLM | FLM. FLM ~~ ~FLM 68/69. DE 2 8 DE DE DE DE DE DE DE DE DE DE - "VDDSAFE 6, 8 1 - - - - - - ~ - +12VSAFE 10 3 = - = = - - ~ VEESAFE 12 3 = - - - - - ~ - - - GND 7,14, 69,12, 14, _ = = 16,18, 17,20,23,26, 20,23, 29,32,35,38, 94,36 41,44,47,50 J3 J2 [+5V] VDDSAFE| 1 | 2 |412 VSAFE GND[_1 | 2 |[DPCLK] VEESAFE 3 | 4 jReserved 3 | 4 |[BLANK#] ENABKL|_5 | 6 |GND 5 | 6 |VR7 J5 M| 7 | 8 |DE VR6 Ml 1/12 IDE GND[9 [10 |LP VRS FLM [11 [12 /|GND VR4 FLM) 3 | 4 |ENABKL SHFCLK [13 [14 |GND VR3 LP| 5 | 6 |VDDSAFE(45V) Pol 15116 |PI VR2 GND|_7 | 8 | VDDSAFE(+5V) GND! 17/18 |P2 VG7 SHFCLK| 9 | 10 |+12 VSAFE P3| 19 | 20 |GND vee UDO|_11 | 12 | VEESAFE P4| 21 | 22 |P5 VG5 upil13 144 GND GND/[23 | 24 |P6 vG4 Development P7| 25 | 26 |GND VG3 Board UD2[15 | 16 |GND (-12V TO -45V) pg ta7 128 1P9 VG2 _pC-Video UD3} 17 | 18 |GND or GND|29 [30 |P10 VB7_ Connector LDO| 19 | 20 |}|GND (4+12V TO +45V) P11] 31 | 32 |GND VE6 LD1! 21 | 22 |IGND P12] 33 | 34 |P13 VB5 GND| 35 | 36 |P14 VB4 rs 3 x OND P15[37138/GND VB3 P16| 39 | 40 |P17 VB2 \ GND(41 [42 |P18 HSYNC _-_ p19 [43 [44 |GND VSYNC DevelopmentBoard Cup - 2 bo ae Panel Connectors p23[ 49150 |GND [Reserved] Revision 1.2 216 65540 / 545 M@ 2094116 0031941 175Panel Interface Examples DK6554x PCB Connector Matsushita S804 NABKL Panel Connector GND GND CLOCK# GND HSYNC GND VSYNC GND DATA-EO DATA-E1 DATA-E2 DATA-E3 DATA-O0 DATA-O1 DATA-02 DATA-03 GND GND GND GND GND GND GND GND GND +5V +5V CBa_) +12VSAFE . 8 +12V P{ 6 +12V re 4 +12V +12V VDDSAFE (+5V) e CC. B-1 Ps 31 33 VEESAFE (+12 to +45 DISPTMG Programming Recommendations/Requirements me Accel Ena 6] 0 XR2F/2D '062h LP Delay (CMPR disa) : : Pulse Width ( 6554x Interface- Matsushita $804 (640x480 16-Gray Level Plasma Panel) > Revision 1.2 217 65540 / 545 M 2098116 0011942 031Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector Sharp LJ64ZUS0 a Panel Connector __A&__) HD. B8 GND A7 CKD IACN Ta B7 GND Accel Ena A9 V.D. BS GND LP Delay (CMPR disa LP Pulse Width LP D13 D12 Dil D10 D03 D02 DO1 we NC GND GND C1) VDDSAFE (+5V) e Bi2 VL VL (3-2) -t12VSAFE B13.) VD ( 6554x Interface- Sharp LJ64ZU50 (640x480 16-Gray Level EL Panel) Revision 1.2 218 65540 / 545 MH 2096116 0031943 175Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = n/c Epson EG-9005F-LS nic Panel Connector FR XSCL Accel Ena = XROF[1] LP YSCL DIN ~ XR54[6} LDO LD1 LD2 LD3 UDI UD3 we (_10) NC ne {__6 ) NC VSS CBI VDDSAFE (+5V) . 1 VDD 19) El FEE) +12VSAFE EO (B3_) VEESAFE (+12 to +45) 19V e735, _) VLCD ( 6554x Interface- Epson EG-9005F-LS (640x480 Monochrome LCD DD Panel) > Revision 1.2 219 65540 / 545 Me 2096116 0013944 904Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = EN Citizen G6481L-FF Panel Connector 9 ) DF Data Width 7 ) cP { 8 ) LOAD I 10 ) FRAME _ |LP Delay Disable XR2F{ 3) VSS VDDSAFE (+5V) C 33-1 > 5 DISPOFF# VDD ea) t12VSAFE +28V CB3_) VEESAFE (+12 to +45) e 1 vO VAA ( 6554x Interface - Citizen G6481L-FF (640x480 Monochrome LCD DD Panel) > Revision 1.2 220 65540 / 545 WM 2096116 0011945 440Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = n/c n/c Sharp LM64P80 Panel Connector CP2 CP1 S Oh XR54[6] DLO, DLI DL2 DL3 DUO DUI DU2 DU3 VSS CoBa_)> VDDSAFE (+5V) . 5 VDD CB3_) VEESAFE (+12 to +45) -18V C_7T_) VEE ( 6554x Interface-Sharp LM64P80 (640x480 Monochrome LCD DD Panel) > Revision 1.2 221 65540 / 545 MB 2094116 0011946 767sense sees Lar Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector n/e Sanyo LCM-6494-24NTK Panel n/c Connector M CL2 CLI FLM LDO LDI LD2 LD3 UDO UDI UD2 UD3 n/c CN1-7_) NC n/c CN2-21 ) NC n/c CN2-24 ) VO VSS VSS VSS VSS 2) VSS (THE WDDSAFE 5) eC CHEE) vob e-CN2-17-) VDD +12VSAFE Lf GND-25) DISPOFF# 23V (73-3 _)-VEESAFE (+12 to +45) e(_CN2-23) VEE ( CN2-22 _) VEE IN Pixel Delay Disable ~~ | XR2F[6] LP Delay (CMPR ena) |XR2F/2D LP Delay Pulse Width _ ( 6554x Interface-Sanyo LCM-6494-24NTK (640x480 Monochrome LCD DD Panel) > Revision 1.2 222 65540 / 545 MH 2098116 0011947 613Panel Interface Examples DK6554x PCB Connector ENABKL C + 4_-Reserved me BLANK#/DE 33-8 Mf (ACDCLK) Me Er GND | Programming Recommendations/Requirements Hitachi LMG5364XUFC Panel Connector 'FT Data Width 3) cp STN Pixel Pecking (2) LOAD C1) FRAME Disable 6} LP Delay (CMPR ena) | XR2F/2D LP Delay (CMPR disa) Pulse Width " (6) vss COTET-YDDSAFE (45) _ =) yop +12VSAFE yj, DISPOFF# (TES -VEESAFE (#12 to 245) _-23V -z ( 6554x Interface - Hitachi LMG5364XUFC (640x480 Monochrome LCD DD Panel) Revision 1.2 223 65540 / 545 MM 2098116 0011948 SSTPanel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = n/ Sanyo LCM-5491-24NAK c nic Panel Connector M CL2 ne Accel Ena CLI FLM Delay ( Pulse Width LDO LD1 LD2 LD3 LD4 LD5 LD6 LD7 UDI UD2 UD3 UD5 UD7 VSS1 VSS1 VSS2 VSS2 CaP sArE ey) C25) vp 93-2) +1 VSAFE ___ 73.3 VEESAFE (+12 to +45) +36V 28 VEE VEE ( 6554x Interface-Sanyo LCM-5491-24NAK (1024x768 LCD DD Panel) > Revision 1.2 224 65540 / 545 Mi 2094116 00319459 445bPanel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = n/c n/c Epson ECM-A9071 Panel Connector XSCL VSS LP VSS DIN LDO LD1 LD2 LD3 LD4 LD5 LD6 LD7 UDO UDI UD2 UD3 UD4 UDS UD6 UD7 vss vss vss vss (TE)-YDDSAFE 5V) ; 43) vpp (__A4__) VDD +12VSAFE I~ Ad) DISP +V VDDH + Voltage not specified in panel data sheet; contact panel manufacturer for more information. ( 6554x Interface- Epson A9071 (1024x768 LCD DD Panel) > Revision 1.2 225 65540 / 545 M@ 20946116 0011950 106Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector Hitachi TM26D50VC2AA - ENABKL nie Panel nic Connector DTMG {16 GND DCLK GND HSYNC GND VSYNC GND ena (CMPR disa) STN Pixel Packing ne Accel Ena 5 PNLIO(G5) PNLO (G4) _. 6 PNL8 (G3) TG n/c VRIi n/c VR2 n/c VR3 DOTE HREV GND GND Cie) VDDSAFE (+5V)} . 33 VDD rt 24 VDD BLC (TIE +1 YSAFE je VEE CEB VEESAFE (+12 to +45) -24V [353 vee ( 6554x Interface - Hitachi TM26D50VC2AA (640x480 512-Color TFT LCD Panel) > Revision 1.2 226 65540 / 545 me 2098116 00119551 044Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector Shap LQ9D011 ENABKL n/c Panel 3 Reserved nic Connector 13.8 BLANK#DE ENAB CN2-5 M (ACDCLK GND ne iColor Levels Data Width SHFCLEK GND LP (HS) GND FLM (vs) GND (CMPR ena) CN1-7 R2 CN1-6 R1 {_ CNI1-5 RO CN1-11 ) G2 CN1-10 ) G1 CN1-9 GO CN1-15 ) B2 CN1-14 > Bi CN1-13_) BO n/c CN2-6_) TST GND GND VDDSAFE (+5V) e C_ 33-1 CN2-1_ ) VCC CN2-2 ) VCC C32 _) +1 YSAFE ___ nyc CB3_) VEESAFE (+12 to +45) n/c ( 6554x Interface-Sharp LQ9D011 (640x480 512-Color TFT LCD Panel) > Revision 1.2 227 65540 / 545 MB 2094116 0011952 Th60Panel Interface Examples DK6554x PCB Connector Toshiba LTM-09C015-1 Panel Connector CN2-7__) ENAB _CNI-8 _) GND CNI1-1 |} NCLK CN1-2__) GND { CN1-6 _) GND {_CN1-12 ) GND ENABKL 3 Reserved 3-8 BLANK#/DE ry CNI-7_) R2 CNIS) RI CNI3 9 RO PNLIO__(G5 CNI-I3.) G2 NEO __(G4) CNI-11) Gl PNL8 (G3) eNOS co B2 Bl BO J3-15 n/c CN1-15) NC GND GND GND GND GND GND - GND CBT) VDDSAFE (+5V) e CN2-0.) VDD ( __CN2-10) VDD C2) + YSAFE __ nye C_B3_)> VEESAFE G12 to +45) n/c Programming Recommendations/Requirements ( 6554x Interface- Toshiba LTM-09C015-1 (640x480 512-Color TFT LCD Panel) > Revision 1.2 228 65540 / 545 MB 2096116 0031953 917Panel Interface Examples Connector Sharp LQ10D311 Panel Connector {_CN2-5_) ENAB CN2-4_) GND GND GND Cri) VBDSAFE (+5V) eC CN21 vcc ( CN2-2_) VCC +12VSAFE n/c C_B3_) VEESAFE (122 to +45) n/c Programming Recommendations/Requirements y/Color Levels TFT Data Width Width = XR2F[3-0] XR54[6] ( 6554x Interface-Sharp LQ10D311 (640x480 256K-Color TFT LCD Panel) > Revision 1.2 229 65540 / 545 M@ 2094116 0011954 453CAlie> Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector - E Sharp LQ10DX01 Panel Connector n/c Ni-21 ) B12 Ni-20.) B11 7 BIO c . (odd pixel blue msb) CN1-18) BO2 - CNI1-17_) BOl (odd pixel blue Isb) CN1-16) BOO c n/c CN2-8 _) TEST2 n/c CN2-7_) TEST1 GND GND GND (BaD VDDSAFE (+5V) +5V vcc vcc +12VSAFE nic CN2-15_) VCC VEESAFE (+12 to +45 n/c Use separate +12V source, not +12VSAFE (_CN2-10 ) VDD (sequenced), for panel VDD (panel VDD ev L ? CN2-11_) VDD must be active before panel VCC) + 2 CN2-12_) VDD ( 6554x Interface-Sharp LQ10DX01 (1024x768 512-Color TFT LCD Panel) Revision 1.2 230 65540 / 545 ME 20946116 0011955 795TPanel Interface Examples DK6554x Programming Recommendations/Requirements PCB Sanyo Connector LM-CK53-22NEZ = ne (LCM 5330) n/c Panel Connector M iColor Levels CL2 CcL1 FLM LDO LD1 UDI LD2 LD3 UD3 LD4 LD5 UDS LD6 LD7 UD7 we 1) NC VSS vss GND GND (Ba > VDDSAFE (+5V) e 7 VDD DISP +12VSAFE J3-2 vO +38V CB) VEESAFE (+12 to +45) e 4 VEE VEE { 6554x Interface-Sanyo LM-CK53-22NEZ (LCM 5330) (640x480 Color STN LCD Panel) > Revision 1.2 231 65540 / 545 MB 2098116 0011956 bebPanel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = we Sanyo LCM-5327-24NAK We Panel Connector M CL2 CLI FLM J3-39 LDO LD1 UDI LD2 LD3 UD3 LD4 LDS UDS LD6 LD7 UD7 VSS1 VSS1 VSS2 VSS2 CBI VDDSAFE (+5V) e 25 yop, OFF C3) C5a)H1AYSAFE ___ nyc +36V C33) VEESAFE (+12 to +45) . 38 VEE VEE ( 6554x Interface- Sanyo LCM5327-24NAK (640x480 Color STN LCD Panel) > Revision 1.2 232 65540 / 545 M@ 2098116 0011957 Sbeenue scenes Ho Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = n/c Sharp LM64C031 Panel Connector XCKL LP YD ena R2I disa) | XR2F/2E we _ 5) NC VSS VSS VSS Coe PsAFE GS) Cs) von +12VSAFE n/e C"B3_) VEESAFE (412 to +45) +32V C3) VEE ( 6554x Interface- Sharp LM64C031 (640x480 Color STN LCD Panel) Revision 1.2 233 65540 / 545 M@@ 2094116 00113958 4795LrarS> Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector ~ ENABKL n/c Kyocera KCL6448 n/c Panel Connector 18) GND ? 27 VDD 9 _) vpp +12VSAFE we $<" 7) DISP# DISP# VEESAFE (+12 to +45 nic ( 6554x Interface- Kyocera KCL6448 (640x480 Color STN-DD LCD Panel) > Revision 1.2 234 65540 / 545 WE 2098116 0011959 335Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = Hitachi LMG9720XUFC Biv (SD) Panel /Color Levels Connector C3) ck2 LP Delay Disable ena 6) VSS * 5 VDD DISPOFF# on ext +12VSAFE n/c C3) VEESAFE (+12 to +45) +27V (_7T_) VEE ( 6554x Interface - Hitachi LMG9720XUFC (640x480 Color STN-DD LCD Panel) > Revision 1.2 235 65540 / 545 MM 2096116 C011960 057eBnesen Sn ae aeeecensezce . So sess se- scae Lars Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector = n/c n/c n/c Sharp LM64C08P Panel Connector XCK LP YD LDO LD1 LD2 LD3 UDI UD3 DL4 DLS DL6 DL7 DU4 DUS DUG DU7 VSS VSS VSS VSS VSS CBI VDDSAFE (+5V) _ oNTS) vo +12VSAFE nie CN1-4) DISP CB3_) VEESAFE (+12 to +45) +25V CNi7) VEE ( 6554x Interface-Sharp LM64C08P (640x480 Color STN-DD LCD Panel) > Revision 1.2 236 65540 / 545 Mi 2094116 0011561 193Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Sanyo LCM-5331-22NTK Connector Panel ve ENABKL n/c Single Dual We Connector Connector (Panel Spec) (Prototypes) Data Width ~~ EXR50[7] Disable ena nic NC DISPOFF# VSS VSS VDD VEESAFE __+50V VEE (12 to #45) C4 EN2-287) VEE C2 DA SATE C2 -CERE) VO ( 6554x Interface-Sanyo LCM-5331-22NTK (640x480 Color STN-DD LCD Panel) > Revision 1.2 237 65540 / 545 MH 2098116 00115be SctLaIrS Panel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector mn n/c n/c Hitachi LMG9721XUFC Panel Connector = CL2 CLI FLM LD4 LD5 LD6 LD7 UDS UD6 UD7 LDO LD1 LD2 LD3 UD1 UD3 VSS VSS VSS C CNi-4 _) +12VSAFE n/c t Voltage not specified in panel data sheet; contact panel manufacturer for more information. ( 6554x Interface - Hitachi LMG9721XUFC (640x480 Color STN-DD LCD Panel) > Revision 1.2 238 65540 / 545 ME 2098116 0011963 6bbPanel Interface Examples DK6554x Programming Recommendations/Requirements PCB Connector a n/c n/c Toshiba TLX-8062S-C3X Panel Connector ~ SCP LP FP | XR54(6] LDO LD1 LD2 LD3 UDI Ub2 UD3 LD4 LDS LD6 LD7 UDS UD7 GND GND GND VDDSAFE (+5V) ef TN) (33-1?) CNi-5_) VDD Le CN1-4 DISP C33) VEESAFE (+12 to +45) +24 5V ENT) VER ( 6554x Interface- Toshiba TLX-8062S-C3X (640x480 Color STN-DD LCD Panel) > Revision 1.2 239 65540 / 545 ME 2094116 00115964 7?ToPanel Interface Examples DK6554x PCB Connector n/c n/c Optrex DMF-50351NC-FW Panel Connector CP LP FLM XR2F{6] DLO DLi DL2 DL3 DUO DUI DU2 DU3 DL4 DLS DL6 DL7 DU4 DUS DU6 DU7 VSS VSS VSS CBI) VDDSAFE (+5V) e vcc CN1-4 DISPOFF# +12VSAFE n/c t Voltage not specified in panel data sheet; contact panel manufacturer for more information. ( 6554x Interface-Optrex DMF-50351NC-FW (640x480 Color STN-DD LCD Panel) > Revision 1.2 240 65540 / 545 M@ 20948116 0011965 639Ee ectricalSpecifications CnirS BlectricalSpei Electrical Specifications 65540/545 ABSOLUTE MAXIMUM CONDITIONS Symbol Parameter Min Typ Max Units P, _PowerDissipation - - 1 WwW ~ Vec Supply Voltage Oo -05 = 70 V- V, InputVoltage -0.5 - Voct0.5 Vv S Vo OutputVoltage O5 = Vect#5 OV Top OperatingTemperature(Ambient) 25 - 85 ee Tstg _StorageTemperature - 40 ~ 125 C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions. 65540/545 NORMAL OPERATING CONDITIONS Symbol _Parameter Min Typ Max Units Voc SupplyVoltageV210%) 45 5 55 Vv Vec Supply Voltage (3.3V + 10%) 3.1 3.3 3.6 Vv T, |_AmbientTemperature 0 - 70 ee 65540/545 DAC CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise) Symbol Parameter Notes Min Typ Max | Units Vo _OutputVoltage Ios 10mA 1.5 - - Vv Io =: OutputCurrent Vo<1V @ 37.5QLoad, 21 ~ - mA Full Scale Error - - +5 % DAC toDAC Correlation ~ 1.27 - % DACLinearity +2 ~ - LSB Full Scale Settling Time - - 28 nS Rise Time 10% to 90% - - 6 nS Glitch Energy - - 200 | pVsec ComparatorSensitivity - 50 - mV Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 11/11/93 241 65540 / 545 M@@ 20946116 0013966 575Crire>. ElectricalSpecifications 65540/545 DC CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise) Symbol Parameter Notes Min Typ Max Units locpE Power Supply Current 0C,5.5V, 68 MHz, DAC on, 65540 - 180. 230 mA locpo Power Supply Current 0C,5.5V, 68 MHz, DAC off, 65540 _ 140 200 mA IKcpg -Power Supply Current 0C,3.3V, 62 MHz, DAC off, 65540 - 78 =: 132 mA Iocpg Power Supply Current 0C,5.5V, 68 MHz, DAC on, 65545 TBD TBD mA lucpo Power Supply Current 0C,5.5V, 68 MHz, DAC off, 65545 - TBD TBD mA lecpo Power Supply Current 0C,3.3V, 56 MHz, DAC off, 65545 - TBD TBD mA Igcs Power Supply Current 0C,5.5V, Standby}, 65540 - - 200 pA Igcg Power Supply Current 0C,5.5V, Standby}, 65545 - - TBD pA I, InputLeakageCurrent 100 - +100 vA Ipz OutputLeakageCurrent HighImpedance 100 - +100 uA Ipz + OutputLeakageCurrent HighImpedance 100 - +100 uA Vi _ Input Low Voltage All input pins -0.5 - 0.8 Vv Vo, OutputLow Voltage Under max load per table below (SV) - - 0.5 Vv Voy, _OutputLow Voltage Under max load per table below (3.3V) - - 0.5 Vv Voy OutputHighVoltage Under max load pertablebelow(SV) =-V,--0.5. - - Vv Voy OutputHigh Voltage Under max load per table below (3.3V) 2.4 - - Vv Vin _ Input High Voltage All pins except XTALI 2.0 | Veet0.5 Vv Vin Input High Voltage All pins except XTALI 2.0 - Veet0.5 Vv 65540/545 DC DRIVE CHARACTERISTICS (Under Normal Operating Conditions Unless Noted Otherwise) Symbol _ Parameter OutpuPins DCTestConditions Min Units Io. Output Low Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ) Vouqg=Vou, Vec=4-5V 12) mA FLM, LP, M, P0-15, SHFCLK, DO-31 Vout You Vec=45VV 8 mA ENAVEE, ENAVDD, ENABKL, ACTI Vour=Vov Voc=45V 8 mA RASA#, CASAH/L#, WEA#, PAR (65545 only) | Vouq=Vop, Vec=4-5V 4 mA -RASB#, CASBH/L#, WEB#, OEAB#, AA0-9 Voug= Voy, Vec=4-5V 4 mA RASC#, CASCH/L#, WEC#, OEC#, CA0-9 Vout Vou Voc=45VV 4 mA All other outputs VouFVov Voc=45V 2. mA Toy Ourpat gh Drive H/VSYNC, LDEV#, LRDY#, ROMCS#, IRQ) Voyy=Vorp Vec=4.5V 12) mA FLM, LP, M, P0-15, SHFCLK, DO-31 VourVYov Vec=4:5V 8 . mA ENAVEE, ENAVDD, ENABKL, ACTI Vout= vow Voc=4.5V 8 mA -RASA#, CASAH/L#, WEA#, PAR (65545 only) Voys=Vop Voc=4-5V 4. mA RASB#, CASBH/L#, WEB#, OEAB#, AAO-9 -Voy7=Vopp Vec=4-5V) 4 mA RASC#, CASCH/L#, WEC#, OEC#, CA0-9 Vout? Vor Voc=45V 4 mA Allother outputs Vour=Vow Vec=45V 2 mA Note: IOL and IOH drive listed above indicates 5V low drive and 3.3V high drive (see also XR6C) Note: {Standby power was measured using Self Refresh DRAMs with all chip inputs driven to inactive levels and outputs not connected (or connected to typical external loads). Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 242 65540 / 545 MB 2098116 0011967 40165540/545 AC TEST CONDITIONS ElectricalSpecifications (Under Normal Operating Conditions Unless Noted Otherwise) Output Output Capacitive OutpuPins LowVoltage HighVoltage Load All 12mA and 8mA outputs plus PAR for PCI bus in the 65545 Vor 2.4V 80pF All Other 4mA output pads Vor 2.4V 50pF All Other 2mA output pads Vor 24V 30pF 65540/65545 AC TIMING CHARACTERISTICS- REFERENCE CLOCK Symbol Parameter Notes Min Typ Max Units Feprp ReferenceFrequency (+100 ppm) 1 14.31818 60 MHz Terr ReferenceClock Period 1/Ferr 16.6 69.84128 1000. nS Tyy/Trgr Reference Clock Duty Cycle 25 - 75 % TREF - THI _____ Reference Clock Input __ (Reference Clock Timing > Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 243 MH 2094116 0011968 345 65540 / 545sucsees Uses susesesseccs CHIPS Electrical Specifications 65540/545 AC TIMING CHARACTERISTICS- CLOCK GENERATOR Symbol Parameter Notes Min Typ s Max Units Tc VCLK Period (SV) 68 MHz 14.7 - - nS Te VCLK Period (3.3V) 56 MHz : 17.6 - - nS Toy VCLK High Time ; oe 0.45T, - 0.55T, nS To VCLK Low Time 045T, - -0.55T, ~soS Ty MCLK Period(5V) 68 MHz 14.7 - - ns Ty MCLK Period (3.3V) 56 MHz 17.6 - - ns Ty MCLKHigh Time 0.45Ty - ___-055Ty aS Ty, MCLK Low Time O0.45Ty, - 0.55T yy ns Tap Clock Rise/ Fall - - 5 nS -MCLK Frequency for 100 ns DRAMs (5V) - 50.350 - MHz - -MCLK Frequency for 80 ns DRAMs (5V) - 56.644 - MHz MCLK Frequency for 70 ns DRAMs (5V) - 65 - MHz Tc TCH TcL - VCLK ___/ : / TMH TML MCLK ] Z f Clock Timing Note: Unless otherwise specified, specifications above apply to both SV & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 244 65540 / 545 ME 2098116 0011969 284ElectricalSpecifications 65540/545 AC TIMING CHARACTERISTICS - RESET Symbol | Parameter Notes Min Max Units Tjpp Reset Active Time from Power Stable See Note 1 5 _ mS Tors Reset Active Time from Ext. Osc. Stable See Note 2 0 - ns Tags Reset Active Time with Power Stable See Note 3 2 - mS Trsp Reset Rise Time Reset fall time is non-critical - 20 nS Tpsq _ResetActiveto Output Float Delay - 40 ns Tesy _ ConfigurationSetup Time See Note 4 20 - ns Toyp Configuration Hold Time 5 - ns Note 1: This parameter includes time for internal voltage stabilization of all sections of the chip, startup and stabilization of the internal clock synthesizer, and setting of all internal logic to a known state. Note 2: The external oscillator input is optional, it may be selected by XRO1 bit 5. Note 3: This parameter includes time for the internal clock synthesizer to reset to its default frequency and time to set all internal logic to a known state. It assumes power is stable and the internal clock synthesizer is already operating at some stable frequency. Note 4: Setup time to latch the state of the configuration bits reliably into XRO1 and XR6C is specified by this parameter. Changes in some configuration bits may take longer to stabilize inside the chip (such as internal clock synthesizer-related bits 4 and 5). It is therefore recommended that configuration bit setup time be TRES (2mS) to insure that the chip is in a completely stable state when Reset goes inactive. ees ResetwithChipOperating InitiaIlPower-UpReset andPowerStable It VCC TIPR | ' Tors 14.318 MHz (fromexternal oscillator) RESET# ConfigurationLines AA0-AA8 Bus Output Pins Reset Timing Note: Unless otherwise specified, specifications above apply to both SV & 3.3V operation & memory clock is assumed to be 683MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 245 65540 / 545 M@ 2094116 0011970 TTL65540/ 65545 AC TIMING CHARACTERISTICS-LOCAL BUS CLOCK (33 MHz) ElectricalSpecifications Symbol Parameter Notes Min : Max Units Tycp Local Bus Clock Period (33MHz) 0.1% stability at 2.0V /0.8V 30 30 ns Ticy Local Bus Clock High Time 12 - nS Ty c_ Local Bus Clock Low Time 12 - nS Ticr Local Bus Clock Rise Time - 3 ns T,cr Local Bus Clock Fall Time - 3 ns Local Bus Clock Slew Rate 1 4 V/nS Tors CPU Reset Setup Time to Local BusClock _ For 2x Clock Sync 2 - ns Tory CPU Reset Hold Time from Local Bus Clock For 2x Clock Sync 5 - ns + CCLK/LCLK ~ -------- ft. nee nnnee 1-7 ( Local Bus Clock Timing > CCLK /LCLK (2x Bus Clock Configuration) CRESETF T 65540/545 CRESET to CCLK timing should match CPU RESET to CLK2 timing of the CPU. ( Local Bus '2x' Clock Synchronization Timing Note: VL-Bus timing is compatible with VL-Bus Specification 2.0. Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 246 M@ 2096116 0011971 132 65540 / 545CHir> ElectricalSpecifications 65540/65545 AC TIMING CHARACTERISTICS-LOCAL BUS INPUT SETUP & HOLD (33 MHz) Symbol Parameter Notes Min __ Max | Units Taps Setup Time - A2-31, BEn#, M/1IO#, W/R# 7 - 2S Tass (Setup Time - ADS# 7 - oS Tpys Setup Time - D0-31 (Write) 7 - nS Tpps Setup Time- RDYRTN# 5 ns Tapy Hold Time - A2-31, BEn#, M/IO#, W/R# 2 - oS Ts Hold Time - ADS# 20 = nS Tpwy Hold Time-D0-31 (Write) 2 = | nS Tpry Hold Time-RDYRTN# 2 = nS CCLK/LCLK _/ \ / \ / \ 1g IDWS, ig... TOWH wana > D31-0(Write) xX tg PRES pig... TRH RDYRTN# x x tg TASS pig... TASH _____g! ADS# x * aEn# A312 ig TADS ig... TADH.__ oy! n#, - M/IO#, W/R# X ) a { Local Bus Input Setup & Hold Timing > Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 247 65540 / 545 M@ 2098116 0011972 879CHir> ElectricalSpecifications 65540/65545 AC TIMING CHARACTERISTICS-LOCAL BUS OUTPUT VALID (33 MHz) Symbol Parameter Notes ,C,Max, Min Max Units Tpay Bus Clock to Output Valid - DO-31 (Read) /125pF 3 18 nS Tapy Bus Clock to Output Valid - LRDY# 100pF: 3 14 ns CCLK / LCLK So \ Ff YY Toav gin ya D31-0 (Read) ValidN OK yA ValidN+1 Trove Bin max * LRDY# ValidN 4 aX ValidN+1 ( Local Bus Output Valid Timing > 65540/65545A CTIMINGCHARACTERISTICS-LOCALBUSFLOATDELA Y(33MHz) Symbol Parameter Notes C,Max Min Max Units Tpar Float Delay - DO-31 (Read) 125pF 20 nS Trpr FloatDelay-LRDY# _-(Drivenhighbeforefloating 100pF - | 30 nS CCLK/LCLK _/ \ f \ / \ ' TDAF \ D31-0(Read) ValidN |X + LRDY# ( Local Bus Output Float Delay Timing Note: Unless otherwise specified, specifications above apply to both SV & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 248 65540 / 545 Me 2094116 0011973 705ElectricalSpecifications 65540/65545 AC TIMING CHARACTERISTICS-VL-BUS LDEV# Symbol: Parameter Notes Min Typ Max Units Trpy .Addressto LDEV# change 3 - 20s nS Address Valid TLDV TLDV LDEV# >| , >| ( VL-Bus LDEV# Timing > Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 MB 2094116 0011974 4) 249 65540 / 54565540/545 AC TIMING CHARACTERISTICS - PCI] BUS FRAME ElectricalSpecifications Symbol Parameter Notes Min Max | Units Trrs FRAME# Setup to CLK 7 - ns Tews C/BE#[3:0] (Bus CMD) Setup to CLK 7 ns Tey =C/BE#[31:0] (Bus CMD) Hold from CLK 2 - ns Tprs C/BE#([3:0] (Byte Enable) Setup to CLK 7 - ns Tpgy C/BE#[3:0] (Byte Enable) Hold from CLK 2 - ns Taps AD[31:0] (Address) Setup to CLK 7 - ns Tapu AD[31:0] (Address) Hold from CLK 2 - nS Tpap ADI[31:0] (Data) Valid from CLK Read Cycles - 11 ns Tpas AD[31:0] (Data) Setup to CLK Write Cycles 7 - nS Tpap ADI[31:0] (Data) Hold from CLK 2 - ns Trzy TRDY# High Z to High from CLK - 11 nS Try, TRDY# Active fromCLK - 11 ns Triy TRDY# Inactive fromCLK - 11 ns Tpyz TRDY# High before High Z 1 1 CLK Tpz_ DEVSEL# Active from CLK 11 ns Tpty DEVSEL# Inactive from CLK il ns Tpyz 4DEVSEL# High before High Z I 1 CLK Tisc IRDY#Setup to CLK 7 - ns Tric IRDY# Hold from CLK 2 - ns Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 250 MH 2098116 0011975 565 65540 / 545CLK TERS FRAME# 4&4 TBEH C/BE#(3:0] leo Hi-Z Bus Hi-Z Turnaround ReadAD{3 1:0] Hi-Z Bus Hi-Z Turnaround WriteAD[31:0] TRDY# IRDY# DEVSEL# ( PCI Bus Frame Timing > ElectricalSpecifications Note: The above diagram shows a typical PCI bus cycle. PCI bus read cycles require a bus turn-around cycle between address output and data input on AD31:0. PCI bus write cycles do not require this bus turnaround cycle so the write data is available from the bus master immediately after address output (in clock cycle 2 instead of clock cycle 3). Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 251 = 2098116 OO1197b 414 65540 / 545Crir> Electrica] Specifications 65540/545 AC TIMING CHARACTERISTICS - PCI BUS STOP Symbol Parameter Notes Min Max _Units Ts7y STOP# High Z to High from CLK - 11 ns Toy, (STOP# Active from CLK 11 ns Top zy STOP# Inactive from CLK - 11 ns Tgyz STOP# High before High Z 1 1 | CLK CLK TSZH TSHL TSLH TSHZ STOP# HighZ i) r J i{t- ( PCI Bus Stop Timing Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 252 65540 / 545 Me 2098116 0011977 350crnir>. ElectricalSpecifications 65540/65545 AC TIMING CHARACTERISTICS - ISA BUS Symbol Parameter Notes Min Typ: Max |: Units Tcpw Command Strobe Pulse Width 6Tm - - nS TcoyR Command Strobe Hold from Ready 0 - - ns Tyxp (Command Strobe Inactive to Next Strobe 3Tm - - ns Tarp Address Setup to ALE Inactive 29 - - ns Tasc Address Setup to Command Strobe 30 - ~ ns Tics Address to IOCS16# & MEMCS16# Delay - - 2Tm | nS Tsp Read Data Setup to Ready Mem Accesses Only 25 - - ns Tppw [RDY Pulse Width Mem Accesses Only 0 - 100Tm: nS Tayc Address Hold to Command Strobe 20 - - nS Tppy Read Data Hold from Command Strobe 10 ~ - ns Tppz Read Data Tri-Stated from Command Strobe - - 30 nS Twpp Write Data Delay from Command Strobe - - 20 ns Tywpy | Write Data Hold from Command Strobe 10 - - ns Trrc RDY Low Delay from Command Strobe (+5V) Mem Accesses Only ~ - 40 ns Tatc RDY Low Delay from Command Strobe (+3.3V) Mem Accesses Only - - 55 ns RFSH#, AEN, AO0-19, BHE# ALE Command Strobe IORD#, IOWR# MEMR#,MEMW# RDY IOCS16#, MCS16# Data(Read) Data(Write) ISA Bus Timing Note: Unless otherwise specified, specifications above apply to both SV & 3.3V operation & memory clock is assumed to be 683MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 253 65540 / 545 MH 2098116 0011975 29765540/65545 AC TIMING CHARACTERISTICS - DRAM READ/ WRITE ElectricalSpecifications Symbol Parameter Notes Min Max _ Units Tpc Read/WriteCycleTime 12Tm5_ - nS Tras RAS#PulseWidth = 8Tm-5 nS Tpp RAS#Precharge 4Tm 3 - ns Topp CAS# to RAS# Precharge 4Tm -5 - nS Tosy CAS#Hold from RAS# 5Tm-2 - ns Tecp RAS#to CAS#Delay 3Tm -5 - ns Trsy RAS# Hold from CAS# 2Tm -5 = ns Top CAS#Precharge 8 Tm 5 - nS Toas CAS# Pulse Width 2Tm5 - ns Tasp Row Address Setup to RAS# Tm-5 - ns Tasc Column Address Setup to CAS# 2Tm-8 ~ nS Tray Row Address Hold from RAS# Tm2 - ns Tcoay (Column Address Hold from CAS# Tm -2 - nS Toac DataAccessTimefromCAS# XRO5[2-1]=0(3MCLKCASCycley) - 2Tm-5 nS XRO5[2-1]=1 (4MCLK CAS Cycle) - 3Tm-5: nS Trac Data Access Time from RAS# XRO5[2-1]=0 (3MCLK CAS Cycle) 5Tm-2 nS XRO05[2-1]=1 (4MCLK CAS Cycle) - 6Tm-2 nS Tps Write Data Setup to CAS# Tm-5 - ns Tpy | Write Data Hold from CAS# Tm 2 - ns Tpe (CASCycleTime 3Tm-1 | - ns Tys | WE# Setup to CAS# ~1Tm-5 = nS Tyy | WE# Hold from CAS# 2Tm5 | - ns Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 254 MM 20981346 0011975 1e3 65540 / 545siti, fttts ElectricalSpecifications ~ TRAS > < Trp ar Address (Co } TRSH _>> t TCAS y TCAH TASR WE# High Z Data ke TCAC>| Trac _ TCAC i Read High Z mene { DRAM Page Mode Read Cycle Timing > ( DRAM Page Mode Write Cycle Timing > Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary. Note: Unless otherwise specified, specifications above apply to both SV & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 255 65540 / 545 M@ 2098116 0011980 945CHirS | ElectricalSpecifications 65545 AC TIMING CHARACTERISTICS - DRAM READ/MODIFY/ WRITE Symbol Parameter Notes Min Max Units Termw RAS# Pulse Width 16Tm 5 - ons Tormw CAS#PulseWidth 6Tm 5 - | nS Tawp Col Address to WE# Delay 6Tm -8 - nS Tpwp RAS#to WE# Delay 7Tm-5 - ons Topwp CAS#PrechargetoWE#Delay . 5STm-5 - ~~ nS Togz Output Turnoff Delay from OE# - Tm nS Togw OE# Write DataDelay Tm +3 - on Tope OE#ReadDataDelay = = = XROS[1]=0(3MCLKCASCycle) = - = 2Tm-5_s nS Tope OE#ReadDataDelay XROS[1] = 1 (4 MCLK CAS Cycle) 3Tm-5 | nS Note: Read Modify Write timing for 65545 only. OE# q os TDH <_>i Data { Read){_ Write } {Read} Write /}-oH+_ ( DRAM Page Mode Read Modify Write Cycle Timing > Note: The above diagrams represent typical page mode cycles. The number of actual CAS cycles may vary. Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 256 65540 / 545 MB 2098116 0011961 6461CAirS Electrical Specifications 65540/65545 AC TIMING CHARACTERISTICS - CBR REFRESH Symbol Parameter Notes Min Typ Max Units Topp RAS#toCAS#Delay Tm = 15.4 @ 65 MHz 5Tm-5 - - nS Tosp (CAS#toRAS#Delay NormalOperation Tm5 - - Standby Mode 2Tm5 _ - ns Tras RAS# Pulse Width 5Tm = 89 ns (56 MHz) or 77 ns (65 MHz) 5Tm5 - - nS TRAS fo Ne CAS# <> Co ( CAS-Before-RAS (CBR) DRAM Refresh Cycle Timing > 65540/65545A CTIMINGCHARACTERISTICS-SELFREFRESH Symbol Parameter Notes Min Typ Max _ Units Tpass RAS# Pulse Width for Self-Refresh 1000, - | _ Bs Tgp RAS#Precharge 4Tm-3, - = ns Tpps RAS# Precharge for Self-Refresh 10Tm | - - ns Trpc RAS#toCAS#Delay is On 3Tm-5 ns Tosp CAS#to RAS# Delay NormalOperation Tm-5 - | = nS Standby Mode 2Tm-5 - | = ns Toys CAS#Hold Time OS Topy (CAS#Precharge Tm-5 - | = ns < TRP p| le TRASS pile TRPS > RAS# y y f X glRPG | | Tose ye Tcus L__ TCPN CAS# L Hy WT Dout High Z MH Mt Address ( 'Self-Refresh DRAM' Refresh Cycle Timing > Note: Upon exiting self-refresh mode, the 65540 / 65545 will perform a complete set of CBR refresh cycles before resuming normal DRAM activity. The duration of the burst refresh will equal the panel powersequencing delay, programmed in XR5B bits7-4. Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 257 65540 / 545 ME 2094116 0011582 715Cries ElectricalSpecifications 65540/545 AC TIMING CHARACTERISTICS - CRT OUTPUT TIMING Symbol Parameter : Notes Min Max __ Units Tsyn HSYNC, VSYNC delay from VCLK in - 50. son'S Tsyn HSYNC, VSYNC delay from VCLKi in (3. SV) : _ 80 ns ' Tsp VCLK in to SHFCLK delay - - 30-7 . ns- Tsp VCLK in to SHFCLK delay (3.3V) - 50s nS VCLK in i \ / TSYN HSYNC, VSYNC out y Tsp SHFCLK out f \ ( CRT Output Timing 65540/545 AC TIMING CHARACTERISTICS - PC VIDEO TIMING Symbol Parameter Notes Min Max _ Units Tpys Video Data setup to PCLK 12 - ns Tpyy Video Data hold to PCLK 0 ns PCLK Tpvs Tpvn VideoData HSYNC VSYNC ( PC Video Timing > Note: Unless otherwise specified, specifications above apply to both 5V & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 258 65540 / 545 Me 2094116 0011983 545CHiFrS ElectricalSpecifications 65540/545 AC TIMING CHARACTERISTICS - PANEL OUTPUT TIMING Symbol Parameter Notes Min Max _ Units Tpsy Panel Data Setup to SHFCLK 5 - | ns Tpy Panel Data Hold to SHFCLK : 10 - = nS Tp_y Panel Data Delay from SHFCLK 10 - ns TL25 SHFCLK Allowance Time from LP Tc - nS Tso1, LP Allowance Time from SHFCLK Tc - / ons Tgesy LM Setup Time 8 Tc - ' ons Tres} FLM Hold Time 8 Tc - es) Prof * TS2L ; TL2s sure NNO NLL Tpsu TDLY th TDH Data XXXKXXX XXX Trsv |!}Trsu FLM / : Fiat Panel Vertical Refresh S\_JSV\_/V_JIV_JIN uw _/\_/\ First Last Line Line Data Data Transfer Transfer < ~~ < < wy FLM / \ / \ / \L. (Panel Output Timing Note: Unless otherwise specified, specifications above apply to both SV & 3.3V operation & memory clock is assumed to be 68MHz. Electrical specifications contained herein are preliminary and subject to change without notice. Revision 1.2 259 65540 / 545 MB 20598116 0011964 550CHir> ElectricalSpecifications PAGE(S) INTENTIONALLY BLANK Revision 1.2 260 65540 / 545 Me 20948116 0011985 427MechanicalSpecifications MechanicalSpecifications Lead Length 0.5 +0.2 (0.020 +0.008) | Lead Pitch fp 0.50 (0.0197) - [_IT_ Lead wi com 020 +010 y COI (0.008 +0.004) _ [7TT7 * por NOCAARAAOON DORN ONDA OAN RHONA ndAnonAAaaAaAenAA 208-Pin 28.0 +0.1 (1.102 +0.004) 30.6 +0.4 (1.205 +0.016) SNE e eee Plastic Flat Pack DIMENSIONS mm (in) CHIPS Part No. and Revision F6554x R Vendor Mask Identifier XXXXXKX Bs r= = & Date Code and Country of Assembly YYww cccccc = 3 2 S=e} Lot Code (Optional) a3 LLGLLLL oa = = Clearance ee = 0.25 (0.010) cS Minimum Gg gu UG UU ee Ooo OU UO UE UU UU Ce eu ooUuU : > Height Body Size 28.0 +0.1 (1.102 +0.004) Seating Plane 4.07 (0.160) Footprint 30.6 #0.4 (1.205 +0.016) 4 Maximum Pin 1 Revision 1.2 261 65540 / 545 MH 2098116 0011986 363