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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FL7921R Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Features Description Integrated PFC and Flyback Controller The highly integrated FL7921R combines a Power Factor Correction (PFC) controller and a QuasiResonant PWM controller. Integration provides costeffect design and allows for fewer external components. Auto Recovery VDD Pin and Output Voltage OVP Critical-Mode PFC Controller Zero-Current Detection for PFC Stage Quasi-Resonant Operation for PWM Stage Internal Minimum tOFF 8 s for QR PWM Stage Internal 10 ms Soft-Start for PWM Brownout Protection High / Low Line Over-Power Compensation Auto Recovery Over-Current Protection Auto Recovery Open-Loop Protection Auto Recovery Over-Temperature Protection Adjustable Over-Temperature with external NTC through the RT pin Applications Medium to High Power LED Lighting Driver Application For PFC, FL7921R uses a controlled on-time technique to provide a regulated DC output voltage and to perform natural power factor correction. An innovative THD optimizer reduces input current distortion at zerocrossing duration to improve THD performance. The PFC function is always on regardless of the PWM stage load condition to ensure that high PF can be achieved at light load condition. For PWM, FL7921R provides several functions to enhance power system performance: valley detection, green-mode operation, high / low line over-power compensation. Protection functions include secondaryside open-loop and over-current with auto-recovery protection, external recovery triggering, adjustable overtemperature protection through the RT pin and external NTC resistor, internal over-temperature shutdown, VDD pin OVP, DET pin over-voltage for output OVP, and brown-in / out for AC input voltage UVP. All protections are auto recovery mode except PWM current sense pin open protection. The FL7921R controller is available in a 16-pin, smalloutline package (SOP). Ordering Information Part Number Protection Mode Operating Temperature Range Package Packing Method FL7921RMX Recovery -40 C to +125C 16-Pin, Small-Outline Package (SOP) Tape & Reel (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 www.fairchildsemi.com FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller October 2015 BCM Boost PFC Quasi-resonant Flyback NBOOST CCLAMP RCLAMP NP NS VO + QPFC CINF2 RINV1 NCZD CPFC_Vo RG1 - RHV RCS1 RCZD RRANGE CINF1 CCOMP RVIN1 RINV2 QPWM 1 RANGE HV 16 2 NC 15 COMP 3 INV ZCD 14 4 CSPFC VIN 13 5 CSPWM RT 12 6 OPFC FB 11 7 VDD DET 10 8 OPWM GND 9 FL7921R RG2 RRT RCS2 CRT NTC CFB VAC RVIN2 CVIN NA RDET1 CDD1 CDD2 RDET2 Figure 1. Typical Application (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Application Diagram www.fairchildsemi.com 2 COMP HV VDD 2 16 7 RANGE Multi-Vector Amp. 2.65V 2.75V RANGE OVP 2.75V 2.9V 24V Recovery S 2.5V CSPFC R Disable Function PFC Current Limit CLR Q 2.1V/1.75V Inhibit Timer 14 FB OLP Timer 50ms 11 2.25ms 28s 2R Soft-Start 10ms IZCD ZCD 10V Recovery VB 2.1V Starter DRV R Latched 3V OPFC 0.2V 4.2V FB 6 PFC Zero Current Detector Blanking Circuit 4 Q Restarter Sawtooth Generator /tON-max THD Optimizer SET 15.5V Latched or Recovery Brownout 3 0.82V NC DRV Debounce 70s 0.45V 15 Two Steps UVLO 18V/10V/7.5V UVP 2.35V INV Internal Bias OVP IHV S SET Q 8 OPWM 1 RANGE CS OVP 17.5V CSPWM Blanking Circuit 5 R PWM Current Limit Over0Power Compensation IDET Latched or Recovery tOFF-MIN (8s/37s/2.25ms) IDET Valley Detector 1st Valley tOFF Blanking (4s) S/H DET pin OVP VDD pin OVP RT Pin Prog OTP RT Pin Externally Triggering tOFF-MIN +9s Startup VB & clamp Vcomp to 1.6V Debounce Time IRT Debounce 100ms 1.2V 0.8V 100A VINV 1V/1.3V Brownout comparator 1V Internal OTP 0.5V Recovery Debounce 100ms 110s 10ms Prog. OTP / Externally Triggering 2.1V/2.45V 9 12 13 GND RT VIN Figure 2. Functional Block Diagram (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 Recovery Output Short Circuit (FB pin) Output Open-loop (FB pin) Output Over Power/ Overload (FB pin) Recovery 2.5V 10 Q Recovery VDET DET OVP DET CLR PFC RANGE Ccontrol FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Internal Block Diagram www.fairchildsemi.com 3 16 - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT-Die-Run Code T - Package Type (M=SOP) M - Manufacture Flow Code ZXYTT FL7921R TM 1 Figure 3. Marking Diagram Pin Configuration RANGE 1 16 HV COMP 2 15 NC 3 14 ZCD CSPFC 4 13 VIN CSPWM 5 12 RT OPFC 6 11 FB VDD 7 10 DET OPWM 8 9 GND INV Figure 4. Pin Configuration Pin Definitions Pin # 1 Name Description RANGE pin's impedance changes according to the VIN pin voltage level. When the input voltage RANGE detected by the VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it sets to low impedance if input voltage is at a high level. 2 COMP 3 INV Output pin of the error amplifier. It's a Trans-conductance-type error amplifier for PFC output voltage feedback. Proprietary multi-vector current is built-in to this amplifier. Therefore, the compensation for PFC voltage feedback loop allows a simple compensation circuit between this pin and GND. Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage divider and provides PFC output over- and under-voltage protections. 4 Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting CSPFC protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal threshold (0.82 V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting. 5 Input to the comparator of the PWM over-current protection and performs PWM current-mode control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch CSPWM and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, currentmode control, and high / low line over-power compensation according to the DET pin source current during PWM tON time. FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Marking Information Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 www.fairchildsemi.com 4 Pin # Name 6 OPFC 7 VDD 8 OPWM 9 GND The power ground and signal ground. DET This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for the following purposes: Producing an offset voltage to compensate the threshold voltage of PWM current limit for providing over-power compensation. The offset is generated in accordance with the input voltage when the PWM switch is on. Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley voltage switching and minimize the switching loss on the PWM switch. Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output OVP and this flat voltage is higher than 2.5 V, the controller enters auto recovery mode. 10 Description Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 15.5 V. Power supply. The threshold voltages for startup and turn-off are 18 V and 7.5 V, respectively. The startup current is less than 30 A and the operating current is lower than 10 mA. Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 17.5 V. 11 FB Feedback voltage pin. This pin is used to receive the output voltage / current level signal to determine PWM gate duty for regulating output voltage / current. The FB pin voltage can also activate open-loop, overload, and output-short circuit protection if the FB pin voltage is higher than a threshold of around 4.2 V for more than 50 ms. The input impedance of this pin is a 5 k equivalent resistance. A one-third attenuator is connected between the FB pin and the input of the CSPWM/FB comparator. 12 RT Adjustable over-temperature protection. A constant current is flowed out of the RT pin. When the RT pin voltage is lower than 0.8 V (typical), the controller stops all PFC and PWM switching operation and enters auto recovery protection mode. 13 VIN Line-voltage detection for brown-in / out protections. This pin can receive the AC input voltage level through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin's status; (ZCD) can also perform brown-in / out protection for AC input voltage UVP. 14 ZCD Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle. When the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC stage and the controller stops PFC switching. This can be achieved with an external circuit if disabling the PFC stage is desired. 15 NC No connection 16 HV High-voltage startup. HV pin is connected to the AC line voltage through a resistor 100 ktypical) for providing a high charging current to VDD capacitor. (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Pin Definitions (Continued) www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit 25 V VDD DC Supply Voltage VHV HV Pin Voltage 500 V VH OPFC, OPWM Pin Voltage -0.3 25.0 V VL Other Pins (INV, COMP, CSPFC, DET, FB, CSPWM, RT) -0.3 7.0 V Input Voltage to ZCD Pin -0.3 12.0 V VZCD PD Power Dissipation 800 mW JA Thermal Resistance (Junction-to-Air) 104 C/W JC Thermal Resistance (Junction-to-Case) 41 C/W TJ Operating Junction Temperature -40 +150 C Storage Temperature Range -55 +150 C +260 C TSTG TL ESD Lead Temperature (Soldering 10 Seconds) Human Body Model, JESD22-A114 (All Pins Except HV Pin) (3) Charged Device Model, JESD22-C101 (All Pins Except HV Pin) 5 (3) 2 kV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. 3. All pins including HV pin: CDM=0.5 kV, HBM=1 kV. (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Absolute Maximum Ratings www.fairchildsemi.com 6 VDD=15 V, TJ=-40C ~125C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 25 V VDD Section VOP Continuously Operating Voltage VDD-ON Turn-On Threshold Voltage 16.5 18.0 19.5 V VDD-PWM-OFF PWM-Off Threshold Voltage 9 10 11 V VDD-OFF Turn-Off Threshold Voltage TA=25C 6.5 7.5 8.5 V IDD-ST Startup Current VDD=VDD-ON - 0.16 V, Gate Open 20 30 A IDD-OP Operating Current VDD=15 V; OPFC, OPWM=100 kHz; CL-PFC, CL-PWM=2 nF 10 mA IDD-GREEN Green-Mode Operating Supply Current (Average) VDD=15 V, OPWM=450 Hz, CL-PWM=2 nF IDD-PWM-OFF Operating Current at PWM-Off Phase VDD=VDD-PWM-OFF - 0.5 V 5.5 mA 70 120 170 A VDD-OVP VDD Over-Voltage Protection (Auto Recovery) 23 24 25 V tVDD-OVP VDD OVP De-bounce Time 100 150 200 s IDD-LATCH CSPWM Pin Open Protection Latch-Up Holding Current VDD=7.5 V A 120 HV Startup Current Source Section VHV-MIN IHV Minimum Startup Voltage on HV Pin Supply Current Drawn from HV Pin 50 VAC=90 V (VDC=120 V), VDD=0 V 1.3 HV=500 V, VDD= VDD-OFF +1 V V mA 1 A VIN and RANGE Section VVIN-UVP Threshold Voltage for AC Input Under-Voltage Protection 0.95 1.00 1.05 V VVIN-RE-UVP Under-Voltage Protection Reset Voltage (for Startup) VVIN-UVP +0.25 V VVIN-UVP +0.30 V VVIN-UVP +0.35 V V 70 100 130 ms tVIN-UVP Under-Voltage Protection Debounce Time (No Need at Startup and Hiccup Mode) VVIN-RANGE-H High VVIN Threshold for RANGE Comparator 2.40 2.45 2.50 V VVIN-RANGE-L Low VVIN Threshold for RANGE Comparator 2.05 2.10 2.15 V 70 100 130 ms tRANGE Range Enable / Disable Debounce Time VRANGE-OL Output Low Voltage of RANGE Pin IO=1 mA 0.5 V IRANGE-OH Output High Leakage Current of RANGE Pin 200 nA 28 s tON-MAX-PFC RANGE=5 V PFC Maximum On-Time 22 25 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 www.fairchildsemi.com 7 VDD=15 V, TJ=-40C ~125C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 100 125 150 mho 2.465 2.500 2.535 V RANGE=Open 2.70 2.75 2.80 RANGE=Ground 2.60 2.65 2.70 VINVH / VREF, RANGE=Open 1.06 1.14 VINVH / VREF, RANGE=Ground 1.04 1.08 PFC Stage Voltage Error Amplifier Section (4) Gm Transconductance VREF Feedback Comparator Reference Voltage VINV-H Clamp High Feedback Voltage VRATIO VINV-L Clamp High Output Voltage Ratio (4) Clamp Low Feedback Voltage V V/V 2.35 2.45 RANGE=Open 2.25 2.90 2.95 V RANGE=Ground 2.75 2.80 50 70 90 s 0.35 0.45 0.55 V 50 70 90 s VINV-OVP Over-Voltage Protection for INV Input tINV-OVP Over-Voltage Protection Debounce Time VINV-UVP Under-Voltage Protection for INV Input tINV-UVP Under-Voltage Protection Debounce Time VINV-BO PWM and PFC Off Threshold for Brownout Protection 1.15 1.20 1.25 V VCOMP-BO Limited Voltage on COMP Pin for Brownout Protection 1.55 1.60 1.65 V VCOMP Comparator Output High Voltage 6.0 V VOZ TA=25C Zero Duty Cycle Voltage on COMP Pin Comparator Output Source Current ICOMP Comparator Output Sink Current 4.8 V 1.10 1.25 1.40 V 15 30 45 A 0.50 0.75 1.00 mA RANGE=Open, VINV=2.75 V, VCOMP=5 V, TA=25C 20 30 40 RANGE=Ground, VINV=2.65 V, VCOMP=5 V 20 VINV=2.3 V, VCOMP=1.5 V VINV=1.5 V, TA=25C A 30 40 PFC Current-Sense Section VCSPFC Threshold Voltage for Peak Current Cycle-by-Cycle Limit tPD Propagation Delay tBNK Leading-Edge Blanking Time AV CSPFC Compensation Ratio for THD VCOMP=5 V 0.82 V 110 200 ns 110 180 250 ns 0.90 0.95 1.00 V/V FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 www.fairchildsemi.com 8 VDD=15 V, TJ=-40C ~125C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 14.0 15.5 17.0 V 1.5 V PFC Output Section VZ PFC Gate Output Clamping Voltage VDD=25 V VOL PFC Gate Output Voltage Low VDD=15 V, IO=100 mA VOH PFC Gate Output Voltage High VDD=15 V, IO=100 mA 8 tR PFC Gate Output Rising Time VDD=12 V, CL=3 nF, 20~80% 30 65 100 ns tF PFC Gate Output Falling Time VDD=12 V, CL=3 nF, 80~20% 30 50 70 ns Input Threshold Voltage Rising Edge VZCD Increasing 1.9 2.1 2.3 V VZCD-HYST Threshold Voltage Hysteresis VZCD Decreasing 0.25 0.35 0.45 V VZCD-HIGH Upper Clamp Voltage IZCD=3 mA 8 10 VZCD-LOW Lower Clamp Voltage 0.40 0.65 0.90 V VZCD-SSC Starting Source Current Threshold Voltage 1.3 1.4 1.5 V 200 ns V PFC Zero-Current Detection Section VZCD tDELAY tRESTART-PFC Maximum Delay from ZCD to Output Turn-On VCOMP=5 V, fS=60 kHz 50 V Restart Time 300 500 700 s Inhibit Time (Maximum Switching VCOMP=5 V Frequency Limit) 1.5 2.5 3.5 s VZCD-DIS PFC Enable / Disable Function Threshold Voltage 0.14 0.20 0.26 V tZCD-DIS PFC Enable / Disable Function Debounce Time 100 150 200 s 1/2.75 1/3.00 1/3.25 V/V tINHIB VZCD=100 mV PWM STAGE Feedback Input Section AV Input-Voltage to Current-Sense (4) Attenuation AV=VCSPWM /VFB, 0<VCSPWM<0.9 ZFB Input Impedance FB>VG IOZ Bias Current VOZ Zero Duty-Cycle Input Voltage VFB-OLP 5 7 k 1.2 2.0 mA 0.7 0.9 1.1 V Open-Loop Protection Threshold Voltage 3.9 4.2 4.5 V tFB-OLP Debounce Time for Open-Loop Protection 40 50 60 ms tFB-SS Internal Soft-Start Time 8 10 12 ms (4) 3 FB=VOZ (4) VFB=0 V~3.6 V FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 www.fairchildsemi.com 9 VDD=15 V, TJ=-40C ~125C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 2.45 2.50 2.55 V DET Pin OVP and Valley Detection Section VDET-OVP Comparator Reference Voltage (4) Av Open-Loop Gain BW Gain Bandwidth tDET-OVP IDET-SOURCE VDET-LOW (4) Output OVP (Auto Recovery) Debounce Time 100 Maximum Source Current VDET=0 V Lower Clamp Voltage IDET=1 mA 60 dB 1 MHz 150 200 s 1 mA -0.5 -0.3 -0.1 V 150 200 250 ns tOFF-BNK Leading-Edge Blanking Time for DET-OVP (2.5 V) and Valley Signal when PWM MOSFET (4) Turns Off 3 4 5 s tTIME-OUT Time-Out After tOFF-MIN 8 9 10 s 38 45 52 s VFBVN, TA=25C 7 8 9 VFB=VG 32 37 42 tVALLEY-DELAY Delay from Valley Signal (4) Detected to Output Turn-on PWM Oscillator Section tON-MAX-PWM Maximum On Time tOFF-MIN Minimum Off-Time s VN Beginning of Green-On Mode at FB Voltage Level TA=25C 1.95 2.10 2.25 V VG Beginning of Green-Off Mode at FB Voltage Level TA=25C 1.00 1.15 1.30 V VG Hysteresis for Beginning of Green-Off Mode at FB Voltage Level 0.1 VFB VG, TA=25C tSTARTER-PWM Start Timer (Time-Out Timer) VFB VFB-OLP, TA=25C V 1.85 2.25 2.65 ms 22 28 34 s 16.0 17.5 19.0 V 1.5 V PWM Output Section VCLAMP PWM Gate Output Clamping Voltage VDD=25 V VOL PWM Gate Output Voltage Low VDD=15 V, IO=100 mA VOH PWM Gate Output Voltage High VDD=15 V, IO=100 mA tR PWM Gate Output Rising Time CL=3 nF, VDD=12 V, 20~80% 80 110 ns tF PWM Gate Output Falling Time CL=3 nF, VDD=12 V, 20~80% 40 70 ns 8 V Continued on the following page... (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) www.fairchildsemi.com 10 VDD=15 V, TJ=-40C ~125C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 150 200 ns Current Sense Section tPD VLIMIT Delay to Output Limit Voltage on CSPWM Pin for Over-Power Compensation (4) VSLOPE Slope Compensation tON-BNK Leading-Edge Blanking Time VCS-FLOATING CSPWM Pin Floating VCSPWM Clamped High Voltage VCS-OV CSPWM Pin Open Protection tCS-H IDET 75 A, TA=25C 0.81 0.84 0.87 IDET=185 A, TA=25C 0.69 0.72 0.75 IDET=350 A, TA=25C 0.55 0.58 0.61 tON=45 s, RANGE=Open 0.25 0.30 0.35 tON=0 s 0.05 0.10 0.15 V V 300 CSPWM Pin Floating 4.5 (4) Delay with CSPWM Pin Floating ns 5.0 V 3 CSPWM Pin Floating V 100 150 200 s 125 140 155 C RT Pin Over-Temperature Protection Section TOTP TOTP-HYST IRT VRT-REC VRT-RE-REC VRT-OTP-LEVEL Internal Threshold Temperature (4) for OTP Hysteresis Temperature for (4) Internal OTP 30 Internal Source Current of RT Pin Auto Recovery-Mode Triggering Voltage Auto Recovery-Mode Release Voltage Threshold Voltage for Two-level Debounce Time tRT-OTP-H Debounce Time for OTP tRT-OTP-L Debounce Time for Externally Triggering 90 100 110 A 0.75 0.80 0.85 V VRT-REC +0.15 VRT-REC +0.20 VRT-REC +0.25 V 0.45 0.50 0.55 V 10 VRT<VRT-OTP-LEVEL, TA=25C Note: 4. Guaranteed by design. (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 C 70 110 ms 150 s FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Electrical Characteristics (Continued) www.fairchildsemi.com 11 18.5 11 18 10.5 VDD-PWM-OFF (V) VDD-ON (V) These characteristic graphs are normalized at TA=25C. 17.5 17 10 9.5 9 16.5 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Temperature ( ) Figure 5. Turn-On Threshold Voltage Figure 6. PWM Off Threshold Voltage 15 28 13 27 26 VDD-OVP (V) VDD-OFF (V) 11 9 7 25 24 23 5 22 21 3 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 35 50 65 80 95 110 125 Figure 8. VDD Over-Voltage Protection Threshold 30 12 25 10 20 8 IDD-OP (mA) IDD-ST (A) Figure 7. Turn-Off Threshold Voltage 15 6 10 4 5 2 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature ( ) 20 35 50 65 80 95 110 125 Temperature ( ) Figure 9. Startup Current Figure 10. Operating Current 2.7 17 2.65 16.5 2.6 16 VZ (V) VREF (V) 20 Temperature ( ) Temperature ( ) 2.55 15.5 2.5 15 2.45 14.5 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Typical Performance Characteristics 14 2.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 Temperature ( ) -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Figure 11. PFC Output Feedback Reference Voltage (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 -25 Figure 12. PFC Gate Output Clamping Voltage www.fairchildsemi.com 12 28 1 27 0.95 26 0.9 VCSPFC (V) tON-MAX-PFC (s) These characteristic graphs are normalized at TA=25C. 25 0.85 24 0.8 23 0.75 0.7 22 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature ( ) Figure 13. PFC Maximum On-Time 35 50 65 80 95 110 125 Figure 14. PFC Peak Current Limit Voltage 60 18.5 55 18 50 tON-MAX-PWM (s) 19 VCLAMP (V) 20 Temperature ( ) 17.5 17 16.5 45 40 35 16 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature ( ) 20 35 50 65 80 95 110 125 Temperature ( ) Figure 15. PWM Gate Output Clamping Voltage Figure 16. PWM Maximum On-Time 1.4 2.8 2.6 1.3 VG (V) VN (V) 2.4 2.2 1.2 2 1.1 1.8 1 1.6 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Temperature ( ) Figure 17. Beginning of Green-On Mode at VFB Figure 18. Beginning of Green-Off Mode at VFB 45 12 43 41 tOFF-MIN (s) tOFF-MIN (s) 10 8 6 39 37 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Typical Performance Characteristics (Continued) 35 4 33 31 2 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 Figure 19. PWM Minimum Off-Time for VFB > VN (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Temperature ( ) Figure 20. PWM Minimum Off-Time for VFB=VG www.fairchildsemi.com 13 These characteristic graphs are normalized at TA=25C. -0.1 2.8 2.7 2.6 VDET-OVP (V) VDET-LOW (V) -0.2 -0.3 2.5 2.4 2.3 -0.4 2.2 2.1 -0.5 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Temperature ( ) Figure 22. Reference Voltage for Output Over-Voltage Protection of DET Pin Figure 21. Lower Clamp Voltage of DET Pin 110 1 0.9 VRT-REC (V) IRT (A) 105 100 0.8 0.7 95 0.6 0.5 90 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -10 5 20 35 50 65 80 95 110 125 Figure 24. Over-Temperature Protection Threshold Voltage of RT Pin Figure 23. Internal Source Current of RT Pin (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 -25 Temperature ( ) Temperature ( ) FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Typical Performance Characteristics (Continued) www.fairchildsemi.com 14 PFC Stage Multi-Vector Error Amplifier and THD Optimizer For better dynamic performance, faster transient response, and precise clamping on PFC output, FL7921R uses a transconductance-type amplifier with proprietary multi-vector error amplifier. The schematic diagram of this amplifier is shown in Figure 25. The PFC output voltage is detected from the INV pin by an external resistor divider circuit that consists of R1 and R2. When PFC output variation voltage reaches 6% over or under the reference voltage 2.5 V, the multivector error amplifier adjusts its output sink or source current to increase the loop response to simplify the compensated circuit. 2.65V VCOMP PFC VO Error Amplifier RS PFC MOS Filp-Flop R1 2.5V 3 THD Optimizer 4 RS + INV R2 + CSPFC Sawtooth Generator FL7921 Figure 26. Multi-Vector Error Amplifier with THD Optimizer PFC VO IL,AVG (Fixed On-Time) IL,AVG (with THD Optimizer) 2.35V R1 COMP 2 CCOMP 2.5V CO INV 3 Error Amplifier Gate Signal with THD Optimizer VCOMP R2 Sawtooth Gate Signal with Fixed On-Time FL7921 Figure 27. Operation Waveforms of Fixed On-Time with and without THD Optimizer Figure 25. Multi-Vector Error Amplifier The feedback voltage signal on the INV pin is compared with reference voltage 2.5 V, which makes the error amplifier source or sink current to charge or discharge its output capacitor CCOMP. The COMP voltage is compared with the internally generated sawtooth waveform to determine the on-time of PFC gate. Normally, with lower feedback loop bandwidth, the variation of the PFC gate on-time should be very small and almost constant within one input AC cycle. However, the power-factor-correction circuit operating at light-load condition has a defect, zero-crossing distortion; which distorts input current and makes the system's Total Harmonic Distortion (THD) worse. To improve the result of THD at light-load condition, especially at high input voltage, an innovative THD Optimizer is inserted by sampling the voltage across the current-sense resistor. This sampling voltage is added into the sawtooth waveform to modulate the on-time of PFC gate, so it is not constant on-time within a half AC cycle. The operation block between THD Optimizer and PWM is shown in Figure 26. After THD Optimizer processes, around the valley of AC input voltage, the compensated on-time becomes wider than the original. The PFC on-time, which is around the peak voltage, is narrowed by the THD Optimizer. The timing sequences of the PFC MOSFET and the shape of the inductor current are shown in Figure 27. Figure 28 shows the difference between calculated fixed on-time mechanism and fixed on-time with THD Optimizer during a half AC cycle. (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.1 OFF ON Input Current 1.8 1.5 Current (A) 1.2 0.9 0.6 PO : 90W Input Voltage : 90VAC PFC Inductor : 460H CS Resistor : 0.15W 0.3 0 0 0.0014 0.0028 0.0042 0.0056 Time (Seconds) 0.0069 0.0083 Fixed On-time with THD Optimizer Fixed On time Figure 28. Calculated Waveforms of Fixed On-Time with and without THD Optimizer During a Half AC Cycle FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Lighting Controller Functional Description www.fairchildsemi.com 15 VZCD 10V 2.1V 1.75V RANGE= Ground VDS t PFCVO VIN,MAX RANGE= Open VVIN-RANGE-L VVIN VVIN-RANGE-H Zero-Current Detection (ZCD Pin) Figure 30 shows the internal block of zero-current detection. The detection function is performed by sensing the information on an auxiliary winding of the PFC inductor. Referring to Figure 31, when the PFC MOSFET is off, the stored energy of the PFC inductor starts to release to the output load. Then the drain voltage of PFC MOSFET starts to decrease since the PFC inductor resonates with parasitic capacitance. Once the ZCD pin voltage is lower than the triggering voltage (1.75 V typical), the PFC gate signal is sent again to start a new switching cycle. If PFC operation needs to be shut down due to abnormal conditions, pull the ZCD pin LOW, to a voltage under 0.2 V (typical), to activate the PFC-disable function to stop PFC switching. For preventing excessive high-switching frequency at light load, a built-in inhibit timer is used to limit the minimum tOFF time. Even if the ZCD signal has been detected, the PFC gate signal is not sent during the inhibit time (2.5 s typical). t PFC Gate Figure 29. Hysteresis Behavior between RANGE Pin and VIN Pin Voltage Inhibit Time t Figure 31. Operation Waveforms of PFC Zero-Current Detection Protection for PFC Stage PFC Output Voltage UVP and OVP (INV Pin) FL7921R provides several kinds of protection for the PFC stage. PFC output over- and under-voltage are essential for the PFC stage. Both are detected and determined by INV pin voltage, as shown in Figure 32. When the INV pin voltage is over 2.75 V or under 0.45 V due to overshoot or abnormal conditions and lasts for a de-bounce time around 70 s, the OVP or UVP circuit is activated to stop PFC switching operation immediately. The INV pin is not only used to receive and regulate PFC output voltage, but can also perform PFC output OVP/ UVP protection. For failure-mode test, this pin can shut down PFC switching if pin floating occurs. PFC VO Driver 1.4V VREF (2.5V) PFC Gate Drive Q Debounce Time COMP R 2 ZCD 0.2V S 5 1.75V VAC CCOMP RZCD Lb 10V S Q R VCOMP PFC Gate On 2.1V 1:n FL7921 R1 INV Voltage Detector CO 1 Error R2 Amplifier OVP = (VINV 2.75V) UVP = (VINV 0.45V) FL7921 FL7921R -- Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Lighting Controller RANGE Pin A built-in low voltage MOSFET can be turned on or off according to VVIN voltage level. The drain pin of this internal MOSFET is connected to the RANGE pin. Figure 29 shows the status curve of VVIN voltage level and RANGE impedance (open or ground). Figure 32. PFC Over-and Under-Voltage Protection Figure 30. Zero-Current Detection (c) 2015 Fairchild Semiconductor Corporation FL7921R Rev. 1.1 www.fairchildsemi.com 16 The PFC peak switching current is adjustable by the current-sense resistor. Figure 33 shows the measured waveform of PFC gate and CSPFC pin voltage. AC Input VCOMP-BO VCOMP 1.6V VVIN-UVP VVIN VVIN-RE-UVP 0V PFC MOS Current Limit 0.82V VINV-BO 2.5V VINV 1.2V CSPFC OPWM OPFC OPFC Brownout Protection Debounce Time 100ms Hiccup Mode Figure 34. Operation Waveforms of Brown-In / Out Protection Figure 33. Cycle-by-Cycle Current Limiting Brown-In / Out Protection (VIN Pin) With AC voltage detection, FL7921R can perform brown-in / out protection (AC voltage UVP). Figure 34 shows the key operation waveforms of brown-in / out protection. Both use the VIN pin to detect AC input voltage level and the VIN pin is connected to AC input by a resistor divider (refer to Figure 1); therefore, the VVIN voltage is proportional to the AC input voltage. When the AC voltage drops and VVIN voltage is lower than 1 V for 100 ms, the UVP protection is activated and the COMP pin voltage is clamped around 1.6 V. Because PFC gate duty is determined by comparing the sawtooth waveform and COMP pin voltage, lower COMP voltage results in narrow PFC on-time, so that the energy converged is limited and the PFC output voltage decreases. When INV pin is lower than 1.2 V, FL7921R stops all PFC and PWM switching operation immediately until VDD voltage drops to turn-off voltage then rises to turn-on voltage again (UVLO). Brownout Protection VDD VDD Hiccup Mode Brownout Brown-In AC Input OPWM OPFC Figure 35. Measured Waveform of Brown-In / Out Protection FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller PFC Peak Current Limiting (CSPFC Pin) During PFC stage switching operation, the PFC switch current is detected by a current-sense resistor on the CSPFC pin and the detected voltage on this resistor is delivered to the input terminal of a comparator and compared with a threshold voltage of 0.82 V (typical). Once the CSPFC pin voltage is higher than the threshold voltage, the PFC gate is turned off immediately. When the brownout protection is activated, all switching operation is turned off, and VDD voltage enters "Hiccup" mode going up and down continuously. Until VVIN voltage is higher than 1.3 V (typical) and VDD reaches turn-on voltage again, the PWM and PFC gate is sent out. The measured waveforms of brown-in / out protection are shown in Figure 35. (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.0 www.fairchildsemi.com 17 HV Startup and Operating Current (HV Pin) The HV pin is connected to the AC line through a resistor (refer to Figure 1). With a built-in high-voltage startup circuit, when AC voltage is applied to power system, FL7921R provides a high current to charge external VDD capacitor to reduce the controller's startup time and build up normal rated output voltage within three seconds. To save power consumption, after VDD voltage exceeds turn-on voltage and enters normal operation; this high-voltage startup circuit is shut down to avoid power loss from the startup resistor. Figure 36 shows the characteristic curve of VDD voltage and operating current IDD. When VDD voltage is lower than VDD-PWM-OFF, FL7921R stops all switching operation and turns off some internal circuits to reduce operating current. By doing so, the period from VDD-PWM-OFF to VDDOFF can be extended and the Hiccup Mode frequency can be decreased to reduce the input power in case of output short circuit. Figure 37 shows the typical waveforms of VDD voltage and gate signal in Hiccup Mode. voltage. When output loading is decreased, FB voltage becomes lower due to secondary feedback movement and the tOFF-MIN is extended. After tOFF-MIN (determined by FB voltage), the internal valley-detection circuit is activated to detect the valley on the drain voltage of the PWM switch. When the valley signal is detected, FL7921R outputs PWM gate signal to turn on the switch and begin a new switching cycle. With Green Mode and valley detection at light-load condition; the power system can perform extended valley switching in DCM operation and can further reduce switching loss for better conversion efficiency. The FB pin voltage vs. tOFF-MIN time characteristic curve is shown in Figure 38. Figure 38 shows, tOFF time narrowed to 2.25 ms, which is around 440 Hz switching frequency. tOFF-MIN 2 .25ms IDD 37s IDD-OP 8 s IDD-PWM-OFF 1 .1 5V ( V G) IDD-ST Figure 38. VFB vs. tOFF-MIN Characteristic Curve VDD VDD-OFF VDD-PWM-OFF VDD-ON Figure 36. VDD vs. IDD-OP Characteristic Curve VDD-ON VDD-PWM-OFF IDD-OP VDD-OFF Gate 2.1 V (V N) IDD-PWM-OFF IDD-ST Figure 37. Typical Waveform of VDD Voltage and Gate Signal in Hiccup Mode Green Mode (FB Pin) Green Mode is used to reduce power loss in the system (e.g. switching loss). An off-time modulation technique regulates switching frequency according to FB pin (c) 2015 Fairchild Semiconductor Corporation FL7921R Rev. 1.1 Valley Detection (DET Pin) When FL7921R operates in Green Mode, t OFF-MIN time is determined by the Green-Mode circuit, according to FB pin voltage level. After tOFF-MIN, the internal valleydetection circuit is activated. During the tOFF time of PWM switch, when transformer inductor current discharges to zero; the transformer inductor and parasitic capacitor of PWM switch start to resonate concurrently. When the drain voltage on the PWM switch falls, the voltage across on auxiliary winding V AUX also decreases since auxiliary winding is coupled to primary winding. Once the VAUX voltage resonates and falls to negative, VDET voltage is clamped by the DET pin (refer to Figure 39) and FL7921R is forced to flow out a current IDET. FL7921R reflects and compares this IDET current. If this source current rises to a threshold current, PWM gate signal is sent out after a fixed delay (200 ns typical). FL7921R -- Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Lighting Controller PWM Stage www.fairchildsemi.com 18 DET 10 0.3V + IDET VDET FL7921 - + RDET VAUX RA - As the input voltage increases, the reflected voltage on the auxiliary winding VAUX becomes higher as well as the current IDET and the controller regulates the VLIMIT to a lower level. The RDET resistor is connected from the auxiliary winding to the DET pin. Engineers can adjust this R DET resistor to get proper VLIMIT voltage to fit power system needs. The characteristic curve of IDET current vs. VLIMIT voltage on CSPWM pin is shown in Figure 42. I DET VIN N A N P RDET Figure 39. Valley Detection where VIN is input voltage; NA is turn number of auxiliary winding; and N P is turn number of primary winding. Start to Idet Flow Out Detect Valley from DET Pin VAUX 0V Delay Time and then Trigger Gate Signal VDET Valley Switching 0V (1) VAUX 0V VDET VAUX= -[VIN*(NA/NP)] DET Pin Voltage is Clamped during ton-time Period OPWM tOFF 0V tON High / Low Line Over-Power Compensation (DET Pin) Generally, when the power switch turns off, there is a delay from gate signal falling edge to power switch off. This delay is produced by an internal propagation delay of the controller and the turn-off delay of PWM switch due to gate resistor and gate-source capacitor CISS of PWM switch. At different AC input voltage, this delay produces different maximum output power under the same PWM current limit level. Higher input voltage generates higher maximum output power since applied voltage on primary winding is higher and causes a higher rising slope inductor current. It results in a higher peak inductor current at the same delay. Furthermore, under the same output wattage, the peak switching current at high line is lower than that at low line. Therefore, to make the maximum output power close at different input voltages, the controller needs to regulate VLIMIT voltage of the CSPWM pin to control the PWM switch current. tOFF Figure 41. Relationship between VAUX and VIN 900 800 700 VLIMIT(mV) Figure 40. Measured Waveform of Valley Detection OPWM 600 500 400 300 Referring to Figure 41, during tON period of the PWM switch, the input voltage is applied to primary winding and the voltage across on auxiliary winding V AUX is proportional to the primary winding voltage. As the input voltage increases, the reflected voltage on the auxiliary winding VAUX becomes higher as well. FL7921R also clamps the DET pin voltage and flows out a current IDET. Since the current IDET is in accordance with VAUX voltage, FL7921R can depend on this current IDET during tON period to regulate the current-limit level of the PWM switch to perform high / low line over-power compensation. (c) 2015 Fairchild Semiconductor Corporation FL7921R * Rev. 1.0 0 100 200 300 400 FL7921R -- Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller Auxiliary Winding IDET(A) Figure 42. IDET vs. VLIMIT Characteristic Curve Leading-Edge Blanking (LEB) When the PFC or PWM switches are turned on, a voltage spike is induced on the current-sense resistor due to the reciprocal effect by reverse-recovery energy of the output diode and COSS of power MOSFET. To prevent this spike, a leading-edge blanking time is built-in to FL7921R and a small RC filter is recommended between the CSPWM pin and GND (e.g. 100 , 470 pF). www.fairchildsemi.com 19 Output Over-Voltage Protection (DET Pin) VDD Pin Over-Voltage Protection (OVP) VDD over-voltage protection is used to prevent device damage once VDD voltage is higher than device stress rating voltage. In case of VDD OVP, the controller enters Auto Recovery Mode. Referring to Figure 44, during the discharge time of PWM transformer inductor; the voltage across on auxiliary winding is reflected from secondary winding and, therefore, the flat voltage on the DET pin is proportional to the output voltage. FL7921R can sample this flat voltage level after a tOFF blanking time to perform output over-voltage protection. This tOFF blanking time is used to ignore the voltage ringing from leakage inductance of PWM transformer. The sampling flat voltage level is compared with internal threshold voltage 2.5 V and, once the protection is activated, FL7921R enters Auto Recovery Mode. Adjustable Over-Temperature Protection and External Fault Triggering (RT Pin) Figure 43 is a typical application circuit with an internal block of RT pin. As shown, a constant current IRT flows out from the RT pin, so the voltage VRT on RT pin can be obtained as IRT current multiplied by the resistor, which consists of NTC resistor and RRT resistor. If the RT pin voltage is lower than 0.8 V and lasts for a debounce time, Auto Recovery Mode is activated. The RT pin is usually used to achieve over-temperature protection with a NTC resistor and provide external fault triggering for additional protection. Engineers can use an external triggering circuit (e.g. transistor) to pull the RT pin LOW and activate controller Auto Recovery Mode. The controller can protect rapidly through this kind of cycle-by-cycle sampling method in the case of output over voltage. The protection voltage level can be determined by the ratio of external resistor divider RA and RDET. The flat voltage on DET pin can be expressed by the following equation: VDET N A N S VO Generally, the external fault triggering needs to activate rapidly since it is usually used to protect power system from abnormal conditions. Therefore, the protection debounce time of the RT pin is set to around 110 s once RT pin voltage is lower than 0.5 V. PWM Gate For over-temperature protection, because the temperature does not change immediately; the RT pin voltage is reduced slowly as well. The debounce time for adjustable OTP does not need a fast reaction. To prevent improper fault triggering on the RT pin due to exacting test condition (e.g. lightning test); when the RT pin triggering voltage is higher than 0.5 V, the protection debounce time is set to around 10 ms. To avoid improper triggering on the RT pin, add a small value capacitor (e.g. 1000 pF) paralleled with NTC and RA resistor. VAUX VO RA RDET RA (2) t NA NS t FL7921 Adjustable Over-Temperature Protection & External Fault Triggering PFC _ VO IRT=100A 12 NTC RRT RT 0.8V 0.5V Debounce Time Auto Recovery VDET VO NA NP NA RA N S RDET R A Sampling here toff Blanking 110s 10ms FL7921R -- Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Lighting Controller Protection for PWM Stage Figure 43. Adjustable Over-Temperature Protection 0.3V t Figure 44. Operation Waveform of Output Over-Voltage Detection (c) 2015 Fairchild Semiconductor Corporation FL7921R Rev. 1.1 www.fairchildsemi.com 20 Referring to Figure 45, outside of FL7921R, the FB pin is connected to the collector of transistor of an optocoupler. Inside of FL7921R, the FB pin is connected to an internal voltage bias through a resistor of around 5 kW. VO FB Open-Loop Short-Circuit / Overload As the output loading is increased, the output voltage is decreased and the sink current of transistor of optocoupler on primary side is reduced so the FB pin voltage is increased by internal voltage bias. In the case of an open-loop, output short-circuit, or overload condition; this sink current is further reduced and the FB pin voltage is pulled to high level by internal bias voltage. When the FB pin voltage is higher than 4.2 V for 50 ms the FB pin protection is activated. Under-Voltage Lockout (UVLO, VDD Pin) Referring to Figure 36 and Figure 37, the turn-on and turn-off VDD threshold voltages of FL7921R are fixed at 18 V and 10 V, respectively. During startup, the hold-up capacitor (VDD cap.) is charged by the HV startup current until VDD voltage reaches the turn-on voltage. Before the output voltage rises to rated voltage and delivers energy to the VDD capacitor from auxiliary winding, this hold-up capacitor has to sustain the VDD voltage energy for operation. When VDD voltage reaches turn-on voltage, FL7921R starts all switching operation if no protection is triggered before VDD voltage drops to turn-off voltage VDD-PWM-OFF. Figure 45. FB Pin Open-Loop, Short Circuit, and Overload Protection (c) 2015 Fairchild Semiconductor Corporation FL7921R Rev. 1.1 FL7921R -- Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Lighting Controller Open-Loop, Short-Circuit, and Overload Protection (FB Pin) www.fairchildsemi.com 21 10.00 9.80 8.89 16 A 8.89 9 1.75 B 6.00 4.00 3.80 1 PIN #1 (0.30) 0.51 1.27 0.31 3.85 7.35 8 0.25 1.27 0.65 LAND PATTERN RECOMMENDATION C B A TOP VIEW 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.05 C FRONT VIEW 0.50 0.25 R0.10 GAGE PLANE R0.10 0.90 0.50 0.36 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 0.10 C 0.25 0.19 NOTES: A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AC, ISSUE C. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-2009 E) LANDPATTERN STANDARD: SOIC127P600X175-16AM F) DRAWING FILE NAME: M16AREV13. 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