Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
VCC = 1.8V to 5.5V
20MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and
Software Data Protection
Self-timed Write Cycle (5ms max)
High Reliability
Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
Green (Pb/Halogen-free/RoHS Compliant) Packaging Options
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT25010B/020B/040B provides 1,024/2,048/4,096 bits of Serial
Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as
128/256/512 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage
operation are essential. The AT25010B/020B/040B is available in space saving,
JEDEC SOIC, UDFN, TSSOP, XDFN, and VFBGA packages.
The AT25010B/020B/040B is enabled through the Chip Select pin (CS) and
accessed via a 3-Wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely
self-timed, and no separate erase cycle is required before write.
Block Write protection is enabled by programming the status register with one of
four blocks of Write Protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware Data Protection
is provided via the WP pin to protect against inadvertent write attempts. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
AT25010B, AT25020B, AT25040B
SPI Serial EEPROM
1K (128x8), 2K (256x8), 4K (512x8)
DATASHEET
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
2
1. Pin Configurations
Table 1-1. Pin Configurations
2. Absolute Maximum Ratings*
Pin Name Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
Operating Temperature . . . . . . . . . . -40C to + 125C
Storage Temperature . . . . . . . . . . . . -65C to + 150C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . . . . -1V to + 7V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
Note: Drawings are not to scale.
8-lead SOIC
CS
SO
WP
GND
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
Top View
Top View
8-lead TSSOP
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-ball VFBGA
Bottom View
8-pad UDFN/XDFN
Bottom View
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
3
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
3. Block Diagram
Figure 3-1. Block Diagram
Memory Array
128/256/512 x 8
Status
Register
Data
Register
Mode
Decode
Logic
Clock
Generator
Output
Buffer
Address
Decoder
VCC
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
4
4. Electrical Characteristics
4.1 Pin Capacitance
Table 4-1. Pin Capacitance(1)
Note: 1. This parameter is characterized and is not 100% tested.
4.2 DC Characteristics
Table 4-2. DC Characteristics
Note: 1. VIL min and VIH max are reference only and are not tested.
Applicable over recommended operating range from TA = 25°C, f = 1MHz, VCC = +5V (unless otherwise noted).
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5V at 20MHz
SO = Open, Read 8.5 10 mA
ICC2 Supply Current VCC = 5V at 10MHz
SO = Open, Read, Write 4.5 5 mA
ICC3 Supply Current VCC = 5V at 1MHz
SO = Open, Read, Write 2 3 mA
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 0.5 μA
ISB2 Standby Current VCC = 2.5V, CS = VCC 0.2 1 μA
ISB3 Standby Current VCC = 5V, CS = VCC 2 3.5 μA
IIL Input Leakage VIN = 0V to VCC 3μA
IOL Output Leakage VIN = 0V to VCC
TAC = 0°C to 70°C 3 3 μA
VIL(1) Input Low-voltage 0.6 VCC x 0.3 V
VIH(1) Input High-voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low-voltage 3.6V VCC 5.5V IOL = 3mA 0.4 V
VOH1 Output High-voltage 3.6V VCC 5.5V IOH = 1.60mA VCC 0.8 V
VOL2 Output Low-voltage 1.8V VCC 3.6V IOL = 0.15mA 0.2 V
VOH2 Output High-voltage 1.8V VCC 3.6V IOH = 100μA VCC 0.2 V
5
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
4.3 AC Characteristics
Table 4-3. AC Characteristics
Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol Parameter Voltage Min Max Units
fSCK SCK Clock Frequency
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
20
10
5
MHz
tRI Input Rise Time
4.5 5.5
2.5 5.5
1.8 5.5
2
2
2
μs
tFI Input Fall Time
4.5 5.5
2.5 5.5
1.8 5.5
2
2
2
μs
tWH SCK High Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tWL SCK Low Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tCS CS High Time
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
ns
tCSS CS Setup Time
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
ns
tCSH CS Hold Time
4.5 5.5
2.5 5.5
1.8 5.5
100
100
200
ns
tSU Data In Setup Time
4.5 5.5
2.5 5.5
1.85.5
20
40
80
ns
tHData In Hold Time
4.5 5.5
2.5 - 5.5
1.8 - 5.5
20
40
80
ns
tHD Hold Setup Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tCD Hold Hold Time
4.5 5.5
2.5 5.5
1.8 5.5
20
40
80
ns
tVOutput Valid
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
20
40
80
ns
tHO Output Hold Time
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
ns
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
6
Note: 1. This parameter is characterized and is not 100% tested.
5. Serial Interface Description
Master: The device that generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, the AT25010B/020B/040B always operates as a
slave.
Transmitter/Receiver: The AT25010B/020B/040B has separate pins designated for data transmission (SO)
and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains
the opcode which defines the operations to be performed. The opcode also contains address bit A8 in both the
read and write instructions for the AT25040B.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25010B/020B/040B, and the
serial output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This
will reinitialize the serial communication.
Chip Select: The AT25010B/020B/040B is selected when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the SO pin will remain in a high impedance state.
Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25010B/020B/040B. When the
device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication
with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while
the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high
impedance state.
Write Protect: The write protect pin (WP) will allow normal read/write operations when held high. When the WP
pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010B/020B/040B. If the internal write cycle
has already been initiated, WP going low will have no effect on any write operation.
tLZ Hold to Output Low Z
4.5 5.5
2.5 5.5
1.8 5.5
0
0
0
25
50
100
ns
tHZ Hold to Output High Z
4.5 5.5
2.5 5.5
1.8 5.5
25
50
100
ns
tDIS Output Disable Time
4.5 5.5
2.5 5.5
1.8 5.5
25
50
100
ns
tWC Write Cycle Time
4.5 5.5
2.5 5.5
1.8 5.5
5
5
5
ms
Endurance(1) 5V, 25C, Page Mode 1,000,000 Write Cycles
Table 4-3. AC Characteristics (Continued)
Applicable over recommended operating range from TAI = -40 to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30pF
(unless otherwise noted).
Symbol Parameter Voltage Min Max Units
7
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
Figure 5-1. SPI Serial Interface
Master:
Microcontroller
Slave:
AT25010B/020B/040B
Data Out (MOSI)
Data In (MISO)
Serial Clock (SPI CK)
SS0
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
8
6. Functional Description
The AT25010B/020B/040B is designed to interface directly with the synchronous Serial Peripheral Interface
(SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25010B/020B/040B utilizes an 8-bit instruction register. The list of instructions and their operation codes
are contained in Figure 6-1. All instructions, addresses, and data are transferred with the MSB first and start
with a high-to-low CS transition.
Table 6-1. Instruction Set for the AT25010B/020B/040B
Note: 1. “A” represents MSB address bit A8 for the AT25040B.
Write Enable (WREN): The device will power-up in the Write Disable state when VCC is applied. All
programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held
high during a WREN instruction.
Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
Read Status Register (RDSR): The Read Status Register instruction provides access to the status register.
The Read/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6-2. Status Register Format
Table 6-3. Read Status Register Bit Definition
Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 A011 Read Data from Memory Array
WRITE 0000 A010 Write Data to Memory Array
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X X X BP1 BP0 WEN RDY
Bit Definition
Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is ready.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 1 (WEN) Bit 1 = 0 indicates the device is not write enabled.
Bit 1 = 1 indicates the device is write enabled.
Bit 2 (BP0) See Table 6-4.
Bit 3 (BP1) See Table 6-4.
Bits 4 – 7 are zeros when device is not in an internal write cycle.
Bits 0 – 7 are ones during an internal write cycle.
9
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
The AT25010B/020B/040B is divided into four array segments. None, one-quarter (¼), one-half (½), or all of the
memory segments can be protected. Any of the data within any selected segment will therefore be read-only.
The block write protection levels and corresponding status register control bits are shown in Table 6-4.
Bits BP1 and BP0 are nonvolatile cells that have the same properties and functions as the regular memory cells
(e.g., WREN, tWC, RDSR).
Table 6-4. Block Write Protect Bits
Read Sequence (READ): Reading the AT25010B/020B/040B via the SO pin requires the following sequence.
After the CS line is pulled low to select a device, the Read opcode (including A8 for the AT25040B) is
transmitted via the SI line followed by the byte address to be read (A7 A0). Upon completion, any data on the
SI line will be ignored. The data (D7 D0) at the specified address is then shifted out onto the SO line. If only
one byte is to be read, the CS line should be driven high after the data comes out. The Read Sequence can be
continued since the byte address is automatically incremented and data will continue to be shifted out. When
the highest address is reached, the address counter will roll-over to the lowest address allowing the entire
memory to be read in one continuous read cycle.
Write Sequence (WRITE): In order to program the AT25010B/020B/040B, the Write Protect pin (WP) must be
held high and two separate instructions must be executed. First, the device must be write enabled via the
WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location selected by the Block Write
Protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write
opcode (including A8 for the AT25040B) is transmitted via the SI line followed by the byte address (A7 A0) and
the data (D7 D0) to be programmed. Programming will start after the CS pin is brought high. The low-to-high
transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR)
instruction. If Bit 0 = 1, the write cycle is still in progress. If Bit 0 = 0, the write cycle has ended. Only the RDSR
instruction is enabled during the write programming cycle.
The AT25010B/020B/040B is capable of an 8-byte Page Write operation. After each byte of data is received, the
three low-order address bits are internally incremented by one; the six high-order bits of the address will remain
constant. If more than eight bytes of data are transmitted, the address counter will roll-over and the previously
written data will be overwritten. The AT25010B/020B/040B is automatically returned to the Write Disable state
at the completion of a write cycle.
Note: If the WP pin is brought low or if the device is not Write Enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS is brought high. A new CS falling edge is
required to reinitiate the serial communication.
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25010B AT25020B AT25040B
0 0 0 None None None
1 (¼) 0 1 607F C0 FF 180 FF
2 (½) 1 0 40 7F 80 FF 100 1FF
3 (All) 1 1 00 7F 00 FF 000 1FF
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
10
7. Timing Diagrams
Figure 7-1. Synchronous Data Timing (for Mode 0)
Figure 7-2. WREN Timing
Figure 7-3. WRDI Timing
SO HI-Z HI-Z
tV
SI
tH
tSU
tDIS
SCK tWH
tCSH
CS
tCSS
tCS
tWL
tHO
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
Valid In
SO
SI
SCK
CS
WREN Opcode
HI-Z
SO
SI
SCK
CS
WRDI Opcode
HI-Z
11
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
Figure 7-4. RDSR Timing
Figure 7-5. WRSR Timing
Figure 7-6. READ Timing
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
76543210
Data Out
High-impedance
MSB
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
7654 3 210
Data In
High-impedance
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction Byte Address
Data Out
High-impedance
MSB
76543210
76543210
9th bit of Address
8
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
12
Figure 7-7. WRITE Timing
Figure 7-8. HOLD Timing
SO
SI
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction Byte Address Data In
High-impedance
7654321076543210
9th bit of Address
8
HOLD
SO
SCK
CS
t
CD
t
CD
t
HD
t
HD
t
LZ
t
HZ
13
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
8. Ordering Code Detail
AT25010B-SSHL-B
Atmel Designator
Product Family
Device Density
Device Revision
Shipping Carrier Option
Package Device Grade or
Wafer/Die Thickness
Package Option
010 = 1k
020 = 2k
040 = 4k
25 = Standard SPI
Serial EPPROM
B = Bulk (Tubes)
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Expanded Quantity Option
Operating Voltage
M = 1.8V to 5.5V
H = Green, NiPdAu Lead Finish,
Industrial Temperature Range
(-40˚C to +85˚C)
U = Green, Matte Sn Lead Finish,
Industrial Temperature Range
(-40˚C to +85˚C)
11 = 11mil Wafer Thickness
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
ME = XDFN
C = VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
14
9. Part Markings
DRAWING NO. REV. TITLE
25010-02-04BSM B
1/15/14
25010-02-04BSM, AT25010B, AT25020B and AT25040B
Package Marking Information
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
AAAAAAAA
###% @
ATMLHYWW
8-lead SOIC 8-lead TSSOP
AAAAAAA
###% @
ATHYWW
8-pad UDFN
###
H%@
YXX
2.0 x 3.0 mm Body
Note 2: Package drawings are not to scale
Note 1: designates pin 1
AT25010B, AT25020B and AT25040B: Package Marking Information
Catalog Number Truncation
AT25010B Truncation Code ###: 51B
AT25020B Truncation Code ###: 52B
AT25040B Truncation Code ###: 54B
Date Codes Voltages
Y = Year M = Month WW = Work Week of Assembly % = Minimum Voltage
4: 2014 8: 2018 A: January 02: Week 2 L: 1.8V min
5: 2015 9: 2019 B: February 04: Week 4
6: 2016 0: 2020 ... ...
7: 2017 1: 2021 L: December 52: Week 52
Country of Assembly Lot Number Grade/Lead Finish Material
@ = Country of Assembly AAA...A = Atmel Wafer Lot Number H: Industrial/NiPdAu
U: Industrial/Matte Tin/SnAgCu
Trace Code Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel
Example: AA, AB.... YZ, ZZ ATM: Atmel
ATML: Atmel
1.5 x 2.0 mm Body
8-ball VFBGA
PIN 1
###U
YMXX
###
YXX
8-pad XDFN
1.8 x 2.2 mm Body
15
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
10. Ordering Information
Note: 1. Contact Atmel Sales for Wafer sales.
Atmel Ordering Code Lead Finish Package
Delivery Information Operation
Range
Form Quantity
AT25010B-SSHL-B
NiPdAu
(Lead-free/Halogen-free)
8S1
Bulk (Tubes) 100 per Tube
Industrial
Temperature
(-40 to 85C)
AT25010B-SSHL-T Tape and Reel 4,000 per Reel
AT25010B-XHL-B
8X
Bulk (Tubes) 100 per Tube
AT25010B-XHL-T Tape and Reel 5,000 per Reel
AT25010B-MAHL-T
8MA2
Tape and Reel 5,000 per Reel
AT25010B-MAHL-E Tape and Reel 15,000 per Reel
AT25010B-MEHL-T 8ME1 Tape and Reel 5,000 per Reel
AT25010B-CUL-T SnAgCu
(Lead-free/Halogen-free) 8U3-1 Tape and Reel 5,000 per Reel
AT25010B-WWU11L (1) N/A Wafer Note 1
AT25020B-SSHL-B
NiPdAu
(Lead-free/Halogen-free)
8S1
Bulk (Tubes) 100 per Tube
Industrial
Temperature
(-40 to 85C)
AT25020B-SSHL-T Tape and Reel 4,000 per Reel
AT25020B-XHL-B
8X
Bulk (Tubes) 100 per Tube
AT25020B-XHL-T Tape and Reel 5,000 per Reel
AT25020B-MAHL-T
8MA2
Tape and Reel 5,000 per Reel
AT25020B-MAHL-E Tape and Reel 15,000 per Reel
AT25020B-MEHL-T 8ME1 Tape and Reel 5,000 per Reel
AT25020B-CUL-T SnAgCu
(Lead-free/Halogen-free) 8U3-1 Tape and Reel 5,000 per Reel
AT25020B-WWU11L (1) N/A Wafer Note 1
AT25040B-SSHL-B
NiPdAu
(Lead-free/Halogen-free)
8S1
Bulk (Tubes) 100 per Tube
Industrial
Temperature
(-40 to 85C)
AT25040B-SSHL-T Tape and Reel 4,000 per Reel
AT25040B-XHL-B
8X
Bulk (Tubes) 100 per Tube
AT25040B-XHL-T Tape and Reel 5,000 per Reel
AT25040B-MAHL-T
8MA2
Tape and Reel 5,000 per Reel
AT25040B-MAHL-E Tape and Reel 15,000 per Reel
AT25040B-MEHL-T 8ME1 Tape and Reel 5,000 per Reel
AT25040B-CUL-T SnAgCu
(Lead-free/Halogen-free) 8U3-1 Tape and Reel 5,000 per Reel
AT25040B-WWU11L (1) N/A Wafer Note 1
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
16
Package Type
8S1 8-lead, 0.15" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X 8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Plastic Ultra Thin Dual Flat No Lead (UDFN)
8ME1 8-pad, 1.80mm x 2.20mm body, 0.40mm pitch, Extra Thin Dual Flat No Lead (XDFN)
8U3-1 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Die Ball Grid Array (VFBGA)
17
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
11. Packaging Information
11.1 8S1 — 8-lead JEDEC SOIC
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
Ø
Ø
0° – 8°
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
Package Drawing Contact:
packagedrawings@atmel.com
8S1 G
6/22/11
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) SWB
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
18
11.2 8X — 8-lead TSSOP
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
b 0.19 0.25 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
C 0.09 - 0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
Package Drawing Contact:
packagedrawings@atmel.com
8X E
2/27/14
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
C
A1
19
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
11.3 8MA2 — 8-pad UDFN
DRAWING NO. REV. TITLE GPC
8MA2 G
11/26/14
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
YNZ
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.50 0.55 0.60
A1 0.0 0.02 0.05
A2 - - 0.55
D 1.90 2.00 2.10
D2 1.40 1.50 1.60
E 2.90 3.00 3.10
E2 1.20 1.30 1.40
b 0.18 0.25 0.30 3
C 1.52 REF
L 0.30 0.35 0.40
e 0.50 BSC
K 0.20 - -
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Package Drawing Contact:
packagedrawings@atmel.com
C
E
Pin 1 ID
D
8
7
6
5
1
2
3
4
A
A1
A2
D2
E2
e (6x)
L (8x)
b (8x)
Pin#1 ID
K
1
2
3
4
8
7
6
5
Notes: 1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
20
11.4 8ME1 — 8-pad XDFN
Package Drawing Contact:
packagedrawings@atmel.com
GPC DRAWING NO.
REV. TITLE
COMMON DIMENSIONS
(Unit of Measure = mm)
DTP
SYMBOL MIN NOM MAX NOTE
–
0.00
1.70
2.10
0.15
0.26
A
A1
D
E
b
e
e1
L
–
–
1.80
2.20
0.20
0.40 TYP
1.20 REF
0.30
0.40
0.05
1.90
2.30
0.25
0.35
End View
8ME1 B
9/10/2012
8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN
(XDFN)
Top View
657
4
3
E
D
8
12
PIN #1 ID
0.10
0.15
b
L
b
e
PIN #1 ID
e1
A1
A
Side View
21
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
11.5 8U3-1 — 8-ball VFBGA
DRAWING NO. REV. TITLE GPC
Package Drawing Contact:
packagedrawings@atmel.com
8U3-1 F
6/11/13
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GXU
COMMON DIMENSIONS
(Unit of Measure - mm)
SYMBOL MIN NOM MAX NOTE
A
0.73 0.79 0.85
A1 0.09 0.14 0.19
A2 0.40 0.45 0.50
b 0.20 0.25 0.30 2
D
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1 0.25 REF
d
1.00 BSC
d1 0.25 REF
1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
Notes:
A2
SIDE VIEW
A
PIN 1 BALL PAD CORNER
TOP VIEW
E
D
A1
b
8 SOLDER BALLS
BOTTOM VIEW
(d1)
d
4
3
2
(e1)
6
e
5
7
PIN 1 BALL PAD CORNER
1
8
2.
AT25010B/020B/040B [DATASHEET]
Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015
22
12. Revision History
Doc. Rev. Date Comments
8707F 01/2015 Add the UDFN Expanded Quantity Option.
Update the 8MA2 package outline drawing and the ordering information section.
8707E 05/2014 Update part markings, package drawings, package 8A2 to 8X, template, logos, and
disclaimer page. No change to functional specification.
8707D 04/2013 Correct WRSR waveform figure 4-5, bit 7 is not writable.
Update Atmel logos and disclaimer page.
8707C 06/2011 Correct AT25040B-SSHL marking detail.
Replace 8A2 package drawing with version E.
8707B 10/2010 Remove Preliminary.
8707B 03/2010 Replace 8Y6 with 8MA2.
8707A 02/2010 Initial document release.
X
XXX
XX
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© 2015 Atmel Corporation. / Rev.: Atmel-8707F-SEEPROM-AT25010B-020B-040B-Datasheet_012015.
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