TDC1007 7 IX Monolithic Video A/D Converter 8bit, 20MSPS The TOC1007 is an 8-bit fully parallel (flash) analog -to ~ digital converter, capable of digitizing an input signal at rates up to 20MSPS (MegaSamples Per Second). It will operate accurately without the use of an external sample-and-hold ampiitier, with analog input signals having frequency components up to 7M. A single CONVert (CONV) signal controls the conversion operation of the device which consists of 255 sampling comparators, encoding logic, and a latched output buffer register. The device will recover from a full-scale input step in 20ns. Control inputs are provided to format the output in binary, two's complement, or inverse data coding formats. The TOC1007 is patented under U.S. Patent No. 3283170 with other patents pending. Features -Bit Resolution Conversion Rates Up ta 20MSPS Sample-And-Hold Amplifier Not Required Bipolar Monolithic Construction TTL Compatible Inputs and Outputs Binary or Two's Complement Mode Differential Phase = 1.0 Degrees Differential Gain = 1.7% Evaluation Boards Available: TDC1007E1C or TDC1007P1C Applications Video Systems 3x or 4x Subcarrier, NTSC or PAL Radar Systems High-Speed Multiplexed Data Acquisition Digital Signa! Processing Functional Block Diagram NMINV NLINY conv Vin Ay > "1 Ae 1s < Re e e e {| R > Ss RRs R AAA Rep < R2S < > A e e e e > R 55 5 93 DIFFERENTIAL Re COMPARTORS LS! Products Division TRW Electronic Components Group P.0. Box 2472 La Jolla, CA 92038 KK \ eee 255 TO B ENCODER LATCH (258) Phone: {619) 457 - 1000 Telex: 697-957 TWX: 910-335 - 1571 TRW Inc. 1985 40G00276 Rev. O- 1/85 Printed in the U.S.A. DidTDC1007 vive Functional Block Diagram NMINV > NLINV> coNY > 10> Ry $ Ms apa | $ as hs e e Vets AI: L, e e ae Dy 4 2 j2> 1 4 R2g 255 TO 8 LATCH 2 ENCODER C7 51-8 Pa > Reo 3 ~~ a as 128 > < yo} as e Do_ |) 4 ; mers : ww e LL : ami Ra mo oar (255) Pin Assignments eo _ NC ae ac wc 3m 62 NC we 4 61 WC NC $i 0 NC NC 6K 59 NC NC 7 58 NC NC 8 57 WC WC 85 c 8 we NC 10K 55 NC Pr ns ce we NC 12 53 WC Vin ne 52 WC Agnp 14 or NC Vn 185 p1 50 Vee Vin 16 aa VEE Ru m5 48 Vee Vy 18 a7 Vee Aguo 195 4% NC Vin ay 45 NE NC 21 4 NC Ap 2 4 Veco NC BS @ Deno NC 24 41 NMINV NC 2 40 Dy (SB) NC 2B 39 Dp NC 7 38 D3 Vec 2B 7 Oy Donn 25 36 NLINV coy 30 = 3 Dy NC 31 Dg (LSB) Dg ze ABD 64 Lead DIP - J1 Package LSI Products Division D 16 TRW Electronic Components Groupa. aaa TDC1007 77tny Pin Assignments eu Sau S sg szea Sy aes SRAGRREGARREASHES NC 8I @ we NC 82 a@ wc NC 83 41 Voc NC 64 Ogno NC 66 39 CONV NC 88 38 DgiLSB) NC 87 7 NC 68 38 Og NC 1 35 Dg NC 2 3M ONLINV NC 3 33 Dy NC 4 2 03 NC 5 1 o2 NC 6 30 Dy {MSB) wc 67 23 NMINV wc 68 28 NC nc 8 27 NC SOUR SPSTSERAARRAB 2222 22202 Se 82 ge a 68 Contact Or Leaded Chip Carrier - 1, L1 Package a a nl Functional Description General Information The TDC1007 has three major functional sections: a comparator array, ancoding logic, and output data latches. The input voltage is compared with 255 separate reference voltage points tapped from the reference resistor chain. The 255 comparator outputs ferm a code {sometimes referred to as a thermometer code, as all the comparators referred to voltages more positive than the input signal will be off, and those referred to voltages more negative than the input signal will be on). The thermometer code from the comparator array is encoded into an eight-bit binary ward by the encading logic section. Each of these eight results is sent through an exclusive-OR gate where they are inverted by use of the NMINV or NLINV inputs. This allows operation in binary, two's complement, or inveried data formats. Power The TDC1007 operates from two supply voltages, +5.0V and ~6.0V. The return for Ipc, the current drawn from the +5.0V supply, is Dgyp. The return path for Ire, the current drawn from the -6.0V supply, is Agno. All power and ground pins must be connected. Name Function Value Ci, L1 Package J1 Package Vee Positive Supply Voltage +5.0V Pins 23, 41 Pins 28, 49 Veg Negative Supply Voltage -6.0V Pins 14, 16, 19, 27 Pins 47, 48, 49, 50 Ognp Oigital Ground .0V Pins 25, 40 Pins 29, 42 Acnp Analog Ground 00 Pins 48, 55 Pins 14, 19 LS} Products Division TRW Electronic Components Group D 17TDC1007 artve Reference The TDC1007 converts analog signals in the range Vag < Vin < Ver into digital form. Vat {the voltage applied to the pin at the top of the reference resistor chain), and Vag {the voltage applied to the pin at the bottom of the reference resistor chain) should be between +0.1V and -2.1V, with the difference between them less than 2.1V. VT should be more positive than Veg within that range. In order to insure optimum operation of the TDC1007, these points should be driven by low-impedance sources capable of providing the necessary reference resistor chain current. The voltages on Ry and Rg may be varied dynamically up ta 7MHz. Due to variations in reference current with clock and input signals, RT and Rp should be lowimpedance-to-ground points. For circuits in which the reference is not varied, a bypass capacitor to ground is recommended. If the reference inputs are varied dynamically {as in an AGC application) a low-impedance reference source is required. Name Function Value C1, L1 Package J1 Package Ry Reference Resistor (Top) 0.0V Pin Pin 11 Ru Reference Resistor (Middle) -10V Pin 51 Pin 17 Rg Reference Resistor (Bottom) -2.0V Pin 44 Pin 22 Control Two control inputs are provided on the TDC1007 for changing the format of the output data. When NMINV is tied to a logic 0, the most significant bit of the output data is inverted; when NLINV is tied to 4 logic 0, the seven least significant bits of the output are inverted. By using these controls, the output data format can be binary, inverted binary, two's complement, or inverted two's complement. Output data versus input voltage and control input state is illustrated in the Output Coding table. Name Function Value Ci, L1 Package J1 Package NMINV Not Most Significant Bit INVert TL Pin 29 Pin 41 NLINV Not Least Significant Bit INVert TTL Pin 34 Pin 36 Convert The analog input to the TDC1007 is sampled (comparators are latched) approximately 10ns after the rising edge of the CONV Signal. This time delay is the sampling time offset (tT) and varies only by a few nanoseconds from device to device and as a function of temperature. The short-term uncertainty (jitter) in sampling time offset is approximately 30 picoseconds. The output data is encoded from the 255 comparators on the falling edge of the CONV signal. The coded result is transferred to the output latches on the next rising edge of the CONV signal. Note that there are minimum pulse width (tpyH. tpwL! requirements on the waveshape of the CONV signal. Name Function Value C1, L1 Package J1 Package CONV Convert TTL Pin 39 Pin 30 D 18 LSI Products Division TAW Electronic Components GroupTDC1007 aitvy aS a as, Analog Input The input impedance of the TDC1007 varies with input signal signal. When the analog input is beyond the range of the level. As the signal varies, the comparator input transistors reference voltage, the output data will be the appropriate change from active to cut-off, causing the net input resistance full-scale value. Note that there are two components ta the and capacitance to change. To prevent this action from input bias current flowing into the Vix pins. One component is degrading the integrity er accuracy of the output data, it is constant for constant input voltage and is the sum of the bias desirable to drive the TDC1007 inputs from a low-impedance currents of the subset of comparators that are active (Ica). source {less than 25 Ohms). The input signal level should The other component is related to the action of the CONV remain within the range of Veg to +0.5V in order to prevent signal on the comparator chain [Igp). All analog input pins of damage to the device. When the input is at a level between the TDC1007 must be used in order to insure operation over VpT and Vag reference voltages, the output data value will be the full input range. directly proportional to the amplitude of the analog input Name Function Value C1, L1 Package J1 Package Vin Analog Input Signal OV to -2V Pins 46, 50, 52, 54, 58 Pins 13, 15, 16, 18, 20 Outputs The outputs of the TD1007 are TTL compatible and capable rising edge of the CONV signal, and the new data becomes of driving four low-power Schottky unit loads (54/74 LS). The valid after a maximum time of tp. For optimum performance, gutputs hold the previous data a minimum time (tyg) after the 2.2 kOhm pull-up resistors are recommended, Name Function Value C1, 11 Package JT Package Dy MSB Output TIL Pin 30 Pin 40 Dy TIL Pin 31 Pin 39 03 TIL Pin 32 Pin 8 Oy TIL Pin 33 Pin 37 Ds TIL Pin 35 Pin 35 Df TIL Pin 36 Pin 4 Dy TIL Pin 37 Pin 3 Dm Dg LSB Output TIL Pin 38 Pin 32 No Connects There are several pins labeled Ne Connect (NCI, which have no connections to the chip. These pins may be left open. Name Function Value C1, L1 Package J1 Package NC No Connect Open Pins 1-13, 15-17, 20, 22, 24, Pins 1-10, 12, 24-27, 26-28, 42, 43, 45, 47, 49, 53, 31, 44-46, 51-64 56, 57, 59, 61, 62-68 LS! Products Division TRW Electronic Components Group D 19TDC1007 7 mIXtvy Figure 1. Timing Diagram CONV ANALOG INPUT tsTo N+2 SAMPLE | DATA DATA DATA | wo LS | Figure 2. Simplified Analog Input Equivalent Circuit Vin 1~ OF -255 COMPARATORS l REFERENCE RESISTOR Vee CHAIN Vin T R Cin IN lop Va VEEA Ciy 'S A NONLINEAR JUNCTION CAPACITANCE Vpg 'S A VOLTAGE EQUAL TO THE VOLTAGE ON PIN Rp Figure 3. Digital Input Equivalent Circuit Vcc -- > 10K > > 5k INPUT JN -- =z = zx D 20 Figure 4. Output Circuits +Vec _ Veco 380.2 > a2 > T0 - OUTPUT > PIN zx OUTPUT ee 4007) a TPUT EQ LoAD1 sO CIRCUtT UIVALENT TEST LOAD FOR DELAY MEASUREMENTS LSI Products Division TRW Electronic Camponents GroupTDC1007 rw Neen rere rere ere aa Absolute maximum ratings (beyond which the device will be damaged! | Supply Voltages Voc {measured to Dgyp) ~05 to +7.0V Veg (measured to Agyp! +05 to -7.0V Agyp (measured to Ognp) -1.0 to +1.0V Input Voltages CONV, NMINV, NLINV (measured to Deyn) 05 to +6.6V Vin Vet. Vag (measured to Agno! +05 to VeeV Vpr (measured to Vp) +22 to -2.2V Output Applied voltage (measured to Dgyp} D5 to +5.5V2 Applied current, externally forced 1.0 to +6.0mA34 Short circuit duration (single output in high state to ground) 1 sec Temperature Operating, ambient -B0 to + 140C junction + 176C Lead, soldering (10 seconds) +300C Storage -B5 to +150C Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, 3. Forcing voltage must be limited to specified range. 4 Current ts specified as positive when lawing into the device. Operating conditions Temperature Range Standard Extended Parameter Min Nom Max Min Nom Max Units Voc Positive Supply Voltage (Measured to Dgiyp! 475 5.0 5.25 45 50 65 Veg Negative Supply Voltage (Measured to Acnp) -5.75 -60 ~6.25 -5.75 -6.0 -6.25 v Vagnp Analag Ground Voltage (Measured to Ogyp} -01 0.0 01 ~0.1 0.0 0.1 towL CONV Pulse Width, LOW 25 Ps.) ns tewH CONV Pulse Width, HIGH 15 15 ns Vie Input Voltage, Logic LOW 0.8 0.8 Vin Input Voltage, Logic HIGH 20 20 low Output Current, Logic LOW 40 40 mA low Output Current, Logic HIGH -40 ~400 uA Ver Most Positive Reference Input | 11 0.0 01 -1i 0.0 0.1 V Vep Most Negative Reference Input | -09 -20 -21 -09 -20 -2.1 V VeT-Vp_ Voltage Reference Differential 1.0 2.0 22 10 20 22 v Vin Input Voltage Vet Vp Vet Veep v Ty Ambient Temperature, Still Air 0 70 Cc Te Case Temperature -55 185 c Note: 1. Vp7 must be more pasitive than Vpg, and voltage reference differential must be within specified range LSI Products Division TRW Electronic Components Group D2TDC1007 7rtre FItvyr Electrical characteristics within specified operating conditions Temperature Ranga Standard Extended Parameter Test Conditions Min Max Min Max | Units Ine Positive Supply Current Vec = MAX, Static | 30 % mA gp Negative Supply Current Veg = MAX, Static Ty = OC to 70C - 400 mA Ty = 70C -350 mA Tp = 55C to 126C -470 mA Tr = 125C -320 mA faep Reference Current Vat. Yap - NOM 3 4 mA Rege Total Reference Resistance 57 50 Ohms Riy Input Equivalent Resistance Vet Vag - NOM, Vin = Vap 5 5 kOhms Cyy Input. Capacitance 250 250 pF log __ Input Constant Bias Current Veg = MAX 400 500 HA Ign Input Clock Synchronous Bias 200 200 LA I Input Current, Logic LOW Voc ~ MAX, Vj = 0.5V -20 -20 mA hy Input Current, Logic HIGH Voc = MAX, Vj = 24V 75 75 uA \ Input Current, Max input Voltage Veg = MAX, V) = 5.5V 14 10 mA Vp, Output Voltage, Logic LOW Veg = MIN, ip, = MAX 05 05 V Voy Output Voltage, Logic HIGH 24 24 V Igg Short Circuit Output Current Vee = MAX, Output HIGH, one pin to ground, - -25 mA one second duration. Cy Digital Input Capacitance Ty = 25C, F = IMHz 15 15 pF Note: 1. Worst case, all digital inputs and outputs LOW. Switching characteristics within specified operating conditions Cee See eee Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units Fs Maximum Conversion Rate Vec - MIN, Veg = MIN 20 20 MSPS tstg Sampling Time Offset Vec - MIN, Veg - MIN q 1D 0 10 ns ty Output Delay Time Vec = MIN, Veg = MIN, Load 1 40 45 Ins tyg Output Hold Time Vec = MIN, Veg = MIN, Load 1 10 1g ns D 22 LS! Products Division TRW Electronic Components GroupTDC1007 SEU System performance characteristics within specified operating conditions Temperature Range art Standard Extended Parameter Test Conditions Min Max Min Max Units Ey Linearity Error Integral, Independent Vat: Yap = NOM 03 03 % Eip Linearity Error Differential Ver. VpB 03 03 h a Code Size Ver. Yap - NOM 15 185 15 185 % Nominal Egr Offset Eror Top Vin = Vat 35 45 mV Egg Offset Error Bottom Vin - Yre -22 -24 mV Teo Offset Error ~~ Temperature Coefficient +50 +50 pverc BW Bandwidth, Fuil Power Input 7 5 MHz trp Transient Response, Full Scale 20 20 ns SNR Signal-te-Noise Ratio 1OMHz Bandwidth 20MSPS Conversion Rate Peak Signal/RMS Naise 1,248MHz Input 53 52 dB 2.438MHz Input 50 49 dB RMS Signal/RMS Noise 1.248MH2z Input 44 8 dB 2.438MH2 Input 41 4 dB NPR = Noise Power Ratio DC to SMHz White Noise Bandwidth 36.5 365 dB 4 Sigma Loading 1.248MHz Slot 20MSPS Conversion Rate Exp Aperture Error 60 60 ps OP Differential Phase NTSC @ 4x Color Subcarrier 1.0 16 Degree OG Differential Gain NTSC @ 4x Color Subcarrier 17 V7 % LS! Products Division TRW Electronic Components Group D 23TDC1007 are Output Coding (Input range from 0.000 to -2.000V) Binary Offset Two's Complement Input Voltage True Inverted True Inverted (-7.84 mViStep) NMINV = 1 0 0 | NLUNV = 1 0 j Q 0.000 qn000eno 440i 10000000 Q1149711 e e e * e e e e e e -0.0078 0000001 1111110 1000001 01111110 e e e e e e e e e e e e e e e e e e e cd - 0.9960 ani 10000000 Vt 00000000 - 1.0039 10000000 01110111 00000000 Www e e e e e a e e e a e e e e e e e e e e - 1.9921 11111110 00000001 01111110 10000001 e e e e e e e e ca e -2.000 W111 00000000 oui 19000000 Calibration To calibrate the TOC1007, the top of the reference resistor chain, Ry, is connected ta analog ground. The reference voltage is then set up by adjusting the bottom of the resistor chain ta ~2.0V. When this technique is used, offset errors are generated by the inherent parasitic resistance between the package pin and the actual resistor chain on the A/D. These parasitic resistars are shown as Ry and Ro in the Functional Block Diagram. The offset voltage error is the result of the resistor chain current flowing through the parasitic resistance. These errors can be compensated for by applying an equal offset to the analog input signal or by adjusting the voltages on Ry and Rp. The effect of the offset error at the bottom of the resistor chain manifests itself in the ferm of a slight gain error which can be compensated for by varying the voltage applied ta Rp. This voltage will necessarily be more negative than the desired reference level of -2.0V. The actual pperating range of the AD converter will be: Vacno - "per x Rill to Wrap + lpee x Re). D 24 However, if bath ends of the resistor chain are driven by transistor-buffered operational amplifiers, the voltages on RT and Ag could then be adjusted to remove the effect of the parasitic resistances and therefore eliminate the need to apply a compensating offset voltage to the analog input signal. Here the operating range of the A/D will be: Vat-llpep x RI) to Vag + llReF x R2H). Since both Vay and VaR are adjustable, the offset voltage error effect can be cancelled and the A/D operated with gain and offset errors removed. The TOC1007 provides access to the mid-point of the reference resistor chain, Riy. This point can be sensed by external circuitry for temperature compensation or gain tracking functions in the system. It can also be driven in the manner shown in Figure 6 for fine linearity correction. LSI Products Division TRW Electronic Components GroupTDC1007 aw Typical Application Figure 5 shows a typical interface circuit for a TDC1007, an input buffer amplifier, and the reference voltage source. The reference voltage is supplied by an inverting amplifier that has been buffered with a PNP transistor. The transistor sinks the current flowing through the reference resistor chain and keeps the driving impedance at the bottom end of the resistor chain low. The gain of the overall circuit is adjusted by varying the input voltage to the operational amplifier. The input amolifier is a bipolar wideband operational amplifier followed by an NPN transistor buffer. The transistor drives the input capacitance of the A/D converter and keeps the overall circuit frequency stable. The offset error is compensated by varying the current into the summing junction of the op-amp. Note that all five Vj, points are connected together and the buffer amplifier feedback loop is closed at that point. The buffer amplifier has a gain af two, raising the 1V p-p video input signal to 2V p~p at the input to the A/D converter. The A/D converter operates with a 2V full-scale. Figure 5. Typical Interface Circuit VIDEO , Wr INPUT wv +N a [as Vee Voc 2 Gnp 2 Eno RIS < at 10071 i 4 v CLOCK Agno 22) ano 05 ie ott be o,nse | MSB is Tw 0, o Toc D3 2 [. D3 Oy Dy n Agnp a5 EE Be v 2 Agno 0, | D 7 NMINV > NLINV 2) convert AY min Og jz Dg LSB % NLINY Vee Yer Vee Vee sc a7 | ai -Bv Figure 6. Method For Driving MidPoint Of Resistor Chain y -2.0V LSI Products Division TRW Electronic Components Group Ry Toc 10071 D2 5TDC1007 IXY Parts List Resistors Ri t aw R2 t 1aw R3 1K aw 5% R 43K 14W 5% R5 10 aw 5% R6 56 VW 5% R7 240 aw 5% Re 68 2W 5% Rg 2K 20 5% R10 . aw 5% R11 2K 14w 10-turn R12 2K 14W 10~turn R13 1.3K 14aw 5% Ri 2.2K 4w 5% R15 680 Vaw 5% R16 2.2K SIP 5% Capacitors C1 OF 50V (2 . 5OV 03 OF SOV C4 OF SOV 65 OF Sv C8 1uF SV C7 Dur 50v C8 OF SOV OF 50V cio OtuF 50V Integrated Circuits ul TOC1007J1 U2 Plessey SL541C U3 ATA u4 MC1403 Diodes CRI 1N4001 Transistors a1 2N5836 02 2N2907 Ordering Information T Indicates input terminatoridivider * Indicates amplifier compensation Caan reer eee Product Temperature Range Screening Package Package Number Marking TOC1007C1F EXT-Tp = -55C to 126C Commercial 68 Contact Chip Carrier 1007C1F3 TOCIOOICIA EXT-Tp = -58C to 126C High Reliability ' 68 Contact Chip Carrier 1007C1A3 TOCIDOT IC STD-Ty = 0C to 70C Commercial 64 Lead OIP 10070103 TOCIOO7JIG STD-Ty = 0C to 7oc* Commercial With Burn-in 64 Lead DIP 1007J1G3 TDOC1007L1F EXT-Trp = -55C to 126C Commercial 88 Leaded Chip Carrier 1007L1F3 TDCIOO7LIA EXT-Tp = -55C to 126C High Reliability ' 68 Leaded Chip Carrier 1007L1A3 TRW reserves the right to change products and specifications without notice. This informatian does not convey any license under patent rights of TRW Inc. or others. Note: 1. Per TAW document 70201757. D 26 LSI Products Division TRW Electronic Companents Group