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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD78062(A), 78063(A), 78064(A) 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD78062(A), 78063(A), and 78064(A) are products to which a quality assurance program more stringent than that used for the PD78062, 78063, and 78064 (standard models) is applied (NEC classifies these products as "special" quality grade models). PD78062(A), 78063(A), and 78064(A) are products in the PD78064 subseries within the 78K/0 series, which incorporate LCD controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt functions and many other peripheral hardwares. Various development tools are also provided. For the details of functional description, refer to the following user's manual.Be sure to read this manual before designing your system. PD78064 78064Y Subseries User's Manual : U10105E 78K/0 Series User's Manual (Instruction : IEU-1372 FEATURES * Large on-chip ROM & RAM Item Product Name PD78062(A) Program Memory (ROM) 16K bytes PD78063(A) 24K bytes PD78064(A) 32K bytes Data Memory Internal High-Speed RAM LCD Display RAM 512 bytes 1024 bytes 40 x 4 bits Package 100-pin plastic QFP (fine pitch) (14 x 14mm, 0.5 mm pitch) 100-pin plastic QFP (14 x 20 mm, 0.65 mm pitch) 100-pin plastic LQFPNote (fine pitch) (14 x 14 mm, 0.5 mm pitch) Note Under planning * Minimum instruction execution time can be varied from high speed (0.4 s) to ultra-low speed (122 s) * I/O ports: 57 (including segment signal output dual-function pins) * LCD controller/driver Supply voltage VDD = 2.0 to 6.0 V (Static display mode) VDD = 2.5 to 6.0 V (1/3 bias) VDD = 2.7 to 6.0 V (1/2 bias) * 8-bit resolution A /D converter : 8 channels * Serial interface : 2 channels * Timer: 5 channels * Supply voltage : VDD = 2.0 to 6.0 V The information in this document is subject to change without notice. Document No. U10335EJ2V0DS00 (2nd edition) Date Published August 1997 N Printed in Japan The mark shows major revised points. (c) 1997 PD78062(A), 78063(A), 78064(A) APPLICATIONS Control units of automobile electronic systems, gas detectors and circuit breakers, various safety systems, hemadynamometers, etc. ORDERING INFORMATION Part Number PD78062GC(A)-xxx-7EA PD78062GC(A)-xxx-8EUNote PD78062GF(A)-xxx-3BA PD78063GC(A)-xxx-7EA PD78063GC(A)-xxx-8EUNote PD78063GF(A)-xxx-3BA PD78064GC(A)-xxx-7EA PD78064GC(A)-xxx-8EUNote PD78064GF(A)-xxx-3BA Note Package 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness: 1.40 mm) 100-pin plastic QFP (14 x 20mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness: 1.40 mm) 100-pin plastic QFP (14 x 20mm) 100-pin plastic QFP (fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm, resin thickness: 1.40 mm) 100-pin plastic QFP (14 x 20mm) Under planning Caution The PD78062GC(A), 78063GC(A), and 78064GC(A) are available in two types of packages (refer to 12. PACKAGE DRAWINGS). For the available packages, consult NEC. Remark xxx indicates a ROM code suffix. QUALITY GRADE Special Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. DIFFERENCES BETWEEN PD78062(A), 78063(A) and 78064(A), and PD78062, 78063 and 78064 Product name Item Quality grade 2 PD78062(A), 78063(A), 78064(A) Special PD78062, 78063, 78064 Standard PD78062(A), 78063(A), 78064(A) 78K/0 SERIES DEVELOPMENT The following shows the 78 K/0 Series products development. Subseries names are shown inside frames. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin PD78075BY PD78078Y PD78075B PD78078 PD78070A PD780058 PD78058F PD78070AY PD780018AY PD780058YNote EMI noise reduction version of the PD78078. A timer was added to the PD78054, and the external interface function was enhanced. ROM-less versions of the PD78078. Serial I/O of the PD78078Y was enhanced, and only selected functions are provided. Serial I/O of the PD78054 was enhanced, EMI noise reduction version. PD78058FY EMI noise reduction version of the PD78054. PD78054Y PD780034Y PD780024Y UART and D/A converter were added to the PD78014, and I/O was enhanced. 64-pin PD78054 PD780034 64-pin 64-pin PD780024 PD78014H 64-pin PD78018F PD78014 PD780001 PD78014Y An A/D converter and 16-bit timer were added to the PD78002. An A/D converter was added to the PD78002. 64-pin PD78002 PD78002Y Basic subseries for control. 42/44-pin PD78083 64-pin PD780964 PD780924 80-pin 64-pin 64-pin PD78018FY An A/D converter of the PD780024 was enhanced. Serial I/O of the PD78018F was enhanced, EMI noise reduction version. EMI noise reduction version of PD78018F. Low-voltage (1.8 V) operation versions of the PD78014 with several ROM and RAM capacities available. On-chip UART, capable of operating at a low voltage (1.8 V). Inverter control 64-pin An A/D converter of the PD780924 was enhanced. On-chip inverter control circuit and UART, EMI noise reduction version. FIPTM drive PD780208 PD780228 The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 100-pin 80-pin PD78044H N-ch open drain input/output was added to the PD78044F, Display output total: 34 80-pin PD78044F Basic subseries for driving FIP, Display output total: 34 100-pin 78K/0 Series The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 LCD drive 100-pin PD780308 PD780308Y 100-pin PD78064B PD78064 SIO of the PD78064 was enhanced, and ROM and RAM were expanded. EMI noise reduced version of the PD78064. PD78064Y Basic subseries for driving LCDs, On-chip UART. 100-pin IEBusTM supported 80-pin PD78098B EMI noise reduction version of the PD78098. 80-pin PD78098 An IEBus controller was added to the PD78054. Meter control 80-pin PD780973 On-chip automobile meter driving controller/driver. LV 64-pin Note PD78P0914 On-chip PWM output, LV digital code decoder, and Hsync counter. Under planning 3 PD78062(A), 78063(A), 78064(A) The following table shows the differences among subseries functions. Function Subseries Name Control Timer ROM Capacity 8-bit 16-bit Watch WDT A/D A/D PD78075B 32 K to 40 K 4ch 1ch PD78078 48 K to 60 K PD78070A 8-bit 10-bit 8-bit 1ch 1ch 8ch - 2ch 3ch (UART: 1ch) - PD780058 24 K to 60 K 2ch PD78058F 48 K to 60 K PD78054 16 K to 60 K PD780034 8 K to 32 K 2ch 3ch (time division UART: 1ch) 3ch (UART: 1ch) - 8ch 8ch - - PD78014H PD78018F 8 K to 60 K PD78014 8 K to 32 K PD780001 8K PD78002 8 K to 16 K - Inverter control PD780964 FIP drive PD780208 32 K to 60 K 2ch 1ch PD780228 48 K to 60 K 3ch PD78044H 32 K to 48 K 2ch 1ch PD78044F 16 K to 40 K PD780308 48 K to 60 K 2ch 1ch PD78064B 32 K PD78064 16 K to 32 K 4 8 K to 32 K 3ch Note - 88 1.8 V 61 2.7 V 68 1.8 V 69 2.7 V 3ch (UART: 1ch, time division 3-wire: 1ch) 51 2ch 53 - 1ch 1ch - - 8ch - - 8ch 8ch - 1ch 1ch 8ch - PD780924 Available 1.8 V 1ch 39 - 53 Available 1ch (UART: 1ch) 33 1.8 V - - 2ch (UART: 2ch) 47 2.7 V Available - 2ch 74 2.7 V - 1ch 72 4.5 V 68 2.7 V 57 2.0 V - 69 2.7 V Available - 1ch 2ch 1ch 1ch 8ch - - 3ch (time division UART: 1ch) 2ch (UART: 1ch) IEBus PD78098B supported PD78098 40 K to 60 K 2ch 1ch Meter control PD780973 24 K to 32 K 3ch 1ch Note VDD MIN. External Value Expansion 2.7 V PD78083 LV I/O 2.0 V PD780024 LCD drive Serial Interface D/A 1ch 1ch 8ch - 2ch 3ch (UART: 1ch) 1ch 1ch 5ch - - 2ch (UART: 1ch) 56 4.5 V - - - 2ch 54 4.5 V Available 32 K to 60 K PD78P0914 32 K 10-bit timer: 1 channel 6ch - - 1ch 8ch PD78062(A), 78063(A), 78064(A) FUNCTIONAL OUTLINE Product Name ROM High-speed RAM LCD display RAM General registers Minimum instruction execution time Internal memory PD78063(A) PD78062(A) Item 16K bytes 512 bytes PD78064(A) 24K bytes 32K bytes 1024 bytes 40 x 4 bits 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time cycle modification function When main system clock selected 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz operation) When subsystem clock selected 122 s (at 32.768 kHz operation) Instruction set * * * * 16-bit operation Multiplication/division (8 bits x 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. * * * * * * * * * * Total : 57 * CMOS input : 02 * CMOS I/O : 55 8-bit resolution x 8 channels Segment signal output : Maximum 40 Common signal output : Maximum 4 Bias : 1/2 or 1/3 switchable 3-wire serial I/O/SBI/2-wire serial I/O mode selectable 3-wire serial I/O/UART mode selectable 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 2 channels Watch timer : 1 channel Watchdog timer : 1 channel I/O ports (including segment signal output pins) A/D converter LCD controller/driver Serial interface Timer : 1 channel : 1 channel Timer output 3 (14-bit PWM output capability : 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (at main system clock 5.0 MHz operation) 32.768 kHz (at subsystem clock 32.768 kHz operation) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0 MHz operation) Vectored interrupt sources Maskable Internal : 12, external : Non-maskable Internal : 1 Softwar 1 Test input Internal: Supply voltage VDD = 2.0 to 6.0 V Package 6 1, external: 1 * 100-pin plastic QFP (Fine pitch) (14 x 14 mm, resin thickness: 1.45 mm) * 100-pin plastic QFP (14 x 20 mm) * 100-pin plastic LQFP (Fine pitch) (14 x 14 mm, resin thickness: 1.40 mm, under planning) 5 PD78062(A), 78063(A), 78064(A) CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ........................................................................................................ 7 2. BLOCK DIAGRAM ................................................................................................................................... 10 3. PIN FUNCTIONS ...................................................................................................................................... 11 3.1 Port Pins .......................................................................................................................................................... 11 3.2 3.3 Other Pins ........................................................................................................................................................ Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................. 13 14 4. MEMORY SPACE ..................................................................................................................................... 18 5. PERIPHERAL HARDWARE FUNCTION FEATURE ............................................................................... 19 6. 5.1 5.2 Port ................................................................................................................................................................... Clock Generator .............................................................................................................................................. 19 20 5.3 5.4 Timer/Event Counter ....................................................................................................................................... Clock Output Control Circuit ......................................................................................................................... 20 23 5.5 5.6 Buzzer Output Control Circuit ....................................................................................................................... A/D Converter .................................................................................................................................................. 23 24 5.7 5.8 Serial Interface ............................................................................................................................................... LCD Controller/Driver ..................................................................................................................................... 24 26 INTERRUPT FUNCTIONS AND TEST FUNCTIONS ............................................................................... 27 6.1 6.2 Interrupt Functions ......................................................................................................................................... Test Functions ................................................................................................................................................. 27 31 7. STANDBY FUNCTION ............................................................................................................................. 32 8. RESET FUNCTION .................................................................................................................................. 32 9. INSTRUCTION SET ................................................................................................................................. 33 10. ELECTRICAL SPECIFICATIONS ............................................................................................................ 35 11. CHARACTERISTIC CURVES (REFERENCE VALUES) ......................................................................... 56 12. PACKAGE DRAWINGS ........................................................................................................................... 58 13. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 61 APPENDIX A. DEVELOPMENT TOOLS ....................................................................................................... 62 APPENDIX B. RELATED DOCUMENTS ....................................................................................................... 64 6 PD78062(A), 78063(A), 78064(A) 1. PIN CONFIGURATION (TOP VIEW) * 100-pin plastic QFP (fine pitch)(14 x 14 mm, resin thickness: 1.45 mm) PD78062GC(A)-xxx-7EA, 78063GC(A)-xxx-7EA, 78064GC(A)-xxx-7EA * 100-pin plastic LQFP (fine pitch)(14 x 14 mm, resin thickness: 1.40 mm) AVREF P100 9 10 P101 VSS P102 11 12 13 P103 P30/TO0 14 15 P31/TO1 P32/TO2 16 17 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 18 19 20 21 P72/SCK2/ASCK X1 X2 IC XT1/P07 VDD XT2 P71/SO2/TXD 71 P70/SI2/RXD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 70 69 68 P81/S38 P82/S37 P83/S36 67 66 65 P84/S35 P85/S34 64 63 62 61 60 59 58 57 56 55 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19 S18 S13 S14 S15 S16 S17 54 22 53 23 52 24 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 COM3 BIAS VLC0 COM0 COM1 COM2 P113 P112 P111 P110 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET 7 8 S6 S7 S8 S9 S10 S11 S12 P17/ANI7 AVDD 5 6 S3 S4 S5 P14/ANI4 P15/ANI5 P16/ANI6 S0 S1 S2 P12/ANI2 P13/ANI3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 74 2 73 3 72 4 VLC1 VLC2 VSS P11/ANI1 AVSS P117 P116 P115 P114 P10/ANI0 PD78062GC(A)-xxx-8EUNote, 78063GC(A)-xxx-8EUNote, 78064GC(A)-xxx-8EUNote Note Under planning Cautions 1. Connect directly the IC (Internally Connected) pin to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 7 PD78062(A), 78063(A), 78064(A) * 100-pin plastic QFP (14 x 20 mm) PD78062GF(A)-xxx-3BA, 78063GF(A)-xxx-3BA VDD XT1/P07 XT2 RESET P00/INTP0/TI00 11 12 13 P01/INTP1/TI01 P02/INTP2 14 15 P03/INTP3 P04/INTP4 16 17 P05/INTP5 P110 P111 P112 P113 18 19 20 21 22 P114 P115 P116 P117 AVSS P10/ANI0 23 24 25 26 27 28 S22 S21 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. P37 P13/ANI3 P14/ANI4 P15/ANI5 53 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Cautions 1. Connect directly the IC (Internally Connected) pin to VSS. 8 S23 7 8 9 10 P11/ANI1 P12/ANI2 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 75 74 73 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ X2 X1 76 5 6 VSS P102 P103 P71/SO2/TXD P72/SCK2/ASCK IC AVREF P100 P101 P27/SCK0 P70/SI2/RXD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 79 2 78 3 77 4 P16/ANI6 P17/ANI7 AVDD P26/SO0/SB1 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P25/SI0/SB0 PD78064G(A)-xxx-3BA S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 P4 S3 S2 S1 S0 VSS VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0 PD78062(A), 78063(A), 78064(A) ANI0-ANI7 ASCK : Analog Input : Asynchronous Serial Clock P110-P117 PCL : Port11 : Programmable Clock AVDD AVREF : Analog Power Supply : Analog Reference Voltage RESET RXD : Reset : Receive Data AVss BIAS : Analog Ground : LCD Power Supply Bias Control S0-S39 SB0-SB1 : Segment Output : Serial Bus BUZ : Buzzer Clock COM0-COM3 : Common Output SI0, SI2 SO0, SO2 : Serial Input : Serial Output IC : Internally Connected INTP0-INTP5 : Interrupt from Peripherals SCK0, SCK2 : Serial Clock TI00, TI01 : Timer Input P00-P05, P07 : port0 P10-P17 : Port1 TI1, TI2 TO0-TO2 : Timer Input : Timer Output P25-P27 P30-P37 : Port2 : Port3 T XD VDD : Transmit Data : Power Supply P70-P72 P80-P87 : Port7 : Port8 VLC0-VLC2 VSS : LCD Power Supply : Ground P90-P97 P100-P103 : Port9 : Port10 X1, X2 XT1, XT2 : Crystal (Main System Clock) : Crystal (Subsystem Clock) 9 PD78062(A), 78063(A), 78064(A) 2. BLOCK DIAGRAM TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 P00 16-bit TIMER/ EVENT COUNTER PORT0 P01-P05 P07 TO1/P31 TI1/P33 TO2/P32 TI2/P34 8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2 PORT1 P10-P17 PORT2 P25-P27 PORT3 P30-P37 PORT7 P70-P72 PORT8 P80-P87 PORT9 P90-P97 PORT10 P100-P103 PORT11 P110-P117 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SERIAL INTERFACE 0 78K/0 CPU CORE ROM SCK0/P27 SI2/RxD/P70 SO2/TxD/P71 SERIAL INTERFACE 2 SCK2/ASCK/P72 S0-S23 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/P00INTP5/P05 BUZ/P36 PCL/P35 RAM A/D CONVERTER LCD CONTROLLER/ DRIVER S24/P97S31/P90 S32/P87S39/P80 COM0-COM3 VLC0-VLC2 INTERRUPT CONTROL BIAS fLCD BUZZER OUTPUT CLOCK OUTPUT CONTROL VDD VSS IC SYSTEM CONTROL RESET X1 X2 XT1/P07 XT2 Remark The internal ROM and RAM capacities differ depending on the product. 10 PD78062(A), 78063(A), 78064(A) 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name I/O P00 Function Input only Input After Reset Input P02 Input/ output P03 P04 Port 0 7-bit I/O port. INTP2 Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Input Input only Input INTP5 Input Note1 P10 to P17 Input/ output Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software.Note2 Input/ output Port 2 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. P25 P27 ANI0 to ANI7 SI0/SB0 Input SO0/SB1 SCK0 TO0 P31 TO1 P32 P34 XT1 Input P30 P33 INTP3 INTP4 P05 P26 INTP0/TI00 INTP1/TI01 P01 P07 DualFunction Pin Input/ output P35 Port 3 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. TO2 Input TI1 TI2 PCL P36 BUZ P37 ---- P70 P71 P72 Input/ output Port 7 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. SI2/RxD SO2/TxD Input SCK2/ ASCK Notes 1. When using the P07/XT1 pins as an input port, set (1) bit 6 (FRC) of the processor clock control register (PCC) (the on-chip feedback resistor of the subsystem clock oscillator should not be used). 2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, port 1 is set to input mode. However, on-chip pull-up resistor is not automatically used. 11 PD78062(A), 78063(A), 78064(A) 3.1 Port Pins (2/2) Pin Name P80 to P87 P90 to P97 P100 to P103 P110 to P117 12 After Reset DualFunction Pin Input/ output Port 8 8-bit input/output port Input/output can be specified bit-wise. When used as an input port , on-chip pull-up resistor can be used in software. Input/output port/segment signal output function can be specified in 2-bit unit by the LCD control register (LCDC). Input S39 to S32 Input/ output Port 9 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Input/output port/segment signal output function can be specified in 2-bit unit by the LCD control register (LCDC). Input S31 to S24 I/O Function Input/ output Port 10 4-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. LED direct drive capability. Input Input/ output Port 11 8-bit input/output port Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Falling edge detection capability. Input PD78062(A), 78063(A), 78064(A) 3.2 Other Pins (1/2) Pin Name Function I/O After Reset P00/TI00 INTP0 P01/TI01 INTP1 INTP2 DualFunction Pin Input INTP3 External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. Input P02 P03 INTP4 P04 INTP5 P05 SI0 Input Serial interface serial data input. Input P70/RxD SI2 SO0 Output Serial interface serial data output. P26/SB1 Input P71/TxD SO2 SB0 P25/SB0 P25/SI0 Input /output Serial interface serial data input/output. Input /output Serial interface serial clock input/output. RxD Input Asynchronous serial interface serial data input. Input P70/SI2 TxD Output Asynchronous serial interface serial data output. Input P71/SO2 Input Asynchronous serial interface serial clock input. Input P72/SCK2 SB1 SCK0 SCK2 ASCK Input P26/SO0 Input P72/ASCK External count clock input to 16-bit timer (TM0). TI00 P00/INTP0 Capture trigger signal input to capture register (CR00). TI01 Input P27 P01/INTP1 Input TI1 External count clock input to 8-bit timer (TM1). TI2 External count clock input to 8-bit timer (TM2). P34 TO0 16-bit timer (TM0) output (shared with 14-bit PWM output). P30 TO1 Output 8-bit timer (TM1) output. P33 Input 8-bit timer (TM2) output. TO2 P31 P32 PCL Output Clock output (for main system clock, subsystem clock trimming). Input P35 BUZ Output Buzzer output. Input P36 Output S0 to S23 S24 to S31 Output LCD controller/driver segment signal output. P97 to P90 Input P87 to P80 S32 to S39 COM0 to COM3 VLC0 to VLC2 BIAS Output LCD controller/driver common signal output. Output LCD drive voltage. Split resistors can be incorporated by mask option. LCD drive power supply. 13 PD78062(A), 78063(A), 78064(A) 3.2 Other Pins (2/2) Pin Name Function I/O After Reset DualFunction Pin Input P10 to P17 ANI0 to ANI7 Input A/D converter analog input. AVREF Input A/D converter reference voltage input. ---- ---- AVDD A/D converter analog power supply. Connect to VDD. ---- ---- AVSS A/D converter ground potential. Connect to VSS. ---- ---- System reset input. ---- ---- ---- ---- ---- ---- Input P07 ---- ---- RESET Input X1 Input Main system clock oscillation crystal connection. X2 XT1 Input Subsystem clock oscillation crystal connection. XT2 VDD Positive power supply. ---- ---- VSS Ground potential. ---- ---- IC Internal connection. Connect directly to VSS pin. ---- ---- 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin (1/2) Input/output Circuit Type I/O 2 Input 8-A Input/output P07/XT1 16 Input P10/ANI0 to P17/ANI7 11 Pin Name P00/INTP0/TI00 Recommended Connection when not Used Connected to VSS . P01/INTP1/TI01 P02/INTP2 P03/INTP3 Independently connected to VSS through resistor. P04/INTP4 P05/INTP5 Connected to VDD . P25/SI0/SB0 P26/SO0/SB1 10-A P27/SCK0 P30/TO0 P31/TO1 P32/TO2 14 5-A Input/output Independently connected to VDD or VSS through resistor. PD78062(A), 78063(A), 78064(A) Table 3-1. Input/Output Circuit Type of Each Pin (2/2) Pin Name P33/TI1 Input/output Circuit Type I/O Recommended Connection when not Used 8-A P34/TI2 P35/PCL P36/BUZ 5-A P37 P70/SI2/RxD 8-A P71/SO2/TxD 5-A P72/SCK2/ASCK 8-A Input/output Independently connected to VDD or VSS through resistor. P80/S39 to P87/S32 17-A P90/S31 to P97/S24 P100 to P103 5-A P110 to P117 8-A S0 to S23 17 COM0 to COM3 18 Independently connected to VDD through resistor. Output Leave open. VLC0 to VLC2 ---- ---- RESET 2 Input XT2 16 BIAS Leave open. Connected to VSS . AVREF AVDD ---- ---- ---- Connected to VDD . AVSS Connected to VSS . IC Connected directly to VSS . 15 PD78062(A), 78063(A), 78064(A) Figure 3-1. Pin Input/Output Circuits (1/2) Type 10-A Type 2 VDD pull-up enable P-ch VDD IN data P-ch IN/OUT open drain output disable N-ch Schmitt-Triggered Input with Hysteresis Characteristic Type 11 Type 5-A VDD VDD pull-up enable pull-up enable P-ch data VDD data P-ch IN/OUT P-ch IN/OUT output disable P-ch VDD output disable N-ch P-ch Comparator N-ch + - N-ch VREF (Threshold Voltage) input enable input enable Type 16 Type 8-A VDD feedback cut-off pull-up enable P-ch P-ch VDD data P-ch IN/OUT output disable 16 N-ch XT1 XT2 PD78062(A), 78063(A), 78064(A) Figure 3-1. Pin Input/Output Circuits (2/2) Type 17-A Type 17 VLC0 VDD P-ch VLC1 N-ch pull-up enable P-ch SEG data P-ch VDD OUT data P-ch N-ch P-ch IN/OUT VLC2 output disable N-ch N-ch input enable VLC0 Type 18 P-ch VLC1 VLC0 N-ch P-ch P-ch VLC1 SEG data N-ch N-ch P-ch P-ch N-ch COM data P-ch OUT N-ch VLC2 N-ch P-ch VLC2 N-ch 17 PD78062(A), 78063(A), 78064(A) 4. MEMORY SPACE The memory map of PD78062(A)/78063(A)/78064(A) is shown in Figure 4-1. Figure 4-1. Memory Map FFFFH Special Function Register (SFR) 256 x 8 Bits FF00H FEFFH General Registers 32 x 8 Bits FEE0H Internal High-Speed RAMNote mmmmH mmmmH-1 nnnnH Program Area Data Memory Space Use Prohibited 1000H 0FFFH FA80H FA7FH CALLF Entry Area LCD Display RAM 40 x 4 Bits FA58H FA57H 0800H 07FFH Program Area Use Prohibited nnnnH+1 nnnnH Program Memory Space CALLT Table Area Internal ROMNote 0040H 003FH Vector Table Area 0000H 0000H Note 0080H 007FH The Internal ROM and Internal High-Speed RAM capacities differ depending on the product. (refer to the following table.) 18 Product Name Last Address of Internal ROM nnnnH Start Address of Internal High-Speed RAM mmmmH PD78062(A) PD78063(A) PD78064(A) 3FFFH 5FFFH 7FFFH FD00H FB00H PD78062(A), 78063(A), 78064(A) 5. PERIPHERAL HARDWARE FUNCTION FEATURE 5.1 Port There are two kinds of I/O port. * CMOS input (P00, P07) * CMOS input/output (P01 to P05, Port 1 to 3, 7 to 11) : 2 : 55 Total : 57 Table 5-1. Functions of Ports Name Pin Name P00, P07 Port 0 Function Dedicated input port 4 P01 to P05 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software . Port 1 P10 to P17 Input/output port. Input/output specifialbe bit-wise. When used as input port, on-chip pull-up resistor can be used in software . Port 2 P25 to P27 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software . Port 3 P30 to P37 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Port 7 P70 to P72 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. P80 to P87 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Input/output port/segment signal output function specifiable in 2-bit units by LCD control register (LCDC). Port 9 P90 to P97 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Input/output port/segment signal output function specifiable in 2-bit units by LCD control register (LCDC). Port 10 P100 to P103 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Direct LED drive capability. Port 11 P110 to P117 Input/output port. Input/output specifiable bit-wise. When used as input port, on-chip pull-up resistor can be used in software. Test flag (KRIF) is set to 1 by falling edge detection. Port 8 19 PD78062(A), 78063(A), 78064(A) 5.2 Clock Generator There are two kinds of clocks, main system clock and subsystem clock. The minimum instruction execution time can also be changed. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (main system clock: in 5.0 MHz operation) * 122 s (subsystem clock: in 32.768 kHz operation) Figure 5-1. Clock Generator Block Diagram XT1/P07 XT2 Subsystem Clock Oscillator fXT Watch Timer Clock Output Function Prescaler X1 X2 Main System Clock Oscillator fX Selector Prescaler fXX Clock to Peripheral Hardware 1/2 Scaler fX 2 fXX 2 fXX 22 fXX 23 fXX fXT 24 2 STOP Selector CPU Clock (fCPU) Standby Control Circuit To INTP0 Sampling Clock 5.3 Timer/Event Counter Five timer/event counter channels are incorporated. * 16-bit timer/event counter * 8-bit timer/event counter : 1 channel : 2 channels * Watch timer * Watchdog timer : 1 channel : 1 channel Table 5-2. Timer/Event Counter Types and Functions Type Function 20 Interval timer External event counter Timer output PWM output Pulse width measurement Square wave output One-shot pulse output 16-bit Timer/ Event Counter 8-bit Timer/ Event Counter Watch Timer Watchdog Timer 1 channel 1 channel 1 output 1 output 2 inputs 1 output 1 output 2 channels 2 channels 2 outputs - - 2 outputs - 1 channel - - - - - - 1 channel - - - - - - Interrupt request 2 2 2 1 Test input - - 1 input - PD78062(A), 78063(A), 78064(A) Figure 5-2. 16-Bit Timer/Event Counter Block Diagram Internal Bus INTP1 TI01/P01/INTP1 16-Bit Capture/Compare Register (CR00) Selector PWM Pulse Output Control Circuit Match Watch Timer Output 2fXX fXX fXX/22 TI00/P00/INTP0 Output Control Circuit 16-Bit Timer Register (TM0) Selector fXX/2 INTTM00 4 Clear Edge Detector TO0/P30 Selector Match INTTM01 INTP0 16-Bit Capture/Compare Register (CR01) Internal Bus Figure 5-3. 8-Bit Timer/Event Counter Block Diagram Internal Bus INTTM1 8-Bit Compare Register (CR10) 8-Bit Compare Register (CR20) Selector Match Match Output Control Circuit INTTM2 fXX/2-fXX/29 fXX/211 TO2/P32 Selector 8-Bit Timer Register 1 (TM1) TI1/P33 Clear Selector 8-Bit Timer Register 2 (TM2) Clear fXX/2-fXX/29 fXX/211 Selector Selector TI2/P34 Output Control Circuit TO1/P31 Internal Bus 21 PD78062(A), 78063(A), 78064(A) Figure 5-4. Watch Timer Block Diagram fW 214 fXX/27 Selector Selec- fW tor 5-Bit Counter Selector Prescaler fXT fW 24 fW 25 fW 26 fW 27 fW 28 INTWT fW 213 fW 29 INTTM3 Selector To 16-Bit Timer/Event Counter To LCD Controller/Driver Figure 5-5. Watchdog Timer Block Diagram fXX 23 Prescaler fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request 22 PD78062(A), 78063(A), 78064(A) 5.4 Clock Output Control Circuit Clocks of the following frequency can be output as clock outputs. * 19.5 kHz/39.1kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: in 5.0 kHz operation) * 32.768 kHz (subsystem clock: in 32.768 kHz operation) Figure 5-6. Clock Output Circuit Block Diagram fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXT 5.5 Synchronization Circuit Selector Output Control Circuit PCL/P35 4 Buzzer Output Control Circuit Clocks of the following frequency can be output as buzzer outputs. * 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock : in 5.0 MHz operation) Figure 5-7. Buzzer Output Control Circuit Block Diagram fXX/29 fXX/210 Selector Output Control Circuit BUZ/P36 fXX/211 23 PD78062(A), 78063(A), 78064(A) 5.6 A/D Converter Eight 8-bit resolution A/D converter channels are incorporated. The following two types of start-up method are available. * Hardware start * Software start Figure 5-8. A/D Converter Block Diagram Series Resistor String AVDD AVREF ANI0/P10 Sample & Hold Circuit ANI1/P11 ANI2/P12 Voltage Comparator ANI3/P13 ANI4/P14 Selector Tap Selector ANI5/P15 ANI6/P16 AVSS Successive Approximation Register (SAR) ANI7/P17 INTP3/P03 Edge Detector Control Circuit INTAD INTP3 A/D Conversion Result Register (ADCR) Internal Bus 5.7 Serial Interface Two clocked serial interface channels are incorporated. * Serial interface channel 0 * Serial interface channel 2 Table 5-3. Serial Interface Channel Block Diagram Function 3-wire serial I/O mode SBI (serial bus interface) mode 2-wire serial I/O mode Asynchronous serial interface (UART) mode 24 Serial Interface Channel 0 (MSB/LSB-first switchable) (MSB-first) (MSB-first) ---- Serial Interface Channel 2 (MSB/LSB-first switchable) ---- ---- (Dedicated baud rate generator incorpoorated) PD78062(A), 78063(A), 78064(A) Figure 5-9. Serial Interface Channel 0 Block Diagram Internal Bus SI0/SB0/P25 Selector Serial I/O Shift Register 0 (SIO0) Output Latch SO0/SB1/P26 Selector SCK0/P27 Busy/Acknowledge Output Circuit Bus Release/Command/ Acknowledge Detector Interrupt Request Signal Generator Serial Clock Counter INTCSI0 4 fXX/2-fXX/28 Serial Clock Control Circuit Selector TO2 Figure 5-10. Serial Interface Channel 2 Block Diagram Internal bus RXD/SI2/P70 Receive Buffer Register (RXB/SIO2) Direction Control Circuit Direction Control Circuit Transmit Shift Register (TXS/SIO2) Receive Shift Register (RXS) Transmit Control Circuit INTST TXD/SO2/P71 Receive Control Circuit INTSER INTSR/INTCSI2 SCK Output Control Circuit ASCK/SCK2/P72 Baud Rate Generator fXX-fXX/210 25 PD78062(A), 78063(A), 78064(A) 5.8 LCD Controller/Driver An LCD controller/driver with the following functions is incorporated. * Selection of 5 types of display mode * 16 of the segment signal of outputs can be switched to input/output ports in units of 2. (P80/S39 to P87/S32, P90/S31 to P97/S24) Table 5-4. Display Mode Types and Maximum Number of Display Pixels Bias Method Time Multiplexing Common Signal Used ---- Static 2 3 3 4 COM0 (COM1 to COM3) COM0, COM1 COM0 to COM2 COM0 to COM2 COM0 to COM3 1/2 1/3 Maximum Number of Display Pixels 40 (40 segments x 1 common) 80 (40 segments x 2 commons) 120 (40 segments x 3 commons) 160 (40 segments x 4 commons) Figure 5-11. LCD Controller/Driver Block Diagram Internal Bus fW 26 Prescaler Display Data Memory fW 29 Timing Controller Segment Data Selector LCDCL Selector Port Output Data LCD Drive Voltage Generator Common Driver Segment Driver S0 26 S23 S24/P97 S39/P80 COM0 COM1 COM2 COM3 VLC2 VLC1 VLC0 BIAS fW 28 fW 27 PD78062(A), 78063(A), 78064(A) 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 Interrupt Functions The following three types, 20 sources of interrupt functions are available: * Non-maskable : 1 * Maskable * Software : 18 : 1 27 PD78062(A), 78063(A), 78064(A) Table 6-1. Interrupt Source List Interrupt Type Default Priority Note1 Nonmaskable ---- Interrupt Source Name INTWDT Trigger Software Notes 1. 2. 28 Vector Table Address Internal 0004H Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) INTWDT 1 INTP0 0006H 2 INTP1 0008H 3 INTP2 (B) INTP3 5 INTP4 000EH 6 INTP5 0010H 7 INTCSI0 Serial interface channel 0 transfer termination 0014H 8 INTSER Serial interface channel 2 UART reception error generation 0018H INTSR Serial interface channel 2 UART reception termination INTCSI2 Serial interface channel 2 3-wire transfer termination 10 INTST Serial interface channel 2 UART transmission termination 11 INTTM3 Reference time interval signal from watch timer 12 INTTM00 16-bit timer register and capture/compare register (CR00) match signal generation 0020H 13 INTTM01 16-bit timer register and capture/compare register (CR01) match signal generation 0022H 14 INTTM1 8-bit timer/event counter 1 match signal generation 0024H 15 INTTM2 8-bit timer/event counter 2 match signal generation 0026H 16 INTAD A/D converter conversion termination 0028H BRK BRK instruction execution ---- (C) 000AH External 4 9 Basic Configuration Type Note2 (A) 0 Pin input edge detection Maskable Internal/ External 000CH (D) 001AH 001CH Internal ---- 001EH 003EH (B) (E) Default priority is a priority order when more than one maskable interrupt request is generated simultaneously. 0 is the highest and 16 the lowest. Basic configuration types (A) to (E) correspond to those shown in Figure 6-1. PD78062(A), 78063(A), 78064(A) Figure 6-1. Basic Configuration of Interrupt Functions (1/2) (A) Internal non-maskable interrupt Internal Bus Priority Control Circuit Interrupt Request Vector Table Address Generator Standby Release Signal (B) Intrnal maskable interrupt Internal Bus MK Interrupt Request IE PR ISP Priority Control Circuit IF Vector Table Address Generator Standby Release Signal (C) External maskable interrupt (INTP0) Internal Bus Interrupt Request Sampling Clock Select Register (SCS) External Interrupt Mode Register (INTM0) Sampling Clock Edge Detector MK IF IE PR Priority Control Circuit ISP Vector Table Address Generator Standby Release Signal 29 PD78062(A), 78063(A), 78064(A) Figure 6-1. Basic Configuration of Interrupt Functions (2/2) (D) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (INTM0, INTM1) Interrupt Request Edge Detector MK IE PR ISP Priority Control Circuit IF Vector Table Address Generator Standby Release Signal (E) Software interrupt Internal Bus Interrupt Request IF IE : Interrupt request flag : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 30 Priority Control Circuit Vector Table Address Generator PD78062(A), 78063(A), 78064(A) 6.2 Test Functions There are two sources of test functions as shown in Table 6-2. Table 6-2. Test Input Source List Test Input Source Trigger Name Internal/External INTWT Watch timer overflow Internal INTPT11 Port 11 falling edge detection External Figure 6-2. Basic Configuration of Test Function Internal Bus MK Test Input Signal IF Standby Release Signal IF : Test input flag MK : Test mask flag 31 PD78062(A), 78063(A), 78064(A) 7. STANDBY FUNCTION The standby function is a function to reduce the consumption current and there are the following two kinds of standby functions. HALT mode : Halts CPU operating clock and can reduce average consumption current by the intermittent operation along with the normal operation. STOP mode : Halts main system clock oscillation. Halts all operations with the main system clock and sets ultra-low consumption current state with subsystem clock only. Figure 7-1. Standby Function CSS=1 Subsystem Clock OperationNote Main System Clock Operation CSS=0 STOP Instruction Interrupt Request ( Note STOP Mode Main System Clock Oscillation Halted HALT Instruction HALT Instruction Interrupt Request Interrupt Request ) HALT Mode Clock Supply to CPU Halted, Oscillation Maintained ( ) HALT ModeNote Clock Supply to CPU Halted, Oscillation Maintained ( ) Halting the main system clock enables the consumption current to be reduced. When the CPU is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction is not available. Caution When the main system clock is stopped and the system is operated by the subsystem clock, the main system clock should be returned to after securing the oscillation stabilization time in software. 8. RESET FUNCTION There are the following two kinds of resetting methods. * External reset by RESET pin. * Internal reset by watchdog timer hung-up time detection. 32 PD78062(A), 78063(A), 78064(A) 9. INSTRUCTION SET (1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBS, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 2nd operand #byte A rNote sfr saddr !addr16 MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP PSW [DE] [HL] 1st operand MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV B, C sfr saddr !addr16 PSW MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP [HL+byte] [HL+B] $addr16 [HL+C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1 None ROR ROL RORC ROLC INC DEC DBNZ MOV MOV MOV [DE] [HL] MOV MOV [HL+byte] [HL+B] [HL+C] X C MOV DBNZ INC DEC PUSH POP ROR4 ROL4 MULU DIVUW Note Except r = A 33 PD78062(A), 78063(A), 78064(A) (2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd operand #word AX rpNote sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW None 1st operand ADDW SUBW CMPW MOVW A rp sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW XCHW MOVWNote INCW, DECW PUSH, POP MOVW MOVW MOVW MOVW Note Only when rp=BC, DE, HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd operand A.bit sfr.bit saddr.bit PSW.bits [HL].bit CY $addr16 None 1st operand A.bit MOV1 sfr.bit MOV1 saddr.bit MOV1 PSW.bit MOV1 [HL].bit MOV1 CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 (4) Call instruction/branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DNZB 2nd Operand AX !addr16 !addr11 [addr5] $addr16 1st Operand Basic instruction Compound Instruction BR CALL BR CALLF CALLT BR, BC, BNC, BZ, BNZ BT, BF, BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 34 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 PD78062(A), 78063(A), 78064(A) 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) Parameter Rating Unit VDD -0.3 to +7.0 V AVDD -0.3 to VDD + 0.3 V AVREF -0.3 to VDD + 0.3 V AVSS -0.3 to +0.3 V Input voltage VI -0.3 to VDD + 0.3 V Output voltage VO -0.3 to VDD + 0.3 V Analog input voltage VAN AVSS - 0.3 to AVREF + 0.3 V -10 mA -15 mA -15 mA Peak value 30 mA rms value 15 mA Peak value 100 mA rms value 70 mA Peak value 100 mA rms value 70 mA Peak value 50 mA rms value 20 mA Symbol Test Conditions Supply voltage P10 to P17 Analog input pin 1 pin Output current high IOH Total for P00 to P05, P07, P10 to P17, P100, P101 & P110 to P117 Total for P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P102 & P103 1 pin Total for P00 to P05, P10 to P17, P100, P101 & P110 to P117 Output current low IOL Note Total for P30 to P37, P102 & P103 Total for P25 to P27, P70 to P72, P80 to P87 & P90 to P97 Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Note The rms value should be calculated as follows: [rms value] = [Peak value] x Duty Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. The absolute maximum rating values must therefore be observed in using the product. Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. 35 PD78062(A), 78063(A), 78064(A) Permissible Inrush Current Characteristics of Pins on Application of Overvoltage (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Positive inrush current (VIN > VDD) Symbol IIJH1 Conditions 1 pin Input ports other than ANIn (n = 0 to 7) ANIn (n = 0 to 7)Note 1 IIJH2 IIJH3 IIJH4 Negative inrush current (VIN < VSS) IIJL1 Total of Input ports other than all input ANIn (n = 0 to 7) pins ANIn (n = 0 to 7)Note 2 1 pin Input ports other than ANIn (n = 0 to 7) IIJL2 IIJL3 IIJL4 ANIn (n = 0 to 7)Note 1 Total of Input ports other than all input ANIn (n = 0 to 7) pins ANIn (n = 0 to 7)Note 2 MIN. TYP. MAX. Unit Peak value 5.00 mA Mean value 0.50 mA Peak value 1.50 mA Mean value 0.15 mA Peak value 40.0 mA Mean value 4.00 mA Peak value 1.50 mA Mean value 0.15 mA Peak value -0.50 mA Mean value -0.05 mA Peak value -0.50 mA Mean value -0.05 mA Peak value -4.00 mA Mean value -0.40 mA Peak value -1.50 mA Mean value -0.15 mA Notes 1. If an inrush current flows to one analog input pin (ANIn: n = 0 to 7), the A/D conversion result of the analog input pin is the value when the inrush current does not flow 2 LSB. 2. If an inrush current flows to two or more analog input pins (ANIn: n = 0 to 7), the A/D conversion result of the analog input pin is the value when the inrush current does not flow 4 LSB. Remarks 1. The mean value (absolute value) of the inrush current of a pin can be calculated by the following expression: Mean value = ((1/T) T0 | i (t) | 3/2 dt)2/3 where i (t) is a pin inrush current, and the maximum value of |i (t)| is the peak value. 2. VIN is the input voltage applied to the pin. Capacitance (TA = 25 C, VDD = VSS = 0 V) Parameter Symbol Input capacitance CIN Output capacitance COUT I/O capacitance CIO 36 Test Conditions f = 1 MHz unmeasured pins returned to 0 V. MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF PD78062(A), 78063(A), 78064(A) Main System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Oscillator Recommended circuit X1 IC X2 Ceramic oscillator C2 IC Crystal resonator C2 C1 X1 X2 Parameter Test conditions Oscillator frequency (fX) Note1 V DD = Oscillator voltage range Oscillation stabilization time Note2 After VDD reaches oscillator voltage range MIN. Oscillator frequency (fX) Note1 MIN. TYP. 1 1 C1 Oscillation stabilization time Note2 X2 External clock PD74HCU04 X1 MAX. Unit 5 MHz 4 ms 5 MHz 10 V DD = 4.5 to 6.0 V ms 30 X1 input frequency (fX) Note1 1.0 5.0 MHz X1 input high/low level width (tXH , tXL) 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. If the main system clock oscillator is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program. 37 PD78062(A), 78063(A), 78064(A) Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 6.0 V) Resonator Parameter Recommended Circuit IC XT1 XT2 R2 Test Conditions Oscillator frequency (fXT) Note1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 Crystal resonator C3 C4 Oscillation stabilization time VDD = 4.5 to 6.0 V Note2 s 10 XT1 XT2 XT1 input frequency (fXT) Note1 32 100 kHz XT1 input high-/low-level width (tXTH/tXTL) 5 15 s External clock Notes 1. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. * Do not ground it to the ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, causing misoperation by noise more frequently than the main system clock oscillation circuit. Special care should therefore be taken to wiring method when the subsystem clock is used. 38 PD78062(A), 78063(A), 78064(A) Recommended Oscillator Constant Main system clock: ceramic oscillator (TA = -40 to +85 C) Manufacturer Murata Mfg. Co., Ltd. Matsushita Electronics Components Co., Ltd. Kyocera Corporation Product Name Frequency (MHz) Recommended Circuit Constant Oscillator Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) Remarks CSA5.00MG 5.00 30 30 2.2 6.0 CST5.00MGW 5.00 Built-in Built-in 2.7 6.0 EF0GC5004A4 5.00 Built-in Built-in 2.7 6.0 Lead type EF0EC5004A4 5.00 Built-in Built-in 2.0 6.0 Round lead type EF0EN5004A4 5.00 33 33 2.7 6.0 Lead type EF0S5004B5 5.00 Built-in Built-in 2.7 6.0 Chip type KBR-5.0MSA 5.00 33 33 2.7 6.0 Lead type PBRC5.00A 5.00 33 33 2.7 6.0 Chip type KBR-5.0MKS 5.00 Built-in Built-in 2.7 6.0 Lead type KBR-5.0MWS 5.00 Built-in Built-in 2.7 6.0 Chip type Subsystem clock: crystal resonator (TA = -40 to +60 C) Manufacturer Kyocera Corporation Product Name KF-38G-12P0200Note (Load capacitance 12 pF) Recommended Circuit Constant Frequency (kHz) 32.768 Oscillator Voltage Range C3 (pF) C4 (pF) R2 (k) MIN. (V) MAX. (V) 15 22 220 2.0 6.0 Note KF-38G-12P0200 is a maintenance product. Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 39 PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Symbol Test Conditions MAX. Unit 0.7 VDD VDD V 0.8 VDD VDD V 0.8 VDD VDD V 0.85 VDD VDD V VDD-0.5 VDD V VDD-0.2 VDD V 4.5 V VDD 6.0 V 0.8 VDD VDD V 2.7 V VDD < 4.5 V 0.9 VDD VDD V 2.0 V VDD < 2.7 V 0.9 VDD VDD V 0 0.3 VDD V 0 0.2 VDD V 0 0.2 VDD V 0 0.15 VDD V 0 0.4 V 0 0.2 V 4.5 V VDD 6.0 V 0 0.2 VDD V 2.7 V VDD < 4.5 V 0 0.1 VDD V 2.0 V VDD < 2.7 VNote 0 0.1 VDD V VDD = 4.5 to 6.0 V, IOH = -1 mA VDD-1.0 VDD V IOH = -100 A VDD-0.5 VDD V 2.0 V 0.4 V 0.2 VDD V 0.5 V P10 to P17, P30 to P32, VIH1 MIN. VDD = 2.7 to 6.0 V P35 to P37, P80 to P87, P90 to P97, P100 to P103 VIH2 P00 to P05, P25 to P27, P33, P34, P70 to P72, VDD = 2.7 to 6.0 V P110 to P117, RESET Input voltage high VDD = 2.7 to 6.0 V VIH3 VIH4 X1, X2 XT1/P07, XT2 P10 to P17, P30 to P32, VIL1 Note VDD = 2.7 to 6.0 V P35 to P37, P80 to P87, P90 to P97, P100 to P103 P00 to P05, P25 to P27, VIL2 Input voltage low VDD = 2.7 to 6.0 V VIL4 Output voltage high VDD = 2.7 to 6.0 V P33, P34, P70 to P72, P110 to P117, RESET VIL3 VOH X1, X2 XT1/P07, XT2 P100 to P103 VDD = 4.5 to 6.0 V, IOL = 15 mA P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P110 to P117 VDD = 4.5 to 6.0 V, IOL = 1.6 mA VOL2 SB0, SB1, SCK0 4.5 V VDD 6.0 V, open-drain, pulled high (R = 1 k) VOL3 IOL = 400 A VOL1 Output voltage low TYP. 0.4 Note When P07/XT1 is used as P07, the inverse phase of P07 should be input to XT2. Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. 40 PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Input leakage current high Input leakage current low Symbol Test Conditions MAX. Unit P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 3 A ILIH2 X1, X2, XT1/P07, XT2 20 A ILIL1 P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 -3 A X1, X2, XT1/P07, XT2 -20 A ILIH1 VI = VDD VI = 0 V ILIL2 MIN. TYP. Output leakage current high ILOH VO = VDD 3 A Output leakage current low ILOL VO = 0 V -3 A 90 k 500 k Software pull-up resistor R IDD1 VI = 0 V, P01 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 5.00 MHz, Crystal oscillation (fXX = 2.5 MHz)Note2 operating mode 5.00 MHz, Crystal oscillation (fXX = 5.0 MHz)Note3 operating mode Supply currentNote1 IDD2 5.00 MHz, Crystal oscillation (fXX = 2.5 MHz)Note2 HALT mode 5.00 MHz, Crystal oscillation (fXX = 5.0 MHz)Note3 HALT mode 4.5 V VDD 6.0 V 15 2.7 V V DD < 4.5 V 20 VDD = 5.0 V 10 %Note4 40 4 12 mA VDD = 3.0 V 10 % Note5 0.6 1.8 mA VDD = 2.2 V 10 % Note5 0.35 1.05 mA VDD = 5.0 V 10 % Note4 6.5 19.5 mA VDD = 3.0 V 10 % Note5 0.8 2.4 mA VDD = 5.0 V 10 % 1.4 4.2 mA VDD = 3.0 V 10 % 500 1500 A VDD = 2.2 V 10 % 280 840 A VDD = 5.0 V 10 % 1.6 4.8 mA VDD = 3.0 V 10 % 650 1950 A Notes 1. Not including currents flowing in on-chip pull-up resistors or LCD split resistors. 2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 3. Main system clock fXX = fX operation (when OSMS is set to 01H) 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 5. Low-speed mode operation (when PCC is set to 04H) Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. 41 PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Symbol Test Conditions IDD3 32,768 kHz, Crystal oscillation operating modeNote2 IDD4 32,768 kHz, Crystal oscillation HALT modeNote2 IDD5 XT1 = VDD STOP mode When feedback resistor is connected IDD6 XT1 = VDD STOP mode When feedback resistor is disconnected Supply currentNote1 MIN. VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD = = = = = = = = = = = = 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 5.0 3.0 2.2 V V V V V V V V V V V V 10 10 10 10 10 10 10 10 10 10 10 10 % % % % % % % % % % % % Notes 1. Not including currents flowing in on-chip pull-up resistors or LCD split resistors. 2. When the main system clock is stopped. 42 TYP. MAX. Unit 60 32 24 25 5 2.5 1 0.5 0.3 0.1 0.05 0.05 120 64 48 55 15 12.5 30 10 10 30 10 10 A A A A A A A A A A A A PD78062(A), 78063(A), 78064(A) DC Characteristics (TA = -10 to +85 C) (1) Static display mode (VDD = 2.0 to 6.0 V) Parameter LCD drive voltage LCD split resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Note Symbol Test Conditions VLCD RLCD VODC IO = 5 A VODS IO = 1 A 2.0 V VLCD VDD VLCD0 = VLCD MIN. TYP. MAX. Unit 2.0 60 100 VDD 150 V k 0 0.2 V 0 0.2 V The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). (2) 1/3 bias method (VDD = 2.5 to 6.0 V) Parameter Symbol LCD drive voltage VLCD LCD split resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) RLCD Note Test Conditions VODC IO = 5 A VODS IO = 1 A 2.5 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 MIN. TYP. MAX. Unit 2.5 60 100 VDD 150 V k 0 0.2 V 0 0.2 V The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). (3) 1/2 bias method (VDD = 2.7 to 6.0 V) Parameter LCD drive voltage LCD split resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) Note Symbol Test Conditions VLCD RLCD VODC IO = 5 A VODS IO = 1 A 2.7 V VLCD VDD VLCD0 = VLCD VLCD1 = VLCD x 1/2 VLCD2 = VLCD1 MIN. TYP. MAX. Unit 2.7 60 100 VDD 150 V k 0 0.2 V 0 0.2 V The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (VLCDn; n = 0, 1, 2). 43 PD78062(A), 78063(A), 78064(A) AC Characteristics (1) Basic operation (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) Parameter Cycle time (Minimum instruction execution time) Symbol Test Conditions Operating on main system clock MIN. VDD = 2.7 to 6.0 V 0.8 2.2 0.4 0.8 40Note3 0 TYP. MAX. Unit 64 64 32 32 125 1/tTI00 s s s s s MHz TI00 input frequency fTI00 (fXX = 2.5 MHz) Note1 Operating on main system clock (fXX = 5.0 MHz) Note2 Operating on subsystem clock tTI00 = tTIH00 + tTIL00 TI00 input high/ low-level width fTIH00, 4.5 V VDD 6.0 V 2/fsam+0.1Note 4 s tTIL00 2.7 V VDD < 4.5 V 2/fsam+0.2Note 4 s 2.0 V VDD < 2.7 V 2/fsam+0.5Note 4 s s TCY 4.5 VDD 6.0 V 2.7 VDD < 4.5 V 122 TI01 input high/ low-level width fTIH01, tTIL01 2.7 V VDD 6.0 V 10 TI1, TI2 input high/ low-level width fTI1 VDD = 4.5 to 6.0 V 20 0 4 s MHz 0 275 kHz TI1, TI2 input high/ low-level width tTIH1, Interrupt input high/low-level width tINTH, RESET low level width Notes 1. 2. 3. 4. VDD = 4.5 to 6.0 V tTIL1 tINTL tRSL INTP0 INTP1 to INTP5, P110 to P117 VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V ns 1.8 s 8/fsamNote4 10 20 10 20 s s s s s Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) Main system clock fXX = fX operation (when OSMS is set to 01H) This is the value when the external clock is used. The value is 114 s (min.) when the crystal resonator is used. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4). 44 100 PD78062(A), 78063(A), 78064(A) TCY vs VDD (At main system clock fXX = fX/2 operation) TCY vs VDD (At main system clock fXX = fX operation) 60 60 Cycle Time TCY [ s] Cycle Time TCY [ s] 32 10 Guaranteed Operation Range 2.0 10 Guaranteed Operation Range 2.0 1.0 0.8 1.0 0.8 0.4 0.4 0 1 2 3 4 5 Supply Voltage VDD [V] 6 0 1 2 3 4 5 6 Supply Voltage VDD [V] 45 PD78062(A), 78063(A), 78064(A) (2) Serial Interface (TA = -40 to +85 C, VDD = 2.0 to 6.0 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output) Parameter Symbol SCK0 cycle time tKCY1 SCK0 high/low-level width tKH1, tKL1 SI0 setup time (to SCK0) tSIK1 SI0 hold time (from SCK0) tKSI1 SO0 output delay time from SCK0 tKSO1 Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V VDD = 4.5 to 6.0 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. Unit 800 1600 3200 tKCY1/2-50 tKCY1/2-100 100 150 300 ns ns ns ns ns ns ns ns 400 ns C = 100 pFNote 300 ns MAX. Unit Note C is the load capacitance of SCK0, SO0 output line. (ii) 3-wire serial I/O mode (SCK0...External clock input) Parameter Symbol Test Conditions SCK0 cycle time tKCY2 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK0 high/low-level width tKH2, tKL2 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SI0 setup time (to SCK0) MIN. TYP. 800 1600 3200 400 800 1600 ns ns ns ns ns ns tSIK2 100 ns SI0 hold time (from SCK0) tKSI2 400 ns SO0 output delay time from SCK0 tKSO2 SCK0 rise, fall time C = 100 pFNote tR2, tF2 Note C is the load capacitance of SO0 output line. 46 300 ns 1000 ns PD78062(A), 78063(A), 78064(A) (iii) SBI mode (SCK0...Internal clock output) Parameter Symbol Test Conditions VDD = 4.5 to 6.0 V SCK0 cycle time SCK0 high/low-level width MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY3/2-50 ns tKCY3/2-150 ns 100 ns 300 ns tKCY3/2 ns tKCY3 tKH3, VDD = 4.5 to 6.0 V tKL3 SB0, SB1 setup time (to SCK0) tSIK3 SB0, SB1 hold time (from SCK0) tKSI3 VDD = 4.5 to 6.0 V SB0, SB1 output delay time from SCK0 tKSO3 SB0, SB1 from SCK0 tKSB tKCY3 ns SCK0 from SB0, SB1 tSBK tKCY3 ns SB0, SB1 high-level width tSBH tKCY3 ns SB0, SB1 low-level width tSBL tKCY3 ns R = 1 k , VDD = 4.5 to 6.0 V C = 100 pFNote 0 250 ns 0 1000 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. (iv) SBI mode (SCK0...External clock input) Parameter Symbol Test Conditions VDD = 4.5 to 6.0 V SCK0 cycle time SCK0 high/low-level width MIN. TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 300 ns tKCY4/2 ns tKCY4 tKH4, VDD = 4.5 to 6.0 V tKL4 SB0, SB1 setup time (to SCK0) tSIK4 SB0, SB1 hold time (from SCK0) tKSI4 VDD = 4.5 to 6.0 V SB0, SB1 output delay time from SCK0 tKSO4 SB0, SB1 from SCK0 tKSB tKCY4 ns SCK0 from SB0, SB1 tSBK tKCY4 ns SB0, SB1 high-level width tSBH tKCY4 ns SB0, SB1 low-level width tSBL tKCY4 ns SCK0 rise, fall time tR4, tF4 R = 1 k , C = 100 pF VDD = 4.5 to 6.0 V Note 0 300 ns 0 1000 ns 1000 ns Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. 47 PD78062(A), 78063(A), 78064(A) (v) 2-wire serial I/O mode (SCK0... Internal clock output) Parameter Symbol SCK0 cycle time tKCY5 SCK0 high-level width tKH5 SCK0 low-level width tKL5 SB0, SB1 setup time (to SCK0) tSIK5 SB0, SB1 hold time (from SCK0) tKSI5 SB0, SB1 output delay time from SCK0 tKSO5 Test Conditions VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V R = 1 k, C = 100 pFNote VDD = 4.5 to 6.0 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. Unit 1600 3200 tKCY5/2-160 tKCY5/2-190 tKCY5/2-50 tKCY5/2-100 300 350 400 ns ns ns ns ns ns ns ns ns 600 ns 300 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0... External clock input) Parameter Symbol Test Conditions TYP. MAX. Unit 1600 3200 650 1300 800 1600 ns ns ns ns ns ns tSIK6 100 ns SB0, SB1 hold time (from SCK0) tKSI6 tKCY6/2 ns SB0, SB1 output delay time from SCK0 tKSO6 SCK0 rise, fall time tR6, tF6 SCK0 cycle time tKCY6 SCK0 high-level width tKH6 SCK0 low-level width tKL6 SB0, SB1 setup time (to SCK0) VDD = 2.7 to 6.0 V MIN. VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V R = 1 k, VDD = 4.5 to 6.0 V C = 100 pFNote 0 0 Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. 48 300 500 ns ns 1000 ns PD78062(A), 78063(A), 78064(A) (b) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2... Internal clock output) Parameter Symbol SCK2 cycle time tKCY7 SCK2 high/low-level width tKH7, tKL7 SI2 setup time (to SCK2) tSIK7 SI2 hold time (from SCK2) tKSI7 SO2 output delay time from SCK2 tKSO7 Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V VDD = 4.5 to 6.0 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. Unit 800 1600 3200 tKCY1/2-50 tKCY1/2-100 100 150 300 ns ns ns ns ns ns ns ns 400 ns C = 100 pFNote 300 ns MAX. Unit Note C is the load capacitance of SCK2, SO2 output line. (ii) 3-wire serial I/O mode (SCK2...External clock input) Parameter Symbol Test Conditions 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V MIN. TYP. 800 1600 3200 400 800 1600 ns ns ns ns ns ns tSIK8 100 ns SI2 hold time (from SCK2) tKSI8 400 ns SO2 output delay time from SCK2 tKSO8 SCK2 cycle time tKCY8 SCK2 high/low-level width tKH8, tKL8 SI2 setup time (to SCK2) SCK2 rise, fall time 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V C = 100 pFNote tR8, tF8 300 ns 1000 ns Note C is the load capacitance of SO2 output line. 49 PD78062(A), 78063(A), 78064(A) (iii) UART mode (Dedicated baud rate generator output) Parameter Symbol Test Conditions MIN. TYP. 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V Transfer rate MAX. Unit 78125 39063 19531 bps bps bps MAX. Unit 39063 19531 9766 ns ns ns ns ns ns bps bps bps 1000 ns (iv) UART mode (External clock input) Parameter Symbol ASCK cycle time tKCY9 ASCK high/low-level width tKH9, tKL9 50 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V Transfer rate ASCK rise, fall time Test Conditions tR9, tF9 MIN. TYP. 800 1600 3200 400 800 1600 PD78062(A), 78063(A), 78064(A) AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test Points Clock Timing 1/fX tXL tXH VIH3 (MIN.) VIL3 (MAX.) X1 Input 1/fXT tXTL tXTH VIH4 (MIN.) VIL4 (MAX.) XT1 Input TI Timing tTIL00, tTIL01 tTIH00, tTIH01 TI00, TI01 1/fTI1 tTIL1 tTIH1 TI0-TI2 51 PD78062(A), 78063(A), 78064(A) Serial Transfer Timing 3-wire serial I/O mode: tKCY 1, 2, 7, 8 tKL1, 2, 7, 8 tKH1, 2, 7, 8 tR2, 8 tF2, 8 SCK0, SCK2 tSIK1, 2, 7, 8 tKSI1, 2, 7, 8 SI0, SI2 Input Data tKSO1, 2, 7, 8 SO0, SO2 Output Data SBI mode (bus release signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBL tSBK tSBH tSIK3, 4 tKSI3, 4 SB0, SB1 tKSO3, 4 SBI mode (command signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBK tSIK3, 4 SB0, SB1 tKSO3, 4 52 tKSI3.4 PD78062(A), 78063(A), 78064(A) 2-wire serial I/O mode: tKCY5.6 tKL5, 6 tKH5, 6 tR6 tF6 SCK0 tSIK5, 6 tKSI5, 6 tKSO5, 6 SB0, SB1 UART mode: tKCY9 tKL9 tKH9 tR9 tF9 ASCK A/D Converter (TA = -40 to +85 C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions Resolution MIN. TYP. MAX. Unit 8 8 8 bit 0.6 % 1.4 % 200 s 2.7 V AVREF 6.0 V Overall error Note Conversion time tCONV 19.1 Sampling time tSAMP 12/fXX Analog input voltage VIAN AVSS AVREF V Reference voltage AVREF 2.0 AVDD V AVREF-AVSS resistance RAIREF 4 s 14 k Note Quantization error (1/2 LSB) is not included. This is expressed in proportion to the full-scale value. 53 PD78062(A), 78063(A), 78064(A) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85 C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time tSREL Oscillation stabilization wait time Test Conditions MIN. TYP. 1.8 VDDDR = 1.8 V Subsystem clock stopped and feed-back resistor disconnected 0.1 MAX. Unit 6.0 V 10 A s 0 Release by RESET 217/fx ms Release by interrupt Note ms tWAIT Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible. Data retention timing (STOP mode release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data retention timing (STOP mode release by standby release signal: Interrupt signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 54 PD78062(A), 78063(A), 78064(A) Interrupt input timing tINTL tINTH INTP0-INTP5 RESET input timing tRSL RESET 55 PD78062(A), 78063(A), 78064(A) 11. CHARACTERISTIC CURVES (REFERENCE VALUES) IDD vs VDD (Main System Clock: 5.0 MHz) (TA = 25 C) 10.0 PCC=00H PCC=01H 5.0 PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation) 1.0 Supply Current IDD (mA) 0.5 0.1 PCC=B0H 0.05 HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation) 0.01 f XX = 5.0 MHz f XT = 32.768 kHz 0.005 0.001 0 1 2 3 4 Supply Voltage VDD (V) 56 5 6 7 8 PD78062(A), 78063(A), 78064(A) IDD vs VDD (Main System Clock: 2.5 MHz) (TA = 25 C) 10.0 5.0 PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation) 1.0 Supply Current IDD (mA) 0.5 0.1 PCC=B0H 0.05 HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation) 0.01 f XX = 2.5 MHz f XT = 32.768 kHz 0.005 0.001 0 1 2 3 4 5 6 7 8 Supply Voltage VDD (V) 57 PD78062(A), 78063(A), 78064(A) 12. PACKAGE DRAWINGS 100 PIN PLASTIC QFP (FINE PITCH) ( 14) A B 75 76 51 50 F Q R S D C detail of lead end 26 25 100 1 G H I M J M P K N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. Remark Dimensions and materials of ES products are same as those of mass production product. ITEM MILLIMETERS INCHES A 16.00.2 B 14.00.2 0.6300.008 0.551 +0.009 -0.008 C 14.00.2 0.551 +0.009 -0.008 D 16.00.2 0.6300.008 F G 1.0 1.0 H 0.22 +0.05 -0.04 I 0.10 J 0.5 (T.P.) K 1.00.2 0.039 +0.009 -0.008 L 0.50.2 0.020 +0.008 -0.009 M 0.17 +0.03 -0.07 0.007 +0.001 -0.003 N 0.10 P 1.45 0.057 Q 0.1250.075 0.0050.003 R S 55 1.7 MAX. 0.039 0.039 0.0090.002 0.004 0.020 (T.P.) 0.004 55 0.067 MAX. P100GC-50-7EA-2 58 PD78062(A), 78063(A), 78064(A) 100 PIN PLASTIC QFP (14 x 20) A B Q F G H I M 55 31 30 S 100 1 detail of lead end D 51 50 C 80 81 J M P K N L P100GF-65-3BA1-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark Dimensions and materials of ES products are same as mass production product. ITEM MILLIMETERS INCHES A 23.6 0.4 0.929 0.016 B 20.0 0.2 0.795+0.009 -0.008 C 14.0 0.2 0.551+0.009 -0.008 D 17.6 0.4 0.693 0.016 F 0.8 0.031 G 0.6 0.024 H 0.30 0.10 0.012+0.004 -0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8 0.2 0.071+0.008 -0.009 L 0.8 0.2 0.031+0.009 -0.008 M 0.15+0.10 -0.05 0.006+0.004 -0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 0.1 0.004 0.004 S 3.0 MAX. 0.119 MAX. 59 PD78062(A), 78063(A), 78064(A) 100 PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I M J K P M N NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. Remark Dimensions and materials of ES products are same as mass production product. L ITEM MILLIMETERS INCHES A 16.000.20 0.6300.008 B 14.000.20 0.551 +0.009 -0.008 C 14.000.20 0.551 +0.009 -0.008 D 16.000.20 0.6300.008 F 1.00 0.039 G 1.00 0.039 H 0.22 +0.05 -0.04 0.0090.002 I 0.08 0.003 J 0.50 (T.P.) 0.020 (T.P.) K 1.000.20 0.039 +0.009 -0.008 L 0.500.20 0.020 +0.008 -0.009 M 0.17 +0.03 -0.07 0.007 +0.001 -0.003 N 0.08 0.003 P 1.400.05 0.0550.002 Q 0.100.05 0.0040.002 R 3 +7 -3 3 +7 -3 S 1.60 MAX. 0.063 MAX. S100GC-50-8EU 60 PD78062(A), 78063(A), 78064(A) 13. RECOMMENDED SOLDERING CONDITIONS The PD78062(A)/78063(A)/78064(A) should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 13-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD78062GC(A)-xxx-7EA : 100-pin plastic QFP (Fine pitch) PD78063GC(A)-xxx-7EA : 100-pin plastic QFP (Fine pitch) (14 x 14mm, resin thickness: 1.45 mm) (14 x 14mm, resin thickness: 1.45 mm) PD78064GC(A)-xxx-7EA : 100-pin plastic QFP (Fine pitch) (14 x 14mm, resin thickness: 1.45 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125C) <precaution> Baking cannot be applied to other than heat-resistant trays (magazine, taping, nonheat-resistant trays) when the product is wrapped. IR35-107-2 VPS Package peak temperature: 215C, Duration: 40 sec. (at 200C or above), Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125C) <precaution> Baking cannot be applied to other than heat-resistant trays (magazine, taping, nonheat-resistant trays) when the product is wrapped. VP15-107-2 Partial heating Pin temperature: 300C max. Duration: 3 sec. max. (per device side) -- Note For the storage period after dry-pack decapsulation, storage conditions are max. 25C, 65% RH. (2) PD78062GF(A)-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD78063GF(A)-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD78064GF(A)-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Thrice max. IR35-00-3 VPS Package peak temperature: 215C, Duration: 40 sec. (at 200C or above), Number of times: Thrice max. VP15-00-3 Wave soldering Solder bath temperature: 260C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120C max. (Package surface temperature) WS60-00-1 Partial heating Pin temperature: 300C max. Duration: 3 sec. max. (per device side) -- Cautions 1. Use of more than one soldering method should be avoided (except in the case of partial heating). 2. The PD78062GC(A)-xxx-8EU, 78063GC(A)-xxx-8EU, and 78064GC(A)-xxx-8EU are under planning. Therefore, soldering conditions for these products have not been specified. 61 PD78062(A), 78063(A), 78064(A) APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using PD78062(A)/78063(A)/78064(A). Language Processing Software RA78K/0 Note 1, 2, 3, 4 78K/0 series common assembler package CC78K/0 Note 1, 2, 3, 4 78K/0 series common C compiler package DF78064 Note 1, 2, 3, 4 PD78064 subseries device file CC78K/0-L Note 1, 2, 3 ,4 78K/0 series common C compiler library source file PROM Writing Tools PG-1500 PROM programmer PA-78P0308GC (or PA-78P064GC) PA-78P0308GF (or PA-78P064GF) PA-78P0308KL-T Programmer adapters connected to PG-1500 PG-1500 controller Notes 1, 2 PG-1500 control program Debugging Tools IE-78000-R 78K/0 series common in-circuit emulator IE-78000-R-A 78K/0 series common in-circuit emulator (for integrated debugger) IE-78000-R-BK 78K/0 series common break board IE-78064-R-EM Note 8 PD78064 subseries evaluation emulation board IE-780308-R-EM PD780308 subseries common emulation board IE-78000-R-SV3 Interface adapter and cable when EWS is used as host machine (for IE-78000-R-A) IE-70000-98-IF-B Interface adapter when PC-9800 series (except notebook type) is used as host machine (for IE78000-R-A) IE-70000-98N-IF Interface adapter and cable when notebook type PC-9800 series is used as host machine (for IE78000-R-A) IE70000-PC-IF-B Interface adapter when IBM PC/ATTM is used as host machine (IE-78000-R-A) EP-78064GC-R EP-78064GF-R PD78064 subseries common emulation probes TGC-100SDW Adapter to be mounted on a target system board made for 100-pin plastic QFP (GC-7EA, GC-8EU type) TGC-100SDW is a product from Tokyo Eletech Corp. (TEL (03) 5295-1661) When purchasing this product, please consult with our sales offices. EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) SM78K0 Note 5, 6, 7 78K/0 series common system simulator ID78K0 62 Note 4, 5, 6, 7 IE-78000-R-A integrated dubugger SD78K/0 Note 1, 2 IE-78000-R screen debugger DF78064 Note 1, 2, 4, 5, 6, 7 PD78064 subseries device file PD78062(A), 78063(A), 78064(A) Real-Time OS RX78K/0 Note 1, 2, 3, 4 78K/0 series real-time OS MX78K0 Note 1, 2, 3, 4 78K/0 series OS Fuzzy Inference Development Support System FE9000 Note 1, FE9200 Note 6 Fuzzy knowledge data creation tool FT9080 Note 1, FT9085 Note 2 Translator FI78K/0 Note 1, 2 Fuzzy inference module FD78K/0 Note 1, 2 Fussy inference debugger Notes 1. PC-9800 series (MS-DOSTM) based 2. 3. IBM PC/AT and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based HP9000 series 300TM (HP-UXTM) based 4. 5. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based PC-9800 series (MS-DOS + WindowsTM) based. 6. 7. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based NEWSTM (NEWS-OSTM) based 8. IE-78064-R-EM is a maintenance product. Remarks 1. 2. For third party development tools, refer to the 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78064. 63 PD78062(A), 78063(A), 78064(A) APPENDIX B. RELATED DOCUMENTS Device Related Documents Document No. Document Name Japanese English PD78062(A), 78063(A) 78064(A) Data Sheet U10335J This document PD78064, 78064Y Subseries User's Manual U10105J U10105E 78K/0 Series User's Manual - Instruction U12326J IEU-1372 78K/0 Series Instruction Table U10903J -- 78K/0 Series Instruction Set U10904J -- PD78018F Subseries Special Function Register Table IEM-5568 -- Fundamental (III) IEA-767 U10182E Floating-Point Arithmetic Program IEA-718 IEA-1289 78K/0 Series Application Note Development Tools Related Documents (User's Manual) (1/2) Document No. Document Name Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation U11802J U11802E Assembly Language U11801J U11801E Structured Assembly Language U11789J U11789E Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Operation U11517J U11517E Language U11518J U11518E Programming Know-how EEA-618 EEA-1208 CC78K Series Library Source File U12322J -- IE-78000-R EEU-810 U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-78064-R-EM EEU-905 EEU-1443 IE-780308-R-EM U11362J U11362E EP-78064 EEU-934 EEU-1469 RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package CC78K Series C Compiler CC78K/0 C Compiler CC78K/0 C Compiler Application Note Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 64 PD78062(A), 78063(A), 78064(A) Development Tools Documents (User's Manual) (2/2) Document No. Document Name Japanese English SM78K Series System Simulator External Components User Open Interface U10092J U10092E SM78K0 System Simulator Windows Based Reference U10181J U10181E ID78K0 Integrated Debugger EWS Based Reference U11515J -- ID78K0 Integrated Debugger PC Based Reference U11539J U11539E ID78K0 Integrated Debugger Windows Based Guide U11649J U11649E SD78K/0 Screen Debugger Introduction EEU-852 U10539E PC-9800 Series (MS-DOS) Based Reference U10952J -- SD78K/0 Screen Debugger Introduction EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Based Reference U11279J U11279E Embedded Software Documents (User's Manual) Document No. Document Name Japanese English Fundamental U11537J -- Installation U11536J -- Fundamental U12257J -- Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System EEU-862 EEU-1444 EEU-858 EEU-1441 EEU-921 EEU-1458 78K/0 Series Real-Time OS 78K/0 Series OS MX78K0 - Translator 78K/0 Series Fuzzy Inference Development Suport System - Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System - Fuzzy Inference Debugger Other Documents Document No. Document Name Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 -- Guide to Quality Assurance for Semiconductor Device C11893J C11893E Guide for Products Related to MicroComputer: Other Companies U11416J -- Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 65 PD78062(A), 78063(A), 78064(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 66 PD78062(A), 78063(A), 78064(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 67 PD78062(A), 78063(A), 78064(A) FIP is a registered trademark of NEC Corporation. IEBus is a trademark of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM-DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. Some of related document may be preliminary, but is not marked as such. Please keep this in mind as you refer to this information. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5