IS34MW04G084/164 IS35MW04G084/164 4Gb SLC-4b ECC 1.8V X8/X16 NAND FLASH MEMORY STANDARD NAND INTERFACE IS34/35MW04G084/164 4Gb(x8/x16) 1.8V NAND FLASH MEMORY with 4b ECC FEATURES - Flexible & Efficient Memory Architecture - Command/Address/Data Multiplexed I/O Interface - Command Register Operation - Automatic Page 0 Read at Power-Up Option - Boot from NAND support - Automatic Memory Download - NOP: 4 cycles - Cache Program Operation for High Performance Program - Cache Read Operation - Copy-Back Operation - EDO mode - OTP operation - Two-Plane Operation - Bad-Block-Protect - Memory Cell: 1bit/Memory Cell - Organization: 512Mb x8 /256Mb x16 - X8: - Memory Cell Array: (512M + 16M) x 8bit - Data Register: (2K + 64) x 8bit - Page Size: (2K + 64) Byte - Block Erase: (128K + 4K) Byte - X16: - Memory Cell Array: (256M + 8M) x 16bit - Data Register: (1K + 32) x 16bit - Page Size: (1K + 32) Byte - Block Erase: (64K + 2K) Byte Efficient Read and Program modes Highest performance - Read Performance - Random Read: 25us (Max.) - Serial Access: 45ns (Max.) - Write Performance - Program time: 300us - typical - Block Erase time: 3ms - typical - Low Power with Wide Temp. Ranges Single 1.8V (1.7V to 1.95V) Voltage Supply 15 mA Active Read Current 10 A Standby Current T emp Grades: - Industrial: -40C to +85C - Extended: -40C to +105C (1) - Automotive, A1: -40C to +85C - Automotive, A2: -40C to +105C (1) Advanced Security Protection - Hardware Data Protection: - Program/Erase Lockout during Power Transitions Industry Standard Pin-out & Packages - T =48-pin TSOP 1 Note: 1. Call Factory - Reliable CMOS Floating Gate Technology - ECC Requirement: X8 - 4bit/512Byte X16 - 4bit/256Word Endurance: 100K Program/Erase cycles Data Retention: 10 years - Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 2 IS34/35MW04G084/164 GENERAL DESCRIPTION The IS34/35MW4G084/164 are 512Mx8/256Mx16 bit with spare 16Mx8/8Mx16 bit capacity. The devices are offered in 1.8V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 4,096 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2,112-Byte page in typical 300us and an erase operation can be performed in typical 3ms on a 128K-Byte for X8 device block (or 64KWord for x16 device block). Data in the page mode can be read out at 45ns cycle time per Word. The I/O pins serve as the ports for address and command inputs as well as data input/output. The copy back function allows the optimization of defective blocks management: when a page program operation fails, the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The cache program feature allows the data insertion in the cache register while the data register is copied into the Flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improving the read throughput when consecutive pages have to be streamed out. This device includes extra feature: Automatic Read at Power Up. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 3 IS34/35MW04G084/164 TABLE OF CONTENTS FEATURES ............................................................................................................................................................ 2 GENERAL DESCRIPTION .................................................................................................................................... 3 TABLE OF CONTENTS ......................................................................................................................................... 4 1. PIN CONFIGURATION ................................................................................................................................... 6 2. PIN DESCRIPTIONS ...................................................................................................................................... 7 3. BLOCK DIAGRAM .......................................................................................................................................... 8 4. OPERATION DESCRIPTION ....................................................................................................................... 12 5. ELECTRICAL CHARACTERISTICS............................................................................................................. 14 5.1 ABSOLUTE MAXIMUM RATINGS (1) ..................................................................................................... 14 5.2 Recommended Operating Conditions .................................................................................................... 14 5.3 DC CHARACTERISTICs ........................................................................................................................ 15 5.4 Valid Block .............................................................................................................................................. 15 5.5 AC Measurement Condition .................................................................................................................... 16 5.6 AC PIN CAPACITANCE (TA = 25C, VCC=1.8V, 1MHz) ...................................................................... 16 5.7 Mode Selection ....................................................................................................................................... 16 5.8 ROGRAM/ERASE PERFORMANCne .................................................................................................... 17 5.9 AC CHARACTERISTICS for address/ command/data input .................................................................. 17 5.10 AC CHARACTERISTICS for Operation ................................................................................................ 18 6. TIMING DIAGRAMS ..................................................................................................................................... 19 6.1 Command Latch Cycle ........................................................................................................................... 19 6.2 Address Latch Cycle ............................................................................................................................... 19 6.3 Input Data Latch Cycle ........................................................................................................................... 20 6.4 Serial Access Cycle after Read (CLE=L, WE#=H, ALE=L) .................................................................... 20 6.5 Serial Access Cycle after Read (EDO Type CLE=L, WE#=H, ALE=L) .................................................. 21 6.6 Status Read Cycle .................................................................................................................................. 21 6.7 Read Operation....................................................................................................................................... 22 6.8 Read Operation (Intercepted by CE#) .................................................................................................... 22 6.9 Random Data Output In a Page ............................................................................................................. 23 6.10 Page program Operation ...................................................................................................................... 23 6.11 Page Program Operation with Random Data Input .............................................................................. 24 6.12 Copy-Back Operation with Random Data InpuT .................................................................................. 24 6.13 Cache Program Operation .................................................................................................................... 25 6.14 Block Erase Operation .......................................................................................................................... 25 6.15 Cache Read Operation ......................................................................................................................... 26 6.16 Read ID Operation ................................................................................................................................ 27 6.17 TWo-plane Page Read Operation with Two-Plane Random Data Out ................................................ 28 6.18 two-plane Cache Read Operation ........................................................................................................ 29 6.19 Two-plane Program Operation ............................................................................................................. 31 Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 4 IS34/35MW04G084/164 6.20 two-plane Cache Program Operation ................................................................................................... 32 6.21 READ Two Plane Block Erase Operation ............................................................................................. 33 7. ID Definition Table ........................................................................................................................................ 34 8. DEVICE OPERATION .................................................................................................................................. 36 8.1 Page READ OPERATION ...................................................................................................................... 36 8.2 Page Program ......................................................................................................................................... 38 8.3 Cache Program ....................................................................................................................................... 39 8.4 Copy-Back Program................................................................................................................................ 40 8.5 Block Erase ............................................................................................................................................. 41 8.6 Read Status ............................................................................................................................................ 41 8.7 Read ID ................................................................................................................................................... 43 8.8 Reset ....................................................................................................................................................... 44 8.9 Cache Read ............................................................................................................................................ 45 8.10 Two-Plane Page Read .......................................................................................................................... 46 8.11 Two-Plane Cache Read ........................................................................................................................ 47 8.12 Two-Plane Page Program .................................................................................................................... 48 8.13 Two-Plane Copy Back Program ........................................................................................................... 49 8.14 Two-Plane Cache Program .................................................................................................................. 51 8.15 Two-Plane Block Erase ........................................................................................................................ 52 8.16 Ready/Busy#......................................................................................................................................... 53 8.17 Data Protection and Power Up Sequence ............................................................................................ 54 8.18 Write Protect Operation ........................................................................................................................ 55 9. INVALID BLOCK AND ERROR MANAGEMENT ......................................................................................... 57 9.1 Mask Out Initial Invalid Block(s)........................................................................................................... 57 9.2 Identifying Initial Invalid Block(s) and Block Replacement Management ............................................... 57 9.3 ERRor in Read or Write operation .......................................................................................................... 59 9.4 Addressing for PROGRAM operation ..................................................................................................... 64 9.5 System Interface Using CE# NOT Care operation ................................................................................. 65 10. PACKAGE TYPE INFORMATION ........................................................................................................... 66 10.1 48-Pin TSOP (TYPE I) Package (T) ..................................................................................................... 66 11. ORDERING INFORMATION - Valid Part Numbers ................................................................................ 67 Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 5 IS34/35MW04G084/164 1. PIN CONFIGURATION x16 x8 1 x8 x16 NC NC NC VSS NC NC NC I/O15 NC NC NC NC NC I/O7 NC I/O14 NC NC I/O7 I/O6 NC NC I/O6 I/O13 R/B# R/B# I/O5 I/O5 RE# RE# I/O4 I/O12 CE# CE# NC I/O4 NC NC NC NC NC NC NC NC VCC VCC 12 37 VCC VCC VSS VSS 13 36 VSS NC NC NC NC NC NC NC NC NC CLE CLE NC I/O11 ALE ALE I/O3 I/O3 WE# WE# I/O2 I/O10 WP# WP# I/O1 I/O2 NC NC I/O0 I/O9 NC NC NC I/O1 NC NC NC I/O8 NC NC NC I/O0 NC NC NC VSS 48-pin TSOP (Type I) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 6 IS34/35MW04G084/164 2. PIN DESCRIPTIONS Pin Name Pin Function DATA INPUTS/OUTPUTS I/O0 ~ I/O7 (X8) I/O0 ~ I/O15 (X16) The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the internal command registers. Commands are latched into the command register through the I/O ports on the rising edge of the WE# signal with CLE high. ALE CE# ADDRESS LATCH ENABLE The ALE input controls the activating path for addresses sent to the internal address registers. Addresses are latched into the address register through the I/O ports on the rising edge of WE# with ALE high. CHIP ENABLE The CE# input is the device selection control. When the device is in the Busy state, CE# high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE# control during read operation, refer to 'Page read' section of Device operation. RE# READ ENABLE The RE# input is the serial data-out control, and when it is active low, it drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE# which also increments the internal column address counter by one. WE# WRITE ENABLE The WE# input controls writes to the I/O ports. Commands, address and data are latched on the rising edge of the WE# pulse. WP# WRITE PROTECT The WP# pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP# pin is active low. R/B# READY/BUSY OUTPUT The R/B# output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in progress and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. VCC POWER VCC is the power supply for device. VSS GROUND N.C. NO CONNECTION Lead is not internally connected. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 7 IS34/35MW04G084/164 3. BLOCK DIAGRAM CLE WP# RE# IO Port ALE WE# X-Decoder High Voltage Circuit CE# Control Logic R/B# IO[7:0] A12-A29 Address Counter A0-A11 Memory Array ( Two Planes for 4Gb) Page Buffer Y-Decoder Data Buffer Figure 3.1 Functional Block Diagram(x8) Figure 3.2 Array Organization(x8) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 8 IS34/35MW04G084/164 Table 3.1 ARRAY Address (x8) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Address 1st cycle A0 A1 A2 A3 A4 A5 A6 A7 Column Address 2nd A8 A9 A10 A11 *L *L *L *L Column Address 3rd cycle A12 A13 A14 A15 A16 A17 A18 A19 Row Address 4th cycle A20 A21 A22 A23 A24 A25 A26 A27 Row Address 5th cycle A28 A29 *L *L *L *L *L *L Row Address cycle Notes: 1. Column Address: Starting Address of the Register. 2. * L must be set to "Low". 3. The device ignores any additional input of address cycles than required. 4. A30 is Row address for 8G DDP. In case of 4G, A30 must be set to "Low". 4. A18 is for Plane Address setting. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 9 IS34/35MW04G084/164 CLE WP# RE# IO Port ALE WE# X-Decoder High Voltage Circuit CE# Control Logic R/B# IO[15:0] A11-A28 Address Counter A0-A10 Memory Array ( Two Planes for 4Gb) Page Buffer Y-Decoder Data Buffer Figure 3.3 Functional Block Diagram(x16) Figure 3.4 Array Organization(x8) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 10 IS34/35MW04G084/164 Table 3.2 ARRAY Address (x16) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Address 1st cycle A0 A1 A2 A3 A4 A5 A6 A7 Column Address 2nd A8 A9 A10 *L *L *L *L *L Column Address 3rd cycle A11 A12 A13 A14 A15 A16 A17 A18 Row Address 4th cycle A19 A20 A21 A22 A23 A24 A25 A26 Row Address 5th cycle A27 A28 *L *L *L *L *L *L Row Address cycle Notes: 1. Column Address: Starting Address of the Register. 2. *L must be set to "Low". 3. The device ignores any additional input of address cycles than required. 4. A29 is Row address for 8G DDP. In case of 4G, A29 must be set to "Low" 5. A17 is for Plane Address setting. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 11 IS34/35MW04G084/164 4. OPERATION DESCRIPTION The IS34/35MW04G084/164 are 4Gbit memory organized as 256K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 128K-byte blocks. It indicates that the bit-by-bit erase operation is prohibited on the device. The device has addresses multiplexed into 8 or 16 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE# to low while CE# is low. Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 12 IS34/35MW04G084/164 Table 4.1 Command Set 1st Cycle 2nd Cycle Read 00h 30h Read for Copy-Back 00h 35h Read ID 90h - Reset FFh - Page Program 80h 10h Copy-Back Program 85h 10h Block Erase 60h D0h 85h - 05h E0h Read Status 70h - O Read Status 2 F1h - O 60h-60h 30h 60h-60h 35h 00h-05h E0h Two-Plane Page Program(2) 80h-11h 81h-10h Two-Plane Copy-Back Program(2) 85h-11h 81h-10h Two-Plane Block Erase 60h-60h D0h Cache Program 80h 15h Cache Read 31h - Read Start For Last Page Cache Read 3Fh - Two-Plane Cache Read(3) 60h-60h 33h Two-Plane Cache Program (2) 80h-11h 81h-15h Function Random Data Input (1) Random Data Output (1) Two-Plane Read(3) Two-Plane Read for Copy-Back Two-Plane Random Data Output(1) (3) Acceptable Command during Busy O Notes: 1. Random Data Input/Output can be executed in a page. 2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh. 3. Two-Plane Random Data Output must be used after Two-Plane Read operation or Two-Plane Cache Read operation. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 13 IS34/35MW04G084/164 5. ELECTRICAL CHARACTERISTICS 5.1 ABSOLUTE MAXIMUM RATINGS (1) Storage Temperature Input Voltage with Respect to Ground on All Pins All I/O Voltage with Respect to Ground VCC -65C to +150C 240C 3 Seconds 260C 3 Seconds -0.6V to +4.6V -0.6V to VCC + 0.3V( < 4.6V) -0.6V to +4.6V Short Circuit Current Electrostatic Discharge Voltage (Human Body Model)(2) 5mA -2000V to +2000V Surface Mount Lead Soldering Temperature Standard Package Lead-free Package Notes: 1. Applied conditions greater than those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. ANSI/ESDA/JEDEC JS-001 5.2 RECOMMENDED OPERATING CONDITIONS Part Number Operating Temperature (Industrial Grade) Operating Temperature (Extended Grade) Operating Temperature (Automotive Grade A1) Operating Temperature (Automotive Grade A2) VCC Power Supply Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 IS34/35MW04G084/164 -40C to 85C -40C to 105C -40C to 85C -40C to 105C 1.7V (VMIN) - 1.95V (VMAX); 1.8V (Typ) 14 IS34/35MW04G084/164 5.3 DC CHARACTERISTICS (Under operating range) Parameter Page Read with Serial Access Operating Current Program Erase Symbol Test Conditions Min Typ. - 15 tRC=tRCMin, CE#=VIL, IOUT=0mA ICC1 ICC2 - - 15 ICC3 - - 15 Max 20 Stand-by Current (TTL) ISB1 CE#=VIH, WP#=0V/VCC - - 1 Stand-by Current (CMOS) ISB2 CE#=VCC-0.2, WP#=0V/VCC - 10 50 Unit mA Input Leakage Current ILI VIN=0 to Vcc (max) - - +/-10 Output Leakage Current ILO VOUT=0 to Vcc (max) - - +/-10 Input High Voltage VIH (1) 0.8xVCC - Vcc+0.3 Input Low Voltage, All inputs VIL (1) -0.3 - 0.2xVCC Output High Voltage Level VOH IOH=-100 uA - - Output Low Voltage Level VOL IOL=+100 uA - - 0.1 Output Low Current (R/B#) IOL (R/B#) VOL=0.2V 3 4 - uA V VCC-0.1 mA Notes: 1. VIL can undershoot to - 2V and VIH can overshoot to VCC + 2V for durations of 20 ns or less. 2. Typical value are measured at Vcc=1.8V, TA=25. Not 100% tested. 5.4 VALID BLOCK Parameter Symbol Min Typ. Max Unit NVB 4,016 - 4,096 Block IS34/35MW04G084/164 Notes: 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to be a valid block up to 1K program/erase cycles with 4bit/512Byte ECC. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 15 IS34/35MW04G084/164 5.5 AC MEASUREMENT CONDITION Symbol Parameter CL Output Load TR,TF Input Rise and Fall Times VIN Input Pulse Voltages VREFI VREFO Min Max Units 1 TTL GATE and CL = 30pF pF 5 ns 0V to VCC V Input Timing Reference Voltages 0.5VCC V Output Timing Reference Voltages 0.5VCC V Note: 1. Refer to 8.16 Ready/Busy#, R/B#'s Busy to Ready time is decided by pull up register (Rp) tied to R/B# pin. 5.6 AC PIN CAPACITANCE (TA = 25C, VCC=1.8V, 1MHZ) Symbol Parameter Test Condition Min Typ Max Units CIN Input Capacitance VIN = 0V - - 10 pF CI/O Input /Output Capacitance VI/O = 0V - - 10 pF Note: 1. These parameters are characterized and not 100% tested. 5.7 MODE SELECTION CLE ALE CE# H L L WE# RE# WP# H X Mode Command Input Read Mode L H L H X H L L H H Address Input (5 clock) Command Input Write Mode L H L H H Address Input (5 clock) L L L H H Data Input L L L H X Data Output X X X X H X During Read (Busy) X X X X X H During Program (Busy) X X X X X H During Erase (Busy) X X(1) X X X L Write Protect X X H X X 0V/VCC(2) Stand-by Notes : 1. X can be VIL or VIH. 2. WP# should be biased to CMOS high or CMOS low for standby. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 16 IS34/35MW04G084/164 5.8 ROGRAM/ERASE PERFORMANCNE (Industriall: TA=-40 to 85, Automotive, A1: TA=-40 to 85, Vcc=1.7V ~ 1.95V) Parameter Symbol tPROG Min - Typ 300 Max 750 Unit us tCBSY - 3 700 us Nop - - 4 cycle Block Erase Time tBERS - 3 10 ms Dummy Busy Time for Two-Plane Page Program tDBSY - 0.5 1 us Average Program Time Dummy Busy Time for Cache Operation Number of Partial Program Cycles in the Same Page Notes: 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and 25 temperature. 2. tPROG is the average program time of all pages. Users should be noted that the program time variation from page to page is possible. 3. tCBSY max.time depends on timing between internal program completion and data-in. 5.9 AC CHARACTERISTICS FOR ADDRESS/ COMMAND/DATA INPUT Parameter CLE Setup Time CLE Hold Time CE# Setup Time CE# Hold Time WE# Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE# High Hold Time Address to Data Loading Time Symbol tCLS(1) tCLH tCS(1) tCH tWP tALS(1) tALH tDS(1) tDH tWC tWH tADL(2) Min 25 10 35 10 25 25 10 20 10 45 15 100(2) Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. The transition of the corresponding control pins must occur only once while WE# is held low. 2. tADL is the time from the WE rising edge of final address cycle to the WE# rising edge of first data cycle. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 17 IS34/35MW04G084/164 5.10 AC CHARACTERISTICS FOR OPERATION Parameter Symbol Data Transfer from Cell to Register tR ALE to RE# Delay tAR CLE to RE# Delay tCLR Ready to RE# Low tRR RE# Pulse Width tRP WE# High to Busy tWB WP# Low to WE# Low (disable mode) tWW WP# High to WE# Low (enable mode) Read Cycle Time tRC RE# Access Time tREA CE# Access Time tCEA RE# High to Output Hi-Z tRHZ CE# High to Output Hi-Z tCHZ CE# High to ALE or CLE Don't care tCSD RE# High to Output Hold tRHOH RE# Low to Output Hold tRLOH CE# High to Output Hold tCOH RE# High Hold Time tREH Output Hi-Z to RE# Low tIR RE# High to WE# Low tRHW WE# High to RE# Low tWHR Read Device Resetting Program tRST Time Erase during... Ready Cache Busy in Read Cache tDCBSYR (following 31h and 3Fh) Min 10 10 20 25 - Max 25 100 Unit us ns ns ns ns ns 100 - ns 45 0 15 5 15 15 0 100 60 - 30 45 100 30 5 10 500 5 (1) ns ns ns ns ns ns ns ns ns ns ns ns ns us us us us - 30 us - Note: If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 18 IS34/35MW04G084/164 6. TIMING DIAGRAMS 6.1 COMMAND LATCH CYCLE Figure 6.1 Command Latch Cycle 6.2 ADDRESS LATCH CYCLE Figure 6.2 Address Latch Cycle Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 19 IS34/35MW04G084/164 6.3 INPUT DATA LATCH CYCLE Figure 6.3 Input Data Latch Cycle 6.4 SERIAL ACCESS CYCLE AFTER READ (CLE=L, WE#=H, ALE=L) Note: 1. 2. Dout transition is measured at 200mV from steady state voltage at I/O with load. tRHOH starts to be valid when frequency is lower than 33MHz. Figure 6.4 Serial Access Cycle after Read Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 20 IS34/35MW04G084/164 6.5 SERIAL ACCESS CYCLE AFTER READ (EDO TYPE CLE=L, WE#=H, ALE=L) Note: 1. Transition is measured at +/-200mV from steady state voltage with load. This parameter is sample and not 100% tested. (tCHZ, tRHZ) 2. tRLOH is valid when frequency is higher than 33MHZ. tRHOH starts to be valid Figure 6.5 Serial Access Cycle after Read (EDO Type CLE=L, WE#=H, ALE=L) 6.6 STATUS READ CYCLE Figure 6.6 Status Read Cycle Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 21 IS34/35MW04G084/164 6.7 READ OPERATION Figure 6.7 Read Operation 6.8 READ OPERATION (INTERCEPTED BY CE#) Figure 6.8 Read Operation (Intercepted by CE#) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 22 IS34/35MW04G084/164 6.9 RANDOM DATA OUTPUT IN A PAGE Figure 6.9 Random Data Output in a Page 6.10 PAGE PROGRAM OPERATION Figure 6.10 Page Program Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 23 IS34/35MW04G084/164 6.11 PAGE PROGRAM OPERATION WITH RANDOM DATA INPUT Note: tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of the first data cycle. Figure 6.11 Page Program Operation with Random Data Input 6.12 COPY-BACK OPERATION WITH RANDOM DATA INPUT Figure 6.12 Copy-Back Operation with Random Data Input Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 24 IS34/35MW04G084/164 6.13 CACHE PROGRAM OPERATION Figure 6.13 Cache Program Operation 6.14 BLOCK ERASE OPERATION Figure 6.14. Block Erase Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 25 IS34/35MW04G084/164 6.15 CACHE READ OPERATION Figure 6.15.Cache Read Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 26 IS34/35MW04G084/164 6.16 READ ID OPERATION Figure 6.16 Read ID Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 27 IS34/35MW04G084/164 6.17 TWO-PLANE PAGE READ OPERATION WITH TWO-PLANE RANDOM DATA OUT Figure 6.17 Two Plane Page Read Operation with Two-Plane Random Data Out Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 28 IS34/35MW04G084/164 6.18 TWO-PLANE CACHE READ OPERATION Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 29 IS34/35MW04G084/164 Notes: 1. The column address will be reset to 0 by the 3Fh command input. 2. Cache Read operation is available only within a block. 3. Make sure to terminate the operation with 3Fh command. If the operation is terminated by 31h command, monitor I/O6 (Ready/Busy) by issuing Status Read Command (70h) and make sure the previous page read operation is completed. If the page read operation is completed, issue FFh reset before next operation. Figure 6.18 Two-Plane Cache Read Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 30 IS34/35MW04G084/164 6.19 TWO-PLANE PROGRAM OPERATION Figure 6.19 Two-Plane Program Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 31 IS34/35MW04G084/164 6.20 TWO-PLANE CACHE PROGRAM OPERATION Figure 6.20 Two-Plane Cache Program Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 32 IS34/35MW04G084/164 6.21 READ TWO PLANE BLOCK ERASE OPERATION Figure 6.21 Two-Plane Block Erase Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 33 IS34/35MW04G084/164 7. ID Definition Table The device contains ID codes that identify the device type and the manufacturer. 1st Cycle (Maker Code) C8h IS34/35MW04G164(X16) IS34/35MW04G084 (X8) C8h Part No. 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte 6th Byte 7th Byte 8th Byte 2nd Cycle (Device Code) BCh 3rd Cycle 4th Cycle 5th Cycle 6th ~ 9th Cycle 90h 55h 90h 15h 54h 54h 7Fh 7Fh ACh Description Maker Code Device Code Internal Chip Number, Cell Type, etc Page Size, Block Size, etc Plane Number, Plane Size, ECC Level JEDEC Maker Code Continuation Code, 7Fh JEDEC Maker Code Continuation Code, 7Fh JEDEC Maker Code Continuation Code, 7Fh 3rd ID Data Item Internal Chip Number Cell Type Number of Simultaneously Programmed Pages Interleave Program Between Multiple Chips Cache Program Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support Support Not Support Support Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 I/O7 I/O6 I/O5 0 0 1 1 I/O4 I/O3 I/O2 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 34 I/O1 0 0 1 1 I/O0 0 1 0 1 IS34/35MW04G084/164 4th ID Data Item Page Size (w/o redundant area) Redundant Area Size (Byte/512Byte) Block Size (w/o redundant area) Organization Serial Access Time 5th ID Data Item ECC Level Plane Number Plane Size(without Redundant Area) Reserved 6th ~ 8th ID Data Item JEDEC Maker Code Continuation Code Description 1KB 2KB 4KB 8KB 8 16 64KB 128KB 256KB 512KB X8 X16 45ns Reserved 25ns Reserved I/O7 Description 4bit/512B 2bit/512B 1bit/512B Reserved 1 2 4 8 64Kb 128Kb 256Kb 512Kb 1Gb 2Gb 4Gb 8Gb Reserved I/O7 Description Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 7F I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 0 0 1 1 I/O0 0 1 0 1 I/O1 0 0 1 1 I/O0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O6 I/O5 I/O4 I/O3 I/O2 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 1 1 1 1 1 1 1 0 35 IS34/35MW04G084/164 8. DEVICE OPERATION 8.1 PAGE READ OPERATION Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h command, five-cycle address, and 30h command. After initial power up, the 00h command can be skipped because it has been latched in the command register. The 2,112Byte of data on a page are transferred to cache registers via data registers within 25us (tR). Host controller can detect the completion of this data transfer by checking the R/B# output. Once data in the selected page have been loaded into cache registers, each Byte can be read out in 45ns cycle time by continuously pulsing RE#. The repetitive high-to-low transitions of RE# clock signal make the device output data starting from the designated column address to the last column address. The device can output data at a random column address instead of sequential column address by using the Random Data Output command. Random Data Output command can be executed multiple times in a page. After power up, device is in read mode so 00h command cycle is not necessary to start a read operation. A page read sequence is illustrated in Figure below, where column address, page address are placed in between commands 00h and 30h. After tR read time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after 30h. Host controller can toggle RE# to access data starting with the designated column address and their successive bytes. CE# CLE ALE WE# RE# tR R/B# I/Ox 00h Address (5cycles) 30h Data Output( Serial Access) Col. Add. 1,2 & Row Add. 1,2,3 (00h Command) Data Field Spare Field Read Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 36 IS34/35MW04G084/164 RE# tR R/B# 00h I/Ox Address 5 cycles 30h Data Output( Serial Access) Col. Add. 1,2 & Row Add. 1,2,3 1 Data Field Spare Field RE# R/B# 05h I/Ox 1 Col.1 Col.2 E0h Data Output( Serial Access) Col. Add. 1,2 Data Field Spare Field Random Page Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 37 IS34/35MW04G084/164 8.2 PAGE PROGRAM The device is programmed based on the unit of a page, and consecutive partial page programming on one page without intervening erase operation is strictly prohibited. Addressing of page program operations within a block should be in sequential order. A complete page program cycle consists of a serial data input cycle in which up to 2,112byteof data can be loaded into data register via cache register, followed by a programming period during which the loaded data are programmed into the designated memory cells. The serial data input cycle begins with the Serial Data Input command (80h), followed by a five-cycle address input and then serial data loading. The bytes not to be programmed on the page do not need to be loaded. The column address for the next data can be changed to the address follows Random Data Input command (85h). Random Data Input command may be repeated multiple times in a page. The Page Program Confirm command (10h) starts the programming process. Writing 10h alone without entering data will not initiate the programming process. The internal write engine automatically executes the corresponding algorithm and controls timing for programming and verification, thereby freeing the host controller for other tasks. Once the program process starts, the host controller can detect the completion of a program cycle by monitoring the R/B# output or reading the Status bit (I/O6) using the Read Status command. Only Read Status and Reset commands are valid during programming. When the Page Program operation is completed, the host controller can check the Status bit (I/O0) to see if the Page Program operation is successfully done. The command register remains the Read Status mode unless another valid command is written to it. A page program sequence is illustrated in Figure below, where column address, page address, and data input are placed in between 80h and 10h. After tPROG program time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after 10h. R/B# tPROG "0" I/Ox 80h Address & Data Input 10h 70h I/O0 Pass Col. Add. 1,2 & Row Add. 1,2,3 Data "1" Fail Program and Read Status Operation R/B# I/Ox tPROG 80h Address & Data Input 85h Col. Add. 1,2 & Row Add. 1,2,3 Data Address & Data Input Col. Add. 1,2 Data "0" 10h 70h I/O0 Pass "1" Fail Random Data Input In a Page Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 38 IS34/35MW04G084/164 8.3 CACHE PROGRAM The Cache Program is an extension of Page Program, which is executed with 2,112 byte(x8) or 1,056 words(x16) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. After writing the first set of data up to 2,112 bytes(x8) or 1,056 words(x16) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identity the completion of internal programming. If the system monitors the progress of programming only with R/B#, the last page of the target programming sequence must be programmed with actual Page Program command (10h). tCBSY tCBSY R/B# I/Ox 80h Address & Data Input 15h 80h Col. Add. 1,2 & Row Add. 1,2,3 Data Address & Data Input 15h Col. Add. 1,2 & Row Add. 1,2,3 Data 1 Max. 63 times repeatable tPROG R/B# I/Ox 80h 1 Address & Data Input 10h Col. Add. 1,2 & Row Add. 1,2,3 Data 70h I/O0 '1' Fail '0' Pass Last Page Input and Program NOTE: 1. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. 2. tPROG = Program time for the last page + Program time for the (last-1)th page - (Program command cycle time + Last page data loading time) Fast Cache Program (Available only within a Block) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 39 IS34/35MW04G084/164 8.4 COPY-BACK PROGRAM Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is no bit error detected in the stored data. The benefit is particularly obvious when a portion of a block is updated and the rest of the block needs to be copied to a newly assigned empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of Copy-Back Program with Destination address. A Read for Copy-Back operation with "35h" command and the Source address moves the whole 2,112byte data into the internal buffer. The host controller can detect bit errors by sequentially reading the data output. Copy-Back Program is initiated by issuing Page-Copy Data-Input command (85h) with Destination address. If data modification is necessary to correct bit errors and to avoid error propagation, data can be reloaded after the Destination address. Data modification can be repeated multiple times as shown in Figure below. Actual programming operation begins when Program Confirm command (10h) is issued. Once the program process starts, the Read Status command (70h) may be entered to read the status register. The host controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The command register remains Read Status mode until another valid command is written to it. R/B# I/Ox tR 00h Address 5Cycles 35h tPROG Data output Col. Add. 1,2 & Row Add. 1,2,3 Source Address 85h Address 5Cycles 10h Col. Add. 1,2 & Row Add. 1,2,3 Destination Address 70h I/O0 '0' Pass '1' Fail Page Copy-Back Program Operation Page Copy-Back Program Operation with Random Data Input Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 40 IS34/35MW04G084/164 8.5 BLOCK ERASE The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a three-cycle row address, in which only Plane address and Block address are valid while Page address is ignored. The Erase Confirm command (D0h) following the row address starts the internal erasing process. The two-step command sequence is designed to prevent memory content from being inadvertently changed by external noise. At the rising edge of WE# after the Erase Confirm command input, the internal control logic handles erase and erase-verify. When the erase operation is completed, the host controller can check Status bit (I/O0) to see if the erase operation is successfully done. Figure below illustrates a block erase sequence, and the address input (the first page address of the selected block) is placed in between commands 60h and D0h. After tBERS erase time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after D0h to check the execution status of erase operation. tBERS R/B# I/Ox 60h Address Input D0h Row Add. 1,2,3 70h I/O0 '1' Fail '0' Pass Block Erase Operation 8.6 READ STATUS A status register on the device is used to check whether program or erase operation is completed and whether the operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle outputs the content of the status register to I/O pins on the falling edge of CE# or RE#, whichever occurs last. These two commands allow the system to poll the progress of each device in multiple memory connections even when R/B# pins are common-wired. RE# or CE# does not need to toggle for status change. The command register remains in Read Status mode unless other commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command (00h) is needed to start read cycles. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 41 IS34/35MW04G084/164 Table 8.1 Status Register Definition for 70h Command I/O Page Program Block Erase Cache Program Read Cache Read Definition Pass : 0 Fail : 1 Pass : 0 Fail : 1 I/O 0 Pass/Fail Pass/Fail Pass/Fail(N) NA NA I/O 1 NA NA Pass/Fail(N-1) NA NA NA NA NA NA Don't cared NA NA NA NA True Ready/Busy NA NA NA NA True Ready/Busy Don't cared Don't cared Busy : 0 Ready : 1 Busy : 0 Ready : 1 Protected :0 Not Protected : 1 I/O 3 I/O 4 NA (Pass/Fail,OTP) NA NA I/O 5 NA NA I/O 6 Ready/Busy Ready/Busy Ready/Busy Ready/Busy Ready/Busy I/O 7 Write Protect Write Protect Write Protect Write Protect Write Protect I/O 2 NA Note: 1. I/Os defined NA are recommended to be masked out when Read Status is being executed. 2. N = current page, N-1 = previous page. Table 8.2 Status Register Definition for F1h Command I/O Page Program Block Erase Cache Program I/O 0 Chip Pass/Fail Chip Pass/Fail Chip Pass/Fail(N) Plane0 Pass/Fail Plane1 Pass/Fail Plane0 Pass/Fail Plane1 Pass/Fail I/O 3 NA NA I/O 4 NA NA I/O 5 NA NA True Read/Busy I/O 6 Ready/Busy Ready/Busy Ready/Busy I/O 7 Write Protect Write Protect Write Protect I/O 1 I/O 2 Plane0 Pass/Fail(N) Plane1 Pass/Fail(N) Plane0 Pass/Fail(N1) Plane1 Pass/Fail(N1) Read Cache Read Definition Pass : 0 NA NA Fail : 1 Pass : 0 NA NA Fail : 1 Pass : 0 NA NA Fail : 1 Pass : 0 NA NA Fail : 1 Pass : 0 NA NA Fail : 1 True Busy : 0 NA Ready/Busy Ready : 1 Busy : 0 Ready/Busy Ready/Busy Ready : 1 Protected :0 Write Protect Write Protect Not Protected : 1 Note: 3. I/Os defined NA are recommended to be masked out when Read Status is being executed. 4. N = current page, N-1 = previous page. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 42 IS34/35MW04G084/164 8.7 READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code (C8h), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Read ID Operation Table 8.3 ID definition Table 1st Cycle 2nd Cycle (Maker Code) (Device Code) IS34/35MW04G084(X8) C8h ACh Part No. IS34/35MW04G164(X16) C8h Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 BCh 3rd Cycle 4th Cycle 5th Cycle 90h 15h 54h 90h 55h 54h 43 IS34/35MW04G084/164 8.8 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B# pin changes to low for tRST after the Reset command is written. Refer to Figure below. tRST R/B# I/Ox FFh Reset Operation Table 8.4 Device Status Table Operation Mode After Power-up After Reset 00h Command is latched Waiting for next command Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 44 IS34/35MW04G084/164 8.9 CACHE READ Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are transferred from data registers to cache registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used to complete data transfer from memory cells to data registers. Read Operation with Cache Read Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 45 IS34/35MW04G084/164 8.10 TWO-PLANE PAGE READ The Two-plane Page Read sequence and its restrictions are shown in Figure below. Two-plane Page Read is initiated by repeating command 60h followed the three address cycles twice, and only same page of same block can be selected from each plane. Once the data is loaded into the cache registers, the data output of the first plane can be read out by issuing command 00h with five address cycles, command 05h with two-cycle column address and finally E0h. The data output of the second plane can be read out using the identical command sequence. tR R/B# I/Ox 60h Address (3 Cycle) 60h Row Add. 1,2,3 Address (3 Cycle) 30h Row Add. 1,2,3 1 Page address: Page M Page address: Page M Plane address: Fixed 'Low' Plane address: Fixed 'High' Block address: Block N Block address: Block N R/B# 00h I/Ox Address (5 Cycle) 05h Col. Add. 1,2 & Row Add. 1,2,3 E0h Data Output Col. Add. 1,2 Column address: Valid Column address: Fixed 'Low' Page address: Page M Plane address: Fixed 'Low' Block address: Block N 1 Address (2 Cycle) 2 R/B# 00h I/Ox Address (5 Cycle) 05h Col. Add. 1,2 & Row Add. 1,2,3 2 Column address: Fixed 'Low' Page address: Page M Plane address: Fixed 'High' Block address: Block N Address (2 Cycle) E0h Data Output Col. Add. 1,2 Column address: Valid Two-Plane Page Read Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 46 IS34/35MW04G084/164 8.11 TWO-PLANE CACHE READ The Two-plane Cache Read sequence is shown in below, only same page of same block can be selected from each plane. After Read Confirm command (33h), the data are transferred to data registers within tR. After issuing Cache Read command (31h), read data in the data registers are transferred to cache registers within a short period of time (tDCBSYR). Once the data are loaded into the cache registers, the data of both planes can be read out in the same way as the Two-Plane Page Read operation. The host controller shall use 3Fh instead of 31h to indicate the Two-plane Cache Read operation for the last target pages. Two-Plane Cache Read Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 47 IS34/35MW04G084/164 8.12 TWO-PLANE PAGE PROGRAM Two-plane Page Program is an extension of Page Program, and which utilizes the two sets of 2,112-byte data registers to enable simultaneous programming of same page of same block from each plane. After writing the first set of data (up to 2,112 bytes) into the selected data registers, Dummy Page Program command (11h) instead of Page Program command (10h) is input to finish data loading for the first memory plane. R/B# remains in Busy state for a short period of time (t DBSY). Read Status (70h) may be issued to find out when the device returns to Ready state by polling the Status bit I/O6. The second set of data for the other memory plane is loaded after the 81h command and address sequence. After that, the Page Program command (10h) must be issued to start the programming process. Refer to Page Program command for the operation of R/B# and Read Status. The Status bit I/O0 is set to "1" when either page fails. Fig 41 shows the restriction in addressing with Two-plane Page Program. Two-Plane Page Program Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 48 IS34/35MW04G084/164 8.13 TWO-PLANE COPY BACK PROGRAM Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2,112 byte data registers. Since the device is equipped with two memory planes, activating the two sets of 2,112 byte data registers enables a simultaneous programming of two pages. tR R/B# I/Ox Address (3 Cycle) 60h 60h Row Add. 1,2,3 Address (3 Cycle) 35h Row Add. 1,2,3 1 Page address: Page M Page address: Page M Plane address: Fixed 'Low' Plane address: Fixed 'High' Block address: Block N Block address: Block N R/B# Address (5 Cycle) 00h I/Ox Address (2 Cycle) 05h Col. Add. 1,2 & Row Add. 1,2,3 Column address: Valid Column address: Fixed 'Low' Page address: Page M Plane address: Fixed 'Low' Block address: Block N 1 Data Output E0h Col. Add. 1,2 2 R/B# Address (5 Cycle) 00h I/Ox Address (2 Cycle) 05h Col. Add. 1,2 & Row Add. 1,2,3 Col. Add. 1,2 Column address: Valid Column address: Fixed 'Low' Page address: Page M Plane address: Fixed 'High' Block address: Block N 2 3 tDBSY tPROG R/B# I/Ox Address 11h (5 Cycle) Destination Address Col. Add. 1,2 & Row Add. 1,2,3 Note Column address: Fixed 'Low' Page address: Page M Plane address: Fixed 'Low' Block address: Block N 85h 3 Address (5 Cycle) 81h 10h 70h/ F1h Destination Address Col. Add. 1,2 & Row Add. 1,2,3 Column address: Fixed 'Low' Page address: Page M Plane address: Fixed 'High' Block address: Block N Plane0 "0" I/Ox "1" Pass Fail Plane1 Data Field Data Field Target page Target page Source page 1 Data Output E0h (1): Two-Plane Read for Copy Back (2): Two-Plane Random Data Out (3): Two-Plane Copy Back Program Source page 3 1 Spare Field 2 3 Spare Field 2 Two-Plane Copy Back Program Notes: 1. Copy Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 49 IS34/35MW04G084/164 Notes: 1. Copy Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. Two-Plane Copy Back Program with Random Data Input Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 50 IS34/35MW04G084/164 8.14 TWO-PLANE CACHE PROGRAM Two-Plane Cache Program Note: Any command between 11h and 81h is prohibited except 70h/F1h and FFh. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 51 IS34/35MW04G084/164 8.15 TWO-PLANE BLOCK ERASE Similar to Two-plane Page Program, two symmetric blocks from each plane can be simultaneously erased by using Two-plane Block Erase command. Following figure illustrates the Two-plane Block Erase sequence. Two-Plane Block Erase Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 52 IS34/35MW04G084/164 8.16 READY/BUSY# The device has a R/B# output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B# pin is normally high but transition to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an opendrain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B#) and current drain during busy (ibusy) , an appropriate value can be obtained with the following reference chart. Its value can be determined by the following guidance. Ready/Busy# Pin Electrical Specifications Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 53 IS34/35MW04G084/164 8.17 DATA PROTECTION AND POWER UP SEQUENCE The timing sequence shown in the figure below is necessary for the power-on/off sequence. The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the initialization the device R/B# signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands are 70h. The WP# signal is useful for protecting against data corruption at power on/off. AC Waveforms for Power Transition Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 54 IS34/35MW04G084/164 8.18 WRITE PROTECT OPERATION Enabling WP# during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: Enable Programming WE# I/Ox 80h 10h WP# R/B# tWW (Min. 100 ns) Note: WP# keeps "High" until programming finish Disable Programming WE# I/Ox 80h 10h WP# R/B# tWW (Min. 100 ns) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 55 IS34/35MW04G084/164 Enable Erasing WE# I/Ox 60h D0h WP# R/B# tWW (Min. 100 ns) NOTE: WP# keeps "High" until erasing finish Disable Erasing WE# I/Ox 60h D0h WP# R/B# tWW (Min. 100 ns) Enable/Disable Programming and Enable Erasing Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 56 IS34/35MW04G084/164 9. INVALID BLOCK AND ERROR MANAGEMENT 9.1 MASK OUT INITIAL INVALID BLOCK(S) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ISSI. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 4bit/512Byte ECC. 9.2 IDENTIFYING INITIAL INVALID BLOCK(S) AND BLOCK REPLACEMENT MANAGEMENT Unpredictable behavior may result from programming or erasing the defective blocks. Figure below illustrates an algorithm for searching factory-mapped defects, and the algorithm needs to be executed prior to any erase or program operations. A host controller has to scan the data at the first byte in the spare area of the first page or second page of each block from block 0 to the last block using page read command. Any block where the 1st byte in the spare area of the first or second page does not contain "FFh" is an invalid block. Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop with Flash memory usage. Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 57 IS34/35MW04G084/164 Check for "FFh" at the first byte in the spare area of the first page or second page of each block. Figure 9.1 Algorithm for Bad Block Scanning Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 58 IS34/35MW04G084/164 9.3 ERROR IN READ OR WRITE OPERATION Within its lifetime, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks. Write Read Failure Mode Erase failure Program failure Up to 4 bit failure Detection and Countermeasure Sequence Read Status after Erase Block Replacement Read Status after Program Block Replacement Verify ECC ECC Correction Note: Error Correcting Code RS Code or BCH Code etc. Example: 4bit correction / 512 Byte Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 59 IS34/35MW04G084/164 Figure 9.2 Program Flow Chart Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 60 IS34/35MW04G084/164 Figure 9.3 Erase Flow Chart Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 61 IS34/35MW04G084/164 Figure 9.4 Read Flow Chart Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 62 IS34/35MW04G084/164 Block A 1st ~ (n-1) th n th An error occurs. page 1 Block B 1st ~ (n-1) th n th Buffer memory of the controller 2 An error occurs. page * Step 1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step 2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step 3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B' * Step 4 Do not erase or program to Block 'A' by creating an 'invalid block' table or other appropriate scheme. Figure 9.5 Blcok Replacement Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 63 IS34/35MW04G084/164 9.4 ADDRESSING FOR PROGRAM OPERATION Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB page doesn't need to be page 0. Figure 9.6 Addressing for Program Operation Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 64 IS34/35MW04G084/164 9.5 SYSTEM INTERFACE USING CE# NOT CARE OPERATION For an easier system interface, CE# may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications that use slow cycle time on the order of -seconds, de-activating CE# during the data-loading and serial access would provide significant savings in power consumption. Figure 9.7 Program/Read-Operation with CE# Not-Care Operation Address Information Data Data In/Out IS34/35MW04G084 (4Gb x8) IS34/35MW04G164 (4Gb X16) Address I/O Device I/Ox Col. Add1 Col. Add2 2,112Byte I/O 0~I/O 7 A0 ~ A7 A8 ~ A11 1,056Word I/O 0~I/O 15 A0 ~ A7 A8 ~ A10 Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 Row Add1 A12 ~ A19 A11 ~ A18 Row Add2 A20 ~ A27 A19 ~ A26 65 Row Add3 A28 ~ A29 A27 ~ A28 IS34/35MW04G084/164 10. PACKAGE TYPE INFORMATION 10.1 48-PIN TSOP (TYPE I) PACKAGE (T) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 66 IS34/35MW04G084/164 11. ORDERING INFORMATION - Valid Part Numbers IS 34 M W 04G 08 4 - T L I TEMPERATURE RANGE I = Industrial (-40C to +85C) E = Industrial (-40C to +105C) (Call Factory) A1 = Automotive Grade (-40C to +85C) A2 = Automotive Grade (-40C to +105C) (Call Factory) PACKAGING CONTENT L = RoHS compliant PACKAGE Type (1) T = 48-pin TSOP (Type I) Die Revision Blank = First Gen. ECC Requirement 4 = 4-bit ECC Bus Width 08 = x8 NAND 16 = x16 NAND (Call Factory) Density 04G = 4 Gigabit VDD W = 1.8V Technology M = Standard NAND (SLC) Product Family 34 = NAND 35 = Automotive NAND BASE PART NUMBER IS = Integrated Silicon Solution Inc. VDD Density Bus 1.8V 4Gb X8 Temp. Grade Order Part Number Package Industrial IS34MW04G084-TLI 48-pin TSOP (Type I) Automotive (A1) IS35MW04G084-TLA1 48-pin TSOP (Type I) Integrated Silicon Solution, Inc.- www.issi.com Rev. A2 06/15/2018 67