Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3
February 2010
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary)
High Speed 10MBit/s Logic Gate Optocouplers
Features
■
Very high speed – 10 MBit/s
■
Superior CMR – 10 kV/µs
■
Fan-out of 8 over -40°C to +85°C
■
Logic gate output
■
Strobable output
■
Wired OR-open collector
■
U.L. recognized (File # E90700, Vol. 2)
Applications
■
Ground loop elimination
■
LSTTL to TTL, LSTTL or 5-volt CMOS
■
Line receiver, data transmission
■
Data multiplexing
■
Switching power supplies
■
Pulse transformer replacement
■
Computer-peripheral interface
Description
The 6N137M, HCPL2601M, HCPL2611M single-channel
and HCPL2630M, HCPL2631M dual-channel optocou-
plers consist of a 850 nm AlGaAS LED, optically coupled
to a very high speed integrated photo-detector logic gate
with a strobable output. This output features an open col-
lector, thereby permitting wired OR outputs. The
switching parameters are guaranteed over the tempera-
ture range of -40°C to +85°C. A maximum input signal of
5mA will provide a minimum output sink current of 13mA
(fan out of 8).
An internal noise shield provides superior common
mode rejection of typically 10kV/µs. The HCPL2601M
and HCPL2631M has a minimum CMR of 5kV/µs. The
HCPL2611M has a minimum CMR of 10kV/µs.
Schematics Package Outlines
A 0.1µF bypass capacitor must be connected between pins 8 and 5(1).
1
2
3
4 5
6
7
8
N/C
_
VCC
VE
VO
GND
+
N/C
VF
1
2
3
4 5
6
7
8
+
_
VF1
VCC
V01
V02
GND
VF2
_
+
HCPL2630M
HCPL2631M
(Preliminary)
6N137M
HCPL2601M
HCPL2611M
Truth Table (Positive Logic)
Input Enable Output
H H L
L H H
H L H
L L H
H NC L
L NC H
8
8
1
8
1
1
8
1
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 2
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings
(T
A
= 25°C unless otherwise specified)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
*6.3mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0mA or less.
Symbol Parameter Value Units
T
STG
Storage Temperature -40 to +125 °C
T
OPR
Operating Temperature -40 to +100 °C
T
SOL
Lead Solder Temperature 260 for 10 sec °C
EMITTER
I
F
DC/Average Forward Single Channel 50 mA
Input Current Dual Channel (Each Channel) 30
V
E
Enable Input Voltage Not to Exceed
V
CC
by more than 500mV
Single Channel 5.5 V
V
R
Reverse Input Voltage Each Channel 5.0 V
P
I
Power Dissipation Single Channel 100 mW
Dual Channel (Each Channel) 45
DETECTOR
V
CC
(1 minute max)
Supply Voltage 7.0 V
I
O
Output Current Single Channel 50 mA
Dual Channel (Each Channel) 50
V
O
Output Voltage Each Channel 7.0 V
P
O
Collector Output Single Channel 85 mW
Power Dissipation Dual Channel (Each Channel) 60
Symbol Parameter Min. Max. Units
I
FL
Input Current, Low Level 0 250 µA
I
FH
Input Current, High Level *6.3 15 mA
V
CC
Supply Voltage, Output 4.5 5.5 V
V
EL
Enable Voltage, Low Level 0 0.8 V
V
EH
Enable Voltage, High Level 2.0 V
CC
V
T
A
Low Level Supply Current -40 +85 °C
NFan Out (TTL load) 8
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 3
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics
(T
A
= 0 to 70°C unless otherwise specified)
Individual Component Characteristics
Switching Characteristics
(T
A
= -40°C to +85°C, V
CC
= 5V, I
F
= 7.5mA unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ.* Max. Unit
EMITTER
V
F
Input Forward Voltage I
F
= 10mA 1.8 V
T
A
= 25°C 1.4 1.75
B
VR
Input Reverse Breakdown
Voltage
I
R
= 10µA 5.0 V
C
IN
Input Capacitance V
F
= 0, f = 1MHz 60 pF
∆
V
F
/
∆
T
A
Input Diode Temperature
Coefficient
I
F
= 10mA -1.4 mV/°C
DETECTOR
I
CCH
High Level Supply Current V
CC
= 5.5V, I
F
= 0mA,
V
E
= 0.5V
Single Channel 6 10 mA
Dual Channel 10 15
I
CCL
Low Level Supply Current Single Channel V
CC
= 5.5V,
I
F
= 10mA
813mA
Dual Channel V
E
= 0.5V 14 21
I
EL
Low Level Enable Current V
CC
= 5.5V, V
E
= 0.5V -0.7 -1.6 mA
I
EH
High Level Enable Current V
CC
= 5.5V, V
E
= 2.0V -0.5 -1.6 mA
V
EH
High Level Enable Voltage V
CC
= 5.5V, I
F
= 10mA 2.0 V
V
EL
Low Level Enable Voltage V
CC
= 5.5V, I
F
= 10mA
(3)
0.8 V
Symbol AC Characteristics Test Conditions Min. Typ.* Max. Unit
T
PLH
Propagation Delay
Time to Output HIGH
Level
R
L
= 350
Ω
,
C
L
= 15pF
(4)
(Fig. 12)
T
A
= 25°C 20 40 75 ns
100
T
PHL
Propagation Delay
Time to Output LOW
Level
T
A
= 25°C
(5)
25 40 75 ns
R
L
= 350
Ω
, C
L
= 15pF (Fig. 12) 100
|T
PHL
–T
PLH
|Pulse Width Distortion (R
L
= 350
Ω
, C
L
= 15pF (Fig. 12) 1 35 ns
t
r
Output Rise Time
(10–90%)
R
L
= 350
Ω
, C
L
= 15pF
(6)
(Fig. 12) 30 ns
t
f
Output Rise Time
(90–10%)
R
L
= 350
Ω
, C
L
= 15pF
(7)
(Fig. 12) 10 ns
t
ELH
Enable Propagation
Delay Time to Output
HIGH Level
I
F
= 7.5mA, V
EH
= 3.5V, R
L
= 350
Ω
, C
L
= 15pF
(8)
(Fig. 13)
15 ns
t
EHL
Enable Propagation
Delay Time to Output
LOW Level
I
F
= 7.5mA, V
EH
= 3.5V, R
L
= 350
Ω
, C
L = 15pF(9)
(Fig. 13)
15 ns
|CMH| Common Mode
Transient Immunity
(at Output HIGH Level)
TA = 25°C, |VCM| = 50V
(Peak), IF = 0mA,
VOH (Min.) = 2.0V,
RL = 350Ω(10) (Fig. 14)
6N137M, HCPL2630M 10,000 V/µs
HCPL2601M,
HCPL2631M
5000 10,000
|VCM| = 400V HCPL2611M 10,000 15,000 V/µs
|CML| Common Mode
Transient Immunity
(at Output LOW Level)
RL = 350Ω, IF = 7.5mA,
VOL (Max.) = 0.8V,
TA = 25°C(11) (Fig. 14)
6N137M, HCPL2630M 10,000
HCPL2601M,
HCPL2631M
5000 10,000
|VCM| = 400V HCPL2611M 10,000 15,000
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 4
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Electrical Characteristics (Continued)
Transfer Characteristics (TA = -40 to +85°C unless otherwise specified)
Isolation Characteristics (TA = -40°C to +85°C unless otherwise specified.)
*All Typicals at VCC = 5V, TA = 25°C
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Each channel.
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
4. tPLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
HIGH state (i.e., VOUT > 2.0V). Measured in volts per microsecond (V/µs).
11. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
LOW output state (i.e., VOUT < 0.8V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
Symbol DC Characteristics Test Conditions Min. Typ.* Max. Unit
IOH HIGH Level Output Current VCC = 5.5V, VO = 5.5V,
IF = 250µA, VE = 2.0V(2) 100 µA
VOL LOW Level Output Current VCC = 5.5V, IF = 5mA, VE = 2.0V,
ICL = 13mA(2) 0.4 0.6 V
IFT Input Threshold Current VCC = 5.5V, VO = 0.6V, VE = 2.0V,
IOL = 13mA
3 5 mA
Symbol Characteristics Test Conditions Min. Typ.* Max. Unit
II-O Input-Output Insulation
Leakage Current
Relative humidity = 45%,
TA = 25°C, t = 5s,
VI-O = 3000 VDC(12)
1.0* µA
VISO Withstand Insulation Test
Voltage
RH < 50%, TA = 25°C,
II-O ≤ 10µA, t = 1 min.(12) 5000 VRMS
RI-O Resistance (Input to Output) VI-O = 500V(12) 1011 Ω
CI-O Capacitance (Input to Output) f = 1MHz(12) 1pF
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 5
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Typical Performance Curves
Fig. 1 Low Level Output Voltage vs. Ambient Temperature Fig. 2 Input Diode Forward Voltage vs. Forward Current
Fig. 3 Switching Time vs. Forward Current Fig. 4 Low Level Output vs. Ambient Temperature
TA – AMBIENT TEMPERATURE (°C)
IF = 5mA
VE = 2V
VCC = 5.5V
Fig. 5 Input Threshold Current vs. Ambient Temperature Fig. 6 Output Voltage vs. Input Forward Current
VCC = 5V
TA = 25°C
VCC = 5V
VE = 2V
VOL = 0.6V
VCC = 5V
VE = 2V
VOL = 0.6V
IF = 15mA
IF = 10mA
IF = 5mA
IOL = 12.8mA
IOL = 16mA
IOL = 9.6mA
IOL = 6.4mA
-40 -20 0 20 40 60 80 100
V
OL
– LOW LEVEL OUTPUT VOLTAGE (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
I
F
– FORWARD CURRENT (mA)
VF – FORWARD VOLTAGE (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
0.001
0.010
0.100
1
10
T
P
– PROPAGATION DELAY (ns)
I
F
– FORWARD CURRENT (mA)
579111315
20
0
40
4.0
3.5
3.0
2.5
2.0
1.5
1.0
60
80
100
120
RL = 4kΩ (tPLH)
RL = 1kΩ (tPLH)
RL = 350Ω
RL = 350Ω
RL = 1kΩ
RL = 1kΩ
RL = 4kΩ
RL = 4kΩ
RL = 350Ω (tPLH)
RL = 4kΩ (tPHL)
RL = 1kΩ (tPHL)
RL = 350Ω (tPHL)
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
I
OL
– LOW LEVEL OUTPUT CURRENT (mA)
20
25
30
35
40
45
50
I
FT
– INPUT THRESHOLD CURRENT (mA)
V
O
– OUTPUT VOLTAGE (V)
I
F
- FORWARD CURRENT (mA)
0123456
0
1
2
3
4
5
6
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 6
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
Fig. 7 Pulse Width Distortion vs. Temperature Fig. 8 Rise and Fall Time vs. Temperature
IF = 7.5mA
VCC = 5V
IF = 7.5mA
VCC = 5V IF = 7.5mA
VCC = 5V
IF = 7.5mA
VCC = 5V
60
50
40
30
20
10
0
-10
100
80
60
40
20
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
500
400
300
200
100
0
-100
100
90
80
70
60
50
40
30
20
RL = 350Ω
RL = 1kΩ
RL = 4kΩ
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
Fig. 9 Enable Propagation Delay vs. Temperature Fig. 10 Switching Time vs. Temperature
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
Fig. 11 High Level Output Current vs. Temperature
TA – AMBIENT TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100
PWD – PULSE WIDTH DISTORTION (ns)
TE – ENABLE PROPAGATION DELAY (ns)
IOH – HIGH LEVEL OUTPUT CURRENT (µA)
TP – PROPAGATION DELAY (ns) tR / tF – RISE AND FALL TIME (ns)
RL = 4kΩ (tR)
RL = 1kΩ (tR)
RL = 350Ω (tR)
RL = 4kΩ (tF)
RL = 1kΩ (tF)
RL = 350Ω (tF)
RL = 4kΩ (tELH)
RL = 4kΩ (tPLH)
RL = 1kΩ (tPLH)
RL = 350Ω (tPLH)
RL = 4kΩ (tPHL)
RL = 1kΩ (tPHL)
RL = 350Ω (tPHL)
RL = 1kΩ (tELH)
RL = 350Ω (tELH)
RL = 4kΩ/1kΩ/350Ω (tEHL)
VCC = 5V
VO = 5.5V
VE = 2V
IF = 250µA
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 7
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Test Circuits
47
PHL
t
F
I = 7.5 mA
1.5 V
90%
10%
7.5 mA
+5V
1.5 V
3.0 V
1.5 V
3
2
1
4
8
7
6
5
4 5
Pulse
1
2
3
Generator
tr = 5ns
Z = 50Ω
O
8
7
6
+5V
PLH
t
I = 3.75 mA
F
Output
O
(V )
Input
(I )
F
Output
(V )
O
f
t
r
t
Output
(V )
O
L
R
C
L
(I )
Input
F
Monitor
O
Z = 50Ω
Pulse
Generator
tr = 5ns (V )
E
Input
Monitor
GND
V
CC
O
(V )
Output
L
R
L
C
(V )
Output
O
Input
(V )
E
EHL
tt
ELH
bypass
.1 µf
bypass
.1 µf
Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, trand tf
Fig. 13 Test Circuit tEHL and tELH
GND
V
CC
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 8
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Test Circuits (Continued)
+5V
Peak
3
2
1
4
8
7
6
5
GND
V
CC
O
(V )
Output
350Ω
V
CM
FF
V
A
B
Pulse Gen
I
F
CM
V
0V
O
V
5V Switching Pos. (A), I = 0
F
O
V (Max)
CM
0.5 V
O
V
Switching Pos. (B), I = 7
.5 mA
F
H
CM
L
V (Min)
O
bypass
.1 µf
Fig. 14 Test Circuit Common Mode Transient Immunity
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 9
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Package Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Through Hole
Surface Mount – 0.3" Lead Spacing (Option S)
Note:
All dimensions are in inches (millimeters)
0.4" Lead Spacing (Option TV) (Pending)
8-Pin Surface Mount DIP – Land Pattern
(Option S)
0.200 (5.08)
MAX
0.100 (2.54) TYP
0.022 (0.56)
0.016 (0.41)
0.020 (0.51)
MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78)
0.045 (1.14)
0.156 (3.94)
0.144 (3.68)
241
56 78
0.300 (7.62)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20)
15° MAX
PIN 1
ID.
SEATING PLANE
0.270 (6.86)
0.250 (6.35)
0.390 (9.91)
0.370 (9.40)
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
0.020 (0.51)
MIN
0.070 (1.78)
0.045 (1.14)
0.156 (3.94)
0.144 (3.68) 0.300 (7.62)
TYP
0.405 (10.30)
MAX.
0.315 (8.00)
MIN
0.015 (0.40) MIN
Both Sides
32 14
5678
0.016 (0.40)
0.008 (0.20)
PIN 1
ID.
0.200 (5.08)
MAX
0.100 (2.54) TYP
0.022 (0.56)
0.031 (0.78)
0.016 (0.41)
0.020 (0.51)
MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78) 0.156 (3.94)
0.144 (3.68)
0.045 (1.14)
241
56 78
0.400 (10.16)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20)
0° to 15°
PIN 1
ID.
SEATING PLANE
0.070 (1.78)
0.060 (1.52)
0.030 (0.76)
0.100 (2.54)
0.295 (7.49)
0.415 (10.54)
0.200 (5.08)
MAX
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 10
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Ordering Information
Marking Information
Option
Example Part
Number Description
No Suffix 6N137M Standard Through Hole Device, 50 pcs per tube
S 6N137SM Surface Mount Lead Bend
SD 6N137SDM Surface Mount; Tape and Reel
V 6N137VM IEC60747-5-2 approval pending (VDE)
TV 6N137TVM IEC60747-5-2 approval pending (VDE), 0.4” lead spacing
SV 6N137SVM IEC60747-5-2 approval pending (VDE), surface mount
SDV 6N137SDVM IEC60747-5-2 approval pending (VDE), surface mount, tape and reel
1
2
6
43 5
6N137
BYYXXV
Note:
‘HCPL’ devices are marked only with the numerical characters (for example, HCPL2630 is
marked as ‘2630’).
The ‘M’ suffix on the part number is an order identifier only. It is used to identify orders for the
white package version. The ‘M’ does not appear on the device’s top mark.
Definitions
1Fairchild logo
2Device number
3VDE mark (Note: Only appears on parts ordered with VDE
option – See order entry table) (pending approval)
4Two digit year code, e.g., ‘07’
5Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 11
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Carrier Tape Specifications (Option SD)
Symbol Description Dimension in mm
WTape Width 16.0 ± 0.3
tTape Thickness 0.30 ± 0.05
P0Sprocket Hole Pitch 4.0 ± 0.1
D0Sprocket Hole Diameter 1.55 ± 0.05
E Sprocket Hole Location 1.75 ± 0.10
FPocket Location 7.5 ± 0.1
P22.0 ± 0.1
PPocket Pitch 12.0 ± 0.1
A0Pocket Dimensions 10.30 ±0.20
B010.30 ±0.20
K04.90 ±0.20
W1Cover Tape Width 13.2 ± 0.2
dCover Tape Thickness 0.1 max
Max. Component Rotation or Tilt 10°
R Min. Bending Radius 30
d
0
P
t2
D0
1
1
W
User Direction of Feed
0
K
B0
A0W
E
D
F
P
P
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 12
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers
Reflow Profile
Time (seconds)
Temperature (°C)
Time 25°C to Peak
260
240
220
200
180
160
140
120
100
80
60
40
20
0
TL
ts
tL
tP
TP
Tsmax
Tsmin
120
Preheat Area
Max. Ramp-up Rate = 3°C/S
Max. Ramp-down Rate = 6°C/S
240 360
Profile Freature Pb-Free Assembly Profile
Temperature Min. (Tsmin) 150°C
Temperature Max. (Tsmax) 200°C
Time (tS) from (Tsmin to Tsmax) 60–120 seconds
Ramp-up Rate (tL to tP) 3°C/second max.
Liquidous Temperature (TL) 217°C
Time (tL) Maintained Above (TL) 60–150 seconds
Peak Body Package Temperature 260°C +0°C / –5°C
Time (tP) within 5°C of 260°C 30 seconds
Ramp-down Rate (TP to TL) 6°C/second max.
Time 25°C to Peak Temperature 8 minutes max.
©2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
6N137M, HCPL2601M, HCPL2611M, HCPL2630M, HCPL2631M Rev. 1.0.3 13
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®*
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Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in
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Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
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at any time without notice to improve the design.
Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Rev. I47
Single-Channel: 6N137M, HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M, HCPL2631M (Preliminary) — High Speed 10MBit/s Logic Gate Optocouplers