LTP5901-IPR/LTP5902-IPR
1
59012iprf
For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR
Typical applicaTion
neTwork FeaTures DescripTion
SmartMesh IP Network Manager
2.4GHz 802.15.4e
Wireless Embedded Manager
lTp5901/2-ipr FeaTures
n Complete Radio Transceiver, Embedded Processor,
and Networking Software for Forming a Self-Healing
Mesh Network
n SmartMesh
®
Networks Incorporate:
n Time Synchronized Network-Wide Scheduling
n Per Transmission Frequency Hopping
n Redundant Spatially Diverse Topologies
n Network-Wide Reliability and Power Optimization
n NIST Certified Security
n SmartMesh Networks Deliver:
n >99.999% Network Reliability Achieved in the
Most Challenging RF Environments
n Sub 50µA Routing Nodes
n Compliant to 6LoWPAN Internet Protocol (IP) and
IEEE 802.15.4e Standards
n Manages Networks of Up to 32 Nodes (LT P 5901/2-
IPRA) or Up to 100 Nodes (LT P 5901/2-IPRB)
n Sub 1mA Average Current Consumption Enables
Battery Powered Network Management
n RF Modular Certification Include USA, Canada, EU,
Japan, Taiwan, Korea, India, Australia and New
Zealand
n PCB Assembly with Chip Antenna (LT P 5901-IPR) or
with MMCX Antenna Connector (LT P 5902-IPR)
SmartMesh IP™ wireless sensor networks are self man-
aging, low power internet protocol (IP) networks built
from wireless nodes called motes. The LT P ™5901-IPR/
LT P 5902-IPR is the IP manager product in the Eterna
®
*
family of IEEE 802.15.4e printed circuit board assembly
solutions, featuring a highly integrated, low power radio
design by Dust Networks
®
as well as an ARM Cortex-M3
32-bit microprocessor running Dust’s embedded Smart-
Mesh IP networking software.
Based on the IETF 6LoWPAN and IEEE-802.15.4e stan-
dards, the LT P 5901/2-IPR runs SmartMesh IP network
management software to monitor and manage network
performance and provide a data ingress/egress point via
a UART interface. The SmartMesh IP software provided
with the LT P 5901/2-IPR is fully tested and validated, and
is readily configured via a software application program-
ming interface. With Dust’s time-synchronized SmartMesh
IP networks, all motes in the network may route, source
or terminate data, while providing many years of battery
powered operation.
SmartMesh IP motes deliver a highly flexible network
with proven reliability and low power performance in an
easy-to-integrate platform.
L, LT , LT C , LT M , Linear Technology, Dust, Dust Networks, Eterna, SmartMesh and the
Linear logo are registered trademarks and LT P , SmartMesh IP and the Dust Networks logo are
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419,
7881239, 7898322, 8222965.
* Eterna is Dust Networks’ low power radio SoC architecture.
59012IPR TA01
µCONTROLLERSENSOR
IN+
IN
SPILT C
®
2379-18
LTP5901/2-IPM
UART
UART
MOTE
EXPANDED VIEW
ANTENNA
LTP5901-IPR
HOST
APPLICATION
LTP5901-IPR/LTP5902-IPR
2
59012iprf
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Table oF conTenTs
Network Features .......................................... 1
LTP5901/2-IPR Features .................................. 1
Typical Application ........................................ 1
Description.................................................. 1
SmartMesh Network Overview ........................... 3
Absolute Maximum Ratings .............................. 4
Pin Configuration .......................................... 4
Order Information .......................................... 5
Recommended Operating Conditions ................... 5
DC Characteristics ......................................... 5
Radio Specifications ...................................... 6
Radio Receiver Characteristics .......................... 6
Radio Transmitter Characteristics ....................... 7
Digital I/O Characteristics ................................ 7
Temperature Sensor Characteristics .................... 7
System Characteristics ................................... 8
UART AC Characteristics .................................. 8
Time AC Characteristics .................................. 9
Radio_INHIBIT AC Characteristics ..................... 10
Flash AC Characteristics ................................. 10
Flash SPI Slave AC Characteristics .................... 10
External Bus AC Characteristics ........................ 11
Typical Performance Characteristics .................. 14
Pin Functions .............................................. 19
Operation................................................... 22
Power Supply ..........................................................23
Supply Monitoring and Reset ................................. 23
Precision Timing ..................................................... 23
Application Time Synchronization ..........................23
Time References ..................................................... 23
Radio ...................................................................... 24
UARTs ..................................................................... 24
API UART Protocol ................................................. 24
CLI UART ................................................................ 25
Autonomous MAC ...................................................25
Security .................................................................. 25
Temperature Sensor ...............................................25
Radio Inhibit ...........................................................25
Factory Installed Software ......................................25
Flash Data Retention ...............................................26
Networking .............................................................27
Applications Information ................................ 29
Regulatory and Standards Compliance ...................29
Soldering Information ............................................. 29
Related Documentation .................................. 29
Package Description ..................................... 30
Typical Application ....................................... 32
Related Parts .............................................. 32
LTP5901-IPR/LTP5902-IPR
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smarTmesh neTwork overview
A SmartMesh network consists of a self-forming multi-hop,
mesh of nodes, known as motes, which collect and relay
data, and a network manager that monitors and manages
network performance and security, and exchanges data
with a host application.
SmartMesh networks communicate using a time slotted
channel hopping(TSCH) link layer, pioneered by Dust
Networks. In a TSCH network, all motes in the network
are synchronized to within less than a millisecond. Time
in the network is organized into timeslots, which enables
collision-free packet exchange and per-transmission
channel-hopping. In a SmartMesh network, every device
has one or more parents (e.g. mote 3 has motes 1 and
2 as parents) that provide redundant paths to overcome
communications interruption due to interference, physical
obstruction or multi-path fading. If a packet transmission
fails on one path, the next retransmission may try on a
different path and different RF channel.
A network begins to form when the network manager
instructs its onboard access point (AP) radio to begin
sendingadvertisementspackets that contain information
that enables a device to synchronize to the network and
request to join. This message exchange is part of thesecu-
rityhandshake that establishes encrypted communications
between the manager or application, and mote. Once motes
have joined the network, they maintain synchronization
through time corrections when a packet is acknowledged.
to the network manager in packets called health reports.
The network manager uses health reports to continually
optimize the network to maintain >99.999% data reliability
even in the most challenging RF environments.
The use of TSCH allows SmartMesh devices to sleep in-
between scheduled communications and draw very little
power in this state. Motes are only active in timeslots
where they are scheduled to transmit or receive, typically
resulting in a duty cycle of < 1%. The optimization soft-
ware in the network manager coordinates this schedule
automatically. When combined with the Eterna low power
radio, every mote in a SmartMesh network—even busy
routing ones—can run on batteries for years. By default,
all motes in a network are capable of routing traffic from
other motes, which simplifies installation by avoiding the
complexity of having distinct routers vs non-routing end
nodes. Motes may be configured as non-routing to further
reduce that particular mote’s power consumption and to
support a wide variety of network topologies.
An ongoing discovery process ensures that the network
continually discovers new paths as the RF conditions
change. In addition, each mote in the network tracks per-
formance statistics (e.g. quality of used paths, and lists of
potential paths) and periodically sends that information
At the heart of SmartMesh motes and network managers
is the Eterna IEEE 802.15.4e System-on-Chip (SoC), fea-
turing Dust Networks’ highly integrated, low power radio
design, plus an ARM Cortex-M3 32-bit microprocessor
running SmartMesh networking software. The SmartMesh
networking software comes fully compiled yet is configu-
rable via a rich set of application programming interfaces
(APIs) which allows a host application to interact with
the network, e.g. to transfer information to a device, to
configure data publishing rates on one or more motes,
or to monitor network state or performance metrics. Data
publishing can be uniform or different for each device,
with motes being able to publish infrequently or faster
than once per second as needed.
HOST
APPLICATION
AP
NETWORK MANAGER
59012IPR SNO01
Mote
2
Mote
1
Mote
3
ALL NODES ARE ROUTERS.
THEY CAN TRANSMIT AND RECEIVE.
THIS NEW NODE CAN JOIN
ANYWHERE BECAUSE ALL
NODES CAN ROUTE.
59012IPR SNO02
LTP5901-IPR/LTP5902-IPR
4
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pin conFiguraTion
absoluTe maximum raTings
Supply Voltage on VSUPPLY ..................................3.76V
Input Voltage on AI_0/1/2/3 Inputs ........................1.80V
Voltage on Any Digital I/O Pin .... 0.3V to VSUPPLY + 0.3V
Input RF Level ...................................................... 10dBm
Storage Temperature Range (Note 3) ..... 55°C to 105°C
(Notes 1, 2) Operating Temperature Range
LTP5901I/LPT5902I .............................40°C to 8C
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions
be observed when handling the LTP5901/LTP5902-IPR.
Pin functions shown in italics are currently not supported in software.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
RESERVED
NC
GPIO17
GPIO18
GPIO19
AI_2
AI_1
AI_3
AI_0
GND
RESERVED
NC
NC
RESETn
TDI
TDO
TMS
TCK
GND
DP4
RESERVED
RESERVED
RESERVED
EB_DATA_7
EB_DATA_6
EB_DATA_4
EB_DATA_0
NC
GND
GND
NC
RADIO_INHIBIT
TIMEn
UART_TX
UART_TX_CTSn
UART_TX_RTSn
UART_RX
UART_RX_CTSn
UART_RX_RTSn
GND
VSUPPLY
RESERVED
NC
NC
FLASH_P_ENn / EB_IO_LE1
EB_IO_OEn
EB_IO_WEn
RESERVED / UARTC1_RX
RESERVED / UARTC1_TX
EB_IO_CS0n
EB_DATA_5
EB_DATA_2
EB_DATA_3
GND
EB_ADDR_0
EB_ADDR_1
IPCS_SSn
EB_IO_LE2
GND
IPCS_MISO
UARTCO_RX / EB_DATA_1
UARTCO_TX / EB_IO_LE0
PC PACKAGE
66-LEAD PCB
IPCS_SCK
IPCS_MOSI
GND
31 32 33 34 35 36
LTP5901-IPR/LTP5902-IPR
5
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orDer inFormaTion
LEAD FREE FINISH** PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT P 5901IPC-IPRA???#PBF LT P 5901IPC-IPRA???#PBF 66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna –40°C to 85°C
LT P 5901IPC-IPRB???#PBF LT P 5901IPC-IPRB???#PBF 66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna –40°C to 85°C
LT P 5901IPC-IPRC???#PBF LT P 5901IPC-IPRC???#PBF 66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna –40°C to 85°C
LT P 5902IPC-IPRA???#PBF LT P 5902IPC-IPRA???#PBF 66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX
Connector
–40°C to 85°C
LT P 5902IPC-IPRB???#PBF LT P 5902IPC-IPRB???#PBF 66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX
Connector
–40°C to 85°C
LT P 5902IPC-IPRC???#PBF LT P 5902IPC-IPRC???#PBF 66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX
Connector
–40°C to 85°C
*The temperature grade is identified by a label on the shipping container.
**The sofware version is indicated by ???. For specific ordering information, go to: www.linear.com/ltp5901-ipr#orderinfo or
www.linear.com/ltp5902-ipr#orderinfo
For a description of the dash options see the IP Manager Options section.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
recommenDeD operaTing conDiTions
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSUPPLY Supply Voltage Including Noise and Load Regulation l 2.1 3.76 V
Supply Noise 50Hz to 2MHz l250 mV
Operating Relative Humidity Non-Condensing l10 90 % RH
Temperature Ramp Rate While Operating in
Network
l–8 8 °C/min
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
Dc characTerisTics
OPERATION/STATE CONDITIONS MIN TYP MAX UNITS
Power-On Reset During Power-On Reset, Maximum 750µs + VSUPPLY Rise Time from 1V to
1.9V
12 mA
Doze RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and
State Retained, 32.768kHz Reference Active
1.2 µA
Deep Sleep RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and
State Retained, 32.768kHz Reference Inactive
0.8 µA
In-Circuit Programming RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz 20 mA
Peak Operating Current
8dBm
0dBm
System Operating at 14.7MHz, Radio Transmitting, During Flash Write.
Maximum Duration 4.33 ms.
30
26
mA
mA
Active ARM Cortex-M3, RAM and Flash Operating, Radio and All Other Peripherals
Off. Clock Frequency of CPU and Peripherals Set to 7.3728MHz, VCORE =
1.2V
1.3 mA
Flash Write Single Bank Flash Write 3.7 mA
Flash Erase Single Bank Page or Mass Erase 2.5 mA
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
LTP5901-IPR/LTP5902-IPR
6
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OPERATION/STATE CONDITIONS MIN TYP MAX UNITS
Radio Tx
0dBm
8dBm
Current with Autonomous MAC Managing Radio Operation, CPU Inactive.
Clock Frequency of CPU and Peripherals Set to 7.3728MHz.
5.4
9.7
mA
mA
Radio Rx Current with Autonomous MAC Managing Radio Operation, CPU Inactive.
Clock Frequency of CPU and Peripherals Set to 7.3728MHz.
4.5 mA
Dc characTerisTics
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Frequency Band l2.4000 2.4835 GHz
Number of Channels l15
Channel Separation l5 MHz
Channel Center Frequency Where k = 11 to 25, as Defined by IEEE.802.4.15 l2405 + 5*(k-11) MHz
Raw Data Rate l250 kbps
Antenna Pin ESD Protection HBM Per JEDEC JESD22-A114F (Note 2) ±6000 V
Range
Indoor
Outdoor
Free Space
25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m Above
Ground
100
300
1200
m
m
m
raDio speciFicaTions
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Receiver Sensitivity Packet Error Rate (PER) = 1% (Note 5) –93 dBm
Receiver Sensitivity PER = 50% –95 dBm
Saturation Maximum Input Level the Receiver Will
Properly Receive Packets
0 dBm
Adjacent Channel Rejection
(High Side)
Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Above the Desired Signal, PER = 1% (Note 5)
22 dBc
Adjacent Channel Rejection
(Low Side)
Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Below the Desired Signal, PER = 1% (Note 5)
19 dBc
Alternate Channel Rejection
(High Side)
Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Above the Desired Signal, PER = 1% (Note 5)
40 dBc
Alternate Channel Rejection
(Low Side)
Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Below the Desired Signal, PER = 1% (Note 5)
36 dBc
Second Alternate Channel
Rejection
Desired Signal at –82dBm, Second Alternate Modulated Channel
Either 15MHz Above or Below, PER = 1% (Note 5)
42 dBc
Co-Channel Rejection Desired Signal at –82dBm, Undesired Signal is an 802.15.4
Modulated Signal at the Same Frequency, PER = 1%
–6 dBc
LO Feed Through –55 dBm
Frequency Error Tolerance
(Note 6)
±50 ppm
Symbol Error Tolerance ±50 ppm
Received Signal Strength
Indicator (RSSI) Input
Range
–90 to -10 dBm
RSSI Accuracy ±6 dB
RSSI Resolution 1 dB
raDio receiver characTerisTics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
LTP5901-IPR/LTP5902-IPR
7
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PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Power
High Calibrated Setting
Low Calibrated Setting
Delivered to a 50Ω Load
8
0
dBm
dBm
Spurious Emissions
30MHz to 1000MHz
1GHz to 12.75GHz
2.4GHz ISM Upper Band Edge (Peak)
2.4GHz ISM Upper Band Edge (Average)
2.4GHz ISM Lower Band Edge
Conducted Measurement with a 50Ω Single-Ended
Load, 8dBm Output Power. All Measurements Made
with Max Hold.
RBW = 120kHz, VBW = 100Hz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 10Hz
RBW = 100kHz, VBW = 100kHz
< –70
–45
–37
–49
–45
dBm
dBm
dBm
dBm
dBc
Harmonic Emissions
2nd Harmonic
3rd Harmonic
Conducted Measurement Delivered to a 50Ω Load,
Resolution Bandwidth = 1MHz, Video Bandwidth =
1MHz.
–50
–45
dBm
dBm
raDio TransmiTTer characTerisTics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
VIL Low Level Input Voltage l–0.3 0.6 V
VIH High Level Input Voltage (Note 8) lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
VOL Low Level Output Voltage Type 1, IOL(MAX) = 1.2mA l0.4 V
VOH High Level Output Voltage Type 1, IOH(MAX) = –0.8mA lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
VOL Low Level Output Voltage Type 2, Low Drive, IOL(MAX) = 2.2mA l0.4 V
VOH High Level Output Voltage Type 2, Low Drive, IOH(MAX) = –1.6mA lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
VOL Low Level Output Voltage Type 2, High Drive, IOL(MAX) = 4.5mA l0.4 V
VOH High Level Output Voltage Type 2, High Drive, IOH(MAX) = –3.2mA lVSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
Input Leakage Current Input Driven to VSUPPLY or GND 50 nA
Pull-Up/Pull-Down Resistance 50
DigiTal i/o characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Offset Temperature Offset Error at 25°C ±0.25 °C
Slope Error ±0.033 °C/°C
TemperaTure sensor characTerisTics
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
LTP5901-IPR/LTP5902-IPR
8
59012iprf
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sysTem characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
Permitted Rx Baud Rate Error Both Application Programming Interface
(API) and Command Line Interface (CLI)
UARTs
l–2 2 %
Generated Tx Baud Rate Error Both API and CLI UARTs l–1 1 %
tRX_RTS to RX_CTS Assertion of UART_RX_RTSn to Assertion of
UART_RX_CTSn, or Negation of UART_RX_
RTSn to Negation of UART_RX_CTSn
l0 2 ms
tCTS_R to RX Assertion of UART_RX_CTSn to Start of Byte l0 20 ms
tEOP to RX_RTS End of Packet (End of the Last Stop Bit) to
Negation of UART_RX_RTSn
l0 22 ms
tBEG_TX_RTS to TX_CTS Assertion of UART_TX_RTSn to Assertion of
UART_TX_CTSn
l0 22 ms
tEND_TX_CTS to TX_RTS Negation of UART_TX_CTSn to Negation of
UART_TX_RTSn
2 Bit
Period
tTX_CTS to TX Assertion of UART_TX_CTSn to Start of Byte l0 2 Bit
Period
tEOP to TX_RTS End of Packet (End of the Last Stop Bit) to
Negation of UART_TX_RTSn
l0 1 Bit
Period
tRX_INTERBYTE Receive Inter-Byte Delay l100 ms
tTX to TX_CTS Start of Byte to Negation of UART_TX_CTSn l0 µs
uarT ac characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
Doze to Active State Transmit 5 µs
Doze to Radio Tx or Rx 1.2 ms
QCCA Charge to Sample RF Channel RSSI Charge Consumed Starting from Doze State
and Completing an RSSI Measurement
4 µC
QMAX Largest Atomic Charge Operation Flash Erase, 21ms Max Duration l200 µC
RESETn Pulse Width l125 µs
LTP5901-IPR/LTP5902-IPR
9
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Figure 1. API UART Timing
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
tSTROBE TIMEn Signal Strobe Width l125 µs
tRESPONSE Delay from Rising Edge of TIMEn to the Start of
Time Packet on API UART
l0 100 ms
tTIME_HOLD Delay from End of Time Packet on API UART to
Falling Edge of Subsequent TIMEn
l0 ns
Timestamp Resolution (Note 9) l1 µs
Network-Wide Time Accuracy (Note 10) l±5 µs
Time ac characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
Figure 2. Timestamp Timing
uarT ac characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
59012IPR F01
UART_TX_RTSn
UART_TX_CTSn
UART_TX BYTE 0 BYTE 1
tBEG_TX_RTS TO TX_CTS
tEND_TX_CTS TO TX_RTS
tTX_CTS TO TX
tTX TO TX_CTS
tEOP TO TX_RTS
tEND_TX_RTS TO TX_CTS
UART_RX_RTSn
UART_RX_CTSn
tRX_RTS TO RX_CTS
UART_RX
tEOP TO RX_RTS
tRX_RTS TO RX_CTS
tRX_CTS TO RX
tRX_INTERBYTE
BYTE 0 BYTE 1
59012IPR F02
TIMEn
UART_TX
tSTROBE tTIME_HOLD
tRESPONSE
TIME INDICATION PAYLOAD
LTP5901-IPR/LTP5902-IPR
10
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Flash spi slave ac characTerisTics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
tFP_EN_to_RESET Setup from Assertion of FLASH_P_ENn to
Assertion of RESETn
l0 ns
tFP_ENTER Delay from the Assertion RESETn to the First
Falling Edge of IPCS_SSn
l125 µs
tFP_EXIT Delay from the Completion of the Last Flash SPI
Slave Transaction to the Negation of RESETn
and FLASH_P_ENn
l10 µs
tSSS IPCS_SSn Setup to the Leading Edge of
IPCS_SCK
l15 ns
tSSH IPCS_SSn Hold from Trailing Edge of IPCS_SCK l15 ns
tCK IPCS_SCK Period l50 ns
tDIS IPCS_MOSI Data Setup l15 ns
tDIH IPCS_MOSI Data Hold l5 ns
tDOV IPCS_MISO Data Valid l3 ns
tOFF IPCS_MISO Data Three-State l0 30 ns
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
tWRITE Time to Write a 32-Bit Word (Note 11) l21 ms
tPAGE_ERASE Time to Erase a 2k Byte Page (Note 11) l21 ms
tMASS_ERASE Time to Erase 256k Byte Flash Bank (Note 11) l21 ms
Data Retention 25°C
85°C
105°C
100
20
8
Years
Years
Years
Flash ac characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS
tRADIO_OFF Delay from Rising Edge of RADIO_
INHIBIT to Radio Disabled
l20 ms
tRADIO_INHIBIT_STROBE Maximum RADIO_INHIBIT Strobe Width l2 s
raDio_inhibiT ac characTerisTics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
Figure 3. RADIO_INHIBIT Timing
59012IPR F03
RADIO_INHIBIT
RADIO STATE
tRADIO_OFF
tRADIO_INHIBIT_STROBE
ACTIVE/OFF ACTIVE/OFFOFF
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Figure 4. Flash Programming Interface Timing
59012IPR F04
IPCS_SCK
IPCS_MOSI
IPCS_SSn
RESETn
FLASH_P_ENn
tFP_EN_TO_RESET
tFP_ENTER
tSSS
tDIS
tDIH
tCK
tSSH
tFP_EXIT
Flash spi slave ac characTerisTics
exTernal bus ac characTerisTics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tLEPW EB_IO_LE0, EB_IO_LE1, EB_IO_LE2 Pulse
Width
l100 ns
tAH EB_DATA_[7:0] Address Hold from the
Rising Edge of EB_IO_LE0, EB_IO_LE1, and
EB_IO_LE2
EB_DATA_[7:0] During Address
Phase
l90 ns
tAV_to_DL EB_ADDR_[1:0] Address Valid Until
EB_DATA_[7:0] Data Latched
l90 ns
tCSn_to_OEn EB_CS0n Asserted Until EB_OEn Asserted l150 ns
tCSn_OFF EB_CS0n Negated Between External Bus
Transfers
l100 ns
tSU_to_CSn EB_ADDR_[1:0], EB_IO_WEn Setup to
EB_CSn Asserted
l50 ns
tH_from_CSn EB_ADDR_[1:0], EB_IO_WEn Hold from
EB_CSn Negated
l50 ns
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
LTP5901-IPR/LTP5902-IPR
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exTernal bus ac characTerisTics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
Figure 5. External Bus Read Timing
Figure 6. External Bus Write Timing
59012IPR F06
EB_DATA_[7:0] A[25:18] A[17:10] A[9:2] D[31:24] D[23:16] D[7:0] D[15:8]X X
EB_IO_LE2
EB_IO_LE1
EB_IO_LE0
tLEPW
tLEPW
tLEPW
tH_from_CSn
tSU_to_CSn
tCSn tCSn_OFF
EB_ADDR_[1:0]
tAH tAH tAH
EB_IO_WEn
EB_IO_CS0n
11XX 10 01 0000
59012IPR F05
EB_DATA_[7:0] A[25:18] A[17:10] A[9:2] D[31:24] D[23:16] D[7:0] D[15:8]X X
EB_IO_LE2
EB_IO_LE1
EB_IO_LE0
tLEPW
tLEPW
tLEPW
tCSn_OFF
tAV_to_DL
tCSn_to_OEn
EB_ADDR_[1:0]
tAH tAH tAH
EB_IO_CS0n
EB_IO_OEn
11XX 10 01 00
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ESD (electrostatic discharge) sensitive device. ESD protection
devices are used extensively internal to Eterna. However, high electrostatic
discharge can damage or degrade the device. Use proper ESD handling
precautions.
Note 3: Extended storage at high temperature is discouraged, as this
negatively affects the data retention of Eterna’s calibration data. See
FLASH Data Retention section for details.
Note 4: Actual RF range is subject to a number of installation-specific
variables including, but not restricted to ambient temperature, relative
humidity, presence of active interference sources, line-of-sight obstacles,
and near-presence of objects (for example, trees, walls, signage, and so
on) that may induce multipath fading. As a result, range varies.
Note 5: As specified by IEEE Std. 802.15.4-2006: Wireless Medium
Access Control (MAC) and Physical Layer (PHY) specifications for Low-
Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.
org/findstds/standard/802.15.4-2011.html.
Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a
frequency tolerance of better than ±40ppm.
Note 7: Per pin I/O types are provided in the Pin Functions section.
Note 8: VIH maximum voltage input must respect the VSUPPLY maximum
voltage specification.
Note 9: See the SmartMesh IP Manager API Guide for the time indication
notification definition.
Note 10: Network time accuracy is a statistical measure and varies over
the temperature range, reporting rate and the location of the device relative
to the manager in the network. See Typical Performance Characteristics
section for a more detailed description.
Note 11: Code execution from flash banks being written or erased is
suspended until completion of the flash operation.
Note 12: Guaranteed by design. Not production tested.
exTernal bus ac characTerisTics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)
LTP5901-IPR/LTP5902-IPR
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Typical perFormance characTerisTics
In mesh networks data can propagate from the manager
to the nodes, downstream, or from the motes to the man-
ager, upstream, via a sequence of transmissions from one
device to the next. As shown in Figure 8, data originating
from mote P1 may propagate to the manager directly or
through P2. As mote P1 may directly communicate with
the manager, mote P1 is referred to as a 1-hop mote. Data
originating from mote D1, must propagate through at least
one other mote, P2 or P1, and as a result is referred to as
a 2-hop mote. The fewest number of hops from a mote to
the manager determines the hop depth.
As described in the Application Time Synchronization section,
Eterna provides two mechanisms for applications to
maintain a time base across a network. The synchroniza-
tion performance plots that follow were generated using
the more precise TIMEn input. Publishing rate is the rate
a mote application sends upstream data. Synchroniza-
tion improves as the publishing rate increases. Baseline
synchronization performance is provided for a network
operating with a publishing rate of zero. Actual performance
for applications in network will improve as publishing
rates increase. All synchronization testing was performed
with the 1-hop mote inside a temperature chamber. Tim-
ing errors due to temperature changes and temperature
differences both between the manager and this mote and
between this mote and its descendents therefore propa-
gated down through the network. The synchronization
of the 3-hop and 5-hop motes to the manager was thus
affected by the temperature ramps even though they were
at room temperature. ForC/minute testing the tempera-
ture chamber was cycled between –40°C and 85°C at this
rate for 24 hours. ForC/minute testing, the temperature
chamber was rapidly cycled between 85°C and 45°C for
eight hours, followed by rapid cycling between –5°C and
45°C for eight hours, and lastly, rapid cycling between
–40°C and 15°C for eight hours.
Figure 8. Example Network Graph
Figure 7a. Supply Current vs Packet Rate
Figure 7b. Packet Latency vs Reporting Interval
PACKET RATE (PACKETS/s)
0
0
SUPPLY CURRENT (mA)
0.8
1.0
1.2
2.0
59012IPR F07a
0.6
0.4
0.2
1.6
1.8
1.4
30
5 10 15 20 25
REPORTING INTERVAL (s)
0
0
MEDIAN LATENCY (s)
1.0
1.5
2.5
59012IPR F07b
0.5
2.0
30
5 10 15 20 25
5 HOPS
4 HOPS
3 HOPS
2 HOPS
1 Hop
MANAGER
1 HOP
2 HOP
3 HOP
5800IPM F08
P1
P2
P3
D1
D2
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Typical perFormance characTerisTics
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, Room Temperature
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 2°C/Min.
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 8°C/Min.
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, Room Temperature
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 2°C/Min.
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 8°C/Min.
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, Room Temperature
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 2°C/Min.
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 8°C/Min.
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
30
40
–10 40
59012IPR G01
20
10
0–30 –20 0 10 20 30
50
60 µ = 0.0
σ = 0.9
N = 89700
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
15
20
–10 40
59012IPR G02
10
5
0–30 –20 0 10 20 30
25
30 µ = –0.2
σ = 1.7
N = 89699
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
8
10
–10 40
59012IPR G03
6
4
2
0–30 –20 0 10 20 30
12
14 µ = –0.2
σ = 3.6
N = 89698
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
10
15
–10 40
59012IPR G04
5
0–30 –20 0 10 20 30
20 µ = 1.5
σ = 3.3
N = 93812
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
8
10
–10 40
59012IPR G05
6
4
2
0–30 –20 0 10 20 30
12
14 µ = 0.9
σ = 3.9
N = 93846
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
4
5
–10 40
59012IPR G06
3
2
1
0–30 –20 0 10 20 30
6
7µ = 1.0
σ = 7.7
N = 93845
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
8
–10 40
59012IPR G07
6
4
2
0–30 –20 0 10 20 30
10
12 µ = 3.6
σ = 5.0
N = 88144
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
8
–10 40
59012IPR G08
6
4
2
0–30 –20 0 10 20 30
10
14
12
µ = 1.1
σ = 3.8
N = 88179
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
4
–10 40
59012IPR G09
3
2
1
0–30 –20 0 10 20 30
5
7
6
µ = 1.0
σ = 7.4
N = 88178
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Typical perFormance characTerisTics
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
40
–10 40
59012IPR G10
30
20
10
0–30 –20 0 10 20 30
50
60
µ = 0.0
σ = 1.2
N = 22753
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
40
–10 40
59012IPR G11
30
20
10
00 –30 –20 0 10 20 30
50
60
µ = –0.2
σ = 1.2
N = 17008
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
40
–10 40
59012IPR G12
30
20
10
0–30 –20 0 10 20 30
50 µ = –0.2
σ = 1.2
N = 17007
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
20
25
–10 40
59012IPR G13
15
10
5
0–30 –20 0 10 20 30
30
35 µ = 0.5
σ = 1.9
N = 85860
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
30
35
–10 40
59012IPR G13
10
5
25
20
15
0–30 –20 0 10 20 30
40
45 µ = 0.1
σ = 1.5
N = 85858
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
35
–10 40
59012IPR G15
15
10
5
30
25
20
0–30 –20 0 10 20 30
µ = 0.1
σ = 1.5
N = 85855
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
60
–10 40
59012IPR G16
20
10
50
40
30
0–30 –20 0 10 20 30
µ = 0.2
σ = 1.4
N = 33932
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
60
–10 40
59012IPR G17
20
10
50
40
30
0–30 –20 0 10 20 30
µ = 0.0
σ = 1.3
N = 33930
SYNCHRONIZATION ERROR (µs)
–40
NORMALIZED FREQUENCY OF OCCURANCE (%)
–10 40
59012IPR G18
20
10
50
40
30
0–30 –20 0 10 20 30
µ = –1.0
σ = 1.3
N = 33929
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, Room Temperature
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, 2°C/Min.
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, 8°C/Min.
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, Room Temperature
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, 2°C/Min.
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, 8°C/Min.
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, Room Temperature
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, 2°C/Min.
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, 8°C/Min.
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Typical perFormance characTerisTics
As described in the SmartMesh Network Overview sec-
tion, devices in network spend the vast majority of their
time inactive in their lowest power state (Doze). On a
synchronous schedule a mote will wake to communicate
with another mote. Regularly occurring sequences which
wake, perform a significant function and return to sleep
are considered atomic. These operations are considered
atomic as the sequence of events can not be separated
into smaller events while performing a useful function.
For example, transmission of a packet over the radio is an
atomic operation. Atomic operations may be characterized
in either charge or energy. In a time slot where a mote
successfully sends a packet, an atomic transmit includes
setup prior to sending the message, sending the message,
receiving the acknowledgment and the post processing
needed as a result of the message being sent. Similarly
in a time slot when a mote successfully receives a packet,
an atomic receive includes setup prior to listening, listen-
ing until the start of the packet transition, receiving the
packet, sending the acknowledge and the post processing
required due to the arrival of the packet.
To ensure reliability each mote in the network is provided
multiple time slots for each packet it nominally will send
and forward. The time slots are assigned to communicate
upstream with at least two different motes. When combined
with frequency hopping this provides temporal, spatial
and spectral redundancy. Given this approach a mote will
often listen for a message that it will never receive, since
the time slot is not being used by the transmitting mote.
It has already successfully transmitted the packet. Since
typically three timeslots are scheduled for every one packet
to be sent or forwarded, motes will perform more of these
atomic idle listens than atomic transmit or atomic receive
sequences. Examples of transmit, receive and idle listen
atomic operations are shown below.
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Typical perFormance characTerisTics
Figure 9.