GX3146 146 x 146 3.5Gb/s Crosspoint Switch with Trace Equalization and Output De-emphasis Key Features Description * The GX3146 is a low-power, high-speed 146 x 146 crosspoint switch, with robust signal conditioning circuits for driving and receiving high-speed signals through backplanes. * * * * * * * * * * * * * * 146 x 146 crosspoint switch architecture supporting broadcast and multi-cast modes Supports all data rates up to 3.5Gb/s Low power consumption: 19.45W typical (all channels active) Sophisticated, dynamic on-chip power management control Independent, programmable input trace equalization to reduce deterministic jitter (ISI) Independent, programmable output de-emphasis for driving long board traces High-speed, video-optimized control for multi-format applications Built-in system test features with on-chip PRBS generators and analyzers 2.5V analog core voltage, 1.8V digital core voltage Input and output voltages support either 1.2V, 1.8V or 2.5V CML JTAG-controlled boundary scan Selectable parallel/serial host interface 50mm x 50mm BGA (2377 ball) Operating temperature range: 0C to +85C RoHS compliant Applications Large m x n cascaded routers/switch fabrics for: * * * * Professional broadcast applications Enterprise and carrier applications High-speed automated test equipment 10GbE and InfiniBand networks GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 The device typically consumes 19.45W of power with all channels operational, and features sophisticated, dynamically scalable power management. Unused portions of the core are automatically turned off without affecting the operation of the remaining channels. The signal conditioning features of the GX3146 include per-input programmable equalization and per-output programmable de-emphasis. The input equalizer removes ISI jitter--typically caused by PCB trace losses--by opening the input data eye in applications where long PCB traces are used. There are four settings available for the input equalizer, allowing flexibility in adjusting the equalization level on a per-input basis. Output de-emphasis capability provides a boost of the high-frequency content of the output signal, such that the data eye remains open after passing through a long interconnect of PCB traces and connectors. There are four de-emphasis settings that can be enabled on a per-output basis. Two integrated programmable pattern generators, and two pattern checkers are provided to assist in system test and configuration. The pattern generators can each be routed to any output of the device without impacting the normal operation of any other channel. Any input can be routed to each of the pattern checkers. The chip features eight independent strobe inputs, UPDATE_EN[7:0], which are used to determine the timing of the output updates. Any output can be linked to any strobe. www.semtech.com 1 of 46 Proprietary & Confidential TDI TMS TCK TDO JTAG and Boundary Scan SDIN HOST_S/P RESET S_CS SCLK SDOUT P_DAT [15:0] P_ADD P_R/W [11:0] P_ADS P_CS Parallel/Serial Interfaces and General Registers Input Configuration Latch Active Configuration Latch UPDATE_EN[7:0] Trace EQ SDI[0]/SDI[0] Output 0 Input 0 Trace EQ SDI[287]/SDI[287] Input 143 EXT_PG0/EXT_PG0 EXT_PG1/EXT_PG1 SDO[0]/SDO[0] De-Emp 146 x 146 Differential Cross-point Switch Matrix SDO[287]/SDO[287] De-Emp Output 143 Trace EQ De-Emp Input 144 Output 144 Trace EQ De-Emp Input 145 Output 145 Programmable Pattern Generator 1 Pattern Checker & Status Monitor 1 Programmable Pattern Generator 0 Pattern Checker & Status Monitor 0 MON0/MON0 MON1/MON1 Reference Clock/Crystal Buffer REF_CLK_IN REF_CLK_OUT GX3146 Functional Block Diagram GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 2 of 46 Proprietary & Confidential Revision History Version ECO PCN Date 2 011839 - March 2013 Changes and/or Modifications Corrected second bullet in Section 4.7.1, and added a note in Section 4.4. 1 158396 - October 2012 Included ESD Voltage Sensitivity in Table 2-1. Modifications to Table 4-18 and Section 4.12.2 to include Auto-Increment Timing and functionality. Updates to Appendix - Relevant Documentation with clear reference to correct documents. Converted document to Data Sheet. 0 157406 - February 2012 Converted document to Preliminary Data Sheet. Updates throughout. B 157284 - November 2011 A 156479 - July 2011 Corrections throughout the entire document. New document. Contents 1. Ball Out .............................................................................................................................................................5 1.1 Ball Assignment ................................................................................................................................5 1.2 Ball Descriptions ...............................................................................................................................6 2. Electrical Characteristics ............................................................................................................................9 2.1 Absolute Maximum Ratings ..........................................................................................................9 2.2 Recommended Operating Conditions .................................................................................... 10 2.3 DC Electrical Characteristics ..................................................................................................... 11 2.4 AC Electrical Characteristics ..................................................................................................... 15 3. Input/Output Equivalent Circuits ......................................................................................................... 17 4. Detailed Description.................................................................................................................................. 20 4.1 Serial Data Input ............................................................................................................................ 20 4.2 Serial Data Output ......................................................................................................................... 21 4.3 Crosspoint Switch Matrix Operation ...................................................................................... 23 4.4 Propagation Delay ......................................................................................................................... 24 4.5 Using Multiple Strobes ................................................................................................................. 24 4.6 Pattern Generator and Pattern Checker ................................................................................ 24 4.6.1 Pattern Generator.............................................................................................................. 24 4.6.2 Pattern Checker.................................................................................................................. 25 4.7 Horizontal Eye Measurement .................................................................................................... 29 4.7.1 Configuration for Horizontal Eye Measurement .................................................... 29 4.8 Temperature Sensors .................................................................................................................... 29 4.9 27MHz Reference Clock .............................................................................................................. 32 4.10 Device Power-Up ........................................................................................................................ 32 4.11 Device Reset .................................................................................................................................. 33 4.12 Host Interface ............................................................................................................................... 33 4.12.1 Parallel Host Interface Specifications ...................................................................... 33 GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 3 of 46 Proprietary & Confidential 4.12.2 Serial Host Interface Specifications .......................................................................... 38 5. Application Information .......................................................................................................................... 40 5.1 Power Supply Filtering and Recommendations .................................................................. 40 5.2 Estimated Worst-Case Load Current Steps ........................................................................... 41 5.2.1 VCC_25_A Supply............................................................................................................. 41 5.2.2 VCC_OUT1, VCC_OUT2 Supplies ................................................................................ 41 5.2.3 VCC_IN1, VCC_IN2 Supplies......................................................................................... 42 6. Package and Ordering Information...................................................................................................... 43 6.1 Package Dimensions ..................................................................................................................... 43 6.2 Package Thermal Data and Information ................................................................................ 44 6.3 Marking Diagram ........................................................................................................................... 44 6.4 Solder Reflow Profile .................................................................................................................... 45 6.5 Ordering Information ................................................................................................................... 45 GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 4 of 46 Proprietary & Confidential 1. Ball Out 1.1 Ball Assignment 1 2 3 4 5 6 7 8 9 10 13 14 15 20 21 24 25 26 29 30 33 34 37 38 48 49 A NC NC NC GND SDO_ 268 SDO_ 268 SDO_ 244 SDO_ 244 SDO_ 264 SDO_ 264 SDO_ 248 SDO_ 248 SDO_ 228 SDO_ 228 GND SDO_ 208 SDO_ 208 SDO_ 192 SDO_ SDO_ 176 192 SDO_ 176 SDO_ 160 SDO_ 160 GND SDO_ 144 SDO_ 144 SDO_ 124 SDO_ 124 SDO_ 112 SDO_ 112 SDO_ 96 SDO_ 96 SDO_ 80 SDO_ 80 GND SDO_ 60 SDO_ 60 SDO_ 44 SDO_ SDO_ 44 28 SDO_ 28 SDO_ 12 SDO_ MON0 MON0 12 GND NC NC NC A B NC NC GND GND GND SDO_ 280 SDO_ 280 SDO_ 236 SDO_ 236 SDO_ 240 SDO_ 240 SDO_ 232 SDO_ 232 GND SDO_ 212 SDO_ 212 SDO_ 188 SDO_ 188 SDO_ 172 SDO_ 172 SDO_ 156 SDO_ 156 GND SDO_ 140 SDO_ 140 SDO_ 128 SDO_ 128 SDO_ 108 SDO_ 108 SDO_ 92 SDO_ 92 SDO_ 76 SDO_ 76 GND SDO_ 64 SDO_ 64 SDO_ 48 SDO_ 48 SDO_ 32 SDO_ 32 SDO_ 16 SDO_ 16 SDO_ 0 SDO_ RSV _DNC 0 GND GND NC NC B C NC GND GND GND GND VCC_ OUT1 SDO_ 284 SDO_ 284 SDO_ 272 SDO_ 272 SDO_ 204 SDO_ 204 GND SDO_ 216 SDO_ 216 SDO_ 196 SDO_ 196 SDO_ 180 SDO_ 180 SDO_ 164 SDO_ 164 GND SDO_ 148 SDO_ 148 SDO_ 132 SDO_ 132 SDO_ 116 SDO_ 116 SDO_ 100 SDO_ 100 SDO_ 84 SDO_ 84 GND SDO_ 68 SDO_ 68 SDO_ 52 SDO_ 52 SDO_ 36 SDO_ 36 SDO_ 20 SDO_ 20 SDO_ 4 SDO_ RSV _DNC 4 GND GND GND GND NC C D GND GND GND GND GND GND RSV _DNC SDO_ 260 SDO_ 260 SDO_ 252 SDO_ 252 SDO_ 224 SDO_ 224 GND SDO_ 200 SDO_ 200 SDO_ 184 SDO_ 184 SDO_ 168 SDO_ 168 SDO_ 152 SDO_ 152 GND SDO_ 136 SDO_ 136 SDO_ 120 SDO_ 120 SDO_ 104 SDO_ 104 SDO_ 88 SDO_ 88 GND SDO_ 72 SDO_ 72 SDO_ 56 SDO_ 56 SDO_ 40 SDO_ SDO_ 24 40 SDO_ 24 SDO_ 8 SDO_ 8 GND GND GND GND GND GND D E EXT _PG1 RSV _DNC GND GND GND GND GND DTHERMA 3 SDO_ 276 SDO_ SDO_ 276 256 SDO_ SDO_ 220 256 SDO_ 220 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO VCC_ OUT1 GND GND GND GND GND GND SDI _0 E F EXT _PG1 SDI_ 3 RSV _DNC GND GND GND GND GND DTHERMK 3 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND GND VCC _IN1 SDI_ 4 SDI_ 0 F G SDI_ 7 SDI_ 3 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO VCC_ OUT1 GND GND RSV _DNC SDI_ 8 SDI_ 4 SDI_ 20 G H SDI_ 7 SDI_ 19 H J SDI_ 15 SDI_ 19 K SDI_ 15 SDI_ 35 SDI_ 43 SDI_ 11 11 12 16 17 18 19 22 23 27 28 31 32 35 36 39 40 GND GND GND GND VCC_ OUT1 VCC _IN2 GND GND GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO GND GND RSV _IO GND GND GND GND GND GND VCC_ OUT1 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND VCC_ OUT1 GND GND RSV _IO RSV _IO VCC _IN2 GND GND GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND VCC_ VCC_ OUT1 OUT1 GND GND GND GND GND GND GND GND GND GND GND GND SDI_ 11 SDI_ 23 SDI_ 43 SDI_ 23 SDI_ 27 L SDI_ 31 SDI_ 35 SDI_ 59 SDI_ 27 RSV _IO RSV _IO RSV _IO GND GND GND GND GND GND GND VCC_ VCC_ OUT1 OUT1 VCC_ OUT1 VCC_ VCC_ OUT1 OUT1 VCC_ VCC_ OUT1 OUT1 VCC_ OUT1 VCC_ VCC_ OUT1 OUT1 M SDI_ 31 SDI_ 51 SDI_ 59 SDI_ 39 RSV _IO RSV _IO RSV _IO RSV _IO VCC _IN2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND N SDI_ 47 SDI_ 51 SDI_ 71 SDI_ 39 RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND GND VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 P SDI_ 47 SDI_ 67 SDI_ 71 SDI_ 55 RSV _IO RSV _IO RSV _IO GND RSV _IO GND GND GND GND GND GND VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 GND R GND SDI_ 67 SDI_ 75 SDI_ 55 RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO GND GND GND GND EXT _CLK2 VCC _25_ LDO2 VCO2 GND VCC_ 25_A VCC_ 25_A GND VCC_ OUT1 VCC_ OUT1 VCC_ OUT1 VCC_ VCC_ VCC_ OUT1 OUT1 OUT1 VCC_ OUT1 GND GND GND GND GND GND GND GND GND VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND VCC_ VCC_ OUT1 OUT1 41 42 43 44 GND 45 46 47 GND GND GND GND GND GND DTHERMA 0 SDI_ 12 SDI_ 8 SDI_ 24 SDI_ 20 GND GND GND DTHERMK 0 SDI_ 16 SDI_ 12 SDI_ 28 SDI_ 24 SDI_ 40 J GND GND VCC _IN1 RSV _IO SDI_ 16 SDI_ 32 SDI_ 28 SDI_ 44 SDI_ 40 K GND GND GND RSV _IO RSV _IO SDI_ 36 SDI_ 32 SDI_ 48 SDI_ 44 SDI_ 60 L GND VCC _IN1 RSV _IO RSV _IO RSV _IO SDI_ 36 SDI_ 52 SDI_ 48 SDI_ 64 SDI_ 60 M N GND GND GND GND VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 GND GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 56 SDI_ 52 GND SDI_ 64 SDI_ 76 VCC_ OUT1 GND VCC_ OUT1 GND VCC_ OUT1 GND GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 56 GND SDI_ 68 GND SDI_ 76 P GND VCC_ 25_A VCC_ 25_A GND LDO0 VCC _25_ VCO0 EXT CLK0 GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND SDI_ 72 SDI_ 68 SDI_ 80 GND R T SDI_ 63 GND SDI_ 75 SDI_ 87 RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND EXT _CLK2 GND LF2 GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND LF0 GND EXT CLK0 GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO SDI_ 72 SDI_ 84 SDI_ 80 SDI_ 92 T U SDI_ 63 SDI_ 83 GND SDI_ 87 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND GND GND GND GND GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND GND GND GND GND GND GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO SDI_ 88 SDI_ 84 SDI_ 96 SDI_ 92 U V SDI_ 79 SDI_ 83 SDI_ 91 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND VDD _25 GND VDD_ 18 VDD_ 18 GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VDD_ VDD_ 18 18 GND GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO SDI_ 88 SDI_ 100 SDI_ 96 SDI_ 108 V W SDI_ 79 SDI_ 99 SDI_ 91 SDI_ 103 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND GND GND RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 104 SDI_ 100 SDI_ 112 SDI_ 108 W GND GND VDD_ 25 GND VCC_ 25_A VCC_ 25_A Y SDI_ 95 SDI_ 99 SDI_ 107 SDI_ 103 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 104 SDI_ 116 SDI_ 112 SDI_ 128 Y AA SDI_ 95 SDI_ 115 SDI_ 107 SDI_ 119 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND VCC _IN2 VCC _IN2 GND GND GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND GND GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 120 SDI_ 116 SDI_ 124 SDI_ 128 AA AB SDI_ 111 SDI_ 115 SDI_ 123 SDI_ 119 RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO GND GND GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND GND VCC_ VCC_ 25_A 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 120 GND SDI_ 124 SDI_ 144 AB AC SDI_ 111 SDI_ 131 SDI_ 123 SDI_ 135 RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO GND GND GND GND GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND SDI_ 132 GND SDI_ 144 AC AD SDI_ 127 SDI_ 131 SDI_ 139 SDI_ 135 RSV _IO VCC _IN2 VCC _IN2 GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_ REF_ CLK RSV _IO RSV _IO RSV _IO GND SDI_ 136 SDI_ 132 SDI_ 140 GND AD AE RSV _IO RSV _IO GND RSV _IO RSV _IO GND GND GND VCC_ 25_A GND GND GND REF_ CLK_ IN REF_ CLK_ OUT GND AE SDI_ 127 SDI_ 147 SDI_ 139 SDI_ 151 RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VDD_ 25 AF GND SDI_ 147 SDI_ 155 SDI_ 151 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND VDD_ 25 GND VDD_ 18 VDD_ 18 GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND VDD_ 18 VDD_ 18 GND AG SDI_ 143 GND SDI_ 155 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND GND GND GND GND GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND GND GND GND GND AH SDI_ 143 SDI_ 163 GND SDI_ 167 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND EXT _CLK1 GND LF1 GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND LF_ DIGITAL GND AJ SDI_ 159 SDI_ 163 SDI_ 171 SDI_ 167 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND EXT _CLK1 VCC_ 25_ VCO1 LDO1 GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND VCC_ 25_A VCC_ 25_A GND GND VCC_ 25_A VCC_ 25_A GND LDO_ DIGITAL AK SDI_ 159 SDI_ 175 SDI_ 171 SDI_ 183 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND GND GND GND GND GND GND GND VDD_ 18 GND GND VDDIO GND _D GND VDD_ 18 GND GND GND GND GND GND GND GND TCK TMS TDO TDI GND GND P_CS P_R/W P_ADS GND GND GND GND GND GND RSV _DNC RSV _DNC RSV _DNC RSV _DNC GND P_ADD P_ADD P_ADD P_ADD P_ADD P_ADD P_ADD P_ADD P_ADD P_ADD P_ADD P_ADD UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE _EN0 _EN1 _EN2 _EN3 _EN4 _EN5 _EN6 _EN7 0 1 2 3 4 5 6 7 8 9 10 11 GND AL SDI_ 179 SDI_ 175 SDI_ 187 SDI_ 183 RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO GND GND GND GND GND AM SDI_ 179 SDI_ 191 SDI_ 187 SDI_ 199 RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND GND AN SDI_ 195 SDI_ 191 SDI_ 203 SDI_ 199 RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO VCC _IN2 VCC _IN2 GND GND HOST_ SCLK S/P AP SDI_ 195 SDI_ 207 SDI_ 203 SDI_ 215 RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND VDD_ 18 AR GND SDI_ 207 SDI_ 219 SDI_ 215 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND VDDIO VDDIO VDDIO GND _D _D _D SDIN SDOUT S_CS VDDIO GND VDDIO _D _D GND VDD_ 18 GND VDD_ VDD_ 18 18 VDDIO VDD_ 18 _D GND VDD_ VDDIO 18 _D GND VDDIO VDDIO GND VDDIO VDDIO _D _D _D _D VDD_ 18 GND VDD_ 18 GND VDD_ 18 VDD_ 18 VDD_ 18 GND VDD_ 18 GND GND GND RSV _IO RSV _IO GND GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO SDI_ 136 SDI_ 148 SDI_ 140 SDI_ 160 GND GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO SDI_ 152 SDI_ 148 SDI_ 156 SDI_ 160 AF GND GND GND GND GND RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO SDI_ 152 SDI_ 164 SDI_ 156 SDI_ 176 AG EXT_ CLK_ DIGITAL GND GND GND GND RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 168 SDI_ 164 SDI_ 172 SDI_ 176 AH VCC_ EXT_ VCO_ CLK_ DIGITAL DIGITAL GND GND VCC _IN1 VCC _IN1 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 168 SDI_ 180 SDI_ 172 SDI_ 192 AJ GND GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 184 SDI_ 180 SDI_ 188 SDI_ 192 AK GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 184 SDI_ 196 SDI_ 188 SDI_ 208 AL GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND SDI_ 196 SDI_ 204 SDI_ 208 AM GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND SDI_ 200 GND SDI_ 204 SDI_ 224 AN GND VCC _IN1 VCC _IN1 RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO SDI_ 200 SDI_ 212 GND SDI_ 224 AP GND GND RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO SDI_ 232 SDI_ 212 SDI_ 220 GND AR P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT GND 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND VDDIO VDDIO GND _D _D GND GND VDD_ 18 POR_ DFT RSV RESET _DNC GND GND GND AT SDI_ 211 GND SDI_ 219 GND SDI_ 231 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND GND GND GND VCC_ 25_A GND RSV _IO GND RSV _IO RSV _IO RSV _IO SDI_ 232 SDI_ 216 SDI_ 220 SDI_ 240 AT AU SDI_ 211 SDI_ 223 GND SDI_ 235 SDI_ 231 RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND VCC_ OUT2 GND GND GND GND VCC_ 25_A GND RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 248 SDI_ 216 SDI_ 236 SDI_ 240 AU GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC _IN1 RSV _IO RSV _IO RSV _IO RSV _IO SDI_ 248 SDI_ 228 SDI_ 236 SDI_ 256 AV VCC_ VCC_ OUT2 OUT2 VCC_ OUT2 VCC_ OUT2 VCC_ VCC_ OUT2 OUT2 VCC_ VCC_ VCC_ OUT2 OUT2 OUT2 VCC_ OUT2 VCC_ OUT2 VCC_ VCC_ OUT2 OUT2 VCC_ VCC_ OUT2 OUT2 VCC_ OUT2 GND GND GND GND GND GND GND RSV _IO RSV _IO RSV _IO SDI_ 260 SDI_ 228 SDI_ 252 SDI_ 256 AW RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND GND VCC _IN1 RSV _IO RSV _IO SDI_ 260 SDI_ 244 SDI_ 252 SDI_ 272 AY RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO VCC_ OUT2 GND GND GND GND GND GND RSV _IO SDI_ 264 SDI_ 244 SDI_ 268 SDI_ 272 BA BB AV SDI_ 227 SDI_ 223 SDI_ 239 SDI_ 235 SDI_ 251 RSV _IO RSV _IO RSV _IO VCC _IN2 GND GND GND GND GND GND GND GND AW SDI_ 227 SDI_ 243 SDI_ 239 SDI_ 255 SDI_ 251 RSV _IO RSV _IO GND GND GND GND GND GND VCC_ 25_A VCC_ OUT2 VCC_ OUT2 VCC_ OUT2 AY SDI_ 247 SDI_ 243 SDI_ 259 SDI_ 255 SDI_ 271 RSV _IO VCC _IN2 GND GND GND GND GND VCC_ 25_A GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO GND RSV _IO BA SDI_ 247 SDI_ 263 SDI_ 259 SDI_ 275 SDI_ 271 DTHERMK 2 GND GND GND GND GND VCC_ OUT2 GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO VCC_ VCC_ OUT2 OUT2 BB SDI_ 267 SDI_ 263 SDI_ 279 SDI_ 275 DTHERMA 2 GND GND GND GND GND GND RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND GND GND GND GND GND VCC _IN1 SDI_ 264 SDI_ 276 SDI_ 268 SDI_ 280 Legend: BC SDI_ 267 SDI_ 283 SDI_ 279 RSV _DNC GND GND GND GND GND VCC_ OUT2 RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO VCC_ OUT2 GND GND GND GND GND GND SDI_ 276 SDI_ 284 SDI_ 280 BC Power BD SDI_ 287 SDI_ 283 VCC _IN2 GND GND GND GND GND GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO DTHERMK 1 GND GND GND GND GND RSV _DNC SDI_ 284 EXT _PG0 BD Ground BE SDI_ 287 GND GND GND GND GND GND VCC_ OUT2 RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO RSV _IO GND SDO_ 67 SDO_ 67 SDO_ 31 SDO_ 31 SDO_ 11 SDO_ 11 DTHERMA 1 GND GND GND GND GND RSV _DNC EXT _PG0 BE Input BF GND GND GND GND GND GND GND SDO_ 279 SDO_ 279 SDO_ 263 SDO_ 263 SDO_ 247 SDO_ 247 SDO_ 231 SDO_ 231 SDO_ 215 SDO_ 215 GND SDO_ 199 SDO_ 199 SDO_ 183 SDO_ 183 SDO_ 167 SDO_ 167 SDO_ 151 SDO_ 151 GND SDO_ 135 SDO_ 135 SDO_ 119 SDO_ 119 SDO_ 103 SDO_ 103 SDO_ 87 SDO_ 87 GND SDO_ 63 SDO_ 63 SDO_ 35 SDO_ 35 SDO_ 27 SDO_ 27 RSV _DNC GND GND GND GND GND GND BF Output BG NC GND GND GND GND RSV _DNC SDO_ 283 SDO_ 283 SDO_ 267 SDO_ 267 SDO_ 251 SDO_ 251 SDO_ 235 SDO_ 235 SDO_ 219 SDO_ 219 GND SDO_ 203 SDO_ 203 SDO_ 187 SDO_ 187 SDO_ 171 SDO_ 171 SDO_ 155 SDO_ 155 SDO_ 139 SDO_ 139 GND SDO_ 123 SDO_ 123 SDO_ 107 SDO_ 107 SDO_ 91 SDO_ 91 SDO_ 71 SDO_ 71 GND SDO_ 83 SDO_ 83 SDO_ 15 SDO_ 15 SDO_ 3 SDO_ 3 VCC_ OUT2 GND GND GND GND NC BG Digital Control BH NC NC GND GND RSV _DNC SDO_ 287 SDO_ 287 SDO_ 271 SDO_ 271 SDO_ 255 SDO_ 255 SDO_ 239 SDO_ 239 SDO_ 223 SDO_ 223 GND SDO_ 211 SDO_ 211 SDO_ 195 SDO_ 195 SDO_ 179 SDO_ 179 SDO_ 159 SDO_ 159 SDO_ 147 SDO_ 147 GND SDO_ 131 SDO_ 131 SDO_ 115 SDO_ 115 SDO_ 99 SDO_ 99 SDO_ 75 SDO_ 75 GND SDO_ 55 SDO_ 55 SDO_ 47 SDO_ 47 SDO_ 51 SDO_ 51 SDO_ 7 SDO_ DIGITAL _CL_SEL GND 7 GND NC NC BH Reserved BJ NC NC NC GND MON1 MON1 SDO_ 275 SDO_ 275 SDO_ 259 SDO_ 259 SDO_ 243 SDO_ 243 SDO_ 227 SDO_ 227 GND SDO_ 207 SDO_ 207 SDO_ 191 SDO_ 191 SDO_ 175 SDO_ 175 SDO_ 163 SDO_ 163 SDO_ 143 SDO_ 143 GND SDO_ 127 SDO_ 127 SDO_ 111 SDO_ 111 SDO_ 95 SDO_ 95 SDO_ 79 SDO_ 79 GND SDO_ 59 SDO_ 59 SDO_ 39 SDO_ 39 SDO_ 23 SDO_ 23 SDO_ 43 SDO_ SDO_ 19 43 SDO_ 19 NC NC NC BJ 1 2 3 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 29 30 33 34 46 47 48 49 4 5 6 22 23 31 32 35 36 37 38 39 40 41 42 43 44 45 GND Figure 1-1: GX3146 Ball Assignment Overview (Top View) GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 5 of 46 Proprietary & Confidential 1.2 Ball Descriptions Table 1-1 shows the descriptions for selected GX3146 balls. For a comprehensive list of balls from the GX3146 Crosspoint family, please refer to GX3290 (and family) Crosspoint Ball Guide. Table 1-1: Ball Descriptions Ball # Ball Name I/O Description AN16 SCLK I Serial Host Interface Clock. If unused, tie to ground. AN17 SDIN I Serial Host Interface Data Input. If unused, tie to ground. AN18 SDOUT O Serial Host Interface Data Output. Leave NC if not used. AN19 S_CS I Serial Host Interface Chip Select. Active-LOW. Must be tied LOW when HOST_S/P is set LOW. AL23 P_CS I Parallel host interface chip select. Active-LOW. Must be tied LOW when HOST_S/P is set HIGH. AL24 P_R/W I Selects between read and write operations on the parallel host interface. HIGH = Read, LOW = Write. If unused, tie to ground. AL25 P_ADS I Address and Data Strobe. Strobe signal for latching the address and data into the chip. See Section 4.12.1 for timing information. If unused, tie to ground. AM27 - AM16 P_ADD[11:0] I Address bus for the parallel interface. If unused, tie to ground. AN35 - AN20 P_DAT[15:0] I/O AN15 HOST_S/P I Host Interface Select pin. Selects between serial and parallel host interfaces. Serial host interface is enabled when HIGH, parallel host interface is enabled when LOW. Must assert RESET after changing this pin. AM35 - AM28 UPDATE_EN [7:0] I Update Strobes used to update the switch matrix configuration (see Section 4.5). If unused, weak pull-down to ground. AR33 POR_DFT I This pin disables the Power On Reset circuitry when HIGH. Weak internal pull-down. Leave NC if not used. AR35 RESET I Active-LOW reset for entire chip (see Section 4.11 for timing details). Weak internal pull-up. Leave NC if not used. AL17 TCK I JTAG test clock. Weak pull-up if not used. AL18 TMS I JTAG test mode start. Weak pull-up if not used. AL19 TDO O JTAG test data out. Leave NC if not used. AL20 TDI I JTAG test data in. Weak pull-up if not used. Serial Interface I/O Parallel Interface I/O Bi-directional data bus for the parallel interface. If P_CS is HIGH, these pins are configured as inputs. If unused, tie to ground. General I/O Test Interface GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 6 of 46 Proprietary & Confidential Table 1-1: Ball Descriptions (Continued) Ball # Ball Name I/O Description R17 LDO2 -- LDO filter capacitor for VCO_2. Connect through a 220nF capacitor to ground. See Figure 3-3 for configuration. R33 LDO0 -- LDO filter capacitor for VCO_0. Connect through a 220nF capacitor to ground. See Figure 3-3 for configuration. T17 LF2 -- PLL loop filter capacitor for VCO_2. See Figure 3-3 for configuration. Leave NC if not used. T33 LF0 -- PLL loop filter capacitor for VCO_0. See Figure 3-3 for configuration. Leave NC if not used. AH17 LF1 -- PLL loop filter capacitor for VCO_1. See Figure 3-3 for configuration. Leave NC if not used. AH33 LF_DIGITAL -- PLL loop filter capacitor for VCO_DIGITAL. Connect through a 47nF capacitor to ground. See Figure 3-3 for configuration. AJ17 LDO1 -- LDO filter capacitor for VCO_1. Connect through a 220nF capacitor to ground. See Figure 3-3 for configuration. AJ33 LDO_DIGITAL -- LDO filter capacitor for VCO_DIGITAL. Connect through a 220nF capacitor to ground. See Figure 3-3 for configuration. AE35 REF_CLK_IN -- Connect a 27MHz crystal between this ball and REF_CLK_OUT (or connect to a 27MHz clock source). See Section 4.9 and Figure 3-5. AF35 REF_CLK_OUT -- Connect a 27MHz crystal between this ball and REF_CLK_IN (if a clock source is used, leave floating). See Section 4.9 and Figure 3-5. Leave NC if not used. R15 EXT_CLK2 I External CML clock for Pattern Generator 1 (true). Leave NC if not used. R35 EXT_CLK0 I External CML clock for Pattern Checker 0 (true). Leave NC if not used. T15 EXT_CLK2 I External CML clock for Pattern Generator 1 (complement). Leave NC if not used. T35 EXT_CLK0 I External CML clock for Pattern Checker 0 (complement). Leave NC if not used. AH15 EXT_CLK1 I External CML clock for Pattern Checker 1 (complement). Leave NC if not used. AH35 EXT_CLK _DIGITAL I External CML clock for Pattern Transmitter 0/Digital Core (complement). Leave NC if not used. AJ15 EXT_CLK1 I External CML clock for Pattern Checker 1 (true). Leave NC if not used. AJ35 EXT_CLK _DIGITAL I External CML clock for Pattern Transmitter 0/Digital Core (true). Leave NC if not used. BH45 DIGITAL_CL_SEL I Clock select between external clock source (EXT_CLK_DIGITAL) and internal VCO (VCO_DIGITAL). This pin has a weak internal pull-up, and should be pulled LOW to use an external clock. Filtering Crystal Oscillator External Clocks GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 7 of 46 Proprietary & Confidential Table 1-1: Ball Descriptions (Continued) Ball # Ball Name I/O Description E8 DTHERMA3 -- Thermometer 3 diode terminals. See Section 4.8. Leave NC if not used. F9 DTHERMK3 -- Thermometer 3 diode terminals. See Section 4.8. Leave NC if not used. H45 DTHERMA0 -- Thermometer 0 diode terminals. See Section 4.8. Leave NC if not used. J44 DTHERMK0 -- Thermometer 0 diode terminals. See Section 4.8. Leave NC if not used. BA6 DTHERMK2 -- Thermometer 2 diode terminals. See Section 4.8. Leave NC if not used. BB5 DTHERMA2 -- Thermometer 2 diode terminals. See Section 4.8. Leave NC if not used. BD41 DTHERMK1 -- Thermometer 1 diode terminals. See Section 4.8. Leave NC if not used. BE42 DTHERMA1 -- Thermometer 1 diode terminals. See Section 4.8. Leave NC if not used. A44 MON0 O Serial monitoring output 0 (complement). Leave NC if not used. A45 MON0 O Serial monitoring output 0 (true). Leave NC if not used. BJ5 MON1 O Serial monitoring output 1 (true). Leave NC if not used. BJ6 MON1 O Serial monitoring output 1 (complement). Leave NC if not used. Temperature Sensors Monitors External Pattern Generators E1 EXT_PG1 I Serial pattern generator input 1 (complement). Leave NC if not used. F1 EXT_PG1 I Serial pattern generator input 1 (true). Leave NC if not used. BD49 EXT_PG0 I Serial pattern generator input 0 (true). Leave NC if not used. BE49 EXT_PG0 I Serial pattern generator input 0 (complement). Leave NC if not used. Reserved - Do Not Connect B45, C44, D7, E2, F3, G46, AL32, AL33, AL34, AL35, AR34, BC4, BD47, BE48, BF43, BG6, BH5, RSV_DNC -- Reserved. Do not connect. SDI/SDO Refer to the GX3290 (and family) Crosspoint Ball Guide for a detailed list of SDI and SDO balls. Power Refer to the GX3290 (and family) Crosspoint Ball Guide for a detailed list of power supply balls. Ground Refer to the GX3290 (and family) Crosspoint Ball Guide for a detailed list of ground balls. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 8 of 46 Proprietary & Confidential 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Value Supply Voltage (VDD_18) -0.3V to +2.1V Supply Voltage (VCC_IN1, VCC_IN2, VCC_25_A, VDD_25, VDDIO_D, VCC_OUT1, VCC_OUT2, VCC_25_REF_CLK, VCC_25_VCO0, VCC_25_VCO1, VCC_25_VCO2) -0.3V to +2.8V -0.3 to (0.3 + min[VCC_IN1, VCC_25_A])V for even numbered SDI inputs and EXT_PG0 Input Voltage Range -0.3 to (0.3 + min[VCC_IN2, VCC_25_A])V for odd numbered SDI inputs and EXT_PG1 ESD Voltage (HBM; all balls) 1kV ESD Voltage (CDM; all balls) 100V Storage Temperature Range -50C to +125C Operating Temperature Range 0C to 85C Solder Reflow Temperature 245C GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 9 of 46 Proprietary & Confidential 2.2 Recommended Operating Conditions Table 2-2: Recommended Operating Conditions Parameter Symbol Min Typ Max Units Notes VCC_25_A, VCC_25_REF_CLK 2.375 2.5 2.625 V 1 1.14 1.2 1.26 V 2 1.71 1.8 1.89 V 3 2.375 2.5 2.625 V 1 1.14 1.2 1.26 V 2 1.71 1.8 1.89 V 3 2.375 2.5 2.625 V 1 1.71 1.8 1.89 V 3 1.71 1.8 1.89 V 3 2.375 2.5 2.625 V 1 VDD_25 2.375 2.5 2.625 V 1 Operating Temperature Range (case) TOP 0 25 85 C -- Start-up Temperature Range TSU -40 -- 85 C -- VCC_IN1, VCC_IN2 Operating Power Supply VCC_OUT1, VCC_OUT2 VDD_18 VDDIO_D Notes: 1. 2.5V supply. 2. 1.2V supply. 3. 1.8V supply. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 10 of 46 Proprietary & Confidential 2.3 DC Electrical Characteristics Table 2-3: DC Electrical Characteristics Parameter Symbol Conditions Min Typ Max Units Note All channels active, VCC_IN[1,2] = VCC_OUT[1,2] = 1.2V5%, VOD = 200mV, VSDI = 800mVppd, de-emphasis=6, without Pattern Generator/Checker, AC-coupled -- 19.45 25.5 W 1 All channels active, VCC_IN[1,2] = VCC_OUT[1,2] = 1.2V5%, VOD = 400mV, VSDI = 800mVppd, de-emphasis=6, without Pattern Generator/Checker, AC-coupled -- 21.29 -- W 1 All channels active, VCC_IN[1,2] = VCC_OUT[1,2] = 2.5V5%, VOD = 800mV, VSDI = 800mVppd, de-emphasis=6, without Pattern Generator/Checker, AC-coupled -- 24.86 32 W 1 All channels active, VCC_IN[1,2] = VCC_OUT[1,2] = 2.5V5%, VOD = 1200mV, VSDI = 800mVppd, de-emphasis=6, without Pattern Generator/Checker, AC-coupled -- 27.37 35 W 1 PRBS Generator/Checker -- 1.86 -- W -- RESET = 0 -- 0.5 -- W -- With de-emphasis, without Pattern Generator/Checker -- 8 9.5 A -- Without de-emphasis, without Pattern Generator/Checker -- 7.6 -- A -- System Power Power in Reset Mode Current - VCC_25_A GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 P P ICC_25_A www.semtech.com 11 of 46 Proprietary & Confidential Table 2-3: DC Electrical Characteristics (Continued) Parameter Current - VCC_IN1 Current - VCC_IN2 Current - VCC_OUT1 GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 Symbol Conditions Min Typ Max Units Note All inputs active, VSDI = 1.2Vppd, DC-coupled -- 0.85 -- A 2 All inputs active, VSDI = 1.2Vppd, AC-coupled -0.2 -- 0 A 3 All inputs active, VSDI = 1.2Vppd, DC-coupled -- 0.85 -- A 2 All inputs active, VSDI = 1.2Vppd, AC-coupled -0.2 -- 0 A 3 VCC_OUT1 = 1.2V 5%, all outputs active, VOD = 200mV, with De-emphasis -- 0.16 0.20 A 4 VCC_OUT1 = 1.2V 5%, all outputs active, VOD = 400mV, with De-emphasis -- 0.30 -- A 4 VCC_OUT1 = 1.2V 5%, all outputs active, VOD = 800mV, with De-emphasis -- 0.56 -- A 4, 5 VCC_OUT1 = 2.5V 5%, all outputs active, VOD = 200mV, with De-emphasis -- 0.17 -- A 4 VCC_OUT1 = 2.5V 5%, all outputs active, VOD = 400mV, with De-emphasis -- 0.30 -- A 4 VCC_OUT1 = 2.5V 5%, all outputs active, VOD = 800mV, with De-emphasis -- 0.62 0.75 A 4 VCC_OUT1 = 2.5V 5%, all outputs active, VOD = 1200mV, with De-emphasis -- 0.82 1.03 A 4 ICC_IN1 ICC_IN2 ICC_OUT1 www.semtech.com 12 of 46 Proprietary & Confidential Table 2-3: DC Electrical Characteristics (Continued) Parameter Current - VCC_OUT2 Symbol ICC_OUT2 Conditions Min Typ Max Units Note VCC_OUT2 = 1.2V 5%, all outputs active, VOD = 200mV, with De-emphasis -- 0.16 0.20 A 4 VCC_OUT2 = 1.2V 5%, all outputs active, VOD = 400mV, with De-emphasis -- 0.30 -- A 4 VCC_OUT2 = 1.2V 5%, all outputs active, VOD = 800mV, with De-emphasis -- 0.56 -- A 4, 5 VCC_OUT2 = 2.5V 5%, all outputs active, VOD = 200mV, with De-emphasis -- 0.17 -- A 4 VCC_OUT2 = 2.5V 5%, all outputs active, VOD = 400mV, with De-emphasis -- 0.30 -- A 4 VCC_OUT2 = 2.5V 5%, all outputs active, VOD = 800mV, with De-emphasis -- 0.62 0.75 A 4 VCC_OUT2 = 2.5V 5%, all outputs active, VOD = 1200mV, with De-emphasis -- 0.82 1.03 A 4 Current - VCC_25_REF_CLK ICC_25 _REF_CLK -- -- 20 40 mA -- Current - VCC_VCO_DIGITAL ICC_VCO _DIGITAL -- -- 6 10 mA -- Current - VCC_25_VCO0 ICC_25 _VCO0 -- -- 6 10 mA -- Current - VCC_25_VCO1 ICC_25 _VCO1 -- -- 6 10 mA -- Current - VCC_25_VCO2 ICC_25 _VCO2 -- -- 6 10 mA -- Current - VDD_18 IDD_18 VDD_18 = 1.8V5% -- 260 750 mA -- Current - VDD_25 IDD_25 VDD_25 = 2.5V5% -- 20 40 mA -- VDDIO_D = 1.8V5%, all inputs active (15pF load) -- 50 100 mA -- VDDIO_D = 2.5V5%, all inputs active (15pF load) -- 70 140 mA -- Current - VDDIO_D GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 IDDIO_D www.semtech.com 13 of 46 Proprietary & Confidential Table 2-3: DC Electrical Characteristics (Continued) Parameter Symbol Conditions Min Typ Max Units Note Differential -- 100 -- Single-ended -- 50 -- Serial Output Termination Differential -- 100 -- -- Serial Input Common Mode Voltage VICM VCC_IN[1,2] = 1.2V5%, VCC_IN[1,2] = 1.8V5%, VCC_IN[1,2] = 2.5V5%, terminated to VCC_IN[1,2] VCC_IN [1,2] (VSDI _max/4) -- VCC_IN [1,2] (VSDI _min/4) V 7, 8, 9, 10 Serial Output Common Mode Voltage VOCM VCC_OUT[1,2] = 1.2V5%, VCC_OUT[1,2] = 1.8V5%, VCC_OUT[1,2] = 2.5V5% VCC_OUT [1,2] (VOD_ max/4) -- VCC_OUT [1,2] (VOD_ min/4) V -- V 11 V 11 High-speed Inputs/Outputs Serial Input Termination 6 Host Interface Logic HIGH voltage on digital input pins VIH Logic LOW voltage on digital input pins VIL Output Logic LOW Output Logic HIGH 0.7 x VDDIO_D -- VDDIO_D + 0.3 0.3 x -0.3 -- IOL = 2mA, 2.5V operation -- -- 0.7 V 11 IOL = 2mA, 1.8V operation -- -- 0.45 V 11 IOH = -2mA, 2.5V operation 1.7 -- -- V 11 IOH = -2mA, 1.8 operation 1.35 -- -- V 11 VDDIO_D VOL VOH Notes: 1. Total Maximum Power is lower than individual maximum currents multiplied by individual maximum supply voltages because the individual maximum currents can not occur simultaneously (they occur at different conditions). 2. The ICC_IN1 and ICC_IN2 current flows out of the GX3146 and into the input signal source, and is subject to variability in that source. Some variability in input signal source current draw should be assumed, and up to 15% is possible. 3. When the common mode termination points for AC-coupled inputs are connected to VCC_IN1, VCC_IN2, the GX3146 equalizer input bias currents can lead to current flowing out of the VCC_IN1, VCC_IN2 supply pins. 4. Currents apply for output DC-coupled applications. When AC-coupled, the current draw may be increased by up to 2x. 5. For DC-coupled applications only. 6. Input termination is selectable between 100 differential and 50 single-ended. See Section 3.. 7. DC common mode current into/out of each EQ input differential pair should not exceed 14mA, and the current into/out of each half of the differential pair should not exceed 14mA. 8. No more than VCC_IN[1,2] - VSDI_actual/4. 9. Where it is understood that VCC_IN[1,2] have a 5% tolerance. 10.In no case should either side of the input differential pair be allowed to rise above VCC_25_A + 0.3V or fall below -0.3V. 11.Specifications relate to all host interface pins. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 14 of 46 Proprietary & Confidential 2.4 AC Electrical Characteristics Table 2-4: AC Electrical Characteristics Parameter Symbol Conditions Min Typ Max Units Notes System Serial Input Data Rate Propagation Delay Propagation Delay Difference DRSDO -- -- -- 3.5 Gb/s -- tP -- -- -- 6 ns 1 Between any two channels -- -- 5.5 ns 1 0.9 -- 1.8 s 2 tP High-speed Inputs/Outputs Output Switch Time using Update Enable Strobes VSDI -- 100 -- 1200 mVppd -- VOD VCC_OUT[1,2] = 1.2V5%, Output = 200mVppd 150 225 300 mVppd -- VCC_OUT[1,2] = 1.2V5%, Output = 400mVppd 300 450 600 mVppd -- VCC_OUT[1,2] = 1.2V5%, Output = 800mVppd 600 900 1200 mVppd 3 VCC_OUT[1,2] = 1.8V5%, Output = 200mVppd 150 225 300 mVppd -- VCC_OUT[1,2] = 1.8V5%, Output = 400mVppd 300 450 600 mVppd -- VCC_OUT[1,2] = 1.8V5%, Output = 800mVppd 600 900 1200 mVppd -- VCC_OUT[1,2] = 2.5V5%, Output = 200mVppd 150 225 300 mVppd -- VCC_OUT[1,2] = 2.5V5%, Output = 400mVppd 300 450 600 mVppd -- VCC_OUT[1,2] = 2.5V5%, Output = 800mVppd 600 900 1200 mVppd -- VCC_OUT[1,2] = 2.5V5%, Output = 1200mVppd 1000 1350 1700 mVppd -- All output swings. 20% to 80%. -- -- 150 ps -- Duty Cycle Distortion All data rates, all output swings. -50 -- +50 ps -- Additive Jitter All inputs active, peak-to-peak (PRBS 31) -- -- 60 psp-p -- 0 -- 12 dB 4 Range 0 -- 11.2 dB Maximum Setting 9 -- -- dB Input Voltage Swing Output Voltage Swing Output Rise/Fall Time tr/tf Input Trace Equalization Output De-Emphasis Setting 4 Host Interface GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 15 of 46 Proprietary & Confidential Table 2-4: AC Electrical Characteristics (Continued) Parameter Symbol Conditions Min Typ Max Units Notes Parallel Rate of Operation 0.1 -- 112.5 Mop/s 5, 6, 7 Serial Interface Operating Speed 0.1 -- 25 MHz 5, 8 Notes: 1. See Section 4.4 for more details. 2. This parameter is the time it takes for the outputs to change to a new switch matrix configuration when the corresponding strobe signal assigned to that output is asserted. 3. DC-coupled. 4. Selectable, maximum gain occurs at 3Gb/s (or 1.5GHz). 5. Specifications relate to all host interface pins. 6. Millions of operations per second. 7. For detailed timing specifications, see Section 4.12.1. 8. For detailed timing specifications, see Section 4.12.2. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 16 of 46 Proprietary & Confidential 3. Input/Output Equivalent Circuits Note: Please refer to the following supplementary documents: Crosspoint Design Guide and EB-GX3290 Schematics, PCB Layout and Bill of Materials. VCC_25_A HIZ_ACCM VCC_25_A VCC_IN[1,2] SDI[0:287] 50 50 SDI[0:287] EQ_TERMINATION[287:0] HIZ_ACCM Figure 3-1: Equalizer Input Equivalent Circuit VCC_OUT[1,2] 50 50 VCC_OUT[1,2] SDO[0:287] VCC_OUT[1,2] SDO[0:287] Delayed Main Figure 3-2: Trace Driver Output Equivalent Circuit Note: the MON0 and MON1 outputs are terminated to the VCC_25_A supply. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 17 of 46 Proprietary & Confidential If the internal temperature ADCs, pattern generators, and checkers are used, these connections are required. If the internal temperature ADCs, pattern generators, and checkers are not used, only these connections are required. VCC_25_A VCC_VCO_DIGITAL VCC_25_VCO0 VCC_25_VCO1 VCC_25_VCO2 267 267 1F 10nF 10F LF_DIGITAL LF2 47nF 1F 10F LF0 LF1 LF2 LF_DIGITAL 47nF 47nF 0 LDO_DIGITAL LDO0 LDO1 LDO2 VCC_25_VCO0 VCC_25_VCO1 VCC_25_VCO2 VCC_VCO_DIGITAL 10nF LF0 LF1 VCC_25_A 0 LDO0 LDO1 LDO2 LDO_DIGITAL 220nF 220nF 220nF Note 1: Each of the VCC_VCO_DIGITAL, VCC_VCO0, VCC_VCO1, and VCC_VCO2 pins require an independent RC network. Note 2: The LF_DIGITAL and LF2 pins each require an independent RC network. Note 3: The LF0 and LF1 pins each require an independent capacitor to ground. Note 4: Each of the LDO_DIGITAL, LDO0, LDO1, and LDO2 pins require an independent capacitor to ground. Note 5: VCC_VCO_DIGITAL, LF_DIGITAL and LDO_DIGITAL used for pattern generator TX0, digital communication (GSPI and APPI), and the internal temperature ADC for JNCTN_TEMP_1. VCC_VCO_DIGITAL, LF_DIGITAL and LDO_DIGITAL must always be connected. Note 6: VCC_25_VCO0, LF0, LDO0 used for pattern checker RX0 and the internal temperature ADC for JNCTN_TEMP_0. If VCC_25_VCO0, LF0, and LDO0 are not connected, pattern checker RX0 and the internal temperature ADC for JNCTN_TEMP_0 will not operate. Note 7: VCC_25_VCO1, LF1, LDO1 used for pattern checker RX1 and the internal temperature ADC for JNCTN_TEMP_2. If VCC_25_VCO1, LF1, and LDO1 are not connected, pattern checker RX1 and the internal temperature ADC for JNCTN_TEMP_2 will not operate. Note 8: VCC_25_VCO2, LF2, LDO2 used for pattern generator TX1 and the internal temperature ADC for JNCTN_TEMP_3. If VCC_25_VCO2, LF2, and LDO2 are not connected, pattern generator TX1 and the internal temperature ADC for JNCTN_TEMP_3 will not operate. Figure 3-3: Required connections for VCC_VCO_DIGITAL, VCC_25_VCO0, VCC_25_VCO1, VCC_25_VCO2, LF_DIGITAL, LF0, LF1, LF2, LDO_DIGITAL, LDO0, LDO1 and LDO2 GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 18 of 46 Proprietary & Confidential DIGITAL_CL_SEL EXT_CLK_DIGITAL /2 0 CMU 1 EXT_CLK_DIGITAL REF_CLK_IN REF_CLK_OUT Pattern TX0 XTAL OSC. Note: The clock used to drive Pattern Generator TX0 is also used to derive the clock timing for the digital core. Therefore, GSPI/APPI interface timing and update timing will track the external clock frequency if one is selected from the EXT_CLK_DIGITAL/EXT_CLK_DIGITAL pins for Pattern Generator TX0. BIST_RX_5 0x83C b4 EXT_CLK0 0 /2 EXT_CLK0 REF_CLK_IN REF_CLK_OUT XTAL OSC. Pattern RX0 CMU 1 BIST_RX_5 0x83C b6 EXT_CLK1 /2 0 EXT_CLK1 REF_CLK_IN REF_CLK_OUT XTAL OSC. Pattern RX1 CMU 1 BIST_TX_0 0x823 b0 EXT_CLK2 /2 0 EXT_CLK2 REF_CLK_IN REF_CLK_OUT XTAL OSC. Pattern TX1 CMU 1 Figure 3-4: PRBS Generator/Checker Clock Selection Using a crystal Using a single-ended 27MHz oscillator REF_CLK_IN REF_CLK_IN 1M 27MHz REF_CLK_OUT 27MHz Oscillator C1 REF_CLK_OUT C2 Note: The value of the C1 and C2 load capacitors are dependent on the chosen crystal. Figure 3-5: Crystal Oscillator GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 19 of 46 Proprietary & Confidential 4. Detailed Description 4.1 Serial Data Input Each of the GX3146 SDI inputs provide on-chip 100 differential terminations (or 50 single-ended). Each is compatible with input differential amplitudes from 100mVppd to 1200mVppd, and input signal sources having CML outputs referred to DC supplies of 1.2V, 1.8V or 2.5V. Note that for AC-coupled inputs, the recommended supply voltage for VCC_IN1 and VCC_IN2 is 1.8V. Each of the 146 SDI input channels include frequency domain equalization, independently-programmable to one of four levels, to compensate from 0 to 47 inches (119 cm) of FR4 trace at 3Gb/s. The boost at the 1.5GHz Nyquist frequency, and recommended trace length range, are shown under EQ_BOOST[287:0], EXT_PG0_EQ_BOOST, EXT_PG1_EQ_BOOST in Table 4-1. See Figure 3-1. Each input can be powered-down independently using the corresponding EQ_POWERDOWN[287:0] or EXT_PG0_EQ_POWERDOWN or EXT_PG1_EQ_POWERDOWN bit. To accommodate input signal sources with 1.2V supplies and 1200mVppd signal amplitudes, the input common mode point should be terminated to the respective VCC_IN1 or VCC_IN2 supply. The common mode termination connection to the respective VCC_IN1 or VCC_IN2 supply of each input can be independently controlled using the EQ_TERMINATION[287:0] or EXT_PG0_EQ_TERMINATION or EXT_PG1_EQ_TERMINATION bit (see Figure 3-1 and Table 4-1). Note 1: When the HIZ_ACCM bit is set (register address 0x400h bit 0), inputs with their common mode termination not connected to VCC_IN1 or VCC_IN2 are connected to an internal common mode bias. When an input EQ is powered-down, its common mode termination is automatically disconnected from the corresponding VCC_IN1 or VCC_IN2. For each of the inputs, there are control parameters (register address 0x401h to 0x522h). See Table 4-1 below. Note 2: The EXT_PG01_SOURCE_PIN_PRBSB and EXT_PG1_SOURCE_PIN_PRBSB bits in the TEST_SETUP register must be set to connect the EXT_PG0 and EXT_PG1 pins to the matrix. Table 4-1: Serial Data Input EQ_BOOST[287:0], EXT_PG0_EQ_BOOST and EXT_PG1_EQ_BOOST bits 1:0 (binary) Boost Applied (@ nominal 1.5GHz) 00 0dB boost 0" to 6" (15 cm) trace 01 3.5dB boost 6" (15 cm) to 16" (40 cm) trace 10 7.6dB boost 16" (40 cm) to 35" (89 cm) trace 11 12dB boost 35" (89 cm) to 47" (119 cm) trace GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 20 of 46 Proprietary & Confidential Table 4-1: Serial Data Input (Continued) EQ_TERMINATION[287:0], EXT_PG0_EQ_TERMINATION and EXT_PG1_EQ_TERMINATION bits 3:3 Input Termination Common Mode Point Switch to VCC_IN_1, VCC_IN_2 0 Open (see Figure 3-1) 1 Closed (see Figure 3-1) EQ_POWERDOWN[287:0], EXT_PG0_EQ_POWERDOWN and EXT_PG1_EQ_POWERDOWN bits 4:4 Equalizer Power 0 On 1 Off 4.2 Serial Data Output Each of the GX3146 SDI outputs have two on-chip 50 single-ended terminations, and can be programmed to output differential amplitudes of 200mVppd, 400mVppd or 800mVppd when the corresponding VCC_OUT1 or VCC_OUT2 is connected to either 1.2V or 1.8V, or 200mVppd, 400mVppd, 800mVppd, or 1200mVppd when the corresponding VCC_OUT1 or VCC_OUT2 is connected to 2.5V. The selection of the output swing is made using the corresponding OUTPUT_SWING_SET[287:0], MON0_OUTPUT_SWING_SET or MON1_OUTPUT_SWING_SET bits, shown in Table 4-3. If the HIGH_OP_V bit is set when either the VCC_OUT1 or VCC_OUT2 supplies are 1.2V or 1.8V, the 800mVppd swing setting is no longer valid for that output bank. Swing settings for an output bank connected to a 2.5V supply are unaffected. Table 4-2: HIGH_OP_V Swing Selection HIGH_OP_V = 0 HIGH_OP_V = 1 Valid Output Swing Selection (mVppd) Valid Output Swing Selection (mVppd) 1.2 200, 400, 800 200, 400 1 1.8 200, 400, 800 200, 400 -- 2.5 200, 400, 800 200, 400, 800, 1200 2 VCC_OUTx Supply Voltage (V) Note Notes: 1. For an 800mVppd output swing when the corresponding VCC_OUT1 or VCC_OUT2 is connected to 1.2V, the output must be DC-coupled to a receiving device terminated to 1.2V. 2. When VCC_OUT1 or VCC_OUT2 is set to 2.5V, the HIGH_OP_V bit must be set to enable 1200mVppd swing selection. Each of the 146 SDI output channels provide independently programmable de-emphasis, to compensate from 0 to 47 inches (119 cm) of FR4 trace at 3Gb/s. The selection of the amount of output de-emphasis is made using the corresponding OUTPUT_DEEMPHASIS[287:0], MON0_OUTPUT_DEEMPHASIS or MON1_OUTPUT_DEEMPHASIS bits, shown in Table 4-3. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 21 of 46 Proprietary & Confidential Each output can be independently powered-down by the setting of the corresponding bit: ACTIVE_POWER_DOWN[287:0], DYNAMIC_POWER_DOWN[287:0] together with the assigned strobe, MON0_POWER_DOWN, or MON1_POWER_DOWN. The polarity of the signal at each output can be independently inverted by setting the corresponding bit: ACTIVE_SIGNAL_INVERT[287:0], DYNAMIC_SIGNAL_INVERT[287:0] together with the assigned strobe, MON0_SIGNAL_INVERT, or MON1_SIGNAL_INVERT. Table 4-3: Serial Data Output OUTPUT_SWING_SET[287:0], MON0_OUTPUT_SWING_SET and MON1_OUTPUT_SWING_SET bits 2:0 (binary) Output Swing 000 200mVppd 001 400mVppd 011 800mVppd 110 1200mVppd 111 Reserved. Do not use. OUTPUT_DEEMPHASIS[287:0], MON0_OUTPUT_DEEMPHASIS and MON1_OUTPUT_DEEMPHASIS bits 5:3 (binary) Level of De-emphasis 000 Off 100 12" (30 cm) nominal 101 24" (60 cm) nominal 110 36" (90 cm) nominal 111 48" (120 cm) nominal ACTIVE_SIGNAL_INVERT[287:0], DYNAMIC_SIGNAL_INVERT[287:0], MON0_SIGNAL_INVERT or MON1_SIGNAL_INVERT Status 0 Not inverted 1 Inverted ACTIVE_POWER_DOWN[287:0], DYNAMIC_POWER_DOWN[287:0], MON0_POWER_DOWN or MON1_POWER_DOWN Status 0 On 1 Off GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 22 of 46 Proprietary & Confidential 4.3 Crosspoint Switch Matrix Operation The crosspoint switch matrix routes the serial digital input signals (SDI[0:287]/SDI[0:287], EXT_PG0/EXT_PG0 or EXT_PG1/EXT_PG1) to one or more serial digital outputs (SDO[0:287]/SDO[0:287], MON0/MON0 or MON1/MON1). The matrix is configured on a per output basis. Each serial digital output can be configured to accept a signal from one serial digital input. Multiple serial digital outputs can accept input from the same serial digital input. Updates to the switch matrix take place as soon as they are written to the host interface when controlling the device through the ACTIVE Configuration and Status Registers. These registers are the ACTIVE[287:0], MON0, and MON1 registers found in Section 2 of the Crosspoint (GX3290 and family) Reference Manual (for CSRs) document. Before the ACTIVE[287:0], MON0, and MON1 registers at addresses 0x200h through 0x321h can be directly used to update the crosspoint switch matrix, an initialization procedure is required. One of the UPDATE_EN[7:0] pins needs be toggled from a low state to a high state, and back to a low state again. Alternatively, set the SOFTWARE_UPDATE_ENABLE bit in the CONTROL_SETUP register at address 0xA00h to a value of 1, and then toggle one of the SOFT_UPDATE_EN[7:0] bits in the SOFT_UPDATE_CONTROL register at address 0xA01h from a value of 0 to a value of 1, and then back to a value of 0. If the ACTIVE[287:0], MON0, and MON1 registers are not being directly written by the system controller, this procedure is not required. Reading from the ACTIVE[287:0], MON0, and MON1 registers will work regardless of whether or not the above procedure is executed. Updating the crosspoint switch matrix using the DYNAMIC[287:0] registers (discussed below) does not require the initialization procedure described above. The switch matrix can also be updated using double-buffering when controlling the device through the DYNAMIC Configuration and Status Registers. These registers are DYNAMIC[287:0] in Section 1 of the Crosspoint (GX3290 and family) Reference Manual (for CSRs) document. When using dynamic configuration, updates to the switch matrix are first written to the DYNAMIC[287:0] registers where they are held until the corresponding update strobe signal, selected using the UPDATE_SELECT[287:0] bits in the DYNAMIC[287:0] registers, changes state from LOW-to-HIGH. The source for the update strobes can either be via external pins (UPDATE_EN[7:0]) or register bits (SOFT_UPDATE_EN[7:0]) as selected by the setting of the SOFTWARE_UPDATE_ENABLE bit in the CONTROL_SETUP register. Setting the SOFTWARE_UPDATE_ENABLE bit LOW causes the device to use the external UPDATE_EN[7:0] pins as update strobes for the switch matrix. Setting the SOFTWARE_UPDATE_ENABLE bit HIGH causes the device to use the SOFT_UPDATE_EN[7:0] bits as update strobes for the switch matrix. See Section 6 of the Crosspoint (GX3290 and family) Reference Manual (for CSRs) document. When the selected update strobe signal (or bit) transitions from LOW-to-HIGH, the state of all the outputs configured to respond to that update strobe signal (or bit) are updated at that time. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 23 of 46 Proprietary & Confidential Regardless of which register set is used to configure the switch matrix, the current configuration of the matrix is always available by reading back the ACTIVE[287:0] registers. Note: The MON0 and MON1 outputs can not be powered up/down, switched, or polarity inverted dynamically (Dynamic Configuration). They can only be configured in the Active Configuration mode described above using the settings in registers 0x320h and 0x321h, respectively. Also, the MON0 and MON1 outputs are terminated to the VCC_25_A supply. 4.4 Propagation Delay The propagation delay is dependent on the path that the signal takes through the device. Although the delay difference from the shortest path to the longest path could be up to 5.5ns, this difference is at a minimum for connections from inputs numerically close together and on the same side of the device to outputs that are numerically close together and on the same side of the device. Propagation delay differences of less than 750ps can be expected when the inputs are adjacent in the ballout and the outputs are also adjacent in the ballout. Note: The 750ps propagation delay difference (skew) between physically adjacent channels is guaranteed by simulation. 4.5 Using Multiple Strobes The GX3146 has eight fully-independent update strobes. Outputs 287 to 0 can be assigned to one of the eight strobes through the setting of the UPDATE_SELECT bits in the corresponding DYNAMIC[287:0] register. The input signal selection, output power switching and signal inversion will take effect on the LOW-to-HIGH edge of its assigned strobe signal or bit. This allows different portions of the crosspoint to be switched at different points in time. This is particularly useful in systems supporting multiple data or video formats, where the switch point/time varies from format to format. 4.6 Pattern Generator and Pattern Checker 4.6.1 Pattern Generator Note 1: There are two pattern generator "Tx" blocks in the GX3146. In the following, wherever only TX0 is mentioned, the corresponding is also true for TX1. Note 2: When the PRBS Generator is disabled, the generated signal does not completely terminate. The PRBS polynomial bits must be re-written in order to terminate the signal. The two pattern generator "Tx" blocks in the GX3146 can each independently generate PRBS 27-1, PRBS 215-1, and PRBS 223-1 data patterns, or alternating 1's and 0's. The built-in clock multiplier PLLs independently synthesize rates of 270Mb/s and 2.97Gb/s from the required, external 27MHz reference clock (see Section 4.9). Other rates up to 3Gb/s can be generated by providing an external clock signal at 2x, 4x, or 22x the desired bit rate to TX1, with a maximum external clock frequency of 6GHz. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 24 of 46 Proprietary & Confidential Table 4-4: Tx External Clocks TX0 TX1 EXT_CLK_DIGITAL (AJ35) EXT_CLK2 (R15) EXT_CLK_DIGITAL (AH35) EXT_CLK2 (T15) While this facility exists for both TX0 and TX1, the user is cautioned that the digital core clock is derived from the TX0 data clock, and therefore interface and update timing will track the external clock frequency if one is provided to TX0. The pattern generators are enabled by the TX0_PRBS_GEN_ENABLE and TX1_PRBS_GEN_ENABLE bits (register address 0x802h, bits [1:0] respectively). The PRBS generating polynomials used are: 1. PRBS7: x7 + x6 + 1 2. PRBS15: x15 + x14 + 1 3. PRBS23: x23 + x18 + 1 The pattern generated is selected via the TX0_PRBS_POLYNOMIAL and TX1_PRBS_POLYNOMIAL bits (register address 0x800h and 0x801h respectively). Table 4-5: Generated Patterns TX0_PRBS_POLYNOMIAL[1:0] (binary) Pattern Generated 00 PRBS7 01 PRBS15 10 PRBS23 11 Square Wave 4.6.2 Pattern Checker The pattern checkers de-serialize incoming serial data before checking for errors in the parallel domain. Three comparison modes are supported: 1. Neutral Phase Comparison Mode. The incoming data is re-timed in a CDR, and sampled at the neutral (eye center) phase recovered by the CDR before de-serialization. Errors with respect to the supported PRBS sequences can be counted. 2. Offset Phase Comparison Mode. The phase at which the incoming data is sampled with respect to the recovered clock is adjustable over a full UI. Errors with respect to the supported PRBS sequences can be counted. By sweeping the sampling phase and counting errors at each phase, an error rate "bathtub curve" can be recorded, and the horizontal eye opening evaluated. 3. Arbitrary Data Comparison Mode. This mode can operate on arbitrary data patterns. The incoming serial data is sampled at both the neutral phase and the adjustable phase, and each of the two sampled data streams is de-serialized and the two streams are compared in the parallel domain. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 25 of 46 Proprietary & Confidential The pattern checker allows a true measurement of bit error rate for the supported PRBS sequences in the first two modes above. The third, arbitrary data comparison mode, gives an indication of the degree of eye closure at a given sampling phase offset, but cannot detect bit errors in the incident data. See Figure 4-1 and Figure 4-2 below. EXT_PG0/EXT_PG0 Input 144 Output 144 Crosspoint Core (146 x 146) MON0/MON0 Serializer/ Pattern Generator CDR /2 Neutral Phase Deserializer /11 Variable Phase Deserializer /2 Pattern Generator 0 CMU /2 Pattern Checker 0 27MHz Pattern Checker EXT_CLK0 EXT_CLK0 REF_CLK_OUT REF_CLK_IN EXT_CLK_DIGITAL EXT_CLK_DIGITAL xtal osc. Figure 4-1: Simplified Pattern Generator/Checker Zero Block Diagram EXT_PG1/EXT_PG1 Input 145 Output 145 Crosspoint Core (146 x 146) MON1/MON1 Serializer/ Pattern Generator CDR /2 Neutral Phase Deserializer /11 Variable Phase Deserializer /2 Pattern Generator 1 CMU /2 Pattern Checker 1 27MHz Pattern Checker EXT_CLK1 EXT_CLK1 REF_CLK_OUT REF_CLK_IN EXT_CLK2 EXT_CLK2 xtal osc. Figure 4-2: Simplified Pattern Generator/Checker One Block Diagram Note: There are two pattern checker "Rx" blocks in the GX3146. In the following, wherever only RX0 is mentioned, the corresponding is also true for RX1. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 26 of 46 Proprietary & Confidential The CDR integrated in each Rx block can independently lock to data at rates of 270Mb/s, 1.485Gb/s and 2.97Gb/s. Other rates up to 3Gb/s can be analyzed by providing an external clock signal of 2x, 4x, or 22x the desired bit rate, with a maximum external clock frequency of 6GHz. Note that retiming is not possible when using an external clock signal for the Rx block. The external clock must be synchronous with any data to be checked and the RX0_PRBS_CHK_MODE bits must be set to a value of '01'. The two pattern checker "Rx" blocks in the GX3146 can each independently check PRBS 27-1, PRBS 215-1, and PRBS 223-1 data patterns. Table 4-6: Rx External Clocks RX0 RX1 EXT_CLK0 (R35) EXT_CLK1 (AJ15) EXT_CLK0 (T35) EXT_CLK1 (AH15) The error checking modes are selected by the RX0_PRBS_CHK_MODE bits and the RX1_PRBS_CHK_MODE bits (addresses 0x804h and 0x810h respectively). Table 4-7: Checking Modes RX0_PRBS_CHK_MODE[1:0] (binary) Input Mode 00 Check data sampled at neutral phase 01 Check data sampled at adjustable phase 10 or 11 Compare nominally sampled data with phase offset data (allows eye monitoring of arbitrary patterns) The pattern checker will check for the PRBS pattern specified by the RX0_PRBS_POLYNOMIAL and RX1_PRBS_POLYNOMIAL bits (addresses 0x803h and 0x811h respectively). The PRBS checkers are enabled by the RX0_PRBS_ENABLE and RX1_PRBS_ENABLE bits (register address 0x81Dh[1:0]). Table 4-8: Checked Patterns RX0_PRBS_POLYNOMIAL[1:0] (binary) Pattern Checked 00 PRBS7 01 PRBS15 10 PRBS23 The incident data can be inverted before checking by setting the corresponding RX0_INVERT_PRBS_IN or RX1_INVERT_PRBS_IN bit (address 0x803h[2:2] and 0x811h[2:2]) to '1'. The number of words to be compared is selectable via the corresponding RX0_PRBS_BER_TIME and RX1_PRBS_BER_TIME bits (registers 0x80Ah and 0x817h). GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 27 of 46 Proprietary & Confidential Table 4-9: Compared Words RX0_PRBS_BER_TIME[3:0] (binary) Number of words* compared (decimal) 0000 Infinite 0001 13 0010 26 0011 3277 0100 6554 0101 838861 0110 1677722 *Note: Each word is comprised of 10 bits, therefore the actual number of samples compared is 10 times the number of words compared. The status of the two pattern checking blocks is available in the RX0_PRBS_LOCK and RX1_PRBS_LOCK, RX0_PRBS_PASS and RX1_PRBS_PASS, RX0_PRBS_FAIL and RX1_PRBS_FAIL, and RX0_PRBS_ERROR_COUNT and RX1_PRBS_ERROR_COUNT read-only bits (see register addresses 0x81Eh to 0x821h). * RX0_PRBS_LOCK [0] - When HIGH, indicates that the pattern checker has acquired the pattern * RX0_PRBS_PASS [1] - When HIGH, indicates that the pattern was locked, and the specified number of words have been compared with fewer detected errors than specified by the RX0_PRBS_BER_THRESH parameter * RX0_PRBS_FAIL [2] - Indicates that the test terminated in a failure condition. There are three possible failure conditions: 1. The pattern generator failed to lock in the number of attempts specified by RX0_PRBS_LOCK_ATTEMPTS (in which case RX0_PRBS_LOCK would still be '0'). 2. The pattern generator locked, but over the period of time indicated by the RX0_PRBS_LOL_TIME bits, a greater number of errors were detected than allowed by the RX0_PRBS_LOL_THRESH setting. In this error condition, the device determines that it has "lost lock", and terminates the test. This error condition is detectable if both RX0_PRBS_LOCK and RX0_PRBS_FAIL bits are HIGH, and the value of RX0_PRBS_ERROR_COUNT is less than RX0_PRBS_BER_THRESH (the same applies for RX1_PRBS_LOCK, RX1_PRBS_FAIL and RX1_PRBS_ERROR_COUNT). 3. The pattern generator locked, but the number of errors observed exceeded the value indicated by the RX0_PRBS_BER_THRESH bits. This error is detectable if RX0_PRBS_LOCK and RX0_PRBS_FAIL are both HIGH, and the value of RX0_PRBS_ERROR_COUNT is equal or greater than the value in RX0_PRBS_BER_THRESH. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 28 of 46 Proprietary & Confidential Note that the values of RX0_PRBS_LOCK and RX1_PRBS_LOCK, RX0_PRBS_PASS and RX1_PRBS_PASS, RX0_PRBS_FAIL and RX1_PRBS_FAIL, RX0_PRBS_ERROR_COUNT and RX1_PRBS_ERROR_COUNT are reset whenever any of the corresponding test parameters for the RX0 and RX1 pattern checkers are updated as well as whenever the corresponding RX0_PRBS_ENABLE or RX1_PRBS_ENABLE bits are set to '1' when previously set to '0'. To start a new PRBS test when the previous one has already been run, either re-write RX0_PRBS_BER_TIME/RX1_PRBS_BER_TIME or toggle RX0_PRBS_ENABLE/RX1_PRBS_ENABLE. Note: The pattern checkers will count zero errors if the incident data is simply a static zero. 4.7 Horizontal Eye Measurement As explained above, the GX3146 enables the measurement of bit error "bathtub" curves at the video rates of 1485Mb/s and 2970Mb/s to assist in evaluating how much margin there is in the system. See Using the Monitoring Features of the GX3290 Application Note for more information. 4.7.1 Configuration for Horizontal Eye Measurement * Route the input signal of interest to the MON0 or MON1 of the matrix * Route the monitor output of matrix to pattern checker Rx , (RX0 in the notes below) by changing the RX0_CHECK_KEY_D2A word from its default value of 512 (decimal) to 288 (decimal) * For a PRBS pattern, select a pattern length with a value of the RX0_PRBS_POLYNOMIAL bits set to match the source pattern, and set the RX0_PRBS_CHK_MODE bits to 1 to select the phase interpolator path * For an arbitrary pattern, set the RX0_PRBS_CHK_MODE bits to 2 to select the direct data comparison mode * Set initial sampling phase with the RX0_PHASE_INTERPOLATOR_PHASE_SEL_D2A bits (in the BIST_RX_4 register) * Initiate error counting as described in Section 4.6.2 above * Increment the sampling phase * Count errors * Repeat last two steps to cover one UI 4.8 Temperature Sensors The GX3146 has twelve on-chip temperature sensors comprised of four junction diode temperature sensors and four ADCs, each with two selectable temperature sensors. Analog output voltages can be used to determine the temperature of the chip at the junction diode temperature sensors in four different locations. An external test current is applied to each sensor, and the voltage across the sensor is measured. Note that the "A" and "K" of the pin names indicate the preferred direction of the test current, but other junctions are present internally. Test currents should be limited to 10mA or less. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 29 of 46 Proprietary & Confidential DTHERMA[3:0] DTHERMK[3:0] Figure 4-3: Temperature Sensors In addition to the diode temperature sensors, four ADCs, each with two selectable temperature sensors, are also provided. Digitized temperatures can be read through the device's host interface. thermo ADC 3 Even Outputs 0 to 288 Crosspoint Core Odd Outputs 1 to 289 thermo ADC 2 Even Inputs 0 to 288 Odd Inputs 1 to 289 thermo ADC 1 Legend: ADC and "local" temperature sensors "remote" temperature sensors thermo ADC 0 Package Top-view of Die Figure 4-4: Map of Thermometer ADC Positions on Die Table 4-10: Junction Temperature Registers Thermometer ADC Sensor Location Select Register Result Register 0 ADC_IN_0 JNCTN_TEMP_0 1 ADC_IN_1 JNCTN_TEMP_1 2 ADC_IN_2 JNCTN_TEMP_2 3 ADC_IN_3 JNCTN_TEMP_3 Digitized 10-bit temperature values can be read through the host interface from registers JNCTN_TEMP_0 (register 0xA08h[9:0]) through JNCTN_TEMP_3 (register 0xA0Bh[9:0]). The temperature word in each register will be updated every 213 clock cycles, provided the value of the respective COUNT_PD_[3:0] bit remains LOW. When a COUNT_PD_[3:0] bit goes HIGH, the ADC is reset and the corresponding JNCTN_TEMP_[3:0] register retains its last updated value. The clock rate can be selected between 211kHz or 844kHz through the corresponding ADC_CTRL_CLK_SEL_[3:0] bits (registers 0xA04h, 0xA05h, 0xA06h and 0xA07h). GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 30 of 46 Proprietary & Confidential The junction temperature at each temperature sensor in terms of the ADC output code is given by: T j = 0.5489 x JNCTN_TEMP_[3:0] - 263 + 3 Where 3 is the temperature uncertainty. The accuracy of the temperature sensors can be improved by calibrating the GX3146 at a known junction temperature. Without calibration, the temperature uncertainty, due to process variations and component mismatch, can be as high as 27C. After calibration, the uncertainty can be reduced to about 2C. See Using the Monitoring Features of the GX3290 Application Note for more information. Table 4-11: Nominal Temperature-to-Code Conversion Tj (C) JNCTN_TEMP_ [3:0] Tj (C) JNCTN_TEMP_ [3:0] Tj (C) JNCTN_TEMP_ [3:0] Tj (C) JNCTN_TEMP_ [3:0] -40 406 2 483 44 559 86 636 -38 410 4 486 46 563 88 639 -36 414 6 490 48 567 90 643 -34 417 8 494 50 570 92 647 -32 421 10 497 52 574 94 650 -30 424 12 501 54 578 96 654 -28 428 14 505 56 581 98 658 -26 432 16 508 58 585 100 661 -24 435 18 512 60 588 102 665 -22 439 20 516 62 592 104 669 -20 443 22 519 64 596 106 672 -18 446 24 523 66 599 108 676 -16 450 26 527 68 603 110 680 -14 454 28 530 70 607 112 683 -12 457 30 534 72 610 114 687 -10 461 32 538 74 614 116 690 -8 465 34 541 76 618 118 694 -6 468 36 545 78 621 120 698 -4 472 38 548 80 625 122 701 -2 475 40 552 82 629 124 705 0 479 42 556 84 632 126 709 GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 31 of 46 Proprietary & Confidential 4.9 27MHz Reference Clock The GX3146 requires an external 27MHz reference clock for correct operation. This clock is multiplied to generate the digital core and interface clocks, and is also used to synthesize video rate clocks in the pattern generation blocks, and to acquire video rate signals in the pattern checker blocks. The reference clock has no impact on the jitter measurement performance when the pattern checker blocks are locked to external data sources, but has a direct impact on jitter performance within the loop bandwidth of the CMU PLL in the pattern generation blocks. The 27MHz reference clock can be generated by connecting a crystal between the REF_CLK_IN and REF_CLK_OUT balls, along with appropriate loading capacitors and a feedback resistor (see Figure 3-5). Alternatively, an LVCMOS 27MHz external clock source can be connected to the REF_CLK_IN ball with the REF_CLK_OUT ball left floating. The frequency variation of the crystal (including aging, supply and temperature variation) should be less than +/-100ppm if the PRBS checking and generation features are to be used in video applications. 4.10 Device Power-Up Note 1: No power supply sequencing is required (see Section 4.11). There is a 50s delay (tidle) between the power supplies reaching their nominal value and the device becoming operational. During this time, there should be no host interface activity, and the UPDATE_EN[7:0] pins must be held LOW. The RC filter, shown in Figure 3-3, on each of the four VCO supplies--VCC_25_VCO0, VCC_25_VCO1, VCC_25_VCO2 and VCC_VCO_DIGITAL--is required to minimize the phase noise of the PLLs in pattern generation/detection modes, but the rise time of the filter on VCC_VCO_DIGITAL in particular can impact the start-up time of the device internal clock. Note 2: In applications where power supplies reach their final voltage in under 1ms (the time for the internal clock to start), approximately two time constants of the RC filter on VCC_VCO_DIGITAL, can dominate the time for the GX3146 to emerge from reset upon power-up. In such cases, the time for VCC_VCO_DIGITAL can be traded-off against supply filtering and hence low-frequency jitter of patterns generated by Pattern Generator Zero. Note 3: RESET must be held LOW until all power supplies have stabilized. Supply voltage { Nominal voltage 95% Nominal voltage tidle Figure 4-5: Power-Up Timing Diagram GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 32 of 46 Proprietary & Confidential 4.11 Device Reset The RESET pin is an active-LOW asynchronous reset for the device. Assertion of the RESET pin sets the device in its minimum power state. The minimum pulse width of the RESET signal is 10ms (treset). There is a 50s delay (tidle) between the RESET signal going HIGH (inactive) and the device becoming operational. During this time (all of treset + tidle), there should be no host interface activity and the UPDATE_EN[7:0] pins must be held LOW. Note 1: RESET must be held LOW until all power supplies have stabilized. Note 2: Upon emerging from reset, all SDI inputs and SDO outputs are powered-down, pattern generation and checking is inactive, and all registers assume their reset values as noted in the Semtech Crosspoint (GX3290 and family) Reference Manual (for CSRs). RESET treset tidle Figure 4-6: Reset Timing Diagram 4.12 Host Interface 4.12.1 Parallel Host Interface Specifications The Asynchronous Parallel Peripheral Interface (APPI) on the GX3146 device allows an external host to access internal registers using parallel read and write operations. The GX3146 APPI is selected by setting the HOST_S/P pin LOW. Note: The S_CS pin must be pulled LOW when HOST_S/P is set LOW for parallel port communication. The host interface communicates with the Control and Status Registers (CSR) over an APPI bridge. It is possible to write one register every 10ns (100MHz write update rate). It is also possible to read one register every 20ns (50MHz read update rate). The parallel interface is asynchronous. During writes, an active-LOW P_CS (Chip Select) enables the interface and ADS (Address/Data Strobe) latches 12-bit write address and 16-bit write data into the device. During reads, the same P_CS signal is used, and the ADS signal latches the 12-bit read address and then clocks out the 16-bit read data. The P_R/W signal is used to differentiate between the two access types. An auto-increment mode exists for both reads and writes. This mode is configured by way of the APPI_AUTO_INCREMENT bit in the HOST_SETUP register. See Section 6 in the Semtech Crosspoint (GX3290 and family) Reference Manual (for CSRs). GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 33 of 46 Proprietary & Confidential Table 4-12: APPI Inputs/Outputs Signal Name I/O Description P_CS I Chip Select from the host. P_ADS I Address/Data Strobe from the host; used to "clock" address and write data into the chip, and to "clock" read data out of the chip. P_R/W I Read/Write indication from the host; HIGH for read, LOW for write. P_ADD[11:0] I Address from the host. P_DAT[15:0] I/O Write data from the host, or read data to the host. 4.12.1.1 APPI External Timing for Normal Write t CSH_w t SCS_w P_CS t HCS_w P_R/W t SRW_w P_ADD [11:0] t HRW_w A[11:0] t SA_w P_DAT [15:0] t HA_w D[15:0] t SD_w t HD_w P_ADS t PW_w Figure 4-7: External Timing for Normal Write Cycle Table 4-13: APPI External Timing Specifications for Normal Write Symbol Equiv. Cycles Min Typ Max Units P_CS LOW before P_ADS positive edge tSCS_w -- 10.0 -- -- ns P_CS hold time after P_ADS positive edge tHCS_w 2 14.8 -- -- ns P_R/W low before P_CS negative edge tSRW_w -- 1.5 -- -- ns P_R/W hold time after P_ADS positive edge tHRW_w 2 14.8 -- -- ns P_ADD[11:0] setup before P_ADS positive edge tSA_w -- 10.0 -- -- ns P_ADD[11:0] hold after P_ADS positive edge tHA_w -- 5.0 -- -- ns P_DAT[15:0] setup before P_ADS positive edge tSD_w -- 5.0 -- -- ns P_DAT[15:0] hold after P_ADS positive edge tHD_w -- 5.0 -- -- ns P_ADS LOW pulse width tPW_w 0.6 4.4 -- -- ns P_CS HIGH before next read/write cycle tCSH_w 5 37.0 -- -- ns -- -- -- -- 16.17 MHz Parameter Frequency for back-to-back single writes GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 34 of 46 Proprietary & Confidential 4.12.1.2 APPI External Timing for Auto-Increment Write t CSH_w P_CS t SCS_w P_R/W t HCS_w t SRW_w P_ADD [11:0] P_DAT [15:0] t HRW_w An [11:0] t SA_w t HA_w Dn [15:0] t SD_w Dn+1 [15:0] t HD_w t SD_w t HD_w P_ADS t PW_w t ADSH_w t PW_w Figure 4-8: External Timing for Auto-Increment Write Cycle Table 4-14: APPI External Timing Specifications for Auto-Increment Write Symbol Equiv. Cycles Min Typ Max Units P_CS LOW before P_ADS positive edge tSCS_w -- 10.0 -- -- ns P_CS hold time after last P_ADS positive edge tHCS_w 2 14.8 -- -- ns P_R/W LOW before P_CS negative edge tSRW_w -- 1.5 -- -- ns P_R/W hold time after P_ADS positive edge tHRW_w 2 14.8 -- -- ns P_ADD[11:0] setup before P_ADS positive edge tSA_w -- 10.0 -- -- ns P_ADD[11:0] hold after P_ADS positive edge tHA_w -- 5.0 -- -- ns P_DAT[15:0] setup before P_ADS positive edge tSD_w -- 4.0 -- -- ns P_DAT[15:0] hold after P_ADS positive edge tHD_w -- 4.0 -- -- ns P_ADS LOW pulse width tPW_w 0.6 4.4 -- -- ns tADSH_w 0.6 4.4 -- -- ns P_CS HIGH before next read/write cycle tCSH_w 5 37.0 -- -- ns Frequency during auto-increment write -- -- -- -- 112.5 MHz Parameter P_ADS HIGH before next pulse GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 35 of 46 Proprietary & Confidential 4.12.1.3 APPI External Timing for Normal Read t CSH_r P_CS t HCS_r t SCS_r t CDZ P_R/W t HRW_r t SRW_r t RDZ P_ADD [11:0] A[11:0] t SA_r P_DAT [15:0] t HA_r t DNZ D[15:0] t DO P_ADS t PW_r Figure 4-9: External Timing for Normal Read Cycle Table 4-15: APPI External Timing Specifications for Normal Read Symbol Equiv. Cycles Min Typ Max Units -- 1 -- -- -- -- P_CS LOW before P_ADS negative edge tSCS_r -- 5.0 -- -- ns P_CS hold time after P_ADS positive edge tHCS_r -- 5.0 -- -- ns P_R/W HIGH before P_CS negative edge tSRW_r -- 1.5 -- -- ns P_R/W hold time after P_ADS positive edge tHRW_r -- 5.0 -- -- ns P_ADD[11:0] setup before P_ADS negative edge tSA_r -- 0.0 -- -- ns P_ADD[11:0] hold after P_ADS positive edge tHA_r -- 0.0 -- -- ns P_DAT[15:0] out of tristate after P_ADS negative edge tDNZ 2 14.8 -- -- ns P_DAT[15:0] becomes valid after P_ADS negative edge tDO -- -- -- 65.0 ns P_DAT[15:0] goes tristate after P_CS positive edge tDZ -- -- -- 45.0 ns P_DAT[15:0] goes tristate after P_ADS positive edge tDZ -- -- -- 45.0 ns P_ADS LOW pulse width tPW -- 65.0 -- -- ns P_CS HIGH before next read/write cycle tCSH_r 3 22.2 -- -- ns Frequency for back-to-back single reads -- -- -- -- 10.29 MHz Parameter Internal read pipeline delay (0 if one-cycle read) GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 36 of 46 Proprietary & Confidential 4.12.1.4 APPI External Timing for Auto-Increment Read t CSH_r t SCS_r P_CS t HCS_r t CDZ P_R/W t HRW_r t SRW_r t RDZ P_ADD [11:0] An[11:0] t SA_r P_DAT [15:0] t HA_r t DNZ Dn [15:0] t DO1 Dn+1 [15:0] t DX t DO2 Dn+2 [15:0] t DX t DX t DO2 P_ADS t PW1_r t ADSH_r t PW2_r t ADSH_r t PW2_r Figure 4-10: External Timing for Auto-Increment Read Cycle Table 4-16: APPI External Timing Specifications for Auto-Increment Read Symbol Equiv. Cycles Min Typ Max Units -- 1 -- -- -- -- P_CS LOW before first P_ADS positive edge tSCS_r -- 5.0 -- -- ns P_CS hold time after last P_ADS positive edge tHCS_r -- 5.0 -- -- ns P_R/W HIGH before P_CS negative edge tSRW_r -- 1.5 -- -- ns P_R/W hold time after last P_ADS positive edge tHRW_r -- 5.0 -- -- ns P_ADD[11:0] setup before P_ADS negative edge tSA_r -- 0.0 -- -- ns P_ADD[11:0] hold after P_ADS positive edge tHA_r -- 0.0 -- -- ns P_DAT[15:0] out of tristate after P_ADS negative edge tDNZ 2 14.8 -- -- ns P_DAT[15:0] becomes valid after first P_ADS negative edge tDO1 -- -- -- 70.0 ns P_DAT[15:0] becomes valid after P_ADS positive edge tDO2 -- -- -- 13.0 ns P_DAT[15:0] becomes invalid after P_ADS positive edge tDX -- 3.0 -- -- ns P_DAT[15:0] goes tristate after P_CS positive edge tDZ -- 12.0 -- 45.0 ns P_DAT[15:0] goes tristate after P_ADS positive edge tDZ -- 12.0 -- 45.0 ns P_ADS first LOW pulse width tPW1_r -- 70.0 -- -- ns P_ADS subsequent LOW pulse widths tPW2_r 1.2 8.9 -- -- ns P_ADS HIGH between pulses tADSH_r 1.2 8.9 -- -- ns P_CS HIGH before next read/write cycle tCSH_r 5 37.0 -- -- ns Frequency during auto-increment read -- -- -- -- 56.2 5 MHz Frequency for back-to-back single reads in auto-increment mode -- -- -- -- 8.54 MHz Parameter Internal read pipeline delay (0 if one-cycle read) GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 37 of 46 Proprietary & Confidential 4.12.2 Serial Host Interface Specifications The Gennum Serial Peripheral Interface (GSPI) handles the communication with an external host over the SPI port. It allows configuration of the Control and Status Registers (CSR) using serial read and write operations. The GX3146 GSPI is selected by setting the HOST_S/P pin HIGH. Note 1: The P_CS pin must be pulled LOW when HOST_S/P is set HIGH for serial port communication. The GX3146 uses a four-wire protocol, with serial communication via the input SDIN pin, the output SDOUT pin, clock input signal (SCLK), and the chip select signal (S_CS). The signalling rate can be up to 25Mb/s. The interface uses 16-bit data and a 16-bit address/control. The 16-bit address and control consists of a 12-bit address, one read/write bit (`1' for read, `0' for write), one bit for auto-increment and two unused bits. The four-wire protocol is implemented as shown in Figure 4-11 and Figure 4-12. When the Auto-Increment bit is set LOW, each Command Word must be followed by only one Data Word to ensure proper operation. If the Auto-Increment bit is set HIGH, the following Data Word is written into the address specified in the Command Word, and subsequent Data Words are written into incremental addresses from the first Data Word. This facilitates multiple address reads or writes without sending a Command Word for each Data Word. Table 4-17: GSPI Inputs/Outputs Signal Name I/O Reference Clock SCLK I -- SDIN I SCLK GSPI serial data input SDOUT O SCLK GSPI serial data output (on the negative edge of SCLK) S_CS I -- t0 t1 Description GSPI clock GSPI Chip Select t2 t4 t7 SCLK t3 t8 S_CS SDIN SDOUT R R/W RSV RSV RSV RSV Auto_Inc Auto_Inc A11 A11 A10 A10 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 A0 D15 D15 D14 D14 D13 D12 D13 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 SDIN signal is looped out on SDOUT Figure 4-11: Serial Host Interface Timing Diagram - Write Mode GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 38 of 46 Proprietary & Confidential t5 t9 SCLK t6 S_CS SDIN SDOUT R/W R/W RSV RSV RSV RSV Auto_Inc A11 Auto_Inc A11 A10 A10 A9 A9 A8 A8 A7 A6 A7 A5 A6 A5 A3 A4 A4 A2 A3 A1 A2 A1 A0 A0 D15 D14 D13 SDIN signal is looped out on SDOUT D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Read Data is output on SDOUT Figure 4-12: Serial Host Interface Timing Diagram - Read Mode Table 4-18: Serial Host Interface Timing Parameter Symbol Conditions Equiv. Cycles Min Typ Max Units S_CS LOW before SCLK positive edge t0 -- 7.0 -- -- ns SCLK frequency -- -- 0.1 -- 25.0 MHz SCLK period t1 -- 40.0 -- 10,000 ns SCLK duty cycle t2 -- 40.0 50.0 60.0 % Input data setup time t3 -- 7.0 -- -- ns Time between end of Command Word (or previous data word in Auto-Increment mode) and the first SCLK of the following Data Word - write cycle t4 -- 40.0 -- -- ns Time between end of Command Word (or previous data word in Auto-Increment mode) and the first SCLK of the following Data Word - read cycle t5 -- 70.0 -- -- ns SDO hold time after SCLK negative edge t6 -- 5.0 -- 16.0 ns S_CS HIGH after last SCLK negative edge t7 1.2 9.0 -- -- ns Input data hold time t8 -- 5.0 -- -- ns S_CS HIGH time t9 2.5 18.5 -- -- ns 50% levels; 3.3V or 1.8V operation 70ns (t5) = 5 clock cycles at 135MHz plus SCLK and SDO signal propagation. 18.5ns (t9) = 2.5 clock cycles at 135MHz. Max t6 (16ns) represents the latest time by which the SDO will be stable after the SCLK negative edge. As SDO must be sampled on the SCLK positive edge, this determines the minimum SCLK period, and therefore the maximum SCLK frequency. SDO maximum transition time with 15pF load: 2ns. SDO maximum transition time with 50pF load: 5ns. Note 2: The GSPI and APPI are mutually exclusive (they can not both be used at the same time). GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 39 of 46 Proprietary & Confidential 5. Application Information Note: Please refer to the following supplementary documents: * Crosspoint Design Guide * EB-GX3290 Schematics, PCB Layout and Bill of Materials 5.1 Power Supply Filtering and Recommendations One of the most important steps that PCB designers can take to ensure power supply integrity for the GX3146 device is to design the PCB layer stack-up to minimize power plane pair inductance. Locating supply planes adjacent to ground planes, and separated by minimum thickness dielectrics in the stack-up, will minimize plane-pair inductance, and incidentally maximize the plane pair capacitance. Holes and cuts in the planes should be avoided as much as possible. While such closely spaced plane pairs allow the lowest inductance connections to supply pins of the GX3146 when they are closest to the device mounting surface of the PCB, the need to balance PCB stack-ups will lead to closely spaced layers on the far side of the PCB. The supply currents drawn from the VDD_18 and VDDIO_D supplies are noisy and activity dependent, and the corresponding supply/ground plane pairs should be treated as for FPGA or CPU devices. Supply currents drawn from the VCC_25_A, VCC_IN1, VCC_IN2, VCC_OUT1 and VCC_OUT2 supplies are continuous except under changes of the high speed signal path configuration. The VCC_OUT1 and VCC_OUT2 supplies in particular are subject to rapid steps in current under some configuration changes: the maximum combined current draw of the VCC_OUT1 and VCC_OUT2 supplies, 4.12A, can be switched in as little as 10ns. This current step may be reduced by appropriate programming of the device. Locating point of use voltage regulators close to the GX3146 device on the PCB will maximize the regulation roll-off frequency. At the highest frequencies, the GX3146 package and mounting parasitics will limit the effectiveness of any measures on the PCB to suppress voltage ripple on the device supplies. In between the voltage regulator roll off frequencies and the frequencies where parasitics on each supply domain within the GX3146 isolate the die from the PCB, decoupling capacitors on the PCB are effective. PCB layout effort should be spent on details of the decoupling capacitor mounting layout. Some simple layout measures can help to reduce the inductance of capacitor mounting. See the Crosspoint Design Guide for more detailed recommendations. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 40 of 46 Proprietary & Confidential 5.2 Estimated Worst-Case Load Current Steps Under normal operation, the power supply networks need to minimize voltage transients due to configuration change related load current steps. When the device reset is asserted while the device is drawing significant current, the load on power supplies could be shed fast enough to raise concerns about the board level voltage regulator dynamics, and the impact of any power supply network inductance. 5.2.1 VCC_25_A Supply The tail currents of CML blocks (the high-speed signal paths) in the matrix switch relatively slowly, with worst case switching times of 30ns and typical times ~50ns. The matrix supply current of ~5.4A could in principle switch in 30ns, but in practice the propagation delay of UPDATE_EN[7:0] signals across the matrix will increase the switching time somewhat. The VCC_25_A supply current drawn by individual EQs takes more than 10ns to rise upon application of control signals. The VCC_25_A supply current drops in as little as 5ns upon assertion of reset, though, and the reset signal arrival times at EQs in a bank are roughly uniformly distributed over an interval of 0.8ns. This means that the VCC_25_A current drawn by all EQs together, ~1.8A, could be shed in 5.8ns. The trace drivers draw significant current from the VCC_25_A supply, up to ~2.3A total for all trace drivers together, and this current can rise in as little as 20ns upon the de-assertion of power-down signals, or fall in as little as 1ns upon the assertion of power-down or reset signals. The arrival times of power-down or reset signals within the bottom trace driver bank are nearly uniformly distributed over an interval of 0.8ns, while the arrival time of power-down or reset signals within the top trace driver bank are nearly uniformly distributed over an interval of 4.4ns. The worst case total load current slew rate on the VCC_25_A supply is estimated from the above to be ~1.1GA/s. 5.2.2 VCC_OUT1, VCC_OUT2 Supplies In simulation, the tail currents of trace driver output stages turn on in as little as 10ns. Should all outputs be configured for maximum swing and enabled simultaneously, the load current step on each of VCC_OUT1, VCC_OUT2 would be as high as 2.06A (for AC-coupled applications) in ~14ns, 11ns respectively (including the propagation delay spread noted above). That large dI/dt can be reduced by appropriate programming of updates. The VCC_OUT1 and VCC_OUT2 supply current drawn by each trace driver drops in as little as 1ns upon the assertion of device reset. The greater spread of signal arrival times in the top bank leads to a significantly smaller magnitude of dI/dt on the VCC_OUT1 supply than on the VCC_OUT2 supply. GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 41 of 46 Proprietary & Confidential 5.2.3 VCC_IN1, VCC_IN2 Supplies The controls for the equalizers are serialized, and hence power switching of the equalizers in mission mode is staggered in time. Assertion of reset will however lead to more nearly synchronous shedding of load. The typical current drawn from the VCC_IN1 and VCC_IN2 supplies is 0.85A each, and this can be shed in 1ns, including the reset signal propagation delay. Table 5-1: Summary Supply Maximum Current (A) Maximum Positive dI/dt Maximum Negative dI/dt (reset/simultaneous power-down) VCC_25_A 9.5 0.41GA/s -1.1GA/s VCC_OUT1 2.06 0.22GA/s -0.8GA/s VCC_OUT2 2.06 0.28GA/s -1.8GA/s VCC_IN1 0.85(typ) <0.1GA/s -0.9GA/s VCC_IN2 0.85(typ) <0.1GA/s -0.9GA/s GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 42 of 46 Proprietary & Confidential 6. Package and Ordering Information 6.1 Package Dimensions 50mm x 50mm FCBGA (1mm pitch) Top View Bottom View 0.20 (4X) A 50.00 A1 Ball Pad Corner 38.00 A1 Ball Pad Corner A 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 A C 1.00 1.350.25 38.00 50.00 (4.00) 4X (6.00) A B D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AT AU AV AW AY BA BB BC BD BE BF BG BH BJ B 4X (6.00) (4.00) 1.00 Side View 36.00 3.690.12 0.500.05 C 0.20 C +0.06 0.60 -0.14 0.25 M C A B 0.10 M C Section A-A Figure 6-1: Package Dimensions GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 43 of 46 Proprietary & Confidential 6.2 Package Thermal Data and Information Table 6-1: Package Thermal Data and Information Parameter Value Package Type 50mm x 50mm HFC BGA Moisture Sensitivity Level 3 Junction to Case Thermal Resistance, j-c 0.31C/W Junction to Air Thermal Resistance, j-a (at zero airflow) N/A. This device requires a heat sink. See Semtech's Crosspoint Design Guide. Junction to Board Thermal Resistance, j-b 2.1C/W Pb-free and RoHS Compliant Yes 6.3 Marking Diagram Pin 1 Indicator GX3146 ZZZZZZE3 XXXXXX-YYWW Instructions: GX3146 ZZZZZZ E3 XXXXXX YYWW Package Mark Marking batch work order information Pb-free & Green indicator Assembly batch work order information Date Code Figure 6-2: Marking Diagram GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 44 of 46 Proprietary & Confidential 6.4 Solder Reflow Profile The GX3146 is available in a Pb-free package. It is recommended that the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 6-3. Device Surface Temperature (C) Peak 245C 250 230C 1.0 - 2.0C/s 200 180C 150 Pre Heating Zone Soldering Zone 150C 60 - 120s 100 10 - 15s 1.5 - 2.0C/s 50 1.0 - 2.0C/s Heating Time Figure 6-3: Maximum Pb-free Solder Reflow Profile 6.5 Ordering Information Table 6-2: Ordering Information Part Number Package Temperature Range GX3146-CBE3 50x50mm HFC-BGA 0C to 85C Appendix - Relevant Documentation Table 6-3: Relevant Documentation Document Description Document Identification EB-GX3290 Schematics, PCB Layout and Bill of Materials GENDOC-056057 GX3290 Host Control Software User Manual GENDOC-055970 Using the Monitoring Features of the GX3290 Application Note GENDOC-058329 GX3290 (and family) Crosspoint Ball Guide GENDOC-056697 Crosspoint Design Guide GENDOC-056004 Crosspoint (GX3290 and family) Reference Manual (for CSRs) GENDOC-056832 GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 45 of 46 Proprietary & Confidential DOCUMENT IDENTIFICATION CAUTION FINAL DATA SHEET ELECTROSTATIC SENSITIVE DEVICES Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right to make changes to the product or this document at any time without notice. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION (c) Semtech 2012 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Contact Information Semtech Corporation Gennum Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com GX3146 146 x 146 3.5Gb/s Crosspoint Final Data Sheet Rev. 2 GENDOC-056075 March 2013 www.semtech.com 46 of 46 46 Proprietary & Confidential