General Description
The MAX19586 is a 3.3V, high-speed, high-perfor-
mance analog-to-digital converter (ADC) featuring a
fully differential wideband track-and-hold (T/H) and a
16-bit converter core. The MAX19586 is optimized for
multichannel, multimode receivers, which require the
ADC to meet very stringent dynamic performance
requirements. With a -82dBFS noise floor, the
MAX19586 allows for the design of receivers with supe-
rior sensitivity requirements.
At 80Msps, the MAX19586 achieves a 79.2dB signal-to-
noise ratio (SNR) and an 84.3dBc/100dBc single-tone
spurious-free dynamic range (SFDR) performance
(SFDR1/SFDR2) at fIN = 70MHz. The MAX19586 is not
only optimized for excellent dynamic performance in
the 2nd Nyquist region, but also for high-IF input fre-
quencies. For instance, at 130MHz, the MAX19586
achieves an 82.5dBc SFDR and its SNR performance
stays flat (within 2.5dB) throughout the 4th Nyquist
region. This level of performance makes the part ideal
for high-performance digital receivers.
The MAX19586 operates from a 3.3V analog supply
voltage and a 1.8V digital voltage, features a 2.56VP-P
full-scale input range, and allows for a guaranteed sam-
pling speed of up to 80Msps. The input track-and-hold
stage operates with a 600MHz full-scale, full-power
bandwidth.
The MAX19586 features parallel, low-voltage CMOS-
compatible outputs in two’s-complement output format.
The MAX19586 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extend-
ed industrial (-40°C to +85°C) temperature range.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
High-Performance Instrumentation
Antenna Array Processing
Features
♦80Msps Minimum Sampling Rate
♦-82dBFS Noise Floor
♦Excellent Dynamic Performance
80dB/79.2dB SNR at fIN = 10MHz/70MHz
and -2dBFS
96dBc/102dBc Single-Tone SFDR1/
SFDR2 at fIN = 10MHz
84.3dBc/100dBc Single-Tone SFDR1/
SFDR2 at fIN = 70MHz
♦Less than 0.1ps Sampling Jitter
♦1.1W Power Dissipation
♦2.56VP-P Fully Differential Analog Input Voltage
Range
♦CMOS-Compatible Two’s-Complement Data
Output
♦Separate Data Valid Clock and Over-Range
Outputs
♦Flexible Input Clock Buffer
♦3.3V Analog Power Supply; 1.8V Digital Output
Supply
♦Small 8mm x 8mm x 0.8mm 56-Pin Thin QFN
Package
♦EV Kit Available for MAX19586
(Order MAX19586EVKIT)
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
________________________________________________________________ Maxim Integrated Products 1
TOP VIEW
MAX19586
THIN QFN
8mm x 8mm
15
17
16
18
19
20
21
22
23
24
25
26
27
28
N.C.
N.C.
AVDD
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
REFOUT
REFIN
AGND
AVDD
AVDD
N.C.
DOR
DGND
DVDD
DAV
D15
D14
D13
D12
D11
D10
D9
48
47
46
45
44
43
54
53
56
55
52
51
50
49
1 2 3 4 5 6 7 8 9 1011121314
42 41 40 39 38 37 36 35 34 33 32 31 30 29
AGND
AGND
AGND
INN
INP
AGND
AGND
AGND
AGND
CLKN
CLKP
AGND
AVDD
AVDD
DGND
DGND
DVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
DVDD
DVDD
Pin Configuration
Ordering Information
19-3758; Rev 0; 8/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
+Denotes lead-free package.
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX19586ETN
-40°C to +85°C56 Thin QFN-EP
T5688-2
MAX19586ETN+
-40°C to +85°C56 Thin QFN-EP
T5688-2
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = 3.3V, DVDD = 1.8V, AGND = DGND = 0, INP and INN driven differentially, internal reference CLKP and CLKN driven differentially,
CL= 5pF at digital outputs, fCLK = 80MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C, unless otherwise
noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND ..................................................... -0.3V to +3.6V
DVDD to DGND..................................................... -0.3V to +2.4V
AGND to DGND.................................................... -0.3V to +0.3V
INP, INN, CLKP, CLKN, REFP, REFN,
REFIN, REFOUT to AGND....................-0.3V to (AVDD + 0.3V)
D0–D15, DAV, DOR, DAV to GND...........-0.3V to (DVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
56-Pin Thin QFN
(derate 47.6mW/°C above +70°C).........................3809.5mW
Operating Temperature Range ..........................-40°C to +85°C
Thermal Resistance θJA ..................................................21°C/W
Thermal Resistance θJC .................................................0.6°C/W
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution N 16 Bits
Offset Error VOS 0 10 20 mV
Gain Error GE
-3.5 +3.5
%FS
ANALOG INPUTS (INP, INN)
Input Voltage Range VDIFF Fully differential input, VIN = VINP - VINN
2.56
VP-P
Common-Mode Voltage VCM Internally self-biased 2.2 V
Differential Input Resistance RIN 10
±20%
kΩ
Differential Input Capacitance CIN 7pF
Full-Power Analog Bandwidth
BW-3dB
-3dB rolloff for FS Input
600
MHz
REFERENCE INPUT/OUTPUT (REFIN, REFOUT)
Reference Input Voltage Range REFIN 1.28
±10%
V
Reference Output Voltage
REFOUT 1.28
V
DYNAMIC SPECIFICATIONS (fCLK = 80Msps)
Thermal Plus Quantization Noise
Floor NF AIN < -35dBFS -82
dBFS
fIN = 10MHz, AIN = -2dBFS 80
fIN = 70MHz, AIN = -2dBFS 77.5
79.2
fIN = 100MHz, AIN = -2dBFS
78.5
fIN = 130MHz, AIN = -2dBFS
77.9
Signal-to-Noise Ratio
(First 4 Harmonics Excluded)
(Notes 2, 3)
SNR
fIN = 168MHz, AIN = -2dBFS
77.2
dB
fIN = 10MHz, AIN = -2dBFS
79.6
fIN = 70MHz, AIN = -2dBFS 75
77.6
fIN = 100MHz, AIN = -2dBFS
77.4
fIN = 130MHz, AIN = -2dBFS
76.4
Signal-to-Noise Plus Distortion
(Notes 2, 3) SINAD
fIN = 168MHz, AIN = -2dBFS
72.7
dB
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 3.3V, DVDD = 1.8V, AGND = DGND = 0, INP and INN driven differentially, internal reference CLKP and CLKN driven differentially,
CL= 5pF at digital outputs, fCLK = 80MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
fIN = 10MHz, AIN = -2dBFS 96
fIN = 70MHz, AIN = -2dBFS 80
84.3
fIN = 100MHz, AIN = -2dBFS 84
fIN = 130MHz, AIN = -2dBFS
82.5
Spurious-Free Dynamic Range
(Worst Harmonic, 2nd and 3rd) SFDR1
fIN = 168MHz, AIN = -2dBFS 78
dBc
fIN = 10MHz, AIN = -2dBFS
102
fIN = 70MHz, AIN = -2dBFS 90
100
fIN = 100MHz, AIN = -2dBFS 92
fIN = 130MHz, AIN = -2dBFS 94
Spurious-Free Dynamic Range
(Worst Harmonic, 4th and Higher)
(Note 3)
SFDR2
fIN = 168MHz, AIN = -2dBFS 90
dBc
fIN = 10MHz, AIN = -2dBFS
-100
fIN = 70MHz, AIN = -2dBFS -95 -84
fIN = 100MHz, AIN = -2dBFS -94
fIN = 130MHz, AIN = -2dBFS
-88.8
Second-Order Harmonic
Distortion HD2
fIN = 168MHz, AIN = -2dBFS -78
dBc
fIN = 10MHz, AIN = -2dBFS -96
fIN = 70MHz, AIN = -2dBFS
-84.3
-80
fIN = 100MHz, AIN = -2dBFS -84
fIN = 130MHz, AIN = -2dBFS
-82.5
Third-Order Harmonic Distortion
HD3
fIN = 168MHz, AIN = -2dBFS -78
dBc
Two-Tone Intermodulation
Distortion TTIMD fIN1 = 65.1MHz, AIN = -8dBFS
fIN2 = 70.1MHz, AIN = -8dBFS
-85.2
dBc
Two-Tone SFDR
TTSFDR
fIN1 = 65.1MHz, fIN2 = 70.1MHz
-100dBFS < AIN < -10dBFS 99
dBFS
CONVERSION RATE
Maximum Conversion Rate
fCLKMAX
80 MHz
Minimum Conversion Rate
fCLKMIN
20 MHz
Aperture Jitter tJ
0.094
psRMS
CLOCK INPUTS (CLKP, CLKN)
Differential Input Swing
VDIFFCLK
Fully differential inputs 1.0 to
5.0 VP-P
Common-Mode Voltage
VCMCLK
Self-biased 1.6 V
Differential Input Resistance RINCLK 10 kΩ
Differential Input Capacitance CINCLK 3pF
CMOS-COMPATIBLE DIGITAL OUTPUTS (D0–D15, DOR, DAV)
Digital Output High Voltage VOH ISOURCE = 200µA DVDD -
0.2 V
Digital Output Low Voltage VOL ISINK = 200µA 0.2 V
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 3.3V, DVDD = 1.8V, AGND = DGND = 0, INP and INN driven differentially, internal reference CLKP and CLKN driven differentially,
CL= 5pF at digital outputs, fCLK = 80MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING SPECIFICATION (Figures 4, 5), CL = 5pF (D0–D15, DOR); CL = 15pF (DAV)
CLKP - CLKN High tCLKP (Note 2) 5 ns
CLKP - CLKN Low tCLKN (Note 2) 5 ns
Effective Aperture Delay tAD
-300
ps
Output Data Delay tDAT 3.3 ns
Data Valid Delay tDAV (Note 2) 2.8 3.8 5.0 ns
Pipeline Latency tP7
Clock
Cycles
CLKP Rising Edge to DATA Not
Valid tDNV (Note 2) 1.2 ns
CLKP Rising Edge to DATA
Guaranteed Valid tDGV (Note 2) 6.5 ns
DATA Setup Time Before Rising
DAV tSClock duty cycle = 50% (Note 2) 3 ns
DATA Hold Time After Rising
DAV tHClock duty cycle = 50% (Note 2) 3 ns
POWER SUPPLIES
Analog Power-Supply Voltage AVDD
3.13
3.3
3.46
V
Digital Output Power-Supply
Voltage DVDD 1.7 1.8 1.9 V
Analog Power-Supply Current IAVDD
320 382
mA
Digital Output Power-Supply
Current IDVDD 28 35 mA
Power Dissipation PDISS
1105 1325
mW
Note 1: ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.
Note 2: Parameter guaranteed by design and characterization.
Note 3: AC parameter measured in a 32,768-point FFT record, where the first 2 bins of the FFT and 2 bins on either side of the carrier
are excluded.
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
_______________________________________________________________________________________ 5
-120
-100
-80
-60
-40
-20
0
0105 152025303540
FFT PLOT
(32,768-POINT RECORD)
MAX19586 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80.00012288MHz
fIN = 10.10011317MHz
AIN = -2.02dBFS
SNR = 80dB
SINAD = 79.8dB
SFDR1 = 96.2dBc
SFDR2 = 101dBc
HD2 = -99.6dBc
HD3 = -96.2dBc
23
-120
-100
-80
-60
-40
-20
0
0105 152025303540
FFT PLOT
(32,768-POINT RECORD)
MAX19586 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
2
3
fCLK = 80.00012288MHz
fIN = 70.16368199MHz
AIN = -2.06dBFS
SNR = 79.3dB
SINAD = 77.7dB
SFDR1 = 83.3dBc
SFDR2 = 98.2dBc
HD2 = -93.5dBc
HD3 = -83.3dBc
-140
-100
-120
-80
-60
-40
-20
0
0105 152025303540
FFT PLOT
(261,244-POINT DATA RECORD)
MAX19586 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
32
fCLK = 80.00012288MHz
fIN = 130.00050486MHz
AIN = -1.82dBFS
SNR = 77.7dB
SINAD = 76.4dB
SFDR1 = 83.1dBc
SFDR2 = 91.2dBc
HD2 = -89.4dBc
HD3 = -83.1dBc
70
72
76
80
74
78
82
0 40608020 100 120 140 160 180
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fCLK = 80MHz, AIN = -2dBFS)
MAX19586toc04
fIN (MHz)
SNR/SINAD (dB)
SNR
SINAD
70
75
85
100
80
90
105
95
110
0 40608020 100 120 140 160 180
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(fCLK = 80MHz, AIN = -2dBFS)
MAX19586toc05
fIN (MHz)
SFDR1/SFDR2 (dBc)
SFDR2
SFDR1
-110
-105
-95
-80
-100
-90
-75
-85
-70
0 40608020 100 120 140 160 180
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fCLK = 80MHz, AIN = -2dBFS)
MAX19586toc06
fIN (MHz)
HD2/HD3 (dBc)
HD3
HD2
40
50
70
60
45
55
65
75
80
85
-40 -30 -25 -20-35 -15 -10 -5 0
SNR vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 10.10011MHz)
MAX19586toc07
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB, dBFS)
SNR (dBFS)
SNR (dB)
60
80
110
90
70
100
120
-40 -30 -25 -20-35 -15 -10 -5 0
SFDR1 vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 10.10011MHz)
MAX19586toc08
ANALOG INPUT AMPLITUDE (dBFS)
SFDR1 (dBc, dBFS)
SFDR1 (dBFS)
SFDR1 (dBc)
SFDR = 90dB
REFERENCE LINE
60
80
110
90
70
100
120
-40 -30 -25 -20-35 -15 -10 -5 0
SFDR2 vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 10.10011MHz)
MAX19586toc09
ANALOG INPUT AMPLITUDE (dBFS)
SFDR2 (dBc, dBFS)
SFDR2 (dBFS)
SFDR2 (dBc)
SFDR = 90dB
REFERENCE LINE
Typical Operating Characteristics
(AVDD = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL= 5pF at
digital outputs, fCLK = 80MHz, TA= +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records and under coherent
sampling conditions.)
Typical Operating Characteristics (continued)
(AVDD = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL= 5pF at
digital outputs, fCLK = 80MHz, TA= +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records and under coherent
sampling conditions.)
72
76
80
74
78
82
20 40 50 6030 70 80 90 100 110
SNR/SINAD vs. SAMPLING FREQUENCY
(fIN = 70.163683MHz, AIN = -2dBFS)
MAX19586toc16
fCLK (MHz)
SNR/SINAD (dB)
SNR
SINAD
75
85
95
80
90
105
20 40 50 6030 70 80 90 100 110
SFDR1/SFDR2 vs. SAMPLING FREQUENCY
(fIN = 70.163683MHz, AIN = -2dBFS)
MAX19586toc17
fCLK (MHz)
SFDR/SFDR2 (dBc)
100 SFDR2
SFDR1
-110
-90
-100
-105
-95
-70
20 40 50 6030 70 80 90 100 110
HD2/HD3 vs. SAMPLING FREQUENCY
(fIN = 70.163683MHz, AIN = -2dBFS)
MAX19586toc18
fCLK (MHz)
HD2/HD3 (dBc)
-80
-85
-75
HD3
HD2
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
6 _______________________________________________________________________________________
73
77
81
75
79
83
20 30 40 50 60 70 80 90 100 110
SNR/SINAD vs. SAMPLING FREQUENCY
(fIN = 9.9757395MHz, AIN = -2dBFS)
MAX19586toc13
fCLK (MHz)
SNR/SINAD (dB)
SINAD
SNR
75
90
110
80
100
95
115
85
105
120
SFDR/SFDR2 vs. SAMPLING FREQUENCY
(fIN = 10.10011MHz, AIN = -2dBFS)
MAX19586toc14
fCLK (MHz)
SFDR1/SFDR2 (dBc)
20 30 40 50 60 70 80 90 100 110
SFDR1
SFDR2
-120
-90
-110
-80
-100
-70
HD2/HD3 vs. SAMPLING FREQUENCY
(fIN = 10.10011MHz, AIN = -2dBFS)
MAX19586toc15
fCLK (MHz)
HD2/HD3 (dBc)
20 30 40 50 60 70 80 90 100 110
HD2
HD3
35
45
85
65
55
40
50
60
70
75
80
90
-40 -30 -25 -20-35 -15 -10 -5 0
SNR vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 70.163683MHz)
MAX19586toc10
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB, dBFS)
SNR (dBFS)
SNR (dB)
40
60
100
80
50
70
90
110
-40 -30 -25 -20-35 -15 -10 -5 0
SFDR1 vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 70.163683MHz)
MAX19586toc11
ANALOG INPUT AMPLITUDE (dBFS)
SFDR1 (dBc, dBFS)
SFDR1 (dBFS)
SFDR1 (dBc)
SFDR = 90dB
REFERENCE LINE
40
60
100
110
80
50
70
90
120
-40 -30 -25 -20-35 -15 -10 -5 0
SFDR2 vs. ANALOG INPUT AMPLITUDE
(fCLK = 80MHz, fIN = 70.163683MHz)
MAX19586toc12
ANALOG INPUT AMPLITUDE (dBFS)
SFDR2 (dBc, dBFS)
SFDR2 (dBFS)
SFDR2 (dBc)
SFDR = 90dB
REFERENCE LINE
Typical Operating Characteristics (continued)
(AVDD = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL= 5pF at
digital outputs, fCLK = 80MHz, TA= +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records and under coherent
sampling conditions.)
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
_______________________________________________________________________________________ 7
76
80
78
77
79
82
-40 -15 10 35 60 85
SNR/SINAD vs. TEMPERATURE
(fCLK = 80MHz, fIN = 10.10011MHz,
AIN = -2dBFS)
MAX19586toc19
TEMPERATURE (°C)
SNR/SINAD (dB)
81
SNR
SINAD
80
100
90
85
95
120
-40 -15 10 35 60 85
SFDR1/SFDR2 vs. TEMPERATURE
(fCLK = 80MHz, fIN = 10.10011MHz,
AIN = -2dBFS)
MAX19586toc20
TEMPERATURE (°C)
SFDR1/SFDR2 (dBc)
110
105
115
SFDR2
SFDR1
-115
-95
-105
-110
-100
-80
-40 -15 10 35 60 85
HD2/HD3 vs. TEMPERATURE
(fCLK = 80MHz, fIN = 10.10011MHz,
AIN = -2dBFS)
MAX19586toc21
TEMPERATURE (°C)
HD2/HD3 (dBc)
-85
-90
HD2
HD3
75
79
77
76
78
81
-40 -15 10 35 60 85
SNR/SINAD vs. TEMPERATURE
(fCLK = 80MHz, fIN = 70.163683MHz,
AIN = -2dBFS)
MAX19586toc22
TEMPERATURE (°C)
SNR/SINAD (dB)
80
SNR
SINAD
60
100
80
70
90
120
-40 -15 10 35 60 85
SFDR1/SFDR2 vs. TEMPERATURE
(fCLK = 80MHz, fIN = 70.163683MHz,
AIN = -2dBFS)
MAX19586toc23
TEMPERATURE (°C)
SFDR1/SFDR2 (dBc)
110
SFDR2
SFDR1
-115
-100
-80
-110
-90
-95
-75
-105
-85
-70
-40 -15 10 35 60 85
HD2/HD3 vs. TEMPERATURE
(fCLK = 80MHz, fIN = 70.163683MHz,
AIN = -2dBFS)
MAX19586toc24
TEMPERATURE (°C)
HD2/HD3 (dBc)
HD3
HD2
1000
1080
1160
1040
1120
1200
-40 -15 10 35 60 85
POWER DISSIPATION
vs. TEMPERTURE
MAX19586toc25
TEMPERATURE (°C)
POWER DISSIPATION (mW)
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
200
400
1200
800
600
300
500
700
900
1000
1100
1300
3.15 3.25 3.30 3.353.20 3.40 3.45
POWER DISSIPATION
vs. ANALOG SUPPLY VOLTAGE
MAX19586toc27
ANALOG SUPPLY VOLTAGE (V)
IAVCC, PDISS (mA, mW)
PDISS
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
IAVCC
1.260
1.275
1.295
1.265
1.285
1.270
1.290
1.280
1.300
-40 -15 10 35 60 85
REFERENCE VOLTAGE
vs. TEMPERTURE
MAX19586toc26
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
Typical Operating Characteristics (continued)
(AVDD = 3.3V, DVDD = 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, CL= 5pF at
digital outputs, fCLK = 80MHz, TA= +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records and under coherent
sampling conditions.)
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
8 _______________________________________________________________________________________
1.270
1.275
1.285
1.280
1.273
1.278
1.283
1.288
1.290
3.15 3.25 3.30 3.353.20 3.40 3.45
REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX19586toc28
ANALOG SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
73
75
77
74
76
81
3.15 3.25 3.30 3.353.20 3.40 3.45
SNR/SINAD vs.
ANALOG SUPPLY VOLTAGE
MAX19586toc29
ANALOG SUPPLY VOLTAGE (V)
SNR/SINAD (dB)
78
79
80 SNR
SINAD
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
70
80
90
75
85
110
3.15 3.25 3.30 3.353.20 3.40 3.45
SFDR1/SFDR2 vs.
ANALOG SUPPLY VOLTAGE
MAX19586toc30
ANALOG SUPPLY VOLTAGE (V)
SFDR1/SFDR2 (dBc)
95
100
105 SFDR1
SFDR2
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
-110
-100
-90
-105
-95
-70
3.15 3.25 3.30 3.353.20 3.40 3.45
HD2/HD3 vs.
ANALOG SUPPLY VOLTAGE
MAX19586to31
ANALOG SUPPLY VOLTAGE (V)
HD2/HD3 (dBc)
-85
-80
-75
HD2
HD3
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
-120
-100
-80
-60
-40
-20
0
0105 152025303540
TWO-TONE SFDR PLOT
(32,768-POINT DATA RECORD)
MAX19586 toc32
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80MHz
fIN1 = 10.1001MHz
fIN2 = 14.871MHz
AIN1 = -8.04dBFS
AIN2 = -8.00dBFS
TTSFDR = 99.6dBFS
fIN1 fIN2
fIN1 + fIN2
-120
-100
-80
-60
-40
-20
0
0105 152025303540
TWO-TONE SFDR PLOT
(32,768-POINT DATA RECORD)
MAX19586 toc33
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80MHz
fIN1 = 65.1002MHz
fIN2 = 70.1MHz
AIN1 = -8.03dBFS
AIN2 = -8.00dBFS
TTSFDR = 93.2dBFS
fIN2
fIN1
2fIN1 - fIN2
0
20
70
110
50
90
10
60
100
40
30
80
120
-100 -80 -70 -60-90 -50 -40 -30 -20 -10 0
TWO-TONE SFDR vs. ANALOG INPUT
AMPLITUDE (fCLK = 80MHz,
fIN1 = 10.1MHz, fIN2 = 14.87MHz)
MAX19586toc34
ANALOG INPUT AMPLITUDE (dBFS)
TTSFDR (dBc, dBFS)
SFDR (dBFS)
SFDR (dBc)
SFDR = 90dB
REFERENCE LINE
0
20
70
110
50
90
10
60
100
40
30
80
120
-100 -80 -70 -60-90 -50 -40 -30 -20 -10 0
TWO-TONE SFDR vs. ANALOG INPUT
AMPLITUDE (fCLK = 80MHz,
fIN1 = 65.1MHz, fIN2 = 70.1MHz)
MAX19586toc35
ANALOG INPUT AMPLITUDE (dBFS)
TTSFDR (dBc, dBFS)
SFDR (dBFS)
SFDR (dBc)
SFDR = 90dB
REFERENCE LINE
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1, 2, 17, 18,
19, 23, 24,
25, 55, 56
AVDD Analog Supply Voltage. Provide local bypassing to ground with 0.01µF and 0.1µF capacitors.
3, 6–9, 12,
13, 14, 20,
21, 22, 28
AGND Converter Ground. Analog, digital, and output-driver grounds are internally connected to the same
potential. Connect the converter’s exposed paddle (EP) to GND.
4 CLKP Differential Clock, Positive Input Terminal
5 CLKN Differential Clock, Negative Input Terminal
10 INP Differential Analog Input, Positive Terminal
11 INN Differential Analog Input, Negative/Complementary Terminal
15, 16, 54
N.C. No Connection. Do not connect to this pin.
26 REFOUT Internal Bandgap Reference Output
27 REFIN Reference Voltage Input
29, 41, 42,
51 DVDD Digital Supply Voltage. Provide local bypassing to ground with 0.01µF and 0.1µF capacitors.
30, 31, 52
DGND Converter Ground. Digital output-driver ground.
32 D0 Digital CMOS Output Bit 0 (LSB)
33 D1 Digital CMOS Output Bit 1
34 D2 Digital CMOS Output Bit 2
35 D3 Digital CMOS Output Bit 3
36 D4 Digital CMOS Output Bit 4
37 D5 Digital CMOS Output Bit 5
38 D6 Digital CMOS Output Bit 6
39 D7 Digital CMOS Output Bit 7
40 D8 Digital CMOS Output Bit 8
43 D9 Digital CMOS Output Bit 9
44 D10 Digital CMOS Output Bit 10
45 D11 Digital CMOS Output Bit 11
46 D12 Digital CMOS Output Bit 12
47 D13 Digital CMOS Output Bit 13
48 D14 Digital CMOS Output Bit 14
49 D15 Digital CMOS Output Bit 15 (MSB)
50 DAV
Data Valid Output. This output can be used as a clock control line to drive an external buffer or data-
acquisition system. The typical delay time between the falling edge of the converter clock and the
rising edge of DAV is 3.8ns.
53 DOR
Data Over-Range Bit. This control line flags an over-/under-range condition in the ADC. If DOR
transitions high, an over-/under-range condition was detected. If DOR remains low, the ADC operates
within the allowable full-scale range.
—EP Exposed Paddle. Must be connected to AGND.
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
10 ______________________________________________________________________________________
Detailed Description
Figure 1 provides an overview of the MAX19586 archi-
tecture. The MAX19586 employs an input track-and-
hold (T/H) amplifier, which has been optimized for low
thermal noise and low distortion. The high-impedance
differential inputs to the T/H amplifier (INP and INN) are
self-biased at 2.2V, and support a full-scale 2.56VP-P
differential input voltage. The output of the T/H amplifier
is applied to a multistage pipelined ADC core, which is
designed to achieve a very low thermal noise floor and
low distortion.
A clock buffer receives a differential input clock wave-
form and generates a low-jitter clock signal for the input
T/H. The signal at the analog inputs is sampled at the
rising edge of the differential clock waveform. The dif-
ferential clock inputs (CLKP and CLKN) are high-
impedance inputs, are self-biased at 1.6V, and support
differential clock waveforms from 1VP-P to 5VP-P.
The outputs from the multistage pipelined ADC core
are delivered to error correction and formatting logic,
which deliver the 16-bit output code in two’s-comple-
ment format to digital output drivers. The output drivers
provide 1.8V CMOS-compatible outputs.
Analog Inputs (INP, INN)
The signal inputs to the MAX19586 (INP and INN) are
balanced differential inputs. This differential configura-
tion provides immunity to common-mode noise coupling
and rejection of even-order harmonic terms. The differ-
ential signal inputs to the MAX19586 should be AC-cou-
pled and carefully balanced to achieve the best dynam-
ic performance (see Differential, AC-Coupled Analog
Inputs in the Applications Information section for more
details). AC-coupling of the input signal is required
because the MAX19586 inputs are self-biasing as
shown in Figure 2. Although the track-and-hold inputs
are high impedance, the actual differential input imped-
ance is nominally 10kΩbecause of the two 5kΩresis-
tors connected to the common-mode bias circuitry.
Avoid injecting any DC leakage currents into these ana-
log inputs. Exceeding a DC leakage current of 10µA
shifts the self-biased common-mode level, adversely
affecting the converter’s performance.
On-Chip Reference Circuit
The MAX19586 incorporates an on-chip 1.28V, low-drift
bandgap reference. This reference potential establish-
es the full-scale range for the converter, which is nomi-
nally 2.56VP-P differential (Figure 3). The internal
reference voltage can be monitored by REFOUT.
To use the internal reference voltage the reference
input (REFIN) must be connected to REFOUT
through a 10kΩresistor. Bypass both pins with sepa-
rate 1µF capacitors to AGND.
The MAX19586 also allows an external reference
source to be connected to REFIN, enabling the user to
overdrive the internal bandgap reference. REFIN
accepts a 1.28V ±10% input voltage range.
MAX19586
CLOCK
BUFFER
CMOS
OUTPUT
DRIVERS
CMOS
DRIVER
AVDD
AGND
DAV
DVDD
CLKP
CLKN
INP
INN
REFOUT REFIN
REFERENCE
PIPELINE
ADC
DOR
D0–D15
DGND
T/H
Figure 1. Block Diagram
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
______________________________________________________________________________________ 11
Clock Inputs (CLKP, CLKN)
The differential clock buffer for the MAX19586 has been
designed to accept an AC-coupled clock waveform.
Like the signal inputs, the clock inputs are self-biasing.
In this case, the self-biased potential is 1.6V and each
input is connected to the reference potential with a 5kΩ
resistor. Consequently, the differential input resistance
associated with the clock inputs is 10kΩ. While differ-
ential clock signals as low as 0.5VP-P can be used to
drive the clock inputs, best dynamic performance is
achieved with 1VP-P to 5VP-P clock input voltage levels.
Jitter on the clock signal translates directly to jitter
(noise) on the sampled signal. Therefore, the clock
source must be a very low-jitter (low-phase-noise)
source. Additionally, extremely low phase-noise oscilla-
tors and bandpass filters should be used to obtain the
true AC performance of this converter. See the
Differential, AC-Coupled Clock Inputs and Testing the
MAX19586 topics in the Applications Information sec-
tion for additional details on the subject of driving the
clock inputs.
System Timing Requirements
Figure 4 depicts the general timing relationships for the
signal input, clock input, data output, and DAV output.
Figure 5 shows the detailed timing specifications and
signal relationships, as defined in the Electrical
Characteristics table.
The MAX19586 samples the input signal on the rising
edge of the input clock. Output data is valid on the ris-
ing edge of the DAV signal, with a 7 clock-cycle data
latency. Note that the clock duty cycle should typically
be 50% ±10% for proper operation.
Digital Outputs (D0–D15, DAV, DOR)
Although designed for low-voltage 1.8V logic systems,
the logic-high level of the low-voltage CMOS-compati-
ble digital outputs (D0–D15, DAV, and DOR) offer some
flexibility, as it allows the user to select the digital volt-
age within the 1.7V to 1.9V range.
For best performance, the capacitive loading on the
digital outputs of the MAX19586 should be kept as low
as possible (< 10pF). Due to the current-limited data-
output driver of the MAX19586, large capacitive loads
increase the rise and fall time of the data and can make
it more difficult to register the data into the next IC. The
loading capacitance can be kept low by keeping the
output traces short and by driving a single CMOS
buffer or latch input (as opposed to multiple CMOS
inputs). The output data is in two’s-complement format,
as illustrated in Table 1.
Data is valid at the rising edge of DAV (Figures 4, 5).
DAV may be used as a clock signal to latch the output
data. Note that the DAV output driver is not current lim-
ited, hence it allows for higher capacitive loading.
T/H AMPLIFIER
T/H AMPLIFIER
TO FIRST QUANTIZER
STAGE
TO FIRST QUANTIZER
STAGE
INP
INN
5kΩ
5kΩ
OTA
Figure 2. Simplified Analog Input Architecture
-640mV
+640mV
INP
INN
2.56VP-P
DIFFERENTIAL FSR
COMMON-MODE
VOLTAGE (2.2V)
Figure 3. Full-Scale Voltage Range
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
12 ______________________________________________________________________________________
Figure 4. General System and Output Timing Diagram
7 CLOCK-CYCLE LATENCY
N
N + 1
N - 7 N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N
N + 2
N + 3
N + 4
N + 6
N + 7
N + 5
ANALOG INPUT
CLOCK INPUT
D0–D15
DAV
Figure 5. Detailed Timing Information for Clock Operation
CLKN
CLKP
D0–D15
DOR
DAV
tDAT
INP
INN
N - 4
tDAV tS
tH
tDNV tDGV
tA
tCLKP
tCLKN
N - 7
N N + 1 N + 2 N + 3
N - 6 N - 5
ENCODE AT CLKP - CLKN > 0 (RISING EDGE)
tCLKP CLKP - CLKN > 0
tCLKN CLKP - CLKN < 0
tAD EFFECTIVE APERTURE DELAY
tDAT DELAY FROM CLKP TO OUTPUT DATA TRANSITION
tDAV DELAY FROM CLKN TO DATA VALID CLOCK DAV
tDNV CLKP RISING EDGE TO DATA NOT VALID
tDGV CLKP RISING EDGE TO DATA GUARANTEED VALID
tSDATA SETUP TIME BEFORE RISING DAV
tHDATA HOLD TIME AFTER RISING DAV
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
______________________________________________________________________________________ 13
The converter’s DOR output signal is used to identify
over- and under-range conditions. If the input signal
exceeds the positive or negative full-scale range for the
MAX19586 then DOR will be asserted high. The timing
for DOR is identical to the timing for the data outputs,
and DOR therefore provides an over-range indication
on a sample-by-sample basis.
Applications Information
Differential, AC-Coupled Clock Inputs
The clock inputs to the MAX19586 are driven with an
AC-coupled differential signal, and best performance is
achieved under these conditions. However, it is often
the case that the available clock source is single-ended.
Figure 6 demonstrates one method for converting a sin-
gle-ended clock signal into a differential signal with a
transformer. In this example, the transformer turns ratio
from the primary to secondary side is 1:1.414. The
impedance ratio from primary to secondary is the
square of the turns ratio, or 1:2. So terminating the sec-
ondary side with a 100Ωdifferential resistance results in
a 50Ωload looking into the primary side of the trans-
former. The termination resistor in this example is com-
prised of the series combination of two 50Ωresistors
with their common node AC-coupled to ground.
Figure 6 illustrates the secondary side of the trans-
former to be coupled directly to the clock inputs. Since
the clock inputs are self-biasing, the center tap of the
transformer must be AC-coupled to ground or left float-
ing. If the center tap of the transformer’s secondary
side is DC-coupled to ground, it is necessary to add
blocking capacitors in series with the clock inputs.
Clock jitter is generally improved if the clock signal has
a high slew rate at the time of its zero-crossing.
Therefore, if a sinusoidal source is used to drive the
clock inputs the clock amplitude should be as large as
possible to maximize the zero-crossing slew rate. The
back-to-back Schottky diodes shown in Figure 6 are not
required as long as the input signal is held to a differen-
tial voltage potential of 3VP-P or less. If a larger ampli-
tude signal is provided (to maximize the zero-crossing
slew rate), then the diodes serve to limit the differential
signal swing at the clock inputs. Note that all AC speci-
fications for the MAX19586 are measured within this
configuration and with an input clock amplitude of
approximately 12dBm.
Any differential mode noise coupled to the clock inputs
translates to clock jitter and degrades the SNR perfor-
mance of the MAX19586. Any differential mode coupling
of the analog input signal into the clock inputs results in
harmonic distortion. Consequently, it is important that the
clock lines be well isolated from the analog signal input
and from the digital outputs. See the Signal Routing sec-
tion for more discussion on the subject of noise coupling.
Differential, AC-Coupled Analog Inputs
The analog inputs INP and INN are driven with a differ-
ential AC-coupled signal. It is important that these
inputs be accurately balanced. Any common-mode sig-
nal applied to these inputs degrades even-order distor-
tion terms. Therefore, any attempt at driving these
inputs in a single-ended fashion will result in significant
even-order distortion terms.
Figure 7 presents one method for converting a single-
ended signal to a balanced differential signal using a
transformer. The primary-to-secondary turns ratio in this
example is 1:1.414. The impedance ratio is the square
of the turns ratio, so in this example the impedance ratio
is 1:2. To achieve a 50Ωinput impedance at the primary
side of the transformer, the secondary side is terminated
with a 100Ωdifferential load. This load, in shunt with the
differential input resistance of the MAX19586, results in
a 100Ωdifferential load on the secondary side. It is rea-
Table 1. MAX19586 Digital Output Coding
INP
ANALOG VOLTAGE LEVEL
INN
ANALOG VOLTAGE LEVEL
D15–D0
TWO’S-COMPLEMENT CODE
VCM + 0.64V VCM - 0.64V 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(positive full-scale)
VCM VCM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(midscale + δ)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(midscale - δ)
VCM - 0.64V VCM + 0.64V 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(negative full-scale)
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
14 ______________________________________________________________________________________
sonable to use a larger transformer turns ratio to achieve
a larger signal step-up, and this may be desirable to
relax the drive requirements for the circuitry driving the
MAX19586. However, the larger the turns ratio, the larg-
er the effect of the differential input impedance of the
MAX19586 on the primary-referred input impedance.
As stated previously, the signal inputs to the MAX19586
must be accurately balanced to achieve the best even-
order distortion performance.
Figure 6. Transformer-Coupled Clock Input Configuration
AGND
CLKP CLKN
DGND
D0–D15
AVDD DVDD
16
MAX19586
0.1µF
INP
INN
T2-1T-KK81
49.9Ω
49.9Ω
0.1µFBACK-TO-BACK DIODE
Figure 7. Transformer-Coupled Analog Input Configuration with Primary-Side Balun Transformer
AGND
CLKP CLKN DGND
D0–D15
AVDD DVDD
16
MAX19586
0.1µF
INP
INN
ADT2-1T T1-1T-KK81 49.9Ω
49.9Ω
POSITIVE
TERMINAL 0.1µF
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
______________________________________________________________________________________ 15
One note of caution in relation to transformers is impor-
tant. Any DC current passed through the primary or
secondary windings of a transformer may magnetically
bias the transformer core. When this happens the trans-
former is no longer accurately balanced and a degra-
dation in the distortion of the MAX19586 may be
observed. The core must be demagnetized to return to
balanced operation.
Testing the MAX19586
The MAX19586 has a very low thermal noise floor
(-82dBFS) and very low jitter (< 100fs). As a conse-
quence, test system limitations can easily obscure the
performance of the ADC. Figure 8a is a block diagram
of a conventional high-speed ADC test system. The
input signal and the clock source are generated by low-
phase-noise synthesizers (e.g., Agilent 8644B).
Bandpass filters in both the signal and the clock paths
then attenuate noise and harmonic components.
Figure 8b shows the resulting power spectrum, which
results from this setup for a 70MHz input tone and an
80Msps clock. Note the substantial lift in the noise floor
near the carrier. The bandwidth of this particular noise-
floor lift near the carrier corresponds to the bandwidth
of the filter in the input signal path.
Figure 8c illustrates the impact on the spectrum if the
input frequency is shifted away from the center fre-
quency of the input signal filter. Note that the funda-
mental tone has moved, but the noise-floor lift remains
in the same location. This is evidence of the validity of
the claim that the lift in the noise floor is due to the test
system and not the ADC. In this figure, the magnitude
of the lift in the noise floor increased relative to the pre-
vious figure because the signal is located on the skirt of
the filter and the signal amplitude had to be increased
to obtain a signal near full scale.
To truly reveal the performance of the MAX19586, the test
system performance must be improved substantially.
Figure 8d depicts such an improved test system. In this
system, the synthesizers provide reference inputs to two
dedicated low-noise phase-locked loops (PLLs), one cen-
tered at approximately 80MHz (for the clock path) and the
other centered at 70MHz (for the signal path). The oscilla-
tors in these PLLs are very low-noise oscillators, and the
Figure 8a. Standard High-Speed ADC Test Setup (Simplified
Block Diagram)
10dB
SIGNAL PATH
CLOCK PATH
BANDPASS
FILTER
BANDPASS
FILTER
AGILENT 8644B
AGILENT 8644B
3dB
PAD
BOTH SIGNAL GENERATORS
ARE PHASE-LOCKED
MAX19586
Figure 8b. 70MHz FFT with Standard High-Speed ADC Test
Setup
-120
-100
-80
-60
-40
-20
0
0105 152025303540
FFT PLOT
(32,768-POINT DATA RECORD)
ANALOG INPUT FREQUENCY (MHz)
POWER (dBFS)
23
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
Figure 8c. 68MHz FFT with Standard High-Speed ADC Test
Setup
-120
-100
-80
-60
-40
-20
0
0105 152025303540
FFT PLOT
(32,768-POINT DATA RECORD)
FREQUENCY (MHz)
POWER (dBFS)
2
3
fCLK = 80.00012288MHz
fIN = 68MHz
AIN = -2dBFS
CARRIER WAS INTENTIONALLY
LOWERED BY 2MHz TO SHOW
THE STATIONARY BEHAVIOR OF
THE NOISE
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
16 ______________________________________________________________________________________
PLLs act as extremely narrow bandwidth filters (on the
order of 20Hz) to attenuate the noise of the synthesizers.
The system provides a total system jitter on the order of
20fs. Note that while the low-noise oscillators could be
used by themselves without being locked to their respec-
tive signal sources, this would result in FFTs that are not
coherent and which would require windowing.
Figure 8e is an FFT plot of the spectrum obtained when
the improved test system is employed. The noise-floor
lift in the vicinity of the carrier is now almost completely
eliminated. The SNR associated with this FFT is about
79.1dB, whereas the SNR obtained using the standard
test system is on the order of 77.6dB.
Figure 8d. Improved Test System Employing Narrowband PLLs (Simplified Block Diagram)
REF
SIGNAL
PLL VCXO
10dB
VARIABLE
ATTENUATOR
SIGNAL PATH
CLOCK PATH
BANDPASS
FILTER
BANDPASS
FILTER
TUNE
LOW-NOISE PLL
AGILENT 8644B
REF
SIGNAL
PLL VCXO
10dB
TUNE
LOW-NOISE PLL
AGILENT 8644B
3dB
PAD
BOTH SIGNAL GENERATORS
ARE PHASE-LOCKED
MAX19586
Figure 8e. 70MHz FFT with Improved High-Speed ADC Test
Setup
-120
-100
-80
-60
-40
-20
0
0105 152025303540
FFT PLOT
(32,768-POINT DATA RECORD)
ANALOG INPUT FREQUENCY (MHz)
ANALOG POWER (dBFS)
2
3
fCLK = 80.00012288MHz
fIN = 70.163683MHz
AIN = -2dBFS
Figure 8f. SNR vs. System Jitter Performance Graph
110
60
10 100 1000
SNR vs. RMS
JITTER PERFORMANCE
65
RMS JITTER (fs)
SNR (dB)
80
95
70
85
100
75
90
105
INPUT FREQUENCY = 140MHz
INPUT FREQUENCY = 70MHz
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
______________________________________________________________________________________ 17
Figure 8f demonstrates the impact of test system jitter
on measured SNR. The figure plots SNR due to test
system jitter only, neglecting all other sources of noise,
for two different input frequencies. For example, note
that for a 70MHz input frequency a test system jitter
number of 100fs results in an SNR (due to the test sys-
tem alone) of about 87.1dB. In the case of the
MAX19586, which has a -82dBFS noise floor, this is not
an inconsequential amount of additional noise.
In conclusion, careful attention must be paid to both the
input signal source and the clock signal source, if the
true performance of the MAX19586 is to be properly
characterized. Dedicated PLLs with low-noise VCOs,
such as those used in Figure 8d, are capable of provid-
ing signals with the required low jitter performance.
Layer Assignments
The MAX19586 EV kit is a 6-layer board, and the
assignment of layers is discussed in this context. It is
recommended that the ground plane be on a layer
between the signal routing layer and the supply routing
layer(s). This prevents coupling from the supply lines
into the signal lines. The MAX19586 EV kit PC board
places the signal lines on the top (component) layer
and the ground plane on layer 2. Any region on the top
layer not devoted to signal routing is filled with the
ground plane with vias to layer 2. Layers 3 and 4 are
devoted to supply routing, layer 5 is another ground
plane, and layer 6 is used for the placement of addi-
tional components and for additional signal routing.
A four-layer implementation is also feasible using layer
1 for signal lines, layer 2 as a ground plane, layer 3 for
supply routing, and layer 4 for additional signal routing.
However, care must be taken to ensure that the clock
and signal lines are isolated from each other and from
the supply lines.
Signal Routing
To preserve good even-order distortion, the signal lines
(those traces feeding the INP and INN inputs) must be
carefully balanced. To accomplish this, the signal
traces should be made as symmetric as possible,
meaning that each of the two signal traces should be
the same length and should see the same parasitic
environment. As mentioned previously, the signal lines
must be isolated from the supply lines to prevent cou-
pling from the supplies to the inputs. This is accom-
plished by making the necessary layer assignments as
described in the previous section. Additionally, it is cru-
cial that the clock lines be isolated from the signal lines.
On the MAX19586 EV kit this is done by routing the
clock lines on the bottom layer (layer 6). The clock lines
then connect to the ADC through vias placed in close
proximity to the device. The clock lines are isolated
from the supply lines as well by virtue of the ground
plane on layer 5.
As with all high-speed designs, digital output traces
should be kept as short as possible to minimize capaci-
tive loading. The ground plane on layer 2 beneath
these traces should not be removed so that the digital
ground return currents have an uninterrupted path
back to the bypass capacitors.
Grounding
The practice of providing a split ground plane in an
attempt to confine digital ground-return currents has
often been recommended in ADC application literature.
However, for converters such as the MAX19586 it is
strongly recommended to employ a single, uninterrupt-
ed ground plane. The MAX19586 EV kit achieves excel-
lent dynamic performance with such a ground plane.
The exposed paddle of the MAX19586 should be sol-
dered directly to a ground pad on layer 1 with vias to
the ground plane on layer 2. This provides excellent
electrical and thermal connections to the PC board.
Supply Bypassing
The MAX19586 EV kit uses 220µF capacitors (and
smaller values such as 47µF and 2µF) on power-supply
lines AVDD and DVDD to provide low-frequency
bypassing. The loss (series resistance) associated with
these capacitors is beneficial in eliminating high-Q sup-
ply resonances. Ferrite beads are also used on each of
the power-supply lines to enhance supply bypassing
(Figure 9).
Combinations of small value (0.01µF and 0.1µF), low-
inductance surface-mount capacitors should be placed
at each supply pin or each grouping of supply pins to
attenuate high-frequency supply noise. Place these
capacitors on the top side of the board and as close to
the converter as possible with short connections to the
ground plane.
Parameter Definitions
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally, the midscale
MAX19586 transition occurs at 0.5 LSB above mid-
scale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
18 ______________________________________________________________________________________
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. The slope of the actual
transfer function is measured between two data points:
positive full scale and negative full scale. Ideally, the
positive full-scale MAX19586 transition occurs at 1.5
LSBs below positive full scale, and the negative full-
scale transition occurs at 0.5 LSB above negative full
scale. The gain error is the difference of the measured
transition points minus the difference of the ideal transi-
tion points.
Small-Signal Noise Floor (SSNF)
Small-signal noise floor is the integrated noise and dis-
tortion power in the Nyquist band for small-signal
inputs. The DC offset is excluded from this noise calcu-
lation. For this converter, a small signal is defined as a
single tone with an amplitude of less than -35dBFS.
This parameter captures the thermal and quantization
noise characteristics of the data converter and can be
used to help calculate the overall noise figure of a digi-
tal receiver signal path.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR[max] = 6.02 x N + 1.76
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first four harmonics (HD2 through
HD5), and the DC offset.
SNR = 20 x log (SIGNALRMS / NOISERMS)
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
Figure 9. Grounding, Bypassing, and Decoupling Recommendations for the MAX19586
AGND
BYPASSING—ADC LEVEL BYPASSING—BOARD LEVEL
ANALOG POWER-
SUPPLY SOURCE
DGND
AGND
DGND
D0–D15
47µF
2µF
0.1µF
0.1µF
220µF
AVDD DVDD
16
MAX19586
0.01µF 0.01µF
AVDD FERRITE BEAD
DIGITAL POWER-
SUPPLY SOURCE
47µF
2µF220µF
DVDD FERRITE BEAD
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
______________________________________________________________________________________ 19
Spurious-Free Dynamic Range
(SFDR1 and SFDR2)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset. SFDR1 reflects the
MAX19586 spurious performance based on worst 2nd-
or 3rd-order harmonic distortion. SFDR2 is defined by
the worst spurious component excluding 2nd- and 3rd-
order harmonic spurs and DC offset.
Two-Tone Spurious-Free Dynamic
Range (TTSFDR)
Two-tone SFDR is the ratio of the full scale of the con-
verter to the RMS value of the peak spurious compo-
nent. The peak spurious component can be related to
the intermodulation distortion components, but does
not have to be. Two-tone SFDR for the MAX19586 is
expressed in dBFS.
Two-Tone Intermodulation
Distortion (TTIMD)
IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones fIN1 and fIN2. The
individual input tone levels are at -8dBFS. The inter-
modulation products are as follows:
Second-Order Intermodulation Products (IM2):
fIN1 + fIN2, fIN2 - fIN1
Third-Order Intermodulation Products (IM3):
2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1
Fourth-Order Intermodulation Products (IM4):
3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1,
2 x fIN1 - 2 x fIN2
Fifth-Order Intermodulation Products (IM5):
3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2,
3 x fIN2 + 2 x fIN1, 4 x fIN1 - fIN2
Note that the two-tone intermodulation distortion is mea-
sured with respect to a single-carrier amplitude and not
the peak-to-average input power of both input tones.
Aperture Jitter
Aperture jitter (tAJ) represents the sample-to-sample
variation in the aperture delay specification.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 5).
MAX19586
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Inc.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Inc.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Inc.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Freed
56L THIN QFN.EPS
