HEF4069UBTT - NXP - Datasheet.Live

1. General description

The HEF4069UB is a general purpose hex inverter. Each inverter has a single stage.

It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to V SS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Specified from 40 C to +85 C and 40 C to +125 C

Complies with JEDEC standard JESD 13-B

3. Applications

Oscillator

4. Ordering information

HEF4069UB

Hex inverter

Rev. 8 — 16 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +125



Type number Package

Name Description Version

HEF4069UBP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4069UBT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

HEF4069UBTT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

Product data sheet Rev. 8 — 16 November 2011 2 of 17

NXP Semiconductors HEF4069UB

Hex inverter

5. Functional diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 1. Functional diagram Fig 2. Schematic diagram (one inv e r ter)

001aag152

1A 1Y

2A 2Y

3A 3Y

4A 4Y

5A 5Y

6A 6Y

001aag154

VDD

VSS

Fig 3. Pin configuratio n

HEF4069UB

1A VDD

1Y 6A

2A 6Y

2Y 5A

3A 5Y

3Y 4A

VSS 4Y

001aag153

7 8

Table 2. Pin description

Symbol Pin Description

1A to 6A 1, 3, 5, 9, 11, 13 input

1Y to 6Y 2, 4, 6, 8, 10, 12 output

VSS 7 ground (0 V)

VDD 14 supply voltage

Product data sheet Rev. 8 — 16 November 2011 3 of 17

NXP Semiconductors HEF4069UB

Hex inverter

7. Limiting values

[1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K.

[2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.

[3] For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K.

8. Recommended operating conditions

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5 V or VI>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

IOK output clamping current VO<0.5 V or VO>V

DD + 0.5 V - 10 mA

II/O input/output current - 10 mA

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +125 C

Ptot total power dissipation Tamb = 40 C to +125 C

DIP14 [1] -750mW

SO14 [2] -500mW

TSSOP14 [3] -500mW

P power dissipation per output - 100 mW

Table 4. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +125 C

Product data sheet Rev. 8 — 16 November 2011 4 of 17

NXP Semiconductors HEF4069UB

Hex inverter

9. Static characteristics

Table 5. Static characteristics

VSS = 0 V; VI=V

SS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 CUnit

Min Max Min Max Min Max Min Max

VIH HIGH-level

input voltage IO<1A5V4-4-4-4-V

10V8-8-8-8-V

15 V 12.5 - 12.5 - 12.5 - 12.5 - V

VIL LOW-level

input voltage IO<1A5V-1-1-1-1V

10V-2-2-2-2V

15 V - 2.5 - 2.5 - 2.5 - 2.5 V

VOH HIGH-level

output voltage IO<1A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - 14.95 - V

VOL LOW-level

output voltage IO<1A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 - 0.05 V

IOH HIGH-level

output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA

VO = 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA

VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA

VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA

IOL LOW-level

output current VO = 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA

VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA

VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA

IIinput leakage

current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A

IDD supply current all valid input

combinations;

IO=0A

5 V - 0.25 - 0.25 - 7.5 - 7.5 A

10 V - 0.5 - 0.5 - 15.0 - 15.0 A

15 V - 1.0 - 1.0 - 30.0 - 30.0 A

CIinput

capacitance digital inputs - - - 7.5 - - - - p F

Product data sheet Rev. 8 — 16 November 2011 5 of 17

NXP Semiconductors HEF4069UB

Hex inverter

10. Dynamic characteristics

[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).

Table 6. Dynamic characteristics

Tamb = 25



C; for wavefo rms see Figure 4; for test circuit see Figure 5.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay nA to nY; 5 V 18 ns + (0.55 ns/pF)CL-4590ns

10 V 9 ns + (0.23 ns/pF)CL-2040ns

15 V 7 ns + (0.16 ns/pF)CL-1525ns

tPLH LOW to HIGH

propagation delay nA to nY 5 V 13 ns + (0.55 ns/pF)CL-4080ns

10 V 9 ns + (0.23 ns/pF)CL-2040ns

15 V 7 ns + (0.16 ns/pF)CL-1530ns

tTHL HIGH to LOW output

transition time output nY 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

tTLH LOW to HIGH output

transition time output nY 5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

Table 7. Dynamic power dissipation

VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical formula Where

PDdynamic power dissipation 5 V PD = 600  fi + (fo  CL)  VDD2 (W) fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

(fo  CL) = sum of the outputs;

VDD = supply voltage in V.

10 V PD = 4000  fi + (fo  CL)  VDD2 (W)

15 V PD = 22000  fi + (fo  CL)  VDD2 (W)

Product data sheet Rev. 8 — 16 November 2011 6 of 17

NXP Semiconductors HEF4069UB

Hex inverter

11. Waveforms

Measurement points: VM = 0.5VDD.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig 4. Propagation delay and transition times

001aag185

PLH

PHL

TLH

90 %

10 %

THL

90 %

10 %

input

output

0 V

Definitions for test circuit:

CL= load capacitance including jig and probe capacitance;

RT= termination resistance should be equal to the output impedance Zo of the pulse generator;

For test data refer to Table 8.

Fig 5. Test circuit for measuring switching times

VDD

VIVO

001aag182

DUT

Table 8. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD 20 ns 50 pF

Product data sheet Rev. 8 — 16 November 2011 7 of 17

NXP Semiconductors HEF4069UB

Hex inverter

11.1 Transfer characteristics

a. VDD = 5 V; IO = 0 A b. VDD = 10 V; IO = 0 A

c. VDD = 15 V; IO = 0 A

(1) VO = output voltage.

(2) ID = drain current.

Fig 6. Typical transfer characteristics

VI (V)

0 5.02.5

001aag159

2.5

5.0

(V) ID

(μA)

250

500

(2) (2)(1)

VI (V)

0105

001aag160

(V) ID

(mA)

(2) (2)(1)

VI (V)

02010

001aag161

(V) ID

(mA)

(2) (2)(1)

Product data sheet Rev. 8 — 16 November 2011 8 of 17

NXP Semiconductors HEF4069UB

Hex inverter

12. Application information

Some examples of applications for the HEF4069UB.

Figure 7 shows an astable relaxation oscillator using two HEF4069UB inverters and 2

BAW62 diodes. The oscillation frequency is mainly determined by R1 C1, provided

R1 << R2 and R2 C2 << R1 C1.

The function of R2 is to minimize the influence of the forward volt age across the protection

diodes on the frequency; C2 is a stray (parasitic) capacitance.

The period Tpis given by Tp=T

1+T

where:

VST = the signal threshold level of the inverter.

The period is fairly independe nt of VDD, VST and temperature. The duty factor , however , is

influenced by VST.

T1R1C1InVDD VST

VST

--------------------------=

T2R1C1In 2VDD VST

–

VDD VST

–

-----------------------------=

Fig 7. Astable relaxation oscillator

001aag162

forward voltage

clamping diode

C2 C1

R2 R1

VDD VDD

0 V

VDD

0 V

1.5VDD

VDD

0.5VDD

0 V

−0.5VDD

VDD

0.5VDD

0 V

VSS

1/6 HEF4069UB 1/6 HEF4069UB

Product data sheet Rev. 8 — 16 November 2011 9 of 17

NXP Semiconductors HEF4069UB

Hex inverter

Figure 8 shows a crystal oscillator for frequencies up to 10 MHz using two HEF4069UB

inverters. The second inverter amplifies the oscillator output voltage to a level sufficient to

drive other Local Oxidation CMOS (LOCMOS) circuits.

Figure 9 and Figure 10 show vo ltage gain and supply current. Figure 11 shows the test

set-up and an example of an analog amplifier using one HEF4069UB.

The output inverter is used to amplify the oscillator output voltage to a level sufficient to drive other LOCMOS circuits.

Fig 8. Crystal oscillator

001aag155

2.2 kΩ

100 pF 22 pF

2 MHz

1 MΩ1 MΩ

22 pF

1/6 HEF4069UB 1/6 HEF4069UB

Fig 9. Typical voltage gain as a function of

supply voltage Fig 10. Typical supply current as a function of

supply voltage

VDD (V)

015105

001aag156

50 typ

gain

(VO/VI)

001aag157

VDD (V)

015105

IDD

(mA)

typ

Fig 11. Test set-up

001aag158

330 kΩ

1/6 HEF4069UB

Product data sheet Rev. 8 — 16 November 2011 10 of 17

NXP Semiconductors HEF4069UB

Hex inverter

Figure 12 shows typical forward transconductance and Figure 13 shows the test set-up.

(1) Average +2; where: ‘’ is the standard deviation.

(2) Average.

(3) Average 2; where: ‘’ is the standard deviation.

at VO is constant.

fi.= 1 kHz

Fig 12. Typical forward transconductance as a

function of supply voltage at Tamb = 25 CFig 13. Test set-up

001aag164

VDD (V)

015105

5.0

2.5

7.5

gfs

(mA/V)

(1)

(2)

(3)

001aag163

VDD

VSS

input output 100 μF

Rbias = 560 kΩ

0.47 μF

ViA

gfs dIo

dVi

--------

Product data sheet Rev. 8 — 16 November 2011 11 of 17

NXP Semiconductors HEF4069UB

Hex inverter

13. Package outline

Fig 14. Package outline SOT27-1 (DIP14)

UNIT A

max. 1 2 (1) (1)

b1cD (1)

Ee M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT27-1 99-12-27

03-02-13

min. A

max. bmax.

1.73

1.13 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 2.24.2 0.51 3.2

0.068

0.044 0.021

0.015 0.77

0.73

0.014

0.009 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0870.17 0.02 0.13

050G04 MO-001 SC-501-14

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

Product data sheet Rev. 8 — 16 November 2011 12 of 17

NXP Semiconductors HEF4069UB

Hex inverter

Fig 15. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 8 — 16 November 2011 13 of 17

NXP Semiconductors HEF4069UB

Hex inverter

Fig 16. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 8 — 16 November 2011 14 of 17

NXP Semiconductors HEF4069UB

Hex inverter

14. Revision history

Table 9. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4069UB v.8 20111116 Product data sheet - HEF4069UB v.7

Modifications: •Legal pages updated.

•Changes in “General description”, “Features and benefits” and “Applications”.

HEF4069UB v.7 20110511 Product data sheet - HEF4069UB v.6

HEF4069UB v.6 20091208 Product data sheet - HEF4069UB v.5

HEF4069UB v.5 20090723 Product data sheet - HEF4069UB v.4

HEF4069UB v.4 20080704 Product data sheet - HEF4069UB_CNV v.3

HEF4069UB_CNV v.3 19950101 Product specification - HEF4069UB_CNV v.2

HEF4069UB_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 8 — 16 November 2011 15 of 17

NXP Semiconductors HEF4069UB

Hex inverter

15. Legal information

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[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

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Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the obj ective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 8 — 16 November 2011 16 of 17

NXP Semiconductors HEF4069UB

Hex inverter

Non-automotive qualified products — Unless this data sheet expressly

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the product is not suitable for automotive use. It i s neither qua lified nor test ed

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In the event that customer uses the product for design-in and use in

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Notice: All referenced b rands, produc t names, service names and trademarks

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16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF4069UB

Hex inverter

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 16 Novem ber 2011

Document identifier: HEF40 69UB

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 3

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

11.1 Transfer characteristics . . . . . . . . . . . . . . . . . . 7

12 Application information. . . . . . . . . . . . . . . . . . . 8

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

15 Legal information . . . . . . . . . . . . . . . . . . . . . . . 15

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

16 Contact information. . . . . . . . . . . . . . . . . . . . . 16

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17