Datasheet Brief 75P42100 IP Co-Processor 32K x 72 Entries To request the full IDT75P42100 datasheet, please contact your local IDT Sales Representative or call 1-831-754-4555 Device Description Block Diagram IDT's 75P42100 IPC is a high performance pipelined low-power, synchronous full-ternary 32K x 72 entry device. Each entry location in the IPC has both a Data entry and an associated Mask entry. IDT's IPC devices integrate content addressable memory (CAM) technology with high-performance logic. The device can perform Lookup and Learn IPC operations plus Read, Write, Burst Write, and Dual Write maintenance operations. The IDT 75P42100 IPC device has a bi-directional bus that is a multiplexed address and data bus that can support 100 million sustained searches per second. This device provides array segments which can be configured to enable multiple width lookups from 36 to 576 bits wide. The IDT 75P42100 requires a 1.8-volt VDD supply, a user selectable 1.8 or 2.5-volt VDDQ supply, and a 2.5-volt VBIAS supply. This IPC device provides the user with flexibility and control in determining the device power. Only the array segments that will be used for a specific IPC operation are powered up while the unused segments are not. The IDT 75P42100 utilizes IDT's latest high-performance 1.8V CMOS processing technology and is packaged in a JEDEC Standard, thermally enhanced, low profile Ball Grid Array. The options include a 304 BGA, satisfying smaller footprint requirements and a 372 BGA package that is compatible with IDT's 64K x 72 Entry (75P52100) and 128K x 72 Entry (75K62100) IPC devices. LAST IPC LAST SRAM CLOCK Configuration Registers and Ram Control Circuits /2 Counter S I Z E RESET ARRAY REQSTB R/W Command Bus L O G I C Instruction IPC REQUEST BUS D E Request Data Bus ASIC FEEDBACK CCLK PHASE BURST SRAM CONTROL C Address O D E P R I O R I T Y Index Bus IPC RESPONSE BUS E N C O D E R Bypass Comparand Registers MMOUT Global Mask Registers DATA MATCHOUT Result Register 5 346 drw 01 Features System Configurations IDT's IPCs are designed to fulfill the needs of various types of networking systems. In solutions requiring data searching such as routers, a system configuration as shown in Figure 1.0 may be realized. Maximum flexibility is provided by allowing one board design to be populated today using either IDT's 75P42100 or 75P52100 IPCs and later upgraded to use IDT's 75K62100 IPC. Applications note AN-279 discusses how to accommodate one board design for any of these IPCs. In this compatible configuration, the IPC interfaces directly to an ASIC/ FPGA for lookups and routes an Index to an associated SRAM device, which supplies the next hop address via an SRAM Data Bus to the ASIC. The IPC provides the required control signals to directly hookup to ZBTTM or Synchronous Pipeline Burst SRAM. Lookup results can also be fed directly back to the ASIC/ FPGA without the use of external SRAM. Control of the associated handshake signals is provided by all IPCs to adapt to either configuration. Figure 1.0 ASIC / Compatible IPC / SRAM configuration Network Interface Full Ternary 32K x 72 bit content addressable memory Upgradeable to 64K x 72 and 128K x 72 IPCs Power Management Global Mask Registers Segments individually configurable 36/72/144/288/576 multiple width lookups 100M sustained lookups per second at 72 and 144 width lookups Burst write for high speed table updates Multi-match Learn new entries Dual bus interface Cascadable to 8 devices with no glue logic or latency penalty Glueless interface to standard ZBTTM or Synchronous Pipelined Burst SRAMs Boundary Scan JTAG Interface (IEEE 1149.1compliant) 1.8V core power supply 2.5V VBIAS power supply User selectable 2.5V or 1.8V I/O supply ASIC or FPGA IDT 75P42100 or 75P52100 or 75K62100 IP Co-Processor Optional ZBT or Sync SRAM 5346 drw02 OCTOBER 2001 1 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5346/01 IP Co-Processor 32K x 72 Entries Datasheet Brief 75P42100 Functional Highlights Data and Mask Array The IPC has Data cell entries and associated Mask cell entries as shown in Fig. 1.1. This combination of Data and Mask cell entries enables the IPC to store 0, 1 or X, making it a full ternary IP Co-Processor. During a lookup operation, both arrays are used along with a Global Mask Register to find a match to a requested data word. Lookup A lookup can be requested in 72-bit, 144-bit, 288-bit or 576-bit widths. A 36-bit lookup can be accomplished by using two Global Mask Registers. Learn The IPC implements a fully autonomous Learn Instruction, which provides a mechanism for the user to write a lookup entry into an unused location in the IPC and the associated data in external SRAM. This allows the user to update an entry into the IPC which had not previously been stored. The Learn writes the new entry, making it available for future lookups. Mask D at a SRAM Interface The IPC provides all required address and control signals for a glueless SRAM interface. The IPC provides a pipelined bypass path for reads or writes to the external SRAM. The ASIC/FPGA handles the pipelining of the data to and from the SRAM. A 5346 drw 03 Figure 1.1 Bus Interface The IPC utilizes a dual bus interface consisting of the IPC Request Bus and the IPC Response Bus. The IPC Request Bus is comprised of the Command Bus and the Request Data Bus. The Command Bus handles the instruction to the IPC while the Request Data Bus is the main data path to the IPC. The 72 bit bi-directional Request Data Bus functions as a multiplexed address and data bus, which performs the writing and reading of IPC entries, as well as presenting lookup data to the device. The IPC Response Bus is comprised of an independent unidirectional Index Bus which drives the result of the lookup (or index) to either an SRAM device or an ASIC. In addition to driving the Index, the IPC Response Bus also drives the associated SRAM control signals (CE/OE, and WE) for either ZBTTM or Synchronous Pipeline Burst SRAM devices. Registers There are four basic types of registers supported: Configuration Registers are used at initialization to define the segmentation of the entries, timing of outputs and the SRAM interface. Global Mask Registers are provided to support Lookup instructions by masking individual bits during a search. Comparand Registers assist in the Learn Instruction. Result Registers are used to store the resulting index of a search from a Lookup or Learn operation. Synchronous Burst Write The burst write feature has no limit on the number of continuous write accesses and supports initialization of the IPC. Command Bus The Command Bus loads the specific instructions into the IPC. These include: Read or Write A Read or Write instruction operates on a specified data entry, mask entry, or register. SRAM No Wait Read An SRAM No Wait Read is a Read instruction to an external SRAM that can be pipelined within a series of operations and does not require the user to wait for the Read to complete before loading the next instruction. Dual Write In addition to individual writes, the IPC has the ability to perform simultaneous writes to a Data entry and a respective external SRAM location. Width Segmentation Capability The IPCs are capable of performing lookups for comparisons on data structures of 72 bits, 144 bits, 288 bits and 576 bits. These devices has can be configured to meet various system requirements. Single Width Array Multiple Width Arrays within a Single Device Multi Match The Multi-Match feature signals to the user that more than one match has resulted. The result of the lookup, which defines the highest priority match, is sent along with the Multi-Match signal. Power Savings and Classification Features See the full IDT75P42100 Datasheet for more information. 2 IP Co-Processor 32K x 72 Entries Datasheet Brief 75P42100 Signal Descriptions Pin Function I/O Description Input This input signifies a valid input request and signals the start of an IPC operation cycle. Instruction Input Lookup Type Input These two fields of the Command b us define the instruction to be performed by the IPC and the lookup type. The lookup type is selected only for operational type commands (Lookups, Learns) and is a "don't care" for maintenance typ e commands (all Reads and Writes). Global Mask Register Select Input This field is within the Command bus. During Lookup or Write operations, this fie ld defines which of the Global Mask Register groups are b eing accessed. This field is a "don't care" for Read, SRAM No Wait Read, and Learn Operations. Comparand and Result Register Select Input This is a multiplexed field within the Command Bus that specifies both the Result Register to store the Index into, and the Comparand Reg ister to use. This field is sampled every input clock cycle. The first cycle decodes the selected Comparand Register and the second decodes the selected Result Register. IPC Request Bus: Request Strobe Command Bus Request Data Bus Input/Output The Request Data Bus is a multiplexed address/data bus used to perform reads (and writes) from (to) the Three State IPC, and to present search data for lookups. IPC Response Bus: Address Index Bus Device ID Lookup Type Chip Enable/ Output Enable Write Enable This bus is used to drive the address of an external SRAM, or feedback Lookup result information Output directly to the IPC's ASIC/FPGA. The Index Bus contain the encoded location at which the compare was Three State found, the address of the IPC which found the result and the Lookup type. Output Three State This signal is driven along with the Index Bus. It is connected to the CE input pin of a ZBT SRAM or to the OE pin of a PBSRAM. Output This signal is driven along with the Index bus. It is used to assert the WE pin of an external SRAM. It is Three State active for both SRAM write operations and the Learn command. Read Acknowledge Output This signal is sent back when the data is read from the IPC on the Request Data Bus, or when the data being read from the associated external SRAM. Match Acknowledge Output This is signal is sent with the Index. It will be driven low if there was no match, high if a match was found. Valid Lookup Bit Output This signal is sent with the Index. It will be driven high upon the completion of a lookup, even if the lookup did not result in a hit. Multi Match Output This signal is sent with the Index. It shall go active when a) multiple hits occur in one segment; or, b) one Output or mo re hits occur in two (or more) segments; or, c) one or more hits occur in multiple devices that are (Open Drain) depth cascaded. Depth Expansion: Device Address Input These three DC pins are used to define the Device Address for each of the eight possible depth expanded IPC devices in an IPC system. Match Input Input The Match Input signal is driven by all upstream Match Output signals. This indicates to all down stream IPCs that a hit in a higher priority IPC has occurred. Match Output Output The Match Output signal signifies that a match has occurred in the IPC. The signal is fed into a Match Input line of all lower priority IPC(s). Clock and Initialization: Clock Input Input All inputs and outputs are referenced to the positive edge of this clock. Clock Phase Enable Input This signal is used to generate an internal clock at 1/2 the freque ncy of the input clock. Reset Input This pin will force all outputs to a high impedence condition, as well as clearing the IPC enable bit. Advance Burst Address Input This signal will advance an internal address counter to allow for burst writes when writing to the Data/Mask memory in the IPC. This provides a mechanism to conveniently initialize the IPC memory. Last IPC Input This pin defines which IPC device will drive the ASIC Feedback signals to the ASIC/FPGA. Last SRAM Input This pin defines which IPC device will drive the SRAM control signals CE/OE and WE. It also defaults this device to driving the Index Bus when there is no ongoing operation preventing the bus from floating. 6.42 3 5346 tbl 01