Triple, 1.5 GHz Op Amp
Data Sheet
AD8003
Rev. C Document Feedback
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FEATURES
High speed
1650 MHz (G = +1)
730 MHz (G = +2, VO = 2 V p-p)
4300 V/µs (G = +2, 4 V step)
Settling time 12 ns to 0.1%, 2 V step
Excellent for QXGA resolution video
Gain flatness 0.1 dB to 190 MHz
0.05% differential gain error, RL = 150 Ω
0.01° differential phase error, RL = 150 Ω
Low voltage offset: 0.7 mV (typical)
Low input bias current: 7 µA (typical)
Low noise: 1.8 nV/√Hz
Low distortion over wide bandwidth: SFDR −73 dBc @ 20 MHz
High output drive: 100 mA output load drive
Supply operation: +5 V to ±5 V voltage supply
Supply current: 9.5 mA/amplifier
APPLICATIONS
High resolution video graphics
Professional video
Consumer video
High speed instrumentation
Muxing
CONNECTION DIAGRAM
1
2
3
4
5
6
18
17
16
15
14
13
7 8 9 10 11 12
24 23 22 21 20 19
+V
S3
FE E DBACK 3
–IN 3
+IN 3
PO WER DO WN 3
–V
S3
–V
S2
PO WER DO WN 2
+IN 2
–IN 2
FE E DBACK 2
+V
S2
+V
S1
FE E DBACK 1
–IN 1
+IN 1
PO WER DO WN 1
–V
S1
NC
NOTES
1. NC = NO CO NNE C T.
2. EXPOSED PAD (LF CS P ONLY): THE EXPOSED PAD CAN BE CONNE CTED TO GND
OR POWER PLANES, OR IT CAN BE LEFT FLOATING.
OUT 1
NC
OUT 2
NC
OUT 3
05721-001
Figure 1. 24-Lead, 4 mm × 4 mm LFCSP_WQ (CP-24)
GENERAL DESCRIPTION
The AD8003 is a triple ultrahigh speed current feedback amplifier.
Using ADI’s proprietary eXtra Fast Complementary Bipolar
(XFCB) process, the AD8003 achieves a bandwidth of 1.5 GHz
and a slew rate of 4300 V/µs. Additionally, the amplifier provides
excellent dc precision with an input bias current of 50 µA
maximum and a dc input voltage of 0.7 mV.
The AD8003 has excellent video specifications with a frequency
response that remains flat out to 190 MHz and 0.1% settling within
12 ns to ensure that even the most demanding video systems
maintain excellent fidelity. For applications that use NTSC video,
as well as high speed video, the amplifier provides a differential
gain of 0.05% and a differential gain of 0.01°.
The AD8003 has very low spurious-free dynamic range (SFDR)
(−73 dBc @ 20 MHz) and noise (1.8 nV/√Hz). With a supply
range between 5 V and 11 V and ability to source 100 mA of
output current, the AD8003 is ideal for a variety of applications.
The AD8003 operates on only 9.5 mA of supply current per
amplifier. The independent power-down function of the AD8003
reduces the quiescent current even further to 1.6 mA.
The AD8003 amplifier is available in a compact 4 mm × 4 mm,
24-lead LFCSP_WQ. The AD8003 is rated to work over the
industrial temperature range of −40°C to +85°C.
05721-009
11001000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAI N ( dB)
10
V
S
= ±5V
G = +1, R
F
=432Ω
G = +2, +5, R
F
=464Ω
R
L
=150Ω
V
OUT
= 2V p-p
G = +1
G = +2
G = +5
Figure 2. Large Signal Frequency Response for Various Gains
AD8003 Data Sheet
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications with ±5 V Supply ..................................................... 3
Specifications with +5 V Supply ..................................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Applications Information .............................................................. 12
Gain Configurations .................................................................. 12
RGB Video Driver ...................................................................... 12
Printed Circuit Board Layout ....................................................... 13
Low Distortion Pinout ............................................................... 13
Signal Routing ............................................................................. 13
Exposed Paddle........................................................................... 13
Power Supply Bypassing ............................................................ 13
Grounding ................................................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
3/14—Rev. B to Rev. C
Changed LFCSP_VQ to LFCSP_WQ (Throughout) ................... 1
Added EPAD Note to Figure 1 ........................................................ 1
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
9/08—Rev. A to Rev. B
Changes Applications Section ......................................................... 1
Changes to Ordering Guide .......................................................... 15
2/06—Rev. 0 to Rev. A
Changes to Figure 34 ...................................................................... 11
10/05—Revision 0: Initial Version
Data Sheet AD8003
Rev. C | Page 3 of 16
SPECIFICATIONS WITH ±5 V SUPPLY
TA = 25°C, VS = ±5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, V
o
= 0.2 V p-p, R
F
= 432 Ω
1650 MHz
G = +2, Vo = 2 V p-p 730 MHz
G = +10, Vo = 0.2 V p-p 290 MHz
G = +5, V
o
= 2 V p-p
330 MHz
Bandwidth for 0.1 dB Flatness Vo = 2 V p-p 190 MHz
Slew Rate G = +2, Vo = 2 V step, RL = 150 Ω 3800 V/µs
Settling Time to 0.1%
G = +2, V
o
= 2 V step
12 ns
Overload Recovery Input/Output 30/40 ns
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic @ 5 MHz G = +1, Vo = 2 V p-p 76/97 dBc
Second/Third Harmonic @ 20 MHz G = +1, Vo = 2 V p-p 79/73 dBc
Input Voltage Noise
f = 1 MHz
1.8
nV/√Hz
Input Current Noise (I−/I+) f = 1 MHz 36/3 pA/√Hz
Differential Gain Error NTSC, G = +2, RL
= 150 Ω 0.05 %
Differential Phase Error NTSC, G = +2, RL
= 150 Ω 0.01 Degree
DC PERFORMANCE
Input Offset Voltage −9.3 +0.7 +9.3 mV
TMIN − TMAX 1.08 mV
Input Offset Voltage Drift 7.4 µV/°C
Input Bias Current +IB/−IB −19/−40 −7/−7 +4/+50 µA
TMIN − TMAX (+IB/−IB) −3.8/+29.5 µA
Input Offset Current ±14.2 µA
Transimpedance Vo = ±2.5 V 400 600 1100 kΩ
INPUT CHARACTERISTICS
Noninverting Input Impedance 1.6/3 MΩ/pF
Input Common-Mode Voltage Range ±3.6 V
Common-Mode Rejection Ratio VCM = ±2.5 V −51 −48 −46 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 150 Ω ±3.85 ±3.9 ±3.92 V
Linear Output Current VO = 2 V p-p, second harmonic < −50 dBc 100 mA
Capacitive Load Drive 40% over shoot 27 pF
POWER DOWN PINS
Power-Down Input Voltage Power down <VS − 2.5 V
Enable >VS − 2.5 V
Turn-Off Time 50% of power-down voltage to
10% of VOUT final, VIN = 0.5 V p-p
40 ns
Turn-On Time
50% of power-down voltage to
90% of VOUT final, VIN = 0.5 V p-p
130
ns
Input Current
Enabled 0.1 µA
Power-Down −365 −235 −85 µA
POWER SUPPLY
Operating Range 4.5 10 V
Quiescent Current per Amplifier Enabled 8.1 9.5 10.2 mA
Quiescent Current per Amplifier
Power down
1.4
mA
Power Supply Rejection Ratio (+PSRR/−PSRR) −59/−57 −57/−53 −55/−50 dB
AD8003 Data Sheet
Rev. C | Page 4 of 16
SPECIFICATIONS WITH +5 V SUPPLY
TA = 25°C, VS = 5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
G = +1, V
o
= 0.2 V p-p, R
F
= 432 Ω
1050 MHz
G = +2, Vo = 2 V p-p 590 MHz
G = +10, Vo = 0.2 V p-p 290 MHz
G = +5, V
o
= 2 V p-p
310 MHz
Bandwidth for 0.1 dB Flatness Vo = 2 V p-p 83 MHz
Slew Rate G = +2, Vo = 2 V step, RL = 150 Ω 2860 V/µs
Settling Time to 0.1%
G = +2, V
o
= 2 V step
12 ns
Overload Recovery Input/Output 40/60 ns
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic @ 5 MHz G = +1, Vo = 2 V p-p 75/78 dBc
Second/Third Harmonic @ 20 MHz G = +1, Vo = 2 V p-p 66/61 dBc
Input Voltage Noise
f = 1 MHz
1.8
nV/√Hz
Input Current Noise (I−/I+) f = 1 MHz 36/3 pA/√Hz
Differential Gain Error NTSC, G = +2, RL
= 150 Ω 0.04 %
Differential Phase Error NTSC, G = +2, RL
= 150 Ω 0.01 Degree
DC PERFORMANCE
Input Offset Voltage −6.5 +2.7 +11 mV
TMIN − TMAX 2.06 mV
Input Offset Voltage Drift 14.2 µV/°C
Input Bias Current (+IB/−IB) −21/−50 −7.7/−2.3 +5/+48 µA
TMIN − TMAX (+IB/−IB) −4/−27.8 µA
Input Offset Current ±5.4 µA
Transimpedance 300 530 1500 kΩ
INPUT CHARACTERISTICS
Noninverting Input Impedance 1.6/3 MΩ/pF
Input Common-Mode Voltage Range 1.3 to 3.7 V
Common-Mode Rejection Ratio −50 −48 −45 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 150 Ω ±1.52 ±1.57 ±1.62 V
Linear Output Current VO = 2 V p-p, second harmonic < −50 dBc 70 mA
Capacitive Load Drive 45% over shoot 27 pF
POWER DOWN PINS
Power-Down Input Voltage Power down <VS − 2.5 V
Enable
>V
S
− 2.5
V
Turn-Off Time 50% of power-down voltage to
10% of VOUT final, VIN = 0.5 V p-p
125 ns
Turn-On Time 50% of power-down voltage to
90% of VOUT final, VIN = 0.5 V p-p
80 ns
Input Current
Enabled
0.1
µA
Power-Down −160 −43 +80 µA
POWER SUPPLY
Operating Range 4.5 10 V
Quiescent Current per Amplifier Enabled 6.3 7.9 9.4 mA
Quiescent Current per Amplifier Power down 0.8 0.9 1.1 mA
Power Supply Rejection Ratio (+PSRR/−PSRR) −59/−56 −57/−53 −55/−50 dB
Data Sheet AD8003
Rev. C | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 11 V
Power Dissipation
See Figure 3
Common-Mode Input Voltage −VS − 0.7 V to +VS + 0.7 V
Differential Input Voltage ±VS
Exposed Paddle Voltage −VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Unit
24-Lead LFCSP_WQ 70 °C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8003 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8003. Exceeding a junction temperature of 175°C for
an extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the AD8003 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
PD = Quiescent Power + (Total Drive Power – Load Power)
( )
L
2
OUT
L
OUTS
SS
D
R
V
–
R
V
2
V
IVP
×+×=
RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
( ) ()
L
S
S
S
D
R
/
V
I
VP
2
4
+
×
=
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduce θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle,
4 mm × 4 mm LFCSP_WQ (70°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
05721-037
0
3.0
–55 125
AMBI E NT TE M P E RATURE ( °C)
MAXIMUM POWER DISSIPATIO N (W)
0.5
1.0
1.5
2.0
2.5
–35 –15 525 45 65 85 105
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
AD8003 Data Sheet
Rev. C | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
05721-002
110 100 1000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAI N ( dB)
G = –2
G = –1
V
S
= ±5V
R
F
= 464Ω
R
L
= 150 Ω
V
OUT
= 200mV p - p
Figure 4. Small Signal Frequency Response for Various Gains
05721-004
1100 1000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAI N ( dB)
10
G = +2
R
L
= 150 Ω
V
OUT
= 200mV p - p
V
S
= ±5V
V
S
= +5V
Figure 5. Small Signal Frequency Response for Various Supplies
05721-007
1100 1000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (d B)
10
G = +2
V
S
= ±5V
R
L
= 150Ω
V
OUT
= 200mV p - p
R
F
= 432Ω
R
F
= 357Ω
R
F
= 464Ω
R
F
= 392Ω
Figure 6. Small Signal Feedback Resistor (RF) Optimization
05721-003
11001000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (d B)
10
V
S
=±5V
G= +1, R
F
=432Ω
G = +2, +10, R
F
=464Ω
R
L
=150Ω
V
OUT
=200mV p-p G = +1
G=+2
G= +10
Figure 7. Small Signal Frequency Response for Various Gains
05721-005
1100 1000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAI N ( dB)
10
G = +2
VS = ±5V
RL = 150Ω
VOUT = 200mV p-p
T = + 25°C
T = –40°C
T = + 105°C
Figure 8. Small Signal Frequency Response for Various Temperatures
05721-008
1100 1000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAI N ( dB)
10
G = +2
V
S
= ±5V
R
L
= 150Ω
V
OUT
= 2V p-p
R
F
= 432Ω
R
F
= 357Ω
R
F
= 464Ω
R
F
= 392Ω
Figure 9. Large Signal Feedback Resistor (RF) Optimization
Data Sheet AD8003
Rev. C | Page 7 of 16
G = +1
V
S
=±5V
R
L
= 150Ω
V
OUT
= 200mV p-p
05721-006
–12
–9
–6
–3
3
0
6
1 10 100 1000 10000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
R
S
= 50Ω
R
S
= 0Ω
R
S
= 25Ω
Figure 10. G = +1 Series Resistor (RS) Optimization
05721-009
1 100 1000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10
V
S
=±5V
G=+1,R
F
=432Ω
G=+2,+5,R
F
= 464Ω
R
L
=150Ω
V
OUT
=2Vp-p
G=+1
G=+2
G=+5
Figure 11. Large Signal Frequency Response for Various Gains
G=+1
R
L
= 100Ω
V
OUT
=2Vp-p
05721-017
–120
–110
–80
–70
–60
–90
–100
–50
–40
–
30
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
THIRD
SECOND
V
S
=±5V
V
S
=+5V
Figure 12. Harmonic Distortion vs. Frequency for Various Supplies
G = +2
R
L
= 150Ω
V
OUT
= 2V p-p
05721-016
–0.9
–0.8
–0.7
–0.6
–0.4
–0.2
–0.1
0.2
–0.5
–0.3
0.1
0
0.3
1 10 100 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
V
S
=±5V
V
S
=+5V
Figure 13. 0.1 dB Flatness Response
05721-010
1 100 1000
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10
V
S
=±5V
G=+2
R
L
= 150Ω
V
OUT
=2Vp-p
T = +25°C
T = –40°C
T = +105°C
Figure 14. Large Signal Frequency Response for Various Temperatures
G=+2
R
L
=150Ω
V
OUT
=2Vp-p
05721-018
–120
–110
–80
–70
–60
–90
–100
–50
–40
–
30
0.1 1 10 100
FREQUENCY (MHz)
DISTORTION (dBc)
V
S
=±5V
V
S
=+5V
THIRD
SECOND
Figure 15. Harmonic Distortion vs. Frequency for Various Supplies
AD8003 Data Sheet
Rev. C | Page 8 of 16
G = +2
V
OUT
= 2V p-p
f
C
= 5MHz
05721-019
–90
–60
–50
–40
–70
–80
–30
–20
–
10
10 12 14 16 18 20 22 24 26 28 30
R
L
(Ω)
DISTORTION (dBc)
V
S
=±5V
V
S
=+5V
THIRD
SECOND
Figure 16. Harmonic Distortion vs. RL
G = +2
R
L
= 150Ω
V
OUT
= 2V p-p
05721-012
–2.0
–1.5
1.5
–1.0
1.0
–0.5
0.5
0
2.0
015
TIME (ns)
OUTPUT VOLTAGE (V)
V
S
= +5V
V
S
=±5V
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.5
1.0
4.0
1.5
3.5
2.0
3.0
2.5
4.5
OUTPUT VOLTAGE (V)
Figure 17. Large Signal Pulse Response for Various Supplies
G=+2
R
L
= 150Ω
V
S
=5V
V
OUT
= 200mV p-p
05721-022
2.2
2.5
2.6
2.7
2.4
2.3
2.8
0 5 10 15 20 25 30 35
TIME (ns)
OUTPUT VOLTAGE (V)
C
L
=0pF
C
L
=15pF
C
L
= 27pF
Figure 18. Small Signal Pulse Response for Various Capacitive Loads
G=+2
R
L
= 150Ω
V
OUT
= 200mV p-p
0
5721-011
–0.20
–0.15
0.15
–0.10
0.10
–0.05
0.05
0
0.20
015
TIME (ns)
OUTPUT VOLTAGE (V)
2.30
2.35
2.65
2.40
2.60
2.45
2.55
2.50
2.70
OUTPUT VOLTAGE (V)
V
S
=+5V
V
S
=±5V
1234567891011121314
Figure 19. Small Signal Pulse Response for Various Supplies
G=+2
R
L
= 150Ω
V
S
=±5V
V
OUT
= 200mV p-p
05721-020
–0.3
0
0.1
0.2
–0.1
–0.2
0.3
0 5 10 15 20 25 30 35
TIME (ns)
OUTPUT VOLTAGE (V)
C
L
=0pF
C
L
= 15pF
C
L
= 27pF
Figure 20. Small Signal Pulse Response for Various Capacitive Loads
05721-021
–1.5
0
0.5
1.0
–0.5
–1.0
1.5
–5 0105 152025303540 45
TIME (ns)
AMPLITUDE (V)
–0.3
0
0.1
0.2
–0.1
–0.2
0.3
SETTLING (%)
V
IN
V
SETTLE
V
OUT
G=+2
V
S
=±5V
R
L
= 150Ω
Figure 21. Short-Term 0.1% Settling Time
Data Sheet AD8003
Rev. C | Page 9 of 16
G=+2
RL= 150Ω
05721-013
0
5000
4000
1000
3000
2000
6000
07
VOUT p-p (V)
SLEW RATE (V/µs)
V
S
=+5V
V
S
=±5V
123456
RISE
FALL
Figure 22. Slew Rate vs. Output Voltage
G = +2
V
S
= ±5V
R
L
= 150Ω
05721-024
–5
–4
–3
–2
–1
0
1
2
3
4
5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (µs)
AMPLITUDE (V)
OUTPUT
INPUT × 2
Figure 23. Output Overdrive Recovery
G=0
V
S
=±5V
R
L
= 150Ω
05721-026
–60
–40
–50
–30
–10
–20
0
0.1 1 10 100
FREQUENCY (MHz)
COMMON-MODE REJECTION (dB)
Figure 24. Common-Mode Rejection vs. Frequency
G = +1
V
S
= ±5V
R
L
= 150Ω
05721-023
–5
–4
–3
–2
–1
0
1
2
3
4
5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (µs)
AMPLITUDE (V)
OUTPUT
INPUT
Figure 25. Input Overdrive Recovery
G=+1/+2
V
S
=±5V
05721-027
0.1
1
100
10
1000
0.1 1 10 100 1000
FREQUENCY (MHz)
IMPEDANCE
(
Ω)
Figure 26. Output Impedance vs. Frequency
G=+2
V
S
=±5V
R
L
= 150Ω
05721-025
–70
–60
–40
–50
–30
–10
–20
0
0.1 1 10 100 1000
FREQUENCY (MHz)
POWER SUPPLY REJECTION (dB)
PSR–
PSR+
Figure 27. Power Supply Rejection vs. Frequency
AD8003 Data Sheet
Rev. C | Page 10 of 16
05721-031
–5 –4 –3 –2 –1 0 1 2 3 4
–60
–40
–20
0
20
60
80
5
V
CM
(V)
V
OS
(mV)
40
V
S
=±5V V
S
=+5V
Figure 28. Offset Voltage vs. Input Common-Mode Range
05721-033
–5 –4 –3 –2 –1 0 1 2 3 4
–10
–8
–6
–4
–2
0
2
4
6
8
10
5
V
OUT
(V)
I
B
(A)
V
S
= ±5V
V
S
= +5V
Figure 29. Inverting Input Bias Current Linearity
G=+2
R
L
=150Ω
V
S
=±5V
05721-028
0
1
9
8
7
2
6
3
5
4
10
–5 5
POWERDOWNPINVOLTAGE(V
DIS
(V))
POSITIVE SUPPLY CURRENT (mA)
–300
–250
150
–200
100
–50
–100
–150
50
0
200
POWER DOWN PIN CURRENT (µA)
I
DIS
I
CC
–4–3–2–101234
Figure 30. POWER DOWN Pin Current and Supply Current vs.
POWER DOWN Pin Voltage
05721-032
–5 –4 –3 –2 –1 0 1 2 3 4
–20
–15
–10
–5
0
5
15
20
5
V
CM
(V)
I
B
(
µA)
10 V
S
=±5V V
S
=+5V
Figure 31. Noninverting Input Bias Current vs. Common-Mode Range
G=+2
R
L
=150Ω
V
IN
=0.5Vdc
05721-014
0
5
4
1
3
2
6
01.0
TIME (µs)
AMPLITUDE (V)
V
DIS(VS=±5V)
V
OUT(VS=±5V)
V
OUT(VS=±5V)
V
OUT(VS=+5V)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
DIS(VS=+5V)
V
OUT(VS=+5V)
Figure 32. Disable Switching Time for Various Supplies
G=+2
R
L
=150Ω
V
S
=5V
05721-029
0
1
9
8
7
2
6
3
5
4
10
05.0
POWERDOWNPINVOLTAGE(V
DIS
(V))
POSITIVE SUPPLY CURRENT (mA)
–60
–50
30
–40
20
–10
–20
–30
10
0
40
POWER DOWN PIN CURRENT (µA)
I
DIS
I
CC
0.51.01.52.02.53.03.54.04.5
Figure 33. POWER DOWN Pin Current and Supply Current vs.
POWER DOWN Pin Voltage
Data Sheet AD8003
Rev. C | Page 11 of 16
05721-034
10 100 1k 10k 100k 1M 10M
1
10
100
1000
FREQUENCY (Hz)
INP UT VOLTAGE NOISE (nV/√Hz)
V
S
= ±5V
R
F
= 1kΩ
Figure 34. Input Voltage Noise vs. Frequency
G=+2
RL=150Ω
DRIVING: CH1AND CH3
RECEIVING: CH2
05721-015
–100
–50
–60
–70
–80
–90
–40
–30
–20
–10
0
0.1 1 10 1001000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
V
S
=±5V
V
S
=+5V
Figure 35. Worst-Case Crosstalk
05721-035
10 1001k10k100k1M 10M
1
100
1000
10000
FREQUENCY (Hz)
10
INPUT CURRENT NOISE (pA/√Hz)
V
S
=±5V
I–
I+
Figure 36. Input Current Noise vs. Frequency
05721-030
1k 10k100k 1M 10M100M 1G
100
1k
10k
100k
1M
FREQUENCY (Hz)
MAG NITUDE ( Ω)
PHASE (Degrees)
0
20
40
60
80
120
140
160
180
200
100
Figure 37. Transimpedance
AD8003 Data Sheet
Rev. C | Page 12 of 16
APPLICATIONS INFORMATION
GAIN CONFIGURATIONS
Unlike conventional voltage feedback amplifiers, the feedback
resistor has a direct impact on the closed-loop bandwidth and
stability of the current feedback op amp circuit. Reducing the
resistance below the recommended value can make the amplifier
response peak and can even become unstable. Increasing the
size of the feedback resistor reduces the closed-loop bandwidth.
Table 5 provides a convenient reference for quickly determining
the feedback and gain set resistor values, and the small and
large signal bandwidths for common gain configurations. The
feedback resistors in Table 5 have been optimized for 0.1 dB
flatness frequency response.
Table 5. Recommended Values and Frequency Response1
Gain RF (Ω) RG (Ω) RS (Ω)
−3 dB
SS BW
(MHz)
Large
Signal
−3 dB
BW
Large
Signal
0.1 dB
BW
−1
300
300
0
734
668
--
+1 432 N/A 24.9 1650 822 --
+2 464 464 0 761 730 190
+5 300 75 0 567 558 165
+10 300 33.2 0 446 422 170
1Conditions: VS = ±5 V, TA = 25°C, RL = 150 Ω.
Figure 38 and Figure 39 show the typical noninverting and inverting
configurations and recommended bypass capacitor values.
FB
AD8003
10µF
0.1µF
R
G
R
S
+V
S
V
O
V
IN
R
L
–
+V
O
+V
–V
S
–V
10µF
0.1µF
R
F
05721-038
Figure 38. Noninverting Gain
FB
AD8003
10µF
0.1µF
RG
+VS
VO
VIN
RL
–
+VO
+V
–VS
–V
10µF
0.1µF
RF
05721-039
Figure 39. Inverting Gain
RGB VIDEO DRIVER
Figure 40 shows a typical RGB driver application using bipolar
supplies. The gain of the amplifier is set at +2, where RF = RG =
464 Ω. The amplifier inputs are terminated with shunt 75 Ω
resistors, and the outputs have series 75 Ω resistors for proper
video matching. In Figure 40, the POWER DOWN pins are not
shown connected to any signal source for simplicity. If the power-
down function is not used, it is recommended that the POWER
DOWN pins be tied to the positive supply and not be left floating
(not connected).
In applications that require a fixed gain of +2, as previously
mentioned, the designer may consider the ADA4862-3.
The ADA4862-3 is another high performance triple current
feedback amplifier. The ADA4862-3 has integrated feedback
and gain set resistors that reduce board area and simplify designs.
+V
S
10µF
0.1µF
–V
S
10µF
0.1µF
+V
S
10µF
0.1µF
–V
S
10µF
0.1µF
75Ω
75Ω
G
IN
05721-036
21
22
19
24
R
F
464Ω
75Ω
R
G
464Ω
75Ω
R
IN
PD1
3
2
4
PD2
PD3
1
+V
S
10µF
0.1µF
75Ω
75Ω
B
IN
G
OUT
R
OUT
B
OUT
16
17
15
18
13
523 14
–V
S
10µF
0.1µF
6
R
F
464Ω
R
G
464Ω
20
R
F
464Ω
R
G
464Ω
AD8003
Figure 40. RGB Video Driver
Data Sheet AD8003
Rev. C | Page 13 of 16
PRINTED CIRCUIT BOARD LAYOUT
Printed circuit board (PCB) layout is usually one of the last
steps in the design process and often proves to be one of the
most critical. A high performance design can be rendered
mediocre due to poor or sloppy layout. Because the AD8003 can
operate into the RF frequency spectrum, high frequency board
layout considerations must be taken into account. The PCB
layout, signal routing, power supply bypassing, and grounding
must all be addressed to ensure optimal performance.
LOW DISTORTION PINOUT
The AD8003 LFCSP features ADI’s low distortion pinout. The
pinout lowers the second harmonic distortion and simplifies the
circuit layout. The close proximity of the noninverting input
and the negative supply pin creates a source of second harmonic
distortion. Physical separation of the noninverting input pin
and the negative power supply pin reduces this distortion.
By providing an additional output pin, the feedback resistor
can be connected directly between the feedback pin and the
inverting input. This greatly simplifies the routing of the
feedback resistor and allows a more compact circuit layout,
which reduces its size and helps to minimize parasitics and
increase stability.
SIGNAL ROUTING
To minimize parasitic inductances, ground planes should be
used under high frequency signal traces. However, the ground
plane should be removed from under the input and output pins
to minimize the formation of parasitic capacitors, which degrades
phase margin. Signals that are susceptible to noise pickup should be
run on the internal layers of the PCB, which can provide
maximum shielding.
EXPOSED PADDLE
The AD8003 features an exposed paddle, which lowers the
thermal resistance by approximately 40% compared to a
standard SOIC plastic package. The paddle can be soldered
directly to the ground plane of the board. Thermal vias or heat
pipes can also be incorporated into the design of the mounting
pad for the exposed paddle. These additional vias improve the
thermal transfer from the package to the PCB. Using a heavier
weight copper also reduces the overall thermal resistance path
to ground.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8003 power supply pins
need to be properly bypassed.
Each amplifier has its own supply pins brought out for the utmost
flexibility. Supply pins can be commoned together or routed to a
dedicated power plane. Commoned supply connections can also
reduce the need for bypass capacitors on each supply line. The
exact number and values of the bypass capacitors are dictated
by the design specifications of the actual circuit.
A parallel combination of different value capacitors from each
of the power supply pins to ground tends to work the best.
Paralleling different values and sizes of capacitors helps to ensure
that the power supply pins see a low ac impedance across a wide
band of frequencies. This is important for minimizing the coupling
of noise into the amplifier. Starting directly at the power supply
pins, the smallest value and physical-sized component should
be placed on the same side of the board as the amplifier, and as
close as possible to the amplifier, and connected to the ground
plane. This process should be repeated for the next largest capacitor
value. It is recommended that a 0.1 µF ceramic 0508 case be used
for the AD8003. The 0508 offers low series inductance and
excellent high frequency performance. The 0.1 µF case provides
low impedance at high frequencies. A 10 µF electrolytic capacitor
should be placed in parallel with the 0.1 µF. The 10 µF capacitor
provides low ac impedance at low frequencies. Smaller values
of electrolytic capacitors can be used depending on the circuit
requirements. Additional smaller value capacitors help provide a
low impedance path for unwanted noise out to higher
frequencies but are not always necessary.
Placement of the capacitor returns (grounds), where the capacitors
enter into the ground plane, is also important. Returning the
capacitor grounds close to the amplifier load is critical for
distortion performance. Keeping the capacitors distance short,
but equal from the load, is optimal for performance.
In some cases, bypassing between the two supplies can help
improve PSRR and maintain distortion performance in
crowded or difficult layouts. Designers should note this as
another option for improving performance.
AD8003 Data Sheet
Rev. C | Page 14 of 16
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduces the trace inductance. A
series inductance with the parallel capacitance can form a tank
circuit, which can introduce high frequency ringing at the output.
This additional inductance can also contribute to increased
distortion due to high frequency compression at the output.
The use of vias should be minimized in the direct path to the
amplifier power supply pins because vias can introduce parasitic
inductance, which can lead to instability. When required, use
multiple large diameter vias because this lowers the equivalent
parasitic inductance.
GROUNDING
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce stray
trace inductance and provide a low thermal path for the amplifier.
Ground and power planes should not be used under any of the
pins of the AD8003. The mounting pads and the ground or power
planes can form a parasitic capacitance at the amplifiers input.
Stray capacitance on the inverting input and the feedback
resistor form a pole, which degrades the phase margin, leading
to instability. Excessive stray capacitance on the output also forms a
pole, which degrades phase margin.
Data Sheet AD8003
Rev. C | Page 15 of 16
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC ST ANDARDS M O-220-W GG D-8.
06-11-2012-A
BOTT OM VIE WTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 RE F
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.20
2.10 SQ
2.00
1
24
7
12
13
1819
6
FOR PROPE R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE CONNECTIO N DIAG RAM
SECTI ON OF THI S DATA SHEET
0.05 M A X
0.02 NOM
Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity
AD8003ACPZ-R2 –40°C to +85°C 24-Lead LFCSP_WQ CP-24-10 250
AD8003ACPZ-REEL7 –40°C to +85°C 24-Lead LFCSP_WQ CP-24-10 1,500
AD8003ACHIPS Die
AD8003ACPZ-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD8003 Data Sheet
Rev. C | Page 16 of 16
NOTES
©2005–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05721-0-3/14(C)
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Authorized Distributor
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