M27C512-10C6X - STMicroelectronics

M27C512

512 Kbit (64Kb x8) UV EPROM and OTP EPROM

November 1998 1/15

5V ± 10% SUPPLY VOLTAGE in READ

OPERATION

FAS T A CCESS T IME: 45ns

LOW POWER “CMOS” CONSUMPTION:

– Active Current 30mA

– Standby Current 100µA

PROG RAMMING VOLTA GE : 12.75V ± 0.25V

PROG RAMMING TIMES of AROUND 6s ec.

(PRESTO IIB A LGORITHM)

ELECTR ON IC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 3Dh

DESCRIPTION

The M27C512 is a 512 K bit E PROM offered in the

two ranges UV (ultra violet erase) and OTP (one

time programmable). It is ideally suited for applica-

tions where fast turn-around and pattern experi-

mentation are important requirements and is

organized as 65,536 by 8 bits.

The FDIP28W (window ceramic frit-seal package)

has transparent lid which allows the user to expose

the chip to ultraviolet light to erase the bit pat tern.

A new pattern can then be written to the device by

following the programming procedure.

For applications where the content is programmed

only one time and erasure is not required, the

M27C512 is offered in PDIP28, PLCC32 and

TSOP28 (8 x 13.4 mm) packages.

AI00761B

Q0-Q7

VCC

M27C512

GVPP

VSS

A0-A15

Figure 1. Logic Diagram

A0-A15 Address Inputs

Q0-Q7 Data Outputs

E Chip Enable

GVPP Output Enable / Program Supply

VCC Supply Voltage

VSS Ground

Table 1. Signal Names

TSOP28 (N)

8 x 13.4mm

PLCC32 (C)

PDIP28 (B)

FDIP28W (F)

A13

A10

A14

A11

GVPP

Q5Q1

Q2 Q3VSS Q4

A12

A15 VCC

AI00762

M27C512

14 16

Figure 2A. DIP Pin Connections

Warning: NC = Not Connected, DU = Don’t Use

AI00763

A13

A10

A14

A15

A11

VCC

M27C512

A12

GVPP

VSS

Figure 2B. LCC Pin Connections

A11 Q7

GVPP E

A13

A14

A12

A15

VCC

AI00764B

M27C512

VSS

A10

Figure 2C. TSOP Pin Connections DEVICE OPERATION

The modes of operations of the M27C512 are listed

in the Operating Modes table. A single power

supply is required in the read mode. All inputs are

TTL levels except for GVPP and 12V on A9 for

Electronic Signature.

Read Mode

The M27C512 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (E) is the power

control and should be used for device selection.

Output Enable (G) is the output control and should

be used to gate data to the output pins, inde-

pendent of device selection. Assuming that the

addresses are stable, the address access time

(tAVQV) is equal to the delay from E to output (tELQV).

Data is available at the output after a delay of tGLQV

from the falling edge of G, assuming that E has

been low and the addresses have been stable for

at least tAVQV-tGLQV.

Standby Mode

The M27C512 has a standby mode which r educes

the active current from 30mA to 100µA The

M27C512 is placed in the standby mode by apply-

ing a CMOS high signal to the E input. When in the

standby mode, the outputs are in a high impedance

state, independent of the GVPP input.

2/15

M27C512

Symbol Parameter Value Unit

TAAmbient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltages (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause perm anent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relev ant quali ty documents .

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC

voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.

3. Depe nds on range.

Table 2. Absolute Maximum Ratings (1)

Mode E GVPP A9 Q0 - Q7

Read VIL VIL X Data Out

Output Disable VIL VIH X Hi-Z

Program VIL Pulse VPP X Data In

Program Inhibit VIH VPP X Hi-Z

Standby VIH X X Hi-Z

Electronic Signature VIL VIL VID Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V

Table 3. Operating Modes

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code VIL 00100000 20h

Device Code VIH 00111101 3Dh

Table 4. Electronic Signature

Two Line Output Control

Because EPROMs are usually used in larger mem-

ory arrays, the product features a 2 line control

function which accommodates the us e of multiple

memory connection. The two line control function

allows:

a. the low est possibl e memory p ower diss ipatio n,

b. complete assuranc e that output bus contention

will not occur.

For the most efficient use of these two control lines,

E should be decoded and used as the primary

device selecting function, while G should be made

a common connection to all devices in the array

and connected to the REA D line from the system

control bus. This ensures that all deselected mem-

ory devices are in their low power standby mode

and that the output pins are only active when data

is required from a part icular memory device.

3/15

M27C512

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 3. AC Testing Input Output W aveform

AI01823B

1.3V

OUT

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Figure 4. AC T esting Load Circuit

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Table 5. AC Measurement Conditions

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 12 pF

Note. 1. Sampl ed o nl y, not 100% tested.

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful de coupling of the

devices. The supply current, ICC, has three seg-

ments that are of interest to t he system designer:

the standby current level, the active current level,

and transient c urrent peaks that are produced by

the falling and rising edges of E. The m agnitude of

the transient current peaks is dependent on the

capacitive and inductive loading of the device at the

output.

The associated transient voltage peaks can be

suppressed by complying with the two line output

control and by properly selected decoupling ca-

pacitors. It is recommended that a 0.1µF ceramic

capacitor be used on every device between VCC

and VSS. This should be a high frequency capacitor

of low inherent inductance and should be placed

as close to the device as possible. In addition, a

4.7µF bulk electrolytic capacitor should be used

between VCC and VSS for every eight devices. The

bulk capacitor should be located near the power

supplyconnection point.The purpose of the bulk

capacitor is to overcome the voltage dr op caused

by the inductive effects of PCB traces.

4/15

M27C512

Sy mbol Parameter T est Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

ICC Supply Current E = VIL, G = VIL,

IOUT = 0mA, f = 5MHz 30 mA

ICC1 Supply Current (Standby) TTL E = VIH 1mA

CC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA

IPP Program Current VPP = VCC 10 µA

VIL Input Low Voltage –0.3 0.8 V

VIH (2) Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –1mA 3.6 V

Output High Voltage CMOS IOH = –100µAV

CC –0.7V V

Notes: 1. VCC must be a ppl ie d simultaneousl y with or before VPP and removed simultaneously or after VPP.

2. Maximum DC voltage on Output is VCC +0.5V.

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Symbol Alt Parameter Test Condition M27C512 Unit

-45 (3) -60 -70 -80

Min Max Min Max Min Max Min Max

tAVQV tACC Address Valid to

Output Valid E = VIL, G = VIL 45 60 70 80 ns

tELQV tCE Chip Enable

Low to Output

Valid G = VIL 45 60 70 80 ns

tGLQV tOE Output Enable

Low to Output

Valid E = VIL 25 30 35 40 ns

tEHQZ (2) tDF Chip Enable

High to Output

Hi-Z G = VIL 0 25 0 25 0 30 0 30 ns

tGHQZ (2) tDF Output Enable

High to Output

Hi-Z E = VIL 0 25 0 25 0 30 0 30 ns

tAXQX tOH Address

Transition to

Output Transition E = VIL, G = VIL 0000ns

Notes. 1. VCC m ust be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2. Sampled only , not 100% tested.

3. In case of 45ns speed see High Speed AC measurement conditions.

Table 8A. Read Mode AC Ch aracteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

5/15

M27C512

Symbol Alt Parameter Test Condition M27C512 Unit

-90 -10 -12 -15/-20/-25

Min Max Min Max Min Max Min Max

tAVQV tACC Address Valid to

Output Valid E = VIL, G = VIL 90 100 120 150 ns

tELQV tCE Chip Enable Low to

Output Valid G = VIL 90 100 120 150 ns

tGLQV tOE Output Enable Low

to Output Valid E = VIL 40 40 50 60 ns

tEHQZ (2) tDF Chip Enable High to

Output Hi-Z G = VIL 030030040 0 50ns

GHQZ (2) tDF Output Enable High

to Output Hi-Z E = VIL 030030040 0 50ns

AXQX tOH Address Transition

Output Transition E = VIL, G = VIL 0000 ns

Notes. 1. VCC m ust be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2. Sampled only , not 100% tested.

Table 8B. Read Mode AC Ch aracteristics (1)

(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

AI00735B

tAXQX

tEHQZ

A0-A15

Q0-Q7

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

VALID

Figure 5. R ead Mode AC W avef orms

Programming

When delivered (and after each erasure for UV

EPROM), all bits of the M27C512 are in the ’1’

state. Dat a is introduced by selectively program-

ming ’0’s into the desired bit locations. Although

only ’0’s will be programmed, both ’1’s and ’0’s can

be present in the data word. The only way to

change a ’0’ to a ’1’ is by die exposure to ultraviolet

light (UV EPROM). The M27C512 is in the pro-

gramming mode when VPP input is at 12.75V and

E is pulsed to VIL. The dat a to be progr ammed is

applied to 8 bits in parallel to the data output p ins.

The levels required for the address and data inputs

are TTL. VCC is specified to be 6.25V ± 0.25V.

The M27C512 can use PRE STO IIB P rogramming

Algorithm that drastically reduces the programming

time (typically less than 6 seconds). Nevertheless

to achieve compatibility with all programming

equipments, PRESTO Programming Algorithm can

be used as well.

6/15

M27C512

Symbol Alt Parameter Test Condition Min Max Unit

tAVEL tAS Address Valid to Chip Enable Low 2 µs

tQVEL tDS Input Valid to Chip Enable Low 2 µs

tVCHEL tVCS VCC High to Chip Enable Low 2 µs

tVPHEL tOES VPP High to Chip Enable Low 2 µs

tVPLVPH tPRT VPP Rise Time 50 ns

tELEH tPW Chip Enable Program Pulse Width (Initial) 95 105 µs

tEHQX tDH Chip Enable High to Input Transition 2 µs

tEHVPX tOEH Chip Enable High to VPP T ran sition 2 µs

tVPLEL tVR VPP Low to Chip Enable Low 2 µs

tELQV tDV Chip Enable Low to Output Valid 1 µs

tEHQZ (2) tDFP Chip Enable High to Output Hi-Z 0 130 ns

tEHAX tAH Chip Enable High to Address T ransitio n 0 ns

Notes: 1. VCC must be a ppl ie d simultaneousl y with or before VPP and removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

Table 11. Programmi ng Mode AC Character istics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA

ICC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –1mA 3.6 V

VID A9 Voltage 11.5 12.5 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)

Symbol Alt Parameter Test Condition Min Max Unit

tA9HVPH tAS9 VA9 High to VPP High 2 µs

tVPHEL tVPS VPP High to Chip Enable Low 2 µs

tA10HEH tAS10 VA10 High to Chip Enable High (Set) 1 µs

tA10LEH tAS10 VA10 Low to Chip Enable High (Reset) 1 µs

tEXA10X tAH10 Chip Enable Transition to VA10 T ransition 1 µs

tEXVPX tVPH Chip Enable Transition to VPP Transiti on 2 µs

tVPXA9X tAH9 VPP Transition to VA9 Transition 2 µs

Note: 1. VCC must be a ppl ie d simultaneousl y with or before VPP and removed simultaneously or after VPP.

Table 10. MARG IN MODE AC Charact eristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)

7/15

M27C512

AI00736B

tA9HVPH tVPXA9X

GVPP

A10 Set

VCC

tVPHEL

tA10LEH

tEXVPX

tA10HEH

A10 Reset

tEXA10X

Figure 6. MARG IN MODE AC Waveforms

AI00737

tVPLEL

PROGRAM

DATA IN

A0-A15

GVPP

Q0-Q7 DATA OUT

tAVEL

tQVEL

tVCHEL

tVPHEL

tEHQX

tEHVPX

tELEH

tELQV

tEHAX

tEHQZ

VERIFY

VALID

VCC

Figure 7. Programm ing and V erify Modes AC W aveforms

Note: A8 High level = 5V; A9 High level = 12V.

8/15

M27C512

AI00738B

n = 0

Last

Addr

VERIFY

E = 100µs Pulse

++n

= 25 ++ Addr

VCC = 6.25V, VPP = 12.75V

FAIL

CHECK ALL BYTES

1st: VCC = 6V

2nd: VCC = 4.2V

YES

SET MARGIN MODE

RESET MARGIN MODE

Figure 8. Pro grammi ng Flowchart

PRESTO IIB Programming Algorithm

PRESTO IIB Programming Algorithm allows the

whole array to b e programmed with a guaranteed

margin, in a typical time of 6.5 seconds. This can

be achieved with STMicroelectronics M27C512

due to several design innovations described in the

M27C512 datasheet to improve programming effi-

ciency and to provide adequate margin for reliabil-

ity. Before starting the programming the internal

MARGIN MODE circuit is set in order to guarantee

that each cell is programmed with enough margin.

Then a sequence of 100µs program pulses are

applied to each byte until a correct verify occurs.

No overprogram pulses are applied since the verify

in MARGIN MODE provides the necessary margin.

Program Inhibit

Programming of multiple M27C512s in parallel with

different data is also easily accomplished. Except

for E, all lik e inputs inc luding GVPP of the parallel

M27C512 may be common. A TTL low level pulse

applied to a M27C512’s E input, with VPP at 12.75V ,

will program that M27C512. A high level E input

inhibits the other M27C512s from being pro-

grammed.

Program Verify

A verify (read) should be performed on the pro-

grammed bits to determine that they were correctly

programmed. T he v erify is ac complished with G at

VIL. Data should be verified with tELQV after the

falling edge of E.

On- Board Program ming

The M27C512 can be directly pr ogrammed in the

application circuit. See the relevant Application

Note AN620.

Electron ic Signature

The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that

will identify its manufacturer and type. This mode

is intended for us e by programming equipment to

automatically match the device to be programmed

with its corresponding programming algorithm. The

ES mode is functional in the 25°C ± 5°C ambient

temperature range that is required when program-

ming the M27C512. To activate the ES mode, the

programming equipment must force 1 1.5V to 12.5V

on address line A9 of the M27C512. T wo identifier

bytes may then be sequenced from the device

outputs by toggling address line A0 from VIL to V IH.

All other address lines must be held at VIL during

Electronic Signature mode.

By te 0 (A0= VIL) represents the manufacturer code

and byte 1 (A0=VIH) the device identifier code. For

the STMicroelectronics M27C512, these two iden-

tifier bytes are given in Table 4 and can be read-out

on outputs Q0 to Q7.

ERASURE OPERATION (applies for UV

EPROM)

The erasure characteristics of the M27C512 is such

that erasure begins when the cells are exposed to

light with wavelengths short er than approximately

4000 Å. It should be noted that sunlight and some

type of fluorescent lamps have wavelengths in the

3000-4000 Å range.

Research shows that constant exposure to room

level fluorescent lighting could erase a typical

M27C512 in about 3 years, while it would take

approximately 1 week t o cause erasure when ex-

posed to direct sunlight. If the M27C512 is to be

exposed to these types of lighting conditions for

extended periods of time, it is suggested that

opaque labels be put over the M27C512 window to

prevent unintentional erasure. The recommended

erasure proc edure for the M 27C512 is exposur e to

short wave ultraviolet light which has wavelength

2537 Å. The integrated dose (i.e. UV intensity x

exposure time) for erasure should be a minimum

of 15 W-sec/cm2. The erasure time with this dosage

is approximately 15 to 20 minutes using an ultra-

violet lamp w ith 12000 µW/cm2 power rating. The

M27C512 should be plac ed within 2. 5 c m (1 inch)

of the lamp tubes during the erasure. S ome lamps

have a filter on their tubes which should be re-

moved before eras ure.

9/15

M27C512

ORDERING INFORMATION SCHEME

Note: 1. High Spee d, see AC Charact eri st i cs sec tion for further information

For a list of available options (Speed, VCC Tolerance, Package, etc...) or for further information on any

aspect of this device, please contact the STMicroelect r onics Sales Office nearest to you.

Speed

-45 (1) 45 ns

-60 60 ns

-70 70 ns

-80 80 ns

-90 90 ns

-10 100 ns

-12 120 ns

-15 150 ns

-20 200 ns

-25 250 ns

VCC Tolerance

X± 5%

blank ± 10%

Package

F FDIP28W

B PDIP28

C PLCC32

N TSOP28

8 x 13.4mm

Temperature Range

1 0 to 70 °C

6 –40 to 85 °C

3 –40 to 125 °C

Option

X Additional

Burn-in

TR Tape & Reel

Packing

Example: M27C512 -70 X C 1 TR

10/15

M27C512

FDIP28W - 28 pin Cer amic Frit-seal DIP, with window

FDIPW-a

B1 B e

E1 E

∅

Symb mm inches

Typ Min Max Typ Min Max

A 5.72 0.225

A1 0.51 1.40 0.020 0.055

A2 3.91 4.57 0.154 0.180

A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022

B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012

D 36.50 37.34 1.437 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – –

E1 13.06 13.36 0.514 0.526

e2.54– –0.100– –

eA 14.99 – – 0.590 – –

eB 16.18 18.03 0.637 0.710

L 3.18 0.125

S 1.52 2.49 0.060 0.098

∅7.11 – – 0.280 – –

α4°11°4°11°

N28 28

Drawing is not to scale

11/15

M27C512

PDIP28 - 28 pin Plastic DIP, 600 mils w idth

PDIP

B1 B e1

E1 E

Symb mm inches

Typ Min Max Typ Min Max

A – 5.08 – 0.200

A1 0.38 – 0.015 –

A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020

B1 1.52 – – 0.060 – –

C 0.20 0.30 0.008 0.012

D 36.83 37.34 1.450 1.470

D2 33.02 – – 1.300 – –

E 15.24 – – 0.600 – –

E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – –

eA 14.99 – – 0.590 – –

eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135

S 1.78 2.08 0.070 0.082

α0°10°0°10°

N28 28

Drawing is not to scal e

12/15

M27C512

PLCC 32 - 32 le ad Plast i c Leaded Ch i p Ca r rier, rectang ul ar

PLCC

Ne E1 E

1 N

D2/E2 e

0.51 (.020)

1.14 (.045)

Symb mm inches

Typ Min Max Typ Min Max

A 2.54 3.56 0.100 0.140

A1 1.52 2.41 0.060 0.095

A2 – 0.38 – 0.015

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

D 12.32 12.57 0.485 0.495

D1 11.35 11.56 0.447 0.455

D2 9.91 10.92 0.390 0.430

E 14.86 15.11 0.585 0.595

E1 13.89 14.10 0.547 0.555

E2 12.45 13.46 0.490 0.530

e1.27– –0.050– –

F 0.00 0.25 0.000 0.010

R 0.89 – – 0.035 – –

N32 32

Nd 7 7

Ne 9 9

CP 0.10 0.004

Drawing is not to scale

13/15

M27C512

TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm

TSOP-c

7 8

DIE

LA1 α

Symb mm inches

Typ Min Max Typ Min Max

A 1.25 0.049

A1 0.20 0.008

A2 0.95 1.15 0.037 0.045

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008

D 13.20 13.60 0.520 0.535

D1 11.70 11.90 0.461 0.469

E 7.90 8.10 0.311 0.319

e0.55– –0.022– –

L 0.50 0.70 0.020 0.028

α0°5°0°5°

N28 28

CP 0.10 0.004

Drawing is not to scal e

14/15

M27C512

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Speci fications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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M27C512