TDF8599ATH/N2CS - NXP SEMICONDUCTORS

1. General description

The TDF8599A is a dual Bridge-Tied Load (BTL) car audio amplifier comprising an

NDMOST-NDMOST output stage based on SOI BCDMOS technology. Low power

dissipation enables the TDF8599A high-efficiency, class-D amplifier to be used with a

smaller heat sink than those normally used with standard class-AB amplifiers.

The TDF8599A can operate in either non-I2C-bus mode or I2C-bus mode. When in

I2C-bus mode, DC load detection results and fault co nditions can be easily read back from

the device. Up to 15 I2C-bus addresses can be selected depending on the value of the

external resistor connected to pins ADS and MOD.

When pin ADS is short circuited to gro und, the TDF85 99A operate s in non-I2C-bus mode.

Switching between Operat ing mode and Mute mode in non-I 2C-bus mode is only possible

using pins EN and SEL_MUTE.

2. Features and benefits

High-efficiency

Low quiescent curren t

Operating voltage from 8 V to 35 V

Two 4 /2  capable BTL channels or one 1  capable BTL channel

Differential inputs

I2C-bus mode with 15 I2C-bus addresses or non-I2C-bus mode operation

Clip detect

Independent short circuit protection for each channel

Advanced short circuit protection for load, GND and supply

Load dump pr otection

Thermal foldback and thermal protection

DC offset protection

Selectable AD or BD modulation

Parallel channel mode for high current drive capability

Advanced clocking:

Switchable oscillator clock source: internal for Master mode or external for Slave

mode

Spread spectrum mode

Phase staggering

Frequency hopping

No ‘pop noise’ caused by DC output offset voltage

TDF8599A

I2C-bus controlled dual channel 135 W/4 , single channel

250 W/2  class-D power amplifier with load diagnostics

Rev. 3 — 2 May 2013 Product data sheet

Product data sheet Rev. 3 — 2 May 2013 2 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

I2C-bus mode:

DC load detection

AC load detection

Thermal pre-warning diagnostic level setting

Identification of ac tiva te d pr ot ec tion s or warn in gs

Selectable diagnostic information available using pins DIAG and CLIP

Qualified in accordance with AEC-Q100

3. Applications

Car audio

4. Quick reference data

[1] In this data sheet supply voltage VP describes VP1, VP2 and VPA.

[2] Output power is measured indirectly based on RDSon measurement.

5. Ordering information

Table 1. Quick reference data

VP= 14.4 V unless otherwise stated.

Symbol Parameter Conditions Min Typ Max Unit

VPsupply voltage [1] 8 14.4 35 V

IPsupply current off state; Tj  85 C; VP=14.4V - 2 10 A

Iq(tot) total quiescent current Operating mode; no load, snubbers and

filter connected -90120mA

Pooutput power Stereo mode: [2]

VP=14.4V; THD=1%; R

L=418 20 - W

VP= 14.4 V; THD = 10 %; RL=423 25 - W

square wave (EIAJ); RL=4-40-W

VP= 35 V; THD = 10 %; RL=4- 135 - W

VP=14.4V; THD=1%; R

L=226 29 - W

VP= 14.4 V; THD = 10 %; RL=234 38 - W

square wave (EIAJ); RL=2-60-W

Parallel mode: [2]

VP= 14.4 V; THD = 10 %; RL=2-50-W

VP= 35 V; THD = 10 %; RL=2- 250 - W

VP=25V; THD=1%; R

L=1135 150 - W

Table 2. Ordering information

Type number Package

Name Description Version

TDF8599ATH HSOP36 plastic, heatsink small outline package; 36 leads; low stand-off height SOT851-2

Product data sheet Rev. 3 — 2 May 2013 3 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

6. Block diagram

Fig 1. Block diagram

001aak071

PWM

CONTROL

TDF8599A DRIVER

HIGH

STABI1

5 V STABI STABI2

VP1

OUT1N

BOOT1P

OUT1P

OUT2N

BOOT2P

OUT2P

VSTAB2

VSTAB1

243110

AGND

SVRR

IN1P

IN1N

ACGND

IN2P

IN2N

VP2

VP1

VDDA

PGND1

VP1

PGND1

DRIVER

LOW

PWM

CONTROL

DRIVER

HIGH

DRIVER

LOW

BOOT1N

BOOT2N

PWM

CONTROL

DRIVER

HIGH

VP2

PGND2

VP2

PGND2

DRIVER

LOW

PWM

CONTROL

DRIVER

HIGH

DRIVER

LOW

OSCILLATOR

OSCSET 19

OSCIO 17

SSM 12

MOD

MODE

SELECT

I2C-BUS

DIAGNOSTICS PROTECTION

OVP, OCP, OTP

UVP, TFP, WP, DCP

GNDD/HW CLIP DCP

EN 7

SEL_MUTE 16

SCL 15

SDA 11

DIAG

14 13 20

ADS

PGND1

PGND2

VDDD 21

Product data sheet Rev. 3 — 2 May 2013 4 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

7. Pinning information

7.1 Pinning

7.2 Pin description

Fig 2. He atsink up (top view) pin configuration TDF859 9AT H

TDF8599ATH

OUT1N

IN1P

BOOT1N

IN1N

VP1

IN2P

PGND1

GNDD/HW

VDDD

VSTAB1

IN2N

BOOT1P

ACGND

OUT1P

OUT2P

SEL_MUTE

BOOT2P

SVRR

PGND2

AGND

VP2

VDDA

ADS

MOD

001aak072

CLIP

BOOT2N DIAG

OUT2N SDA

VSTAB2 SCL

DCP SSM

OSCIO OSCSET

Table 3. Pin description

Symbol Pin Type[1] Description

IN1P 1 I channel 1 positive audio input

IN1N 2 I channel 1 negativ e audio input

IN2P 3 I channel 2 positive audio input

IN2N 4 I channel 2 negativ e audio input

ACGND 5 I decoupling for input refe rence voltage

EN 6 I enable input:

non-I2C-bus mode: switch between off and Mute mode

I2C-bus mode: off and Standby mode

SEL_MUTE 7 I select mute or unmute

SVRR 8 I decoupling for internal half supply reference voltage

AGND 9 G analog supply ground

VDDA 10 P analog supply voltage

ADS 11 I non-I2C-bus mode: connected to ground

I2C-bus mode: selection and address selection pin

MOD 12 I modulation mode, pha se shift and parallel mode select

Product data sheet Rev. 3 — 2 May 2013 5 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

[1] I = input, O = output, I/O = input/output, G = ground and P = power supply.

[2] In this data sheet supply voltage VP describes VP1, VP2 and VPA.

8. Functional description

8.1 General

The TDF8599A is a dual full b ridge (BTL) audi o power amplifier using class-D technology.

The audio inpu t signal is con v erted in to a Pulse-Width Modulate d (PWM) sign al u sing th e

analog input and PWM control stages. A PWM signal is applied to driver circuits for both

high-side and low-side enabling the DMOS power output transistors to be driven. An

external 2nd order low-pass filter converts the PWM signal into an analog audio signal

across the loudspeakers.

CLIP 13 O clip output; open-drain

DIAG 14 O diagnostic output; open-drain

SDA 15 I/O I2C-bus data input and output

SCL 16 I I2C-bus clock input

SSM 17 master setting: Spread spectrum mode frequency

slave setting: phase lock operation

OSCSET 18 master/slave oscillator setting

master only setting: set internal oscillator frequency

OSCIO 19 I/O extern al oscillator slave setting: input

internal oscillator master setting: output

DCP 20 I DC protection inp ut for the filtered output voltages

VSTAB2 21 decoupling internal stabilizer 2 for DMOST drivers

OUT2N 22 O channel 2 negative PWM output

BOOT2N 23 boot 2 negative bootstrap capacitor

VP2[2] 24 P channel 2 power supply voltage

PGND2 25 G channel 2 power ground

BOOT2P 26 boot 2 positive bootstrap capacitor

OUT2P 27 O channel 2 positive PWM output

OUT1P 28 O channel 1 positive PWM output

BOOT1P 29 boot 1 positive bootstrap capacitor

PGND1 30 G channel 1 power ground

VP1[2] 31 P channel 1 power supply voltage

BOOT1N 32 boot 1 negative bootstrap capacitor

OUT1N 33 O channel 1 negative PWM output

VSTAB1 34 decoupling internal stabilizer 1 for DMOST drivers

VDDD 35 decoupling of the internal 5 V logic supply

GNDD/HW 36 G ground digital supply voltage

handle wafer connection

Table 3. Pin description …continued

Symbol Pin Type[1] Description

Product data sheet Rev. 3 — 2 May 2013 6 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

The TDF8599A includes integrated common circuits for all channels such as the oscillator,

all reference so ur ce s, mo d e functionality and a digital timing manager. In addition, the

built-in protec tio n in clu d es ther m al fold b ac k, temperature, overcurrent and overvoltage

(load dump).

The TDF8599A operates in either I2C-bus mode or non-I2C-bus mode. In I2C-bus mode,

DC load detection, frequency hopping and extended configuration functions are provided

together with enhanced diagnostic information.

8.2 Mode selection

The mode pins EN, ADS and SEL_MUTE enable mute state, I2C-bus mode and

Operating mode switching.

Pin SEL_MUTE is used to mute and unmute the device and must be connected to an

external capacitor (CON). This capacitor generates a time constant which is used to

ensure smooth fade-in and fade-out of the input signal.

The TDF8599A is enab led when pin EN is HIGH. Whe n pi n EN is L OW, the TDF85 99A is

off an d the supply current is at it s lowest value (typically 2 A). When of f, the TDF8599A is

completely deactivated and will not react to I2C-bus commands.

I2C-bus mode is selected by connecting a resistor between pin s ADS and AGN D . In

I2C-bus mode with pin EN HIGH, the TDF8599A waits for further commands (see

Table 4). I2C-bus mode is described in Section 9 on page 23.

Non-I2C-bus mode is selected by conne cting pin ADS to pin AGND. In non- I2C-bus mode,

the default TDF8599A state is Mute mode. The amplifiers switch idle (50 % duty cycle)

and the audio signal is suppressed at the output. In addition, the capacitor (CSVRR) is

charged to half the supply voltage. To enter Operating mode, pin SEL_MUTE must be

HGH with S1 open, enabling capacitor (CON) charged by an internal pull-up (see

Figure 3). In addition, pin EN must be driven HIGH.

I2C-bus mode and non-I2C-bus mode control are described in Table 4 on page 7 and

Table 5 on page 7. Switches S1 and S2 are shown in Figure 3.

a. Non-I2C-bus mode b. I2C-bus mode

See Table 13 for detailed information on

RADS.

Fig 3. Mode selection

001aak073

SEL_MUTE

3.3 V

CON

TDF8599A ADS

AGND

001aak074

SEL_MUTE

3.3 V

CON

TDF8599A ADS

RADS

AGND

Product data sheet Rev. 3 — 2 May 2013 7 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

[1] X = do not care.

8.3 Pulse-width modulation frequency

The output signal from the amplifier is a PWM signal with a clock frequency of fosc. This

frequency is set by connecting a resistor (Rosc) between pins OSCSET and AGND. The

optimal clock frequency setting is between 300 kHz and 400 kHz. Conne cting a resistor

with a value of 39 k, for example, sets the clock frequency to 320 kHz (see Figure 5).

The external capacitor (Cosc) has no influence on the oscillator frequency. It does

however, reduce jitter and sensitivity to disturbance. Using a 2nd order LC demodu lation

filter in the application generates an analog audio signal across the lou dspeaker.

8.3.1 Master and slave mode selection

In a master and slave configuration, multiple TDF8599A devices are daisy-chained

together in one audio application with a single device providing the clock frequency signal

for all other devices. In this situation, it is recommended that the oscillators of all devices

are synchronized for optimum EMI behavior as follows:

All OSCIO pins are connected together and one TDF8599A in the application is

configured as the clock-master. All other TDF8599A devices are configured as

clock-slaves (see Figure 5).

•The clock-master pin OSCIO is configured as the oscillator output. When a resistor

(Rosc) is connected between pins OSCSET and AGND, the TDF8599A is in Master

mode.

•The clock-slave pins OSCIO are configured as the oscillator inputs. When pin

OSCSET is directly connec te d to pin AGND (see Table 6), the TDF8599A is in Slave

mode.

Table 4. I2C-bus mode operation

Pin EN Pin SEL_MUTE Bit IB1[D0] Bit IB2[D0] Mode

HIGH (S2 closed) HIGH 1 0 Operating mode

LOW 1 1 Mute mode

LOW 0 X[1] Standby mo de

LOW (S2 open) X[1] X[1] X[1] off (def au l t)

Table 5. Non-I2C-bus mode operation

Pin EN Pin SEL_MUTE Mode

HIGH (S2 closed) HIGH (S1 open) Operating mode

LOW (S1 closed) Mute mode (default)

LOW (S2 open) X[1] off

Table 6. Mode setting pin OSCIO

Mode Settings

Pin OSCSET Pin OSCIO

Master Rosc > 26 koutput

Slave Rosc =0; shorted to pin AGND input

Product data sheet Rev. 3 — 2 May 2013 8 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

The value of the resistor Rosc sets the clock frequency b ased on Equation 1:

(1)

In Master mode, Spread spectrum mode and freq uency hopping can be en abled. In Slave

mode, phase st aggering and phase lock oper ation can be selected. An external clock can

be used as the master-clock on pin OSCIO of the slave devices. When using an external

clock, it must remain active during the shutdown sequence to ensure that all de vices are

switched off and able to enter the off state as described in Section 8.2 on page 6.

In Slave mode, an in ternal watchdog timer on pi n OSCIO is triggered when th e TDF8599A

is switched off by pulling do wn pin EN. If the external clock fails, the watchdog timer fo rces

the TDF8599A to switch off.

8.3.2 Spread spectrum mode (Master mode)

Spread spectrum mode is a technique of modulating the oscillator frequency with a slowly

varying signal to broaden th e switching spectrum, thereby re ducing the spectral density of

the EMI. Connecting a capacitor (CSSM) to pin SSM en ables Spread spectrum mode (see

Figure 6). When pin SSM is connected to pin AGND, Spread spectrum mode is disabled.

Fig 4. Clock frequency as a function of Rosc

Fig 5. Master and slave configuration

fosc 12.45 109



Rosc

----------------------------Hz=

001aai771

fosc (kHz)

300 500450350 400

Rosc

(kΩ)

001aak075

OSCSET

OSCIO

Master

Cosc

osc

Rosc

TDF8599A

OSCSET

OSCIO

Slave 1

TDF8599A

OSCSET

OSCIO

Slave 2

TDF8599A

Product data sheet Rev. 3 — 2 May 2013 9 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

The capacitor on pin SSM (CSSM) sets the spreading frequency when Spread spectrum

mode is active. The current (ISSM) flowing in and out of pin SSM is typically 5 A. This

gives a triangula r voltage on pin SSM that sweeps ar ound the volta ge set by pin OSCSET

5 %. The voltage on pin SSM is used to modulate the oscillator frequency.

The spread spectrum frequency (fSSM) can be calculated using Equation 2:

(2)

where the voltage on pin OSCSET = V1 and is calculated as 100 ARosc (V) with

ISSM =5A.

The frequency swings between 0.95 fosc and 1.05 fosc; see Figure 7.

8.3.3 Frequency hopping (Master mode)

Frequency hopping is a technique used to change the oscillator frequency for AM tuner

compatibility. In Master mode, the resistor connected between pins OSCSET and AGND

sets the oscillator frequency (fosc). In I2C-bus mode, this frequency can be varied by

10 %. Set bit IB1[D4] to logic 1 and bit IB1[D3] to either logic 0 (0.9 fosc) or logic 1

(1.1 fosc).

fSSM ISSM

SSM

V1

10 %

----------------------------------------------------- Hz=

a. Off b. On

Fig 6. Spread spectrum mode

001aai773

100 μA

Rosc

SSM

Cosc

OSCSET

001aai774

100 μA

5 μA

ISSM

Rosc

SSM

Cosc

CSSM

OSCSET

Fig 7. Spread spectrum operation in Master mode

001aai775

t (ms)

OSCIO

max(V)

min(V)

SSM

Product data sheet Rev. 3 — 2 May 2013 10 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

8.3.4 Phase lock operation (Slave mode)

In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect

of the external oscillator signal connected to pin OSCIO. Phase lock operation is also

needed to enable phase staggering, see Section 8.4.2 on page 13. Phase lock operation

is enabled when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and

CPLL_p) and a resistor (RPLL) between pin SSM an d pin AGND (see Figure 8). Connecting

pin SSM to pin AGND disables phase lock operation and causes the slave to directly use

the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on the desired

loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL =8.4BPLL . The

corresponding values for CPLL_s and CPLL_p are given by Equation 3 and Equation 4:

(3)

Remark: CPLL_p is only needed when 1⁄4 phase shift is selected. See Section 8.4.2 for

more detailed information.

(4)

When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,

the PLL loop bandwidth BPLL should be 100 fSSM.

Table 7 lists all oscillator modes.

(1) Only needed when 1⁄4 phase shift is

selected

a. Off b. On

Fig 8. Phase lock operation

Table 7. Oscillator modes

OSCSET pin OSCIO pin SSM pin Oscillato r modes

Rosc > 26 koutput CSSM to pin AGND master, spread spectrum

Rosc > 26 koutput shorted to pin AGND master, no spread spectrum

Rosc =0 input CPLL + RPLL to pin AGND slave, PLL enabled

Rosc =0 input shorted to pin AGND slave, PLL disabled

CPLL_p 0.032

RPLL BPLL



------------------------------ F=

CPLL_s 0.8

RPLL BPLL



------------------------------ F=

001aai776

100 μA

SSM

OSCSET

PLL

001aai777

100 μA

PLL

OSCSET

RPLL CPLL_p(1)

CPLL_s

SSM

Product data sheet Rev. 3 — 2 May 2013 11 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

8.4 Operation mode selection

Pin MOD is used to select specific operating modes. The resistor (RMOD) connected

between pins MOD and AGND together with the non-I2C-bus/I2C-bus mode determin e the

operating mode (see Table 8). The mode of operation depends on whether non-I2C-bus

mode or I2C-bus mode is active. This in turn is determined by the resistor value connected

between pins ADS and AGND.

In non-I2C-bus mode, pin MOD is used to select:

•AD or BD modulation (see Section 8.4.1).

•1⁄2  phase shift when oscillator is used in Slave mode (see Section 8.4.2).

•Parallel mode operation (see Section 8.4.3).

In I2C-bus mode, pin MOD can only select Parallel mode. In addition, the modulation

mode and phase shift are programmed using I2C-bus commands.

[1] RADS  4.7 k; See Table 13 on page 23.

[2] RADS = 0 ; pin ADS is short circuited to pin AGND.

[3] See Section 8.4.3 on page 14 for more detailed information.

In I2C-bus mode, pin M OD is latched using the I2C-bu s command IB3[D7] = 1. This avoids

amplifier switching interference generatin g incorrect information on pin MOD.

In non-I2C-bus mode or when IB3[D7] = 0, the information on pin MOD is latched when

one of the TDF8599A’s outputs starts switching.

8.4.1 Modulation mode

In non-I2C-bus mode, pin MOD is used to select either AD or BD modulation mode (see

Table 8). In I2C-bus mode, the modulation mode is selected using an I2C-bus command.

•AD modulation mode: the bridge halves switch in opposite phase.

•BD modulation mode: the bridge halves switch in phase but the input signal for the

modulators is inverted.

Figure 10 and Figure 11 show simplified representations of AD an d BD modulation.

Table 8. Operation mo de selection with the MOD pin

RMOD (k) I2C-bus mode[1] Non-I2C-bus mode[2]

0 (short to AGND) Stereo mode AD modulation: no phase shift in Slave mode

4.7 BD modulation: no phase shift in Slave mode

13 AD modulation: 1⁄2  phase shift in Slave mode

33 Parallel mode [3] BD modulation: 1⁄2  phase shift in Slave mode

100 AD modulation: no phase shift in Slave mode

 (open) BD modulation: no phase shift in Slave mode

Product data sheet Rev. 3 — 2 May 2013 12 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

Fig 9. AD/BD modulation switching circuit

a. Bridge hal f 1.

b. Bridge half 2 switched in the opposite phase to bridge half 1.

Fig 10. AD modulation

001aai778

+VP

OUTP

INxP INxNOUTN

+VP

001aai779

INxP

OUTxP

001aai780

INxN

OUTxN

Product data sheet Rev. 3 — 2 May 2013 13 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

8.4.2 Phase staggering (Slave mode)

In Slave mode with phase lock operation enabled, a phase shift with respect to the

incoming clock signal can be selected to distribute th e switching moments over time. In

non-I2C-bus mode, 1⁄2  phase shift can be progr ammed using pin MOD. In I2C-bus mode,

five different phase shifts (1⁄4 , 1⁄3 , 1⁄2 , 2⁄3 , 3⁄4 ) can be selected using the I2C-bus

bits (IB3[D1:D3]). See Table 8 for selection of the phase shif t in non-I2C-bus m ode with pin

MOD. An additional capacitor must be connected to pin SSM when 1⁄4  phase shift is

used (see Figure 8). An example of using 1⁄2  phase shift for BD modulation is shown in

Figure 12.

a. Phase switching cycle.

b. Inverted signal to the modulator.

Fig 11. BD modulation

001aai781

INxP

OUTxP

OUTxP - OUTxN

001aai782

INxN

OUTxN

Product data sheet Rev. 3 — 2 May 2013 14 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

8.4.3 Parallel mode

In Parallel mode; the two output stages operate in parallel to enlarge the drive capability.

The inputs and ou tputs for Parallel mode must be connected on the Prin te d-Cir c uit Board

(PCB) as shown in Figure 13. The parallel connection can be made af ter the output filter,

as shown in Figure 13 or directly to the device output pins (OUTxP and OUTxN).

In Parallel mode, the channel 1 I2C-bus bits can be programmed using the I2C-bus.

8.5 Protection

The TDF8599A includes a range of built-in protection functions. How the TDF8599A

manages the various possible fault conditions for e ach protection is described in the

following sections:

Fig 12. Master and slave operation with 1⁄2  phase shift

001aai783

OUT1P phase

OUT1N

OUT2P

OUT2N

OUT1P

OUT1N

OUT2P

master

slave

OUT2N

Fig 13. Parallel mode

001aak077

IN1P

MOD

RMOD

IN2N

IN1N

OUT1N

OUT2N

OUT1P

OUT2P

−

IN2P

TDF8599A

Product data sheet Rev. 3 — 2 May 2013 15 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

8.5.1 Thermal foldback

Thermal Foldback Protection (TFP) is tripped when the average junction temperature

exceeds the threshold level (145 C). TFP decreases amplifier gain such that the

combination of power dissipation and Rth(j-a) create a junction temperature around the

threshold level. The device will not completely switch off but remains operational at the

lower output power levels. If the average junction temperature continues to increase, a

second built-in temperature protection threshold level shuts down the amplifier

completely.

8.5.2 Overtemperature protection

If the average jun ction temper atu r e (Tj) > 160 C, OverTemperature Protection (OTP) is

tripped and the power stage shuts down immediately.

8.5.3 Overcurrent protection

OverCurrent Protection (OCP) is tripped when the output current exceeds the maximum

output current of 8 A. OCP regulates the output voltage such that the maximum output

current is limited to 8 A. The amplifier outputs keep switching and the amplifier is NOT

shutdown completely. This is called current limiting.

OCP also detects when the loudspeaker terminals are short circuited or one of the

amplifier’s demo dulated outputs is shor t circuited to one of the supply lines. In either case,

the shorted channel(s) are switched off.

The amplifier can distinguish between loudspeaker impedance drops and a low-ohmic

short across the load or on e of the supply lines. This impedance threshol d depends on the

supply voltage used. When a short is made across the load causing the impedance to

drop below the threshold level, the shorted channel(s) are switched of f. They try to rest art

every 50 ms. If the short circuit condition is still present after 50 ms, the cycle repeats. The

average power dissipation will be low because of this reduced duty cycle.

When a channel is switched off due to a short circuit on one of the supply lines, Window

Protection (WP) is activated. WP ensures the amplifier does not start-up after 50 ms until

the supply line short circuit is removed.

8.5.4 Window protection

Window Protection (WP) checks the PWM output voltage before switching from Standby

mode to Mute mode (with both outputs switching) and is activated as follows:

Table 9. Overview of protection types

Protection type Reference

Thermal foldback Section 8.5.1

Overtemperature Section 8.5.2

Overcurrent Section 8.5.3

Window Section 8.5.4

DC Offset Section 8.5.5

Undervoltage Section 8.5.6

Overvoltage Section 8.5.6

Product data sheet Rev. 3 — 2 May 2013 16 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

•During the start-up sequence:

–When the TDF8599A is switched from standby to mute (td(stb-mute)) . W hen a sh or t

circuit on one of the output terminals (i.e. between VP or GND) is detected, the

start-up procedure is interrupted and the TDF8599A waits for open circuit outputs.

No large current s flow in the event of a short circuit to the supply lines because the

check is performed before the power stages are enabled.

•During operation:

– A short to one of the supply lines trips OCP causing the amplifier channel to

shutdown. After 50 ms the amplifier channel restarts and WP is activated.

However, the corresponding amplifier channel will not start-up until the supply line

short circuit has been removed.

8.5.5 DC offset protection

DC Protection (DCP) is activated when the DC content in th e demodulate d output volt age

exceeds a set thre sh o ld (ty pica lly 2 V). DCP is active in both Mut e mo d e and Op e ra tin g

mode. Figure 14 shows how false triggering of th e DCP by low frequencies in the audio

signal is prevented using the external capacitor (CF) to generate a cut-off frequency.

In I2C-bus mode, DC offsets generate a voltage shift around the bias voltage. When the

voltage shift exceeds threshold values, the offset alarm bit DB1[D2] is set and if bit

IB1[D7] is not set, diagnostic information is also given. Any detected offset shuts do wn

both channels when bit IB2[D7] is not set. To restart the TDF8599A in I2C-bus mode, pin

EN must be toggled or DCP disabled by connecting pin DCP to pin AGND.

Fig 14. DC offset protection an d di ag nostic output

001aak078

OUT1P

OUT1N

V to I

OUT2P

OUT2N

DCP

DIAG

switch off channels

IB1[D6] IB2[D6]

V to I Vref

DB1[D2]

IB1[D7]

IB2[D7]

50 kΩ

Product data sheet Rev. 3 — 2 May 2013 17 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

In non-I2C-bus mode, when an offset is detected, DCP always gives diagnostic

information on pin DIAG and shuts down both channels.

Connecting a capacitor between pins DCP and AGND enables DC offset protection.

Connecting pin DCP to pin AGND disables DCP in both I2C-bus and non-I2C-bus mode.

8.5.6 Supply voltages

UnderVoltage Pr otection (UVP) is activated when the supp ly voltage dr ops below the UVP

threshold. UVP triggers the UVP circuit causing the system to fir st mute and then stop

switching. When the supply voltage rises above the threshold level, the system restarts.

OverVoltage Protection (OVP) is activated when the supply voltage exce eds the OVP

threshold. The OVP (or load dump) circuit is activated and the power stages are

shutdown.

An overview of all protection circuits and the amplifier states is given in Table 10.

8.5.7 Overview of protection circuits and amplifier states

[1] When fault is removed.

[2] Amplifier gain depends on the junction temperature and size of the heat sink.

[3] TFP influences restart timing depending on heat sink size.

[4] Shorted load causes a restart of the channel every 50 ms.

[5] Latched protection is reset by toggling pin EN or by disabling DCP in I2C-bus mode.

[6] In I2C-bus mode deep supply voltage drops will cause a Power-On Reset (POR). The restart requires an

I2C-bus command.

8.6 Diagnostic output

8.6.1 Diagnostic table

The diagnostic infor mation for I 2C-bus mo de and non-I 2C-bus mode is shown in Table 11.

The instruction bitmap and data bytes are described in Table 14 and Table 15.

Pins DIAG and CLIP have an open-drain output which must have an external pull-up

resistor connected to an external voltage. Pins CLIP and DIAG can show both fixed and

I2C-bus selectable information.

Table 10. Overview of TDF8599A protection circuits and amplifier states

Protection circuit name Amplifier state

Complete

shutdown Channel

shutdown Restart[1]

TFP N[2] N[2] Y[3]

OTP Y N Y[3]

OCP N Y Y[4]

WP N Y Y

DCP Y N N[5]

UVP Y N Y[6]

OVP Y N Y

Product data sheet Rev. 3 — 2 May 2013 18 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

Pin DIAG goes LOW when a short circuit to one of the amplifier outputs occurs. The

microprocessor reads the failure information using the I2C-bus. The I2C-bus bits are set

for a short circuit. These bits can be reset with the I2C-bus read command.

Even after the short has been removed, the microprocessor knows what was wrong after

reading the I2C-bus. Old information is read when a single I2C-bus read command is

used. To read the current information, two read commands must be sent, one after

another.

When selected, pin DIAG gives the current diagnostic information. Pin DIAG is released

instantly when the failure is removed, independent of the I2C-bus latches.

When OCP is triggered, the open-drain DIAG output is activated. The diagnostic output

signal during different short circuit conditions is illustrated in Figure 15.

8.6.2 Load identification (I2C-bus mode only)

8.6.2.1 DC lo ad de te c tio n

DC load detection is only available in I2C-bus mode and is controlled using bit IB2[D2].

The default setting is logic 0 for bit IB2[D2] which disables DC load detection. DC load

detection is enabled when bit IB2[D2] = 1. Load detection takes place before the class-D

amplifier output stage starts switching in Mute mode and the start-up time from Standby

mode to Mute mod e is increa se d by tdet(DCload) (see Figure 16).

Table 11. Available data on pins DIAG and CLIP

Diagnostic I2C-bus mode Non-I2C-bus mode

Pin DIAG Pin CLIP Pin DIAG Pin CLIP

Power-on reset yes yes yes yes

UVP or OVP yes no yes no

Clip detection no sele ctable no yes

Temper ature pre-warning no selectable no yes

OCP/WP yes no yes no

DCP selectable no yes no

OTP yes no yes no

Fig 15. Diagnostic ou tput for short circuit conditions

001aai786

AMPLIFIER

RESTART

shorted load

pull up V

AGND = 0 V

≈50 ms ≈50 ms≈50 ms

RESTART

short to GND or VP line

Product data sheet Rev. 3 — 2 May 2013 19 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

The capacitor connected to pin SEL_MUTE (see Figure 3 on page 6) is used to create an

inaudible current test pulse, drawn from the positive amplifier output. The diagnostic

‘speaker load’ (or ‘open load’), based on the voltage difference between pins OUTxP and

OUTxN is shown in Figure 18.

Remark: DC load detection identifies a short circuited speaker as a valid speaker load.

OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,

performs diagnostics on shorted loads. However, the diagnostics are performed after the

DC load detection cycle has finished and once the amplifier is in Operating mode.

The result of the DC load detection is stored in bits DB1[D4] and DB2[D4].

Fig 16. DC load detection circuit

Fig 17. DC load detection procedure

Fig 18. DC load detection limits

001aai787

PWM

CONTROL

DRIVER

HIGH

PGND1

OUTN

OUTP

DRIVER

LOW

PWM

CONTROL

DRIVER

HIGH

PGND2

DRIVER

LOW

001aai788

out (V)

det(DCload)

d(stb-mute)

t (s)

out−

out+

001aaj956

0 Ω25 Ω350 Ω

SPEAKER LOAD OPEN LOAD

Product data sheet Rev. 3 — 2 May 2013 20 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

Remark: After DC load detection has be en performed, the DC load vali d bit DB1[D6] must

be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load

detection is interrupted by a sudden large change in supply voltage (triggered by UVP or

OVP) or if the amplifier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC

load detection enable bit IB2[D2] must be reset after the DC load protection cycle to

release any amplifier hang-up. Once the DC load detection cycle has finished, DC load

detection can be rest arted by to ggling the DC load detection enable bit IB2[D2]. However,

this can only be used if both amplifier chan nel s ha ve not be en enab led with bit IB1 [D1] or

bit IB2[D1]. See Section 8.6.2.2 “Recommended start-up sequence with DC load

detection enabled” for detailed information.

8.6.2.2 Recommended start-up sequence with DC load detection enabled

The flow diagram (Figure 19) illustrates the TDF8599A’s ability to perform a DC load

detection without starting the amplifiers. After a DC load detection cycle finishes without

setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is

toggled).

To limit the maximum number of DC load detection cycle loops, a counter and limit have

been added. The loop exits after the predefined number of cycles (COUNTMAX), if the

DC load detection cycle finishes with an invalid detection.

Depending on the application needs, the invalid DC load detection cycle can be handled

as follows:

•the amplifier can be started without DC load detection

•the DC load detection loop can be executed again

Table 12. Interpretation of DC load detection bits

DC load bits DB1[D4] and DB2[D4] OCP bits DB1[D3] and DB2[D3] Description

0 0 speaker load

0 1 shorte d lo a d

1 0 open load

Product data sheet Rev. 3 — 2 May 2013 21 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

8.6.2.3 AC lo ad de te c tio n

AC load detection is only available in I2C-bus mode and is controlled using bit IB3[D4].

The default setting for bit IB3[D4] = 0 disables AC load detection. Whe n AC load detection

is enabled (bit IB3[D4] = 1), the amplifier load current is measured and compar ed with a

reference level. Pin CLIP is activated when this threshold is reached. Using this

information, AC load detection can be performed using a predetermined input signal

frequency and level. The frequency and signal level should be chosen so that the load

current exceeds the program med current threshold when the AC coupled load (tweeter ) is

present.

8.6.2.4 CLIP detection

CLIP detection gives information for clip levels 0.2 %. Pin CLIP is used as the output for

the clip detection circuitr y on both channel 1 and channel 2. Setting either bit IB1[D5] or bit

IB2[D5] to logic 0 defines which channel reports clip information on the CLIP pin.

Fig 19. Recommended start-up sequence with DC load detection enabled

001aaj061

YES

restart

DC load

start amplifier

anyway

C-bus TX

IB1[D0] = 1 startup

IB2[D2] = 1 enable DC load

IB1[D1] = 1 disable channel 1

IB2[D1] = 1 disable channel 2

C-bus RX

DB1[D4] = 1 channel 1 open load

DB2[D4] = 1 channel 2 open load

DB1[D6] = 1 DC load valid

C-bus TX

IB1[D0] = 1 startup

IB2[D2] = 0 disable DC load

IB1[D1] = 0 enable channel 1

IB2[D1] = 0 enable channel 2

C-bus TX

IB1[D0] = 1 startup

IB2[D2] = 0 disable DC load

IB1[D1] = 1 disable channel 1

IB2[D1] = 1 disable channel 2

C-bus TX

IB1[D0] = 1 startup

IB2[D2] = 1 enable DC load

IB1[D1] = 1 disable channel 1

IB2[D1] = 1 disable channel 2

ERROR HANDLING

COUNT = 0

WAIT DC load

COUNT = COUNT + 1

DB1[D6] = 1

DC load valid

COUNT ≤ COUNTMAX

Product data sheet Rev. 3 — 2 May 2013 22 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

8.6.3 Start-up and shutdown sequence

To prevent switch on or switch off ‘pop noises’, a capacitor (CSVRR) connected to pin

SVRR is used to smooth st art-up and shut down. During st art-up and shut down, the outp ut

voltage tr acks the voltage on pin SVRR. Increasing CSVRR results in a lo nger start-up and

shutdown time. Enhanced pop noise performan ce is achieved by muting the amplifier until

the SVRR voltage reaches its final value and the outputs start switching. The capacitor

value on pin SEL_MUTE (CON) determ ines the unmute and mute timing. The voltage on

pin SEL_MUTE determines the amplifier gain. Increasing CON increases the unmute and

mute times. In addition, a larger CON value increases the DC load detection cycle.

When the amplifier is switched off with an I2C-bus command or by pulling pin EN LOW,

the amplifier is first muted and then capacitor (CSVRR) is discharged.

In Slave mode, the device enters the off state immediately after capacitor (CSVRR) is

discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of

approximately 50 ms to allow slave devices to enter the off state.

When an external clock is connected to pin OSCIO (in Slave mode), the clock must

remain active during the shutdown sequence for delay (td(1)) to ensure that the slaved

TDF8599A device s ar e ab le to ent er the off state.

(1) Shutdown hold delay.

(2) Master mode shutdown delay.

(3) Shutdown delay.

Fig 20. Start-up and shutdown timing in I2C-bus mode with DC load detection

001aai790

VDDA

DIAG

ACGND

IB1[D0] and

IB2[D0] = 0

SEL_MUTE

SVRR

OUTn

td(2)

td(1)

td(mute-fgain) mute delay

td(stb-mute)

twake tdet(DCload)

td(3)

Product data sheet Rev. 3 — 2 May 2013 23 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

9. I2C-bus specification

TDF8599A address with hardware address select.

[1] Required external resistor accuracy is 1 %.

[2] Short circuited to ground.

In I2C-bus mode, pins MOD and ADS can be latched using the I2C-bus command

IB3[D7] = 1. This avoids disturbances from amplifier outputs of other TDF8599A devices

in the same application switching and generating incorrect inform ation on the MOD and

ADS pins.

(1) Shutdown hold delay.

(2) Shutdown delay.

(3) Master mode shutdown delay.

Fig 21. Start-up and shutdown timing in non-I2C-bus mode

001aai791

DDA

DIAG

d(2)

d(1)

d(3)

d(stb-mute)

ACGND

SEL_MUTE

SVRR

OUTn

d(mute-fgain)

Table 13. I2C-bus write addres s se le c tion using pins MOD and ADS

RADS[1] (k) RMOD[1] (k) R/W

Stereo mode Parallel mode

0[2] 4.7 13 33 100 open

Open 58h 68h 7 8h 58h 68h 78h 1 = Read from TDF8599A

0 = Write to TDF8599A

100 56h 66h 76h 56h 66h 76h

33 54h 64h 74h 54h 64h 74h

13 52h 62h 72h 52h 62h 72h

4.7 50h 60h 70h 50h 60h 70h

0[2] non-I2C-bus mode select

Product data sheet Rev. 3 — 2 May 2013 24 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

In non-I2C mode or when IB3[D7] = 0, the informatio n on the MOD and ADS pins is

latched when one of the TDF8599A’s outputs starts switching.

(1) When SCL is HIGH, SDA changes to form the start or

stop condition. (1) SDA is allowed to change.

(2) All data bits must be valid on the positive edges of SCL.

Fig 22. I2C-bus start and stop conditions Fig 23. Data bits sent from Master microproc ess or

(Mp)

STOPSTART

001aai792

SCL

SDA

Mμp

SLAVE (1)

SCL

SDA

001aai793

(2)

(1)

Mμp

SLAVE

(1) To stop the transfer after the last acknowledge a stop condition must be generated.

Fig 24. I2C-bus write

001aai794

LSB + 1 LSB + 1 LSBMSB − 1MSB MSB − 1MSBACK ACK

ACK(1)

ACK

STOPWRITE DATAWRITESTART ADDRESS

12 789 78912

SCL

SDA

Mμp

SLAVE

(1) To stop the transfer, the last byte must not be acknowledged (SDA is HIGH) and a stop condition must be generated.

Fig 25. I2C-bus read

001aai795

LSB + 1 LSB + 1 LSBMSB − 1MSB MSB − 1MSBACK

ACK(1)

ACKNOWLEDGE

STOP

READ DATA

READSTART ADDRESS

12 789 78912

SCL

SDA

Mμp

SLAVE

Product data sheet Rev. 3 — 2 May 2013 25 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

9.1 Instruc tion bytes

If R/W bit = 0, the TDF8599A expects three instruction bytes: IB1, IB2 and IB3. After a

power-on reset, all unspecified instruction bits must be set to zero.

[1] See Section 8.3.3 on page 9 for information on IB1[D4] and IB1[D3].

[2] See Table 15 “Phase shift bit settings” for information on IB3[D3] to IB3[D1].

[3] See Table 4 for information on IB1[D0] and IB2[D0].

Table 14. Instr uction byte descriptions

Bit Value Description

Instruction byte IB1 Instruction byte IB2 Instruction byte IB3

D7 0 offset detection on pin DIAG offset protection on latch information on pins ADS

and MOD when the amplifier

starts switching

1 no offset detection on pin DIAG offset protection off latch information on pins ADS

and MOD; see Section 9 on

page 23

D6 0 channel 1 offset monitoring on channel 2 offset monitoring on -

1 channel 1 offset monitoring off channel 2 offset monitoring off -

D5 0 channel 1 clip detect on pin CLIP channel 2 clip detect on pin CLIP -

1 channel 1 no clip detect on pin CLIP channel 2 no clip detect on pin CLIP -

D4 0 disab le frequency hopping thermal pre-warning on pin CLIP disable AC load detection

1 enable frequency hopping[1] no thermal pre warning on pin CLIP enable AC load detection

D3 0 oscill ator frequency as set with

Rosc 10 % temperature pre-warning at 140 C oscillator phase shift bits

IB3[D3] to IB3[D1][2]

1 oscillator frequency as set with

Rosc +10% temperature pre-warn ing at 120 C

D2 0 - DC-load detection disabled

1 - DC-load detection enabled

D1 0 channel 1 enabled channel 2 enabled

1 channel 1 disabled channel 2 disabled

D0 0 TDF 8599A in Standby mode all channels operating AD modulation

1 TDF8599A in Mute or Operating

modes[3] all channels muted BD modulation

Table 15. Phase shift bit settings

D3 D2 D1 Phase

0000

0011⁄4

0101⁄3

0111⁄2

1002⁄3

1013⁄4

Product data sheet Rev. 3 — 2 May 2013 26 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

9.2 Data bytes

If R/W = 1, the TDF8599A sends two dat a bytes to the microproce ssor (DB1 and DB2). All

short diagnos tic an d offset protectio n bits are latche d . In ad dit i on , all bits are reset after a

read operation except the DC load detection bits (DBx[D4], DB1[D6]). The default setting

for all bits is logic 0.

In Parallel mode, the diagnostic information is stored in byte DB1.

Data byte DB1[D7] indicates whether the instruction bits have been set to logic 0. In

principle, DB1[D7] is set after a POR or when all the instruction bits are programmed to

logic 0. Pin DIAG is driven HIGH when bit DB1[D7] = 1.

Table 16. Description of data bytes

Bit Value DB1 channel 1 DB2 channel 2

D7 0 at least 1 instruction bit set to logic 1 below maximum temperature

1 all instruction bits are set to logic 0 maximum temperature protection

activated

D6 0 invalid DC load data no temperature warning

1 valid DC load data temperature pre-warning active

D5 0 no overvoltage no undervoltage

1 overvoltage protection active undervoltage protection active

D4 0 speaker load channel 1 speaker load channel 2

1 open load channel 1 open load channel 2

D3 0 no shorted load channel 1 no shorted load channel 2

1 shorted load channel 1 shorted load channel 2

D2 0 no offset reserved

1 offset detected reserved

D1 0 no short to VP channel 1 no short to VP channel 2

1 short to VP channel 1 short to VP channel 2

D0 0 no short to ground channel 1 no short to ground channel 2

1 short to ground channel 1 short to ground channel 2

Product data sheet Rev. 3 — 2 May 2013 27 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

10. Limiting values

[1] Floating condition assumed for outputs.

[2] Current limiting concept.

[3] Human Body Model (HBM).

[4] Charged-Device Model (CDM).

[5] The output pins are defined as the output pins of the filter connected between the TDF 8599A output pins

and the load.

Table 17. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VPsupply voltage Operating mode - 40 V

off st ate [1] 1+50V

load dump; duration

50 ms; tr > 2.5 ms -50V

IORM repetitive peak output

current maximum output current

limiting [2] 8- A

IOM peak output current maximum; non-repetitive

stereo mode - 18 A

parallel mode - 12 A

Viinput voltage pins SCL, SDA, ADS,

MOD, SSM, OSCIO, EN

and SEL_MUTE

05.5V

pins IN1N, IN1P, IN2N

and IN2P 010V

Vooutput voltage pins DIAG and CLIP 0 10 V

RESR equivalent series resistance as seen between pins VP

and PGNDn -350m

Tjjunction temperature - 150 C

Tstg storage temperature 55 +150 C

Tamb ambient temperature 40 +85 C

VESD electrostatic discharge

voltage HBM [3]

C = 100 pF;

Rs=1.5k- 2000 V

CDM [4]

non-corner pins - 500 V

corner pins - 750 V

V(prot) protection voltage AC and DC short circuit

voltage of output pins

across load and to

supply and ground

[5] 0V

Product data sheet Rev. 3 — 2 May 2013 28 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

11. Thermal characteristics

12. Static characteristics

Table 18. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambien t in free air 35 K/W

Rth(j-c) thermal resistance from junction to case 1 K/W

Table 19. Static characteristics

VP=V

DDA = 14.4 V; fosc = 320 kHz;





C < Tamb < +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply

VPsupply voltage 8 14.4 35 V

IPsupply current off state; Tj  85 C; VP= 14.4 V - 2 10 A

Iq(tot) total quiescent current Operating mode; no load,

snubbers and filter connected -90120mA

Series resistance output switches

RDSon drain-source on-state

resistance power switch;

Tj=25C-170180m

Tj= 100 C-235250m

I2C-bus interface: pins SCL and SDA

VIL LOW-level input voltage 0 - 1.5 V

VIH HIGH-level input voltage 2.3 - 5.5 V

VOL LOW-level output voltage pin SDA; Iload =5mA 0 - 0.4 V

Address, phase shift and modulation mode select: pins ADS and MOD

Viinput voltage pins not connected [1] 1.5 2 2.7 V

Iiinput current pins shorted to GND [1] 80 105 160 A

Enable and SEL_MUTE input: pins EN and SEL_MUTE

Viinput voltage pin EN; off st at e 0 - 0.8 V

pin EN; Standby mode; I2C-bus

mode 2- 5V

pin EN; Mute mode or Operating

mode; non-I2C-bus mode 2- 5V

pin SEL_MUTE; Mute mode;

voltage on pin EN > 2 V 0- 0.8V

pin SEL_MUTE; Operating mode;

voltage on pin EN > 2 V 3- 5V

Iiinput current pin EN; 2.5 V - - 5 A

pin SEL_MUTE; Operating mode;

0.8 V --50A

Product data sheet Rev. 3 — 2 May 2013 29 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

Diagnostic output

THDclip total harmonic distortion clip

detection level -0.2-%

Vth(offset) threshold voltage for offset

detection [2][3] 123V

VOL LOW-level output voltage DIAG or CLIP pins activated;

Io=1mA --0.3V

ILleakage current DIAG and CLIP pins; diagnostic

not activated --50A

Audio inputs; pins IN1N, IN1P, IN2N and IN2P

Viinput voltage - 2.45 - V

SVRR voltage and ACGND input bias voltage in Mute and Operating modes

Vref reference voltage input ACGND pin 2 2.45 3 V

half supply reference SVRR pin 6.9 7.2 7.5 V

Amplifier outputs; pins OUT1N, OUT1P, OUT2N and OUT2P

VO(offset) output offset voltage BTL; Mute mode - - 25 mV

BTL; Operating mode [4][6] --70mV

Stabilizer output; pins VSTAB1 and VSTAB2

Vooutput voltage stabilizer output in Mute mode and

Operating mode 8 1012V

Voltage protections

V(prot) protection voltage undervoltage; amplifier is muted 6.8 7.2 8 V

overvoltage; load dump protection

is activated 37 38 - V

VP that a POR occurs at 3 3.7 4.6 V

Current protection

IO(ocp) overcurrent protection output

current current limiting concept 8 9.5 11 A

Temperature protection

Tprot protectio n te mp erature 155 - 160 C

Tact(th_fold) thermal foldback activation

temperature gain = 1 dB 140 - 150 C

Tj(AV)(warn1) average junction temperature

for pre-warni ng 1 IB2[D3] = 0; non-I2C-bus mode - 140 150 C

Tj(AV)(warn2) average junction temperature

for pre-warni ng 2 IB2[D3] = 1 - 120 130 C

DC load detection levels: I2C-bus mode only[7]

Zth(load) load detection threshold

impedance for normal speaker loa d;

DB1[D4] = 0; DB2[D4] = 0 --25

Zth(open) open load detection threshold

impedance DB1[D4] = 1; DB2[D4] = 1 350 - - 

AC load detection levels: I2C-bus mode only

Ith(o)det(load)AC AC load detection outpu t

threshold current 250 500 700 mA

Table 19. Static characteristics …continued

VP=V

DDA = 14.4 V; fosc = 320 kHz;





C < Tamb < +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 3 — 2 May 2013 30 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

[1] Required resistor accuracy for pins ADS and MOD is 1 %; see Section 9 on page 23.

[2] Maximum leakage current from DCP pin to ground = 3 A.

[3] The output offset values can be either positive or negative. The Vth(offset) limit values (excluding Typ) are the valid absolute values.

[4] DC output offset voltage is applied to the output gradually during the transition between Mute mode and Operating mode.

[5] I2C-bus mode only.

[6] The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin.

[7] The DC load valid bit DB1[D6] must be used; Section 8.6.2.1 on page 18. The DC load enable bit IB2[D2] must be reset after each load

detection cycle to prevent amplifier hang-up incidents.

Start-up/shut-down/mute timing

twake wake-up time on pin EN before first I2C-bus

transmission is recogn ized [5] --500s

tdet(DCload) DC load detection time CON =470nF [5] -380-ms

td(stb-mute) delay time from standby to

mute measured from amplifier enabling

to start of unmute (no DC load

detection); CSVRR =47F

CON =470nF

-140-ms

td(mute-fgain) mute to full gain delay time CON =470nF [6] -15-ms

tddelay time shutdown delay time from EN pin

LOW to SVRR LOW; voltage on

pin SVRR < 0.1 V; CSVRR =47F

200 350 550 ms

shutdown delay time from EN pin

LOW to SVRR LOW; voltage on

pin SVRR < 0.1 V; CSVRR =47F;

VP=35V

300 400 700 ms

shutdown hold delay time from pin

EN LOW to ACGND LOW; voltage

on pin ACGND < 0.1 V; Master

mode

-370-ms

hold delay in Master mode to allow

slaved devices to shutdown

fosc = 320 kHz

-50-ms

Speaker load impedance

RLload resistance at supply voltage equal to or below

25 V

stereo mode 1.6 4 - 

parallel mode 0.8 - - 

at supply voltage equal to or below

35 V

stereo mode 3.2 4 - 

parallel mode 1.6 - - 

Table 19. Static characteristics …continued

VP=V

DDA = 14.4 V; fosc = 320 kHz;





C < Tamb < +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 3 — 2 May 2013 31 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

12.1 Switching characteristics

Table 20. Switching characteristics

VP=V

DDA = 14.4 V;





C < Tamb < +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Internal oscillator

fosc oscillator frequency external clock frequency;

Rosc =39k-320 -kHz

internal fixed frequency and Spread

spectrum mode frequency based on

the resistor value connected to pin

OSCSET for the master setting

300 - 450 kHz

Master/slave setting (OSCIO pin)

Rosc oscillator resistance resistor value on pin OSCSET;

master setting 26 39 49 k

VOL LOW-level output voltage output - - 0.8 V

VOH HIGH-level output voltage output 4 - - V

VIL LOW-level input voltage input - - 0.8 V

VIH HIGH-level input voltage input 4 - - V

ftrack tracking fre quency PLL enabled 300 - 500 kHz

Nslave number of slaves driven by one master 12 - -

Spread spectrum mode setting

fosc oscillator frequency variation between maximum and minimum

values; Spread spectrum mode

activated

-10 -%

fsw switching frequency Spread spectrum mode activated;

CSSM =1F-7 -Hz

Frequency hopping

fosc(int) internal oscillator frequency change positive; IB1[D4] = 1;

IB1[D3] = 1 -f

osc +10% - kHz

change negative; IB1[D4] = 1;

IB1[D3] = 0 -f

osc 10 % - kHz

Timing

trrise time PWM output; Io=0A - 10 - ns

tffall time PWM output; Io=0A - 10 - ns

tw(min) minimum pulse width Io=0A - 80 - ns

Product data sheet Rev. 3 — 2 May 2013 32 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

13. Dynamic characteristics

[1] Rs(L) is the sum of the inductor series resistance from the low-pass LC filter in the application together with all resistance from PCB

traces or wiring between the output pin of the TDF8599A and the inductor to the measurement point. LC filter dimensioning is

L=10H, C = 1 F for 4  load and L = 5 H, C = 2.2 F for 2  load.

[2] Output power is measured indirectly based on RDSon measurement.

Table 21. Dy namic characteristics

VP=V

DDA = 14.4 V; RL=4



; fi= 1 kHz; fosc = 320 kHz; Rs(L) < 0.04



[1];





C < Tamb < +85



C; Stereo mode; unless

otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Pooutput power Stereo mode: [2]

VP=14.4V; THD=1%; R

L=418 20 - W

VP= 14.4 V; THD = 10 %; RL=423 25 - W

square wave (EIAJ); RL=4-40-W

VP= 35 V; THD = 10 %; RL=4-135-W

VP=14.4V; THD=1%; R

L=226 29 - W

VP= 14.4 V; THD = 10 %; RL=234 38 - W

square wave (EIAJ); RL=2-60-W

Parallel mode: [2]

VP= 14.4 V; THD = 10 %; RL=2-50-W

VP= 35 V; THD = 10 %; RL=2-250-W

VP=25V; THD=1%; R

L=1135 150 - W

THD total harmonic distor ti on fi= 1 kHz; Po=1 W [3] - 0.02 0.1 %

fi=10kHz; P

o=1 W [3] - 0.02 0.1 %

Gv(cl) closed-loop voltage gain 25 26 27 dB

cs channel separation fi= 1 kHz; Po=1 W - 70 - dB

SVRR supply voltage rejection ra tio Operatin g mode

fripple =100Hz [4] 60 70 - dB

fripple = 1 kHz [4] 60 70 - dB

Mute mode

fripple = 1 kHz [4] 60 70 - dB

off state and Standby mode

fripple = 1 kHz [4] -90-dB

Zi(dif)differential input impedance 60 100 150 k

Vn(o) output noise voltage Operating mode

BD mode [5] -6077V

AD mode [5] -100140V

Mute mode

BD mode [6] -2532V

AD mode [6] -85110V

bal(ch) channel balance - 0 1 dB

mute mute attenuation [7] 66 - - dB

CMRR common mode rejection ratio Vi(cm) =1 V RMS 65 80 - dB

po output power efficiency Po=20 W - 90 - %

Product data sheet Rev. 3 — 2 May 2013 33 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

[3] Total harmonic distortion is measured at the bandwidth of 22 Hz to 20 kHz, AES brick wall. The maximum limit is guaranteed but may

not be 100 % tested.

[4] Vripple =V

ripple(max) = 2 V (p-p); Rs=0 .

[5] B = 22 Hz to 20 kHz, AES brick wall, Rs=0 .

[6] B = 22 Hz to 20 kHz, AES brick wall, independent of Rs.

[7] Vi=V

i(max) = 0.5 V RMS.

14. Application information

14.1 Output power estimation (Stereo mode)

The output power, just before clipping, can be estimated using Equation 5:

(5)

Where,

•VP= supply voltage (V)

•RL= load impedance ()

•RDSon = drain source on-st ate resistance ()

•Rs= series resistance of the output inductor ()

•tw(min) = minimum pulse width(s) depending on output current (s)

•fosc = oscillator frequency in Hz (typically 320 kHz)

The output power at 10 % THD can be estimated by: where

Po(1) = 0.5 % and Po(2) =10%.

Figure 26 and Figure 27 show the estimated output power at THD = 0.5 % and

THD = 10 % as a function of supply voltage for different load impedances in stereo mode.

RL2R

DSon Rs

++

-----------------------------------------------------





wmin

fosc

--------

–







2









------------------------------------------------------------------------------------------------------------------------------------- W=

Po2 1.25 Po1

=

Product data sheet Rev. 3 — 2 May 2013 34 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

14.2 Output power estimation (Parallel mode)

Figure 28 and Figure 29 show the estimated output power at THD = 0.5 % and

THD = 10 % as a function of the supply voltage for different load impedances in parallel

mode.

THD = 0.5 %.

RDSon =0.2 (at Tj= 100 C), Rs=0.05,

tw(min) = 190 ns and IO(ocp) = 8 A (minimum).

(1) RL=2.

(2) RL=4.

THD = 10 %.

RDSon =0.2 (at Tj= 100 C), Rs=0.05,

tw(min) = 190 ns and IO(ocp) = 8 A (minimum).

(1) RL=2.

(2) RL=4.

Fig 26. Po as a function of VP in stereo mode wi th

THD = 0.5 % Fig 27. Po as a function of VP in stereo mode with

THD = 10 %

VP (V)

840322416

(1)

(2)

001aaj181

100

140

120

(W)

VP (V)

840322416

(1)

(2)

001aaj182

120

160

(W)

Product data sheet Rev. 3 — 2 May 2013 35 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

14.3 Output current limiting

The peak output cu rrent is internally limited to 8 A maximum. During normal operation, the

output current should not exceed this threshold level otherwise the output signal will be

distorted. The peak output curr ent can be estimated using Equation 6:

(6)

•Io= outpu t current (A)

•VP= supply voltage (V)

•RL= load impedance ()

•RDSon = on-resistance of power switch ()

•Rs= series resistance of output inductor ()

Example: A 2  speaker can be used with a supply voltage of 19 V before current limiting

is triggered.

Current limiting (clipping) avoids audio holes but can cause distortion similar to voltage

clipping. In Parallel mode, the output current is internally limited above 16 A.

THD = 0.5 %.

RDSon =0.1 (at Tj= 100 C), Rs= 0.025 ,

tw(min) = 190 ns and IO(ocp) = 16 A (minimum).

(1) RL=1.

(2) RL=2.

(3) RL=4.

THD = 10 %.

RDSon =0.1 (at Tj= 100 C), Rs= 0.025 ,

tw(min) = 190 ns and IO(ocp) = 16 A (minimum).

(1) RL=1.

(2) RL=2.

(3) RL=4.

Fig 28. Po as a function of VP in parallel mode with

THD = 0.5 % Fig 29. Po as a function of VP parallel mode with

THD = 10 %

VP (V)

840322416

(1)

(2)

(3)

001aaj183

150

100

200

250

(W)

VP (V)

840322416

(1)

(2)

(3)

001aaj184

100

200

300

150

250

(W)

IoVP

RL2+RDSon Rs

+

----------------------------------------------------- 8 [A]

Product data sheet Rev. 3 — 2 May 2013 36 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

14.4 Speaker configuration and impedance

A flat-frequency response (due to a 2nd order Butterworth filter) is obtained by changing

the low-pass filter components (LLC, CLC) based on the speaker configuration and

impedance. Table 22 shows the required values.

Remark: When using a 1  load impedance in Parallel mo de , th e ou tp uts are shorte d

after the low-pass filter switches two 2  filters in parallel.

14.5 Heat sink requirements

In most applications, it is necessary to connect an external heat sink to the TDF8599A.

Thermal foldback activates at Tj=140 C. The expression below shows the relationship

between the maximum power dissipation before activation of thermal foldback and the

total thermal resistance from junction to ambient:

(7)

Pmax is determined by the efficiency () of the TDF8599A. The efficiency measured as a

function of output power is given in Figure 43. The power dissipation can be derived as a

function of outp u t pow er (see Figure 42).

Example 1:

•VP=14.4V

•Po=225 W into 4  (THD = 10 % continuous)

•Tj(max) = 140 C

•Tamb = 25 C

•Pmax = 5.8 W (from Figure 42)

•The required Rth(j-a) =115 C / 5.8W=19K/W

The total thermal resistance Rth(j-a) consists of: Rth(j-c) + Rth(c-h) + Rth(h-a)

Where:

•Thermal resistance from junction to case (Rth(j-c)) = 1 K/W

•Thermal resist ance from case to heat sink (Rth(c-h)) = 0.5 K/W to 1 K/W (depending on

mounting)

•Thermal resistance from he at sink to am b ien t (R th(h-a)) would then be

19 (1 + 1) = 17 K/W.

If an audio signal has a crest factor of 10 (the ratio between peak power and average

power = 10 dB) then Tj will be much lower.

Table 22. Filter component values

Load impedance () LLC (H) CLC (F)

12.54.4

252.2

4101

Rth j-a

Tjmax

Tamb

–

Pmax

-----------------------------------K/W=

Product data sheet Rev. 3 — 2 May 2013 37 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

Example 2:

•VP=14.4V

•Po=2(25 W / 10) = 2  2.5 W into 4  (audio with crest factor of 10)

•Tamb = 25 C

•Pmax =2.5W

•Rth(j-a) =19K/W

•Tj(max) = 25 C + (2.5 W  19 K/W) = 72 C

14.6 Curves measured in reference design

(1) VP= 14.4 V; RL=2 at 100 Hz.

(2) VP= 14.4 V; RL=2 at 1 kHz.

(3) VP= 14.4 V, RL=2 at 6 kHz.

(1) VP= 14.4 V; RL=4 at 100 Hz.

(2) VP= 14.4 V; RL=4 at 1 kHz.

(3) VP= 14.4 V, RL=4 at 6 kHz.

Fig 30. THD + N as a function of output power with a

2 load; VP = 14.4 V Fig 31. THD + N as a function of output power with a

4 load; VP = 14.4 V

001aaj185

Po (W)

10−1102

101

10−1

10−2

102

THD + N

(%)

10−3

(1)

(2)

(3)

001aaj186

Po (W)

10−1102

101

10−1

10−2

102

THD + N

(%)

10−3

(1)

(2)

(3)

Product data sheet Rev. 3 — 2 May 2013 38 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

(1) VP=35V; R

L=2 at 100 Hz.

(2) VP=35V; R

L=2 at 1 kHz.

(3) VP=35V, R

L=2 at 6 kHz.

(1) VP=35V; R

L=4 at 100 Hz.

(2) VP=35V; R

L=4 at 1 kHz.

(3) VP=35V, R

L=4 at 6 kHz.

Fig 32. THD + N as a function of output power with a

2 load; VP = 35 V Fig 33. THD + N as a function of output power with a

4 load; VP = 35 V

(1) VP= 14.4 V; RL=2 at 1 W.

(2) VP= 14.4 V; RL=2 at 10 W. (1) VP= 14.4 V; RL=4 at 1 W.

(2) VP= 14.4 V; RL=4 at 10 W.

Fig 34. THD + N as a function of frequency with a 2 

load, BD modulatio n; VP = 14.4 V Fig 35. THD + N as a function of frequency with a 4 

load, BD modulation; VP = 14.4 V

001aaj187

10−1

10−2

102

THD + N

(%)

10−3

Po (W)

10−1103

102

110

(1)

(2)

(3)

001aaj188

10−1

10−2

102

THD + N

(%)

10−3

Po (W)

10−1103

102

110

(1)

(2)

(3)

001aaj190

10−1

10−2

THD + N

(%)

10−3

f (Hz)

10 105

104

102103

(1)

(2)

001aaj189

10−1

10−2

THD + N

(%)

10−3

f (Hz)

10 105

104

102103

(1)

(2)

Product data sheet Rev. 3 — 2 May 2013 39 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

(1) VP=35V; R

L=2 at 1 W.

(2) VP=35V; R

L=2 at 10 W.

Fig 36. THD + N as a function of frequency with a 2 

load, BD modulatio n; VP = 35 V Fig 37. Gain as a function of frequency

001aaj191

10−1

10−2

THD + N

(%)

10−3

f (Hz)

10 105

104

102103

(1)

(2)

001aaj192

(dB)

f (Hz)

10 105

104

102103

f=1kHz; R

L=2.

(1) THD = 1 %.

(2) THD = 10 %.

(3) Maximum output power.

f=1kHz; R

L=4.

(1) THD = 1 %.

(2) THD = 10 %.

(3) Maximum output power.

Fig 38. Output power as a function of supply voltage

with a 2  load Fig 39. Output power as a function of sup ply vo ltage

with a 4  load

VP (V)

10 302618 2214

001aaj193

120

160

(W)

(3)

(2)

(1)

VP (V)

10 353020 2515

001aaj194

160

240

120

200

(W)

(2)

(1)

(3)

Product data sheet Rev. 3 — 2 May 2013 40 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

VP= 14.4 V; Ri=4;P

o=1W.

(1) Channel 1 to channel 2.

(2) Channel 2 to channel 1.

VP= 14.4 V; Ri=4;P

o=10W.

(1) Channel 1 to channel 2.

(2) Channel 2 to channel 1.

Fig 40. Channel separation as a function of frequ ency

with 1 W output power Fig 41. Channel separation as a function of frequency

with 10 W output power

001aaj195

−80

−90

−70

−60

αcs

(dB)

−100

f (Hz)

10 105

104

102103

(2)

(1)

001aaj196

−80

−90

−70

−60

αcs

(dB)

−100

f (Hz)

10 105

104

102103

(2)

(1)

(1) VP= 14.4 V; RL=2 at 1 kHz.

(2) VP= 14.4 V; RL=4 at 1 kHz. (1) VP= 14.4 V; RL=2 at 1 kHz.

(2) VP= 14.4 V; RL=4 at 1 kHz.

Fig 42. Power dissipation as a function of output

power Fig 43. Efficiency as a function of total output power

Po (W)

0504020 3010

001aaj197

(W)

(1)

(2)

Po (W)

0504020 3010

001aaj198

100

(%)

(1)

(2)

Product data sheet Rev. 3 — 2 May 2013 41 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

VP=35V; R

L=4.V

P=35V; R

L=4.

Fig 44. Power dis si pation as a function of total output

power with both channels driven Fig 45. Efficiency as a function of ou tput power of one

channel with both channels driven

Po (W)

0 15012060 9030

001aaj199

(W)

Po (W)

0 15012060 9030

001aaj200

100

(%)

VP= 14.4 V; Vi=1VRMS.

Fig 46. CMRR as a function of frequency

001aak079

−82

−78

−86

−74

−70

CMRR

(dB)

−90

f (Hz)

10 105

104

102103

Product data sheet Rev. 3 — 2 May 2013 42 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

14.7 Typical application schematics

Dual BTL mode (stereo) in non-I2C-bus mode with DC offset protection disabled, Spread spectrum

mode enabled BD modulation.

(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.

(2) See Section 8.3.2 on page 8 for detailed information.

(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.

Fig 47. E xample application diagram: dual BTL in non-I2C-bus mode

001aak080

22 Ω

39 kΩ

10 kΩ

4.7 kΩ

10 Ω

22 Ω

100 μF

35 V

100 μF

35 V

100 nF 15 nF

470 nF

100 nF

15 nF

470 pF 470 pF

CLC

CIN1P

470 nF

CIN1N

470 nF

CIN2P

470 nF

2.2 μF

47 μF

CIN2N

LLC

CLC

100 nF

PGND1

VP1

VP2

VPA

TDF8599A

bead

OUT1N

OUT1P

OUT1N

GND

OUT1P

VSTAB1

GNDD/HW

BOOT1N

BOOT1P

VP1

PGND1

PGND2

VDDD

1000 μF

35 V

100 nF

220 nF

VSTAB2

DCP

OSCIO

220 nF

22 Ω

10 Ω

22 Ω

100 nF 15 nF

100 nF

15 nF

470 pF 470 pF

CLC

LLC

CLC

100 nF

PGND2

VP2

PGND2

OUT2P

OUT2N

OUT2P

OUT2N

BOOT2P

BOOT2N

VP2

PGND2

IN2N

AGND

IN2P

IN1P

ACGND

SVRR

SEL_MUTE

IN1N

IN2N

100 nF

1 μF(2)

CACGND

enable(1)

mute/on(1)

IN2P

IN1P

IN1N

SCL

SSM

OSCSET

VDDA

SDA

VPull-up

VPA

BD modulation

setting

MASTER

MODE

non-I2C-bus

mode

ADS

DIAG

MOD

CLIP

(3)

Product data sheet Rev. 3 — 2 May 2013 43 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

Dual BTL mode (stereo) in I2C-bus mode with DC offset protection enabled, Spread spectrum

mode disabled.

(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.

(2) See Section 8.3.2 on page 8 for detailed information.

(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.

Fig 48. Example application diagram: dual BTL in I2C-bus mode

001aak081

22 Ω

39 kΩ

10 kΩ

≤ 13 kΩ

10 Ω

22 Ω

100 μF

35 V

100 μF

35 V

100 nF 15 nF

470 nF

100 nF

15 nF

470 pF 470 pF

CLC

CIN1P

470 nF

CIN1N

470 nF

CIN2P

470 nF

2.2 μF

47 μF

CIN2N

LLC

CLC

100 nF

PGND1

VP1

VP2

VPA

TDF8599A

bead

RADS

bead

OUT1N

OUT1P

OUT1N

GND

OUT1P

VSTAB1

GNDD/HW

BOOT1N

BOOT1P

VP1

PGND1

PGND2

VDDD

1000 μF

35 V

4.7 μF

100 nF

220 nF

VSTAB2

DCP

OSCIO

220 nF

22 Ω

10 Ω

22 Ω

100 nF 15 nF

100 nF

15 nF

470 pF 470 pF

CLC

LLC

CLC

100 nF

PGND2

VP2

OUT2P

OUT2N

OUT2P

OUT2N

BOOT2P

BOOT2N

VP2

PGND2

IN2N

AGND

IN2P

IN1P

ACGND

SVRR

SEL_MUTE(1)

IN1N

IN2N

100 nF

100 nF (2)

CACGND

enable(1)

IN2P

IN1P

IN1N

SCL

SSM

OSCSET

VDDA

SDA

VPull-up

VPA

stereo mode

setting

connect

to μP

MASTER

MODE

I2C-bus

address select

ADS

DIAG

MOD

CLIP

(3)

Product data sheet Rev. 3 — 2 May 2013 44 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

Single BTL mode (parallel) in I2C-bus mode with DC offset protection enabled, Spread spectrum

mode disabled.

(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.

(2) See Section 8.3.2 on page 8 for detailed information.

(3) See Section 8.5.5 on page 16 for detailed information on DC offset protection.

Fig 49. Example application diagram: single BTL in I2C-bus mode

001aak082

22 Ω

39 kΩ

10 kΩ

≥ 33 kΩ

10 Ω

22 Ω

100 μF

35 V

100 μF

35 V

100 nF

15 nF

470 nF

100 nF

15 nF

470 pF 470 pF

CLC

CINP

470 nF

CINN

470 nF

2.2 μF

47 μF

LLC

CLC

100 nF

PGND1

VP1

VP2

VPA

TDF8599A

bead

RADS

bead

OUT1N

OUT1P

OUTN

GND

OUTP

VSTAB1

GNDD/HW

BOOT1N

BOOT1P

VP1

PGND1

PGND2

VDDD

1000 μF

35 V

4.7 μF

100 nF

220 nF

VSTAB2

DCP

OSCIO

220 nF

10 Ω

15 nF

100 nF

15 nF

470 pF 470 pF

LLC

PGND2

VP2

OUT2P

OUT2N

BOOT2P

BOOT2N

VP2

PGND2

IN2N

AGND

IN2P

IN1P

ACGND

SVRR

SEL_MUTE(1)

IN1N

100 nF

CACGND

enable(1)

INP

INN

SCL

SSM

OSCSET

VDDA

SDA

VPull-up

VPA

parallel mode

setting

connect

to μP

fixed

frequency(2)

MASTER

MODE

I2C-bus

address select

ADS

DIAG

MOD

CLIP

(3)

Product data sheet Rev. 3 — 2 May 2013 45 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

I2C-bus mode: dual BTL in Master mode, one BTL in Slave mode; DC offset protection enabled.

(1) See Figure 3 on page 6 for a diagram of the connection for pins EN and SEL_MUTE.

(2) See Section 8.3.2 on page 8 for detailed information.

(3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection.

(4) See Section 8.3.4 on page 10 for detailed information on PLL operation.

Fig 50. Example application diagram: dual BTL master, single BTL slave in I2C-bus mode

22 Ω

39 kΩ20 kΩ

10 kΩ

≤ 13 kΩ

10 Ω

22 Ω

100 μF

35 V

100 μF

35 V

100 nF 15 nF

470 nF

100 nF

15 nF

470 pF 470 pF

CLC

CIN1P

470 nF

CIN1N

470 nF

CIN2P

470 nF

2.2 μF

47 μF

1 μF

CIN2N

LLC

CLC

100 nF

PGND1

VP1

VP2

VPA

TDF8599A

bead

RADS

bead

OUT1N

OUT1P

OUT1N

GND

OUT1P

VSTAB1

GNDD/HW

BOOT1N

BOOT1P

VP1

PGND1

PGND2

VDDD

1000 μF

35 V

4.7 μF

100 nF

220 nF

VSTAB2

DCP

OSCIO

220 nF

22 Ω

10 Ω

22 Ω

100 nF 15 nF

100 nF

15 nF

470 pF 470 pF

CLC

LLC

CLC

100 nF

PGND2

VP2

OUT2P MASTER

SLAVE

OUT2N

OUT2P

OUT2N

BOOT2P

BOOT2N

VP2

PGND2

IN2N

AGND

IN2P

IN1P

ACGND

SVRR

EN(1)

SEL_MUTE(1)

IN1N

IN2N

100 nF

CACGND

enable

IN2P

IN1P

IN1N

SCL

SSM

OSCSET

VDDA

SDA

VPAPull-up

VPull-up

VPA

stereo mode

setting

spread

spectrum

mode(2)

DC offset

protection enabled

(3)

DC offset

protection enabled

(3)

MASTER

MODE

I2C-bus

address select

ADS

DIAG

MOD

CLIP

001aak083

22 Ω

5.1 kΩ

10 kΩ

≥ 33 kΩ

10 Ω

22 Ω

100 nF

15 nF

470 nF

100 nF

15 nF

470 pF 470 pF

CLC

CINP

470 nFCINN

470 nF

2.2 μF

47 μF

LLC

CLC

100 nF

PGND1

VP1

TDF8599A

bead

RADS

OUT1N

OUT1P

OUT3N

OUT3P

VSTAB1

GNDD/HW

BOOT1N

BOOT1P

VP1

PGND1

VDDD

4.7 μF

100 nF

220 nF

VSTAB2

DCP

OSCIO

220 nF

10 Ω

15 nF

100 nF

15 nF

470 pF 470 pF

LLC

PGND2

VP2

OUT2P

OUT2N

BOOT2P

BOOT2N

VP2

PGND2

IN2N

AGND

IN2P

IN1P

ACGND

SVRR

EN(1)

SEL_MUTE(1)

IN1N

100 nF

10 nF

270 nF

CACGND

IN3P

IN3N

SCL

SSM

OSCSET

VDDA

SDA

VPull-up

VPA

parallel mode

setting

connect

to μP

phase lock

operation

(4)

SLAVE MODE

I2C-bus

address select

ADS

DIAG

MOD

CLIP

Product data sheet Rev. 3 — 2 May 2013 46 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

15. Package outline

Fig 51. Package outline SOT851-2 (HSOP36)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT851-2

04-05-04

HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height

118

36 19

D1D2

E A

ewM

pin 1 index

detail X

(A3)

0 5 10 mm

scale

UNIT A4(1)

mm +0.08

−0.04

3.5 0.35

DIMENSIONS (mm are the original dimensions)

Notes

1. Limits per individual lead.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max. A2

3.5

3.2

1.1

0.9

14.5

13.9

1.1

0.8

1.7

1.5 2.55

2.20

0.25

0.12

8°

0°

0.07

0.03

13.0

12.6

6.2

5.8

2.9

2.5

bpc

0.32

0.23

0.65

D(2)

16.0

15.8

E(2)

11.1

10.9

0.38

0.25

Product data sheet Rev. 3 — 2 May 2013 47 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

16. Handling information

In accordance with SNW -FQ- 611-D. The number of the qua lity specificatio n can be foun d

in the Quality Reference Handbook. The handbook can be ordered using the code

9398 510 63011.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circui t board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 3 — 2 May 2013 48 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 52) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 23 and 24

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 52.

Table 23. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 24. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 25 0 245

> 2.5 250 245 245

Product data sheet Rev. 3 — 2 May 2013 49 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 52. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 25. Abbreviations

Abbreviation Description

BCDMOS Bipolar Complementary and double Diffused Metal-Oxide Semiconductor

BTL Bridge-Tied Load

DCP D C o ffset Protection

DMOST double Diffused Metal-Oxide Semiconductor Transistor

EMI ElectroMagnetic Interference

I2C Inter-Integrated Circuit

LSB Least Significant Bit

Mp Master microprocessor

MSB Most Significant Bit

NDMOST N-type double Diffused Metal-Oxide Semiconductor Tra nsistor

OCP OverCurrent Protection

OTP OverTemperature Protection

OVP OverVoltage Protection

PLL Phase-Locked Loop

POR Power-On Reset

PWM Pulse-Width Modulation

SOI Silicon On Insulator

Product data sheet Rev. 3 — 2 May 2013 50 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

19. Revision history

TFP Thermal Foldback Protection

UVP UnderVoltage Protection

WP Window Protection

Table 25. Abbreviations …continued

Abbreviation Description

Table 26. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TDF8599A v.3 20130502 Product data sheet - TDF8599A v.2

Modifications: •Changed title Figure 45.

TDF8599A v.2 20090630 Product data sheet - TDF8599A v.1

Modifications: •Data sheet status changed from Objective data sheet to Product data sheet.

•Various minor textual inconsistencies in the data sheet corrected.

•Changed Section 8.2: Figure 3 on page 6.

•Changed Section 8.2: Table 4 on page 7.

•Changed Section 8.2: Table 5 on page 7.

•Changed Section 8.6.3: Figure 20 on page 22.

•Changed Section 8.6.3: Figure 21 on page 23.

•Changed Section 14.7: Figure 47 on page 42, Figure 48 on page 43, Figure 49 on page 44

and Figure 50 on page 45.

TDF8599A v.1 20090602 Objective data sheet - -

Product data sheet Rev. 3 — 2 May 2013 51 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless ot herwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data fro m the objective specification fo r product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specificatio n.

Product data sheet Rev. 3 — 2 May 2013 52 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

No offer to sell or license — Nothing in this document may be interpret ed or

construed as an of fer to sell product s that is op en for accept ance or the grant ,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

20.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 3 — 2 May 2013 53 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

22. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4

Table 4. I2C-bus mode operation . . . . . . . . . . . . . . . . . . .7

Table 5. Non-I2C-bus mode operation . . . . . . . . . . . . . . .7

Table 6. Mode setting pin OSCIO . . . . . . . . . . . . . . . . . .7

Table 7. Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .10

Table 8. Operation mode selection with th e MOD pin . .11

Table 9. Overview of protection types . . . . . . . . . . . . . .15

Table 10. Overview of TDF8599A protection circuits and

amplifier states . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 11. Available data on pins DIAG and CLIP . . . . . .18

Table 12. Interpretation of DC load detection bits . . . . . .20

Table 13. I2C-bus write address selection using pins

MOD and ADS . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 14. Instruction byte descriptions . . . . . . . . . . . . . .25

Table 15. Phase shift bit settings . . . . . . . . . . . . . . . . . . .2 5

Table 16. Description of data bytes . . . . . . . . . . . . . . . . .26

Table 17. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 18. Thermal characteristics . . . . . . . . . . . . . . . . . .28

Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . .28

Table 20. Switching characteristics . . . . . . . . . . . . . . . . .31

Table 21. Dynamic characteristics . . . . . . . . . . . . . . . . . .32

Table 22. Filter component values . . . . . . . . . . . . . . . . .36

Table 23. SnPb eutectic process (from J-STD-020D) . . .48

Table 24. Lead-free process (from J-STD-020D) . . . . . .48

Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .50

Product data sheet Rev. 3 — 2 May 2013 54 of 55

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

23. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Fig 2. Heatsink up (top view) pin configuration

TDF8599ATH. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 3. Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Fig 4. Clock frequency as a function of Rosc . . . . . . . . . .8

Fig 5. Master and slave configuration . . . . . . . . . . . . . . .8

Fig 6. Spread spectrum mode . . . . . . . . . . . . . . . . . . . . .9

Fig 7. Spread spectrum operation in Master mode . . . . .9

Fig 8. Phase lock operation. . . . . . . . . . . . . . . . . . . . . .10

Fig 9. AD/BD modulation switching circuit. . . . . . . . . . .12

Fig 10. AD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Fig 11. BD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Fig 12. Master and slave operation with 1⁄2 p phase shift 14

Fig 13. Parallel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 14. DC offset protection and diagnostic output . . . . .16

Fig 15. Diagnostic output for short circuit conditions . . . .18

Fig 16. DC load detection circuit . . . . . . . . . . . . . . . . . . .19

Fig 17. DC load detection procedure. . . . . . . . . . . . . . . .1 9

Fig 18. DC load detection limits. . . . . . . . . . . . . . . . . . . .19

Fig 19. Recommended start-up sequence with DC load

detection enabled . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 20. Start-up and shutdown timing in I2C-bus mode

with DC load detection. . . . . . . . . . . . . . . . . . . . .22

Fig 21. Start-up and shutdown timing in non-I2C-bus

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 22. I2C-bus start and stop conditions. . . . . . . . . . . . .24

Fig 23. Data bits sent from Master microprocessor

(Mmp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 24. I2C-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 25. I2C-bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 26. Po as a function of VP in stereo mode with

THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Fig 27. Po as a function of VP in stereo mode with

THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Fig 28. Po as a function of VP in parallel mode with

THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 29. Po as a function of VP parallel mode with

THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 30. THD + N as a function of output power with a

2 load; VP = 14.4 V. . . . . . . . . . . . . . . . . . . . . .37

Fig 31. THD + N as a function of output power with a

4 load; VP = 14.4 V. . . . . . . . . . . . . . . . . . . . . .37

Fig 32. THD + N as a function of output power with a

2 load; VP = 35 V . . . . . . . . . . . . . . . . . . . . . . .38

Fig 33. THD + N as a function of output power with a

4 load; VP = 35 V . . . . . . . . . . . . . . . . . . . . . . .38

Fig 34. THD + N as a function of frequen cy with a 2 

load, BD modulation; VP = 14.4 V . . . . . . . . . . . .38

Fig 35. THD + N as a function of frequen cy with a 4 

load, BD modulation; VP = 14.4 V . . . . . . . . . . . .38

Fig 36. THD + N as a function of frequen cy with a 2 

load, BD modulation; VP = 35 V. . . . . . . . . . . . . .39

Fig 37. Gain as a function of frequency. . . . . . . . . . . . . .39

Fig 38. Output power as a function of supply voltage

with a 2  load. . . . . . . . . . . . . . . . . . . . . . . . . . .3 9

Fig 39. Output power as a function of supply voltage

with a 4  load . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Fig 40. Channel separation as a function of frequency

with 1 W output power. . . . . . . . . . . . . . . . . . . . . 40

Fig 41. Channel separation as a function of frequency

with 10 W output power. . . . . . . . . . . . . . . . . . . . 40

Fig 42. Power dissipation as a function of output power. 40

Fig 43. Efficiency as a function of total output power . . . 40

Fig 44. Power dissipation as a function of total output

power with both channels driven. . . . . . . . . . . . . 41

Fig 45. Efficiency as a function of output power of one

channel with both channels driven . . . . . . . . . . . 41

Fig 46. CMRR as a function of frequency . . . . . . . . . . . . 41

Fig 47. Example appli c ation diagram: dual BTL in

non-I2C-bus mode. . . . . . . . . . . . . . . . . . . . . . . . 42

Fig 48. Example appli c ation diagram: dual BTL in

I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Fig 49. Example application diagram: single BTL in

I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Fig 50. Example appli c ation diagram: dual BTL master,

single BTL slave in I2C-bus mode. . . . . . . . . . . . 45

Fig 51. Package outline SOT851-2 (HSOP36) . . . . . . . . 46

Fig 52. Temperature profiles for large an d small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

NXP Semiconductors TDF8599A

I2C-bus controlled dual channel class-D power amplifier

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 May 2013

Document identifier: TDF8599A

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

24. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

5 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Functional description . . . . . . . . . . . . . . . . . . . 5

8.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 6

8.3 Pulse-width modulation frequency . . . . . . . . . . 7

8.3.1 Master and slave mode selection. . . . . . . . . . . 7

8.3.2 Spread sp ectrum mode (Master mode) . . . . . . 8

8.3.3 Frequency hopping (Master mode). . . . . . . . . . 9

8.3.4 Phase lock operation (Slave mode) . . . . . . . . 10

8.4 Operation mode selection. . . . . . . . . . . . . . . . 11

8.4.1 Modulation mode . . . . . . . . . . . . . . . . . . . . . . 11

8.4.2 Phase staggering (Slave mode) . . . . . . . . . . . 13

8.4.3 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.5 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.5.1 Thermal foldback . . . . . . . . . . . . . . . . . . . . . . 15

8.5.2 Overtemperature protection . . . . . . . . . . . . . . 15

8.5.3 Overcurrent protection . . . . . . . . . . . . . . . . . . 15

8.5.4 Window protection . . . . . . . . . . . . . . . . . . . . . 15

8.5.5 DC offset protection . . . . . . . . . . . . . . . . . . . . 16

8.5.6 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . 17

8.5.7 Overview of protection circuits and amplifier

states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.6 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . 17

8.6.1 Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 17

8.6.2 Load identification (I2C-bus mode only) . . . . . 18

8.6.2.1 DC load detection. . . . . . . . . . . . . . . . . . . . . . 18

8.6.2.2 Recommended start-up sequence with DC

load detection enabled . . . . . . . . . . . . . . . . . . 20

8.6.2.3 AC load detection. . . . . . . . . . . . . . . . . . . . . . 21

8.6.2.4 CLIP detection . . . . . . . . . . . . . . . . . . . . . . . . 21

8.6.3 Start-up and shutdown sequence. . . . . . . . . . 22

9 I2C-bus specification. . . . . . . . . . . . . . . . . . . . 23

9.1 Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 25

9.2 Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27

11 Thermal characteristics . . . . . . . . . . . . . . . . . 28

12 Static characteristics. . . . . . . . . . . . . . . . . . . . 28

12.1 Switching characteristics . . . . . . . . . . . . . . . . 31

13 Dynamic characteristics. . . . . . . . . . . . . . . . . 32

14 Application information . . . . . . . . . . . . . . . . . 33

14.1 Output power estimation (Stereo mode) . . . . 33

14.2 Output power estimation (Parallel mode). . . . 34

14.3 Output current limiting . . . . . . . . . . . . . . . . . . 35

14.4 Speaker configuration and impedance. . . . . . 36

14.5 Heat sink requiremen ts . . . . . . . . . . . . . . . . . 36

14.6 Curves measured in reference desig n. . . . . . 37

14.7 Typical application schematics. . . . . . . . . . . . 42

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 46

16 Handling information . . . . . . . . . . . . . . . . . . . 47

17 Soldering of SMD packages. . . . . . . . . . . . . . 47

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 47

17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 47

17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47

17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 48

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49

19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 50

20 Legal information . . . . . . . . . . . . . . . . . . . . . . 51

20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 51

20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51

20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52

21 Contact information . . . . . . . . . . . . . . . . . . . . 52

22 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

23 Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55