1
Motorola Small–Signal Transistors, FETs and Diodes Device Data
  
PNP Silicon
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage VCEO –45 Vdc
Emitter–Base Voltage VEBO –5.0 Vdc
Collector Current — Continuous IC–100 mAdc
DEVICE MARKING
BCW69LT1 = H1; BCW70LT1 = H2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR-5 Board (1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient RθJA 556 °C/W
Total Device Dissipation
Alumina Substrate, (2) TA = 25°C
Derate above 25°C
PD300
2.4
mW
mW/°C
Thermal Resistance, Junction to Ambient RθJA 417 °C/W
Junction and Storage Temperature TJ, Tstg 55 to +150 °C
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage (IC = –2.0 mAdc, IB = 0) V(BR)CEO –45 Vdc
Collector–Emitter Breakdown Voltage (IC = –100 µAdc, VEB = 0) V(BR)CES –50 Vdc
Emitter–Base Breakdown Voltage (IE = –10 µAdc, IC = 0) V(BR)EBO –5.0 Vdc
Collector Cutoff Current
(VCB = –20 Vdc, IE = 0)
(VCB = –20 Vdc, IE = 0, TA = 100°C)
ICBO
–100
–10 nAdc
µAdc
1. FR–5 = 1.0 x 0.75 x 0.062 in.
2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina
Thermal Clad is a trademark of the Bergquist Company
Order this document
by BCW69LT1/D

SEMICONDUCTOR TECHNICAL DATA
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12
3
CASE 31808, STYLE 6
SOT–23 (TO236AB)
Motorola, Inc. 1996
COLLECTOR
3
1
BASE
2
EMITTER
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2 Motorola Small–Signal Transistors, FETs and Diodes Device Data
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic Symbol Min Max Unit
ON CHARACTERISTICS
DC Current Gain
(IC = –2.0 mAdc, VCE = –5.0 Vdc) BCW69
BCW70
hFE 120
215 260
500
Collector–Emitter Saturation Voltage (IC = –10 mAdc, IB = –0.5 mAdc) VCE(sat) –0.3 Vdc
Base–Emitter On Voltage (IC = –2.0 mAdc, VCE = –5.0 Vdc) VBE(on) –0.6 –0.75 Vdc
SMALL–SIGNAL CHARACTERISTICS
Output Capacitance
(IE = 0, VCB = –10 Vdc, f = 1.0 MHz) Cobo 7.0 pF
Noise Figure
(IC = –0.2 mAdc, VCE = –5.0 Vdc, RS = 2.0 k, f = 1.0 kHz, BW = 200 Hz) NF 10 dB
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3
Motorola Small–Signal Transistors, FETs and Diodes Device Data
TYPICAL NOISE CHARACTERISTICS
(VCE = –
ā
5.0 Vdc, TA = 25°C)
Figure 1. Noise Voltage
f, FREQUENCY (Hz)
5.0
7.0
10
3.0
Figure 2. Noise Current
f, FREQUENCY (Hz)
1.010 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k
1.0
7.0
5.0
3.0
2.0
1.0
0.7
0.5
0.3
0.1
BANDWIDTH = 1.0 Hz
RS
0
IC = 10
µ
A
100
µ
A
en, NOISE VOLTAGE (nV)
In, NOISE CURRENT (pA)
30
µ
A
BANDWIDTH = 1.0 Hz
RS
≈ ∞
IC = 1.0 mA
300
µ
A
100
µ
A
30
µ
A
10
µ
A
10 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k
2.0 1.0 mA
0.2
300
µ
A
NOISE FIGURE CONTOURS
(VCE = –
ā
5.0 Vdc, TA = 25°C)
500 k
100
200
500
1.0 k
10 k
5.0 k
20 k
50 k
100 k
200 k
2.0 k
1.0 M
500 k
100
200
500
1.0 k
10 k
5.0 k
20 k
50 k
100 k
200 k
2.0 k
1.0 M
Figure 3. Narrow Band, 100 Hz
IC, COLLECTOR CURRENT (
µ
A)
Figure 4. Narrow Band, 1.0 kHz
IC, COLLECTOR CURRENT (
µ
A)
10
0.5 dB
BANDWIDTH = 1.0 Hz
RS, SOURCE RESISTANCE (OHMS)
RS, SOURCE RESISTANCE (OHMS)
Figure 5. Wideband
IC, COLLECTOR CURRENT (
µ
A)
10
10 Hz to 15.7 kHz
RS, SOURCE RESISTANCE (OHMS)
Noise Figure is Defined as:
NF
+
20 log10
ƪ
en2
)
4KTRS
)
In2RS2
4KTRS
ƫ
1
ń
2
= Noise V oltage of the Transistor referred to the input. (Figure 3)
= Noise Current of the Transistor referred to the input. (Figure 4)
= Boltzman’s Constant (1.38 x 10–23 j/°K)
= Temperature of the Source Resistance (°K)
= Source Resistance (Ohms)
en
In
K
T
RS
1.0 dB
2.0 dB
3.0 dB
20 30 50 70 100 200 300 500 700 1.0 k 10 20 30 50 70 100 200 300 500 700 1.0 k
500 k
100
200
500
1.0 k
10 k
5.0 k
20 k
50 k
100 k
200 k
2.0 k
1.0 M
20 30 50 70 100 200 300 500 700 1.0 k
BANDWIDTH = 1.0 Hz
5.0 dB
0.5 dB
1.0 dB
2.0 dB
3.0 dB 5.0 dB
0.5 dB
1.0 dB
2.0 dB
3.0 dB
5.0 dB
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4 Motorola Small–Signal Transistors, FETs and Diodes Device Data
TYPICAL STATIC CHARACTERISTICS
Figure 6. Collector Saturation Region
IC, COLLECTOR CURRENT (mA)
1.4
Figure 7. Collector Characteristics
IC, COLLECTOR CURRENT (mA)
V, VOLTAGE (VOLTS)
1.0 2.0 5.0 10 20 50
1.6
100
TJ = 25
°
C
VBE(sat) @ IC/IB = 10
VCE(sat) @ IC/IB = 10
VBE(on) @ VCE = 1.0 V
*
q
VC for VCE(sat)
q
VB for VBE
0.1 0.2 0.5
Figure 8. “On” Voltages
IB, BASE CURRENT (mA)
0.4
0.6
0.8
1.0
0.2
0
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
0.002
TA = 25
°
C
IC = 1.0 mA 10 mA 100 mA
Figure 9. Temperature Coefficients
50 mA
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
40
60
80
100
20
00
IC, COLLECTOR CURRENT (mA)
TA = 25
°
C
PULSE WIDTH = 300
µ
s
DUTY CYCLE
2.0%
IB = 400
µ
A
350
µ
A
300
µ
A250
µ
A
200
µ
A
*APPLIES for IC/IB
hFE/2
25
°
C to 125
°
C
55
°
C to 25
°
C
25
°
C to 125
°
C
55
°
C to 25
°
C
0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 5.0 10 15 20 25 30 35 40
1.2
1.0
0.8
0.6
0.4
0.2
02.4
0.8
0
1.6
0.8
1.0 2.0 5.0 10 20 50 100
0.1 0.2 0.5
V, TEMPERATURE COEFFICIENTS (mV/ C)
°θ
150
µ
A
100
µ
A
50
µ
A
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5
Motorola Small–Signal Transistors, FETs and Diodes Device Data
TYPICAL DYNAMIC CHARACTERISTICS
C, CAPACITANCE (pF)
Figure 10. Turn–On Time
IC, COLLECTOR CURRENT (mA)
500
Figure 11. Turn–Off Time
IC, COLLECTOR CURRENT (mA)
2.0 5.0 10 20 30 50
1000
Figure 12. Current–Gain — Bandwidth Product
IC, COLLECTOR CURRENT (mA)
Figure 13. Capacitance
VR, REVERSE VOLTAGE (VOLTS)
3.01.0
500
0.5
10
t, TIME (ns)
t, TIME (ns)
f, CURRENT–GAIN — BANDWIDTH PRODUCT (MHz)
T
5.0
7.0
10
20
30
50
70
100
300
7.0 70 100
VCC = 3.0 V
IC/IB = 10
TJ = 25
°
C
td @ VBE(off) = 0.5 V
tr
10
20
30
50
70
100
200
300
500
700
ā
2.0
–1.0
VCC = –
ā
3.0 V
IC/IB = 10
IB1 = IB2
TJ = 25
°
C
ts
tf
50
70
100
200
300
0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
TJ = 25
°
C
VCE = 20 V
5.0 V
1.0
2.0
3.0
5.0
7.0
0.1 0.2 0.5 1.0 2.0 5.0 10 20 500.05
Cib
Cob
200
ā
3.0
ā
5.0
ā
7.0
ā
20
–10
ā
30
ā
50
ā
70 –100
TJ = 25
°
C
Figure 14. Thermal Response
t, TIME (ms)
1.0
0.01
r(t) TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.01
0.02
0.03
0.05
0.07
0.1
0.2
0.3
0.5
0.7
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k
D = 0.5
0.2
0.1
0.05
0.02
0.01 SINGLE PULSE
DUTY CYCLE, D = t1/t2
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1 (SEE AN–569)
Z
θ
JA(t) = r(t)
R
θ
JA
TJ(pk) – TA = P(pk) Z
θ
JA(t)
t1t2
P(pk)
FIGURE 16
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6 Motorola Small–Signal Transistors, FETs and Diodes Device Data
TJ, JUNCTION TEMPERATURE (
°
C)
104
4
0
IC, COLLECTOR CURRENT (nA)
Figure 15. Typical Collector Leakage Current
DESIGN NOTE: USE OF THERMAL RESPONSE DATA
A train of periodical power pulses can be represented by the model
as shown in Figure 16. Using the model and the device thermal
response the normalized effective transient thermal resistance of
Figure 14 was calculated for various duty cycles.
To find ZθJA(t), multiply the value obtained from Figure 14 by the
steady state value RθJA.
Example:
Dissipating 2.0 watts peak under the following conditions:
t1 = 1.0 ms, t2 = 5.0 ms (D = 0.2)
Using Figure 14 at a pulse width of 1.0 ms and D = 0.2, the reading of
r(t) is 0.22.
The peak rise in junction temperature is therefore
T = r(t) x P(pk) x RθJA = 0.22 x 2.0 x 200 = 88°C.
For more information, see AN–569.
10–2
10–1
100
101
102
103
2
00 +20 +40 +60 +80 +100 +120 +140 +160
VCC = 30 V
ICEO
ICBO
AND
ICEX @ VBE(off) = 3.0 V
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7
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by TJ(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T A of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
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8 Motorola Small–Signal Transistors, FETs and Diodes Device Data
PACKAGE DIMENSIONS
DJ
K
L
A
C
BS
H
GV
3
12
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
DIM
AMIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0180 0.0236 0.45 0.60
L0.0350 0.0401 0.89 1.02
S0.0830 0.0984 2.10 2.50
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.
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BCW69LT1/D
*BCW69LT1/D*