MC14001B Series B-Suffix Series CMOS Gates MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B http://onsemi.com The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. MARKING DIAGRAMS 14 * Supply Voltage Range = 3.0 Vdc to 18 Vdc * All Outputs Buffered * Capable of Driving Two Low-power TTL Loads or One Low-power * * PDIP-14 P SUFFIX CASE 646 1 Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B Pin-for-Pin Replacements for Corresponding CD4000 Series B Suffix Devices 14 SOIC-14 D SUFFIX CASE 751A VDD Vin, Vout Iin, Iout PD Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Value Unit - 0.5 to +18.0 V - 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin 10 mA Power Dissipation, per Package (Note 2) 500 mW TA Ambient Temperature Range - 55 to +125 C Tstg Storage Temperature Range - 65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C 140xxB AWLYWW 1 14 TSSOP-14 DT SUFFIX CASE 948G MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1) Symbol MC140xxBCP AWLYYWW 14 0xxB ALYW 1 14 SOEIAJ-14 F SUFFIX CASE 965 MC140xxB AWLYWW 1 xx A WL, L YY, Y WW, W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week DEVICE INFORMATION 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/C From 65C To 125C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Device Description MC14001B Quad 2-Input NOR Gate MC14011B Quad 2-Input NAND Gate MC14023B Triple 3-Input NAND Gate MC14025B Triple 3-Input NOR Gate MC14071B Quad 2-Input OR Gate MC14073B Triple 3-Input AND Gate MC14081B Quad 2-Input AND Gate MC14082B Dual 4-Input AND Gate ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Semiconductor Components Industries, LLC, 2003 March, 2003 - Rev. 3 1 Publication Order Number: MC14001B/D MC14001B Series LOGIC DIAGRAMS NAND OR AND MC14001B Quad 2-Input NOR Gate MC14011B Quad 2-Input NAND Gate MC14071B Quad 2-Input OR Gate MC14081B Quad 2-Input AND Gate 2 INPUT NOR 1 2 3 1 2 3 1 2 3 1 2 3 5 6 4 5 6 4 5 6 4 5 6 4 8 9 10 8 9 10 8 9 10 8 9 10 12 13 11 12 13 11 12 13 11 12 13 11 3 INPUT MC14025B Triple 3-Input NOR Gate 1 2 8 3 4 5 11 12 13 9 6 10 MC14023B Triple 3-Input NAND Gate 1 2 8 3 4 5 11 12 13 MC14073B Triple 3-Input AND Gate 1 2 8 3 4 5 11 12 13 9 6 10 9 6 10 MC14082B Dual 4-Input AND Gate 2 3 4 5 9 10 11 12 1 13 NC = 6, 8 VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES PIN ASSIGNMENTS MC14001B Quad 2-Input NOR Gate MC14023B Triple 3-Input NAND Gate MC14011B Quad 2-Input NAND Gate MC14025B Triple 3-Input NOR Gate IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD IN 2A 2 13 IN 2D IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 3C OUTA 3 12 IN 1D OUTA 3 12 IN 1D IN 1B 3 12 IN 2C IN 1B 3 12 IN 2C OUTB 4 11 OUTD OUTB 4 11 OUTD IN 2B 4 11 IN 1C IN 2B 4 11 IN 1C IN 1B 5 10 OUTC IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 3B 5 10 OUTC IN 2B 6 9 IN 2C IN 2B 6 9 IN 2C OUTB 6 9 OUTA OUTB 6 9 OUTA VSS 7 8 IN 1C VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 3A MC14071B Quad 2-Input OR Gate MC14073B Triple 3-Input AND Gate MC14081B Quad 2-Input AND Gate MC14082B Dual 4-Input AND Gate IN 1A 1 14 VDD IN 1A 1 14 VDD IN 1A 1 14 VDD OUTA 1 14 VDD IN 2A 2 13 IN 2D IN 2A 2 13 IN 3C IN 2A 2 13 IN 2D IN 1A 2 13 OUTB OUTA 3 12 IN 1D IN 1B 3 12 IN 2C OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTB 4 11 OUTD IN 2B 4 11 IN 1C OUTB 4 11 OUTD IN 3A 4 11 IN 3B IN 1B 5 10 OUTC IN 3B 5 10 OUTC IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 2B 6 9 IN 2C OUTB 6 9 OUTA IN 2B 6 9 IN 2C NC 6 9 IN 1B VSS 7 8 IN 1C VSS 7 8 IN 3A VSS 7 8 IN 1C VSS 7 8 NC NC = NO CONNECTION http://onsemi.com 2 MC14001B Series IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIII IIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIII IIIIIIIII IIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55C 25C 125C VDD Vdc Min Max Min Typ (3) Max Min Max Unit "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 -- -- -- 1.5 3.0 4.0 -- -- -- 2.25 4.50 6.75 1.5 3.0 4.0 -- -- -- 1.5 3.0 4.0 "1" Level VIH 5.0 10 15 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 0.25 0.5 1.0 -- -- -- 0.0005 0.0010 0.0015 0.25 0.5 1.0 -- -- -- 7.5 15 30 Adc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Total Supply Current (4) (5) (Dynamic plus Quiescent, Per Gate, CL = 50 pF) Sink mAdc IT = (0.3 A/kHz) f + IDD/N IT = (0.6 A/kHz) f + IDD/N IT = (0.9 A/kHz) f + IDD/N Adc 3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. http://onsemi.com 3 MC14001B Series B-SERIES GATE SWITCHING TIMES IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III SWITCHING CHARACTERISTICS (6) (CL = 50 pF, TA = 25C) Characteristic Symbol Output Rise Time, All B-Series Gates tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns tTLH Output Fall Time, All B-Series Gates tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL Propagation Delay Time MC14001B, MC14011B only tPLH, tPHL = (0.90 ns/pF) CL + 80 ns tPLH, tPHL = (0.36 ns/pF) CL + 32 ns tPLH, tPHL = (0.26 ns/pF) CL + 27 ns All Other 2, 3, and 4 Input Gates tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 8-Input Gates (MC14068B, MC14078B) tPLH, tPHL = (0.90 ns/pF) CL + 155 ns tPLH, tPHL = (0.36 ns/pF) CL + 62 ns tPLH, tPHL = (0.26 ns/pF) CL + 47 ns VDD Vdc Min Typ (7) Max 5.0 10 15 -- -- -- 100 50 40 200 100 80 5.0 10 15 -- -- -- 100 50 40 200 100 80 Unit ns ns tPLH, tPHL ns 5.0 10 15 -- -- -- 125 50 40 250 100 80 5.0 10 15 -- -- -- 160 65 50 300 130 100 5.0 10 15 -- -- -- 200 80 60 350 150 110 6. The formulas given are for the typical characteristics only at 25C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 14 PULSE GENERATOR 20 ns VDD 20 ns OUTPUT 7 0V tPLH tPHL CL * VDD 90% 50% 10% INPUT INPUT OUTPUT INVERTING VSS tTHL tPLH OUTPUT NON-INVERTING *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. tTLH Figure 1. Switching Time Test Circuit and Waveforms http://onsemi.com 4 VOH 90% 50% 10% tTLH tPHL 90% 50% 10% tTHL VOL VOH VOL MC14001B Series CIRCUIT SCHEMATIC NOR, OR GATES MC14001B, MC14071B One of Four Gates Shown MC14025B One of Three Gates Shown VDD VDD 14 VDD 1, 6, 8, 13 1, 3, 11 * 2, 4, 12 2, 5, 9, 12 14 3, 4, 10, 11 VDD * VSS VSS 7 9, 6, 10 VSS VDD *Inverter omitted in MC14001B 8, 5, 13 7 VSS VSS *Inverter omitted in MC14025B CIRCUIT SCHEMATIC NAND, AND GATES MC14023B, MC14073B One of Three Gates Shown MC14011B, MC14081B One of Four Gates Shown VDD 14 VDD * 3, 4, 10, 11 2, 4, 12 1, 3, 11 14 VSS VDD 2, 5, 9, 12 VDD 1, 6, 8, 13 7 VSS *Inverter omitted in MC14011B * 9, 6, 10 8, 5, 13 VSS 7 VSS *Inverter omitted in MC14023B http://onsemi.com 5 MC14001B Series TYPICAL B-SERIES GATE CHARACTERISTICS N-CHANNEL DRAIN CURRENT (SINK) P-CHANNEL DRAIN CURRENT (SOURCE) - 10 5.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) - 9.0 4.0 TA = - 55C 3.0 - 40C + 85C + 25C 2.0 + 125C 1.0 - 8.0 TA = - 55C - 7.0 - 40C - 6.0 - 5.0 + 25C + 85C - 4.0 + 125C - 3.0 - 2.0 - 1.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 0 5.0 0 Figure 2. VGS = 5.0 Vdc - 50 - 45 TA = - 55C 16 14 - 40C 12 + 25C + 85C 10 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 18 + 125C 8.0 6.0 - 40 - 35 - 30 - 5.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 9.0 0 10 + 85C - 15 2.0 1.0 + 125C 0 Figure 4. VGS = 10 Vdc - 100 45 - 90 30 - 40C 25 + 25C ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) 40 TA = - 55C + 85C 20 + 125C 15 - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 5. VGS = - 10 Vdc 50 35 - 40C + 25C - 20 - 10 0 TA = - 55C - 25 4.0 10 5.0 0 - 5.0 Figure 3. VGS = - 5.0 Vdc 20 0 - 1.0 - 2.0 - 3.0 - 4.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) - 80 - 70 - 60 TA = - 55C - 50 - 40C + 25C - 40 + 85C - 30 + 125C - 20 - 10 0 2.0 4.0 6.0 8.0 10 12 14 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 18 0 20 0 Figure 6. VGS = 15 Vdc - 2.0 - 4.0 - 6.0 - 8.0 - 10 - 12 - 14 - 16 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 7. VGS = - 15 Vdc These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin. http://onsemi.com 6 - 18 - 20 MC14001B Series TYPICAL B-SERIES GATE CHARACTERISTICS (cont'd) V out , OUTPUT VOLTAGE (Vdc) V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 5.0 4.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 3.0 2.0 1.0 0 0 1.0 2.0 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 10 8.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 6.0 4.0 2.0 0 3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc) 0 2.0 Figure 8. VDD = 5.0 Vdc V out , OUTPUT VOLTAGE (Vdc) 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 9. VDD = 10 Vdc DC NOISE MARGIN 16 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 14 The DC noise margin is defined as the input voltage range from an ideal "1" or "0" input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the "1" and "0" levels = 12 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 10 8.0 6.0 4.0 2.0 0 4.0 0 2.0 4.0 1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 10. VDD = 15 Vdc Vout VDD Vout VO VO VO VO VDD VDD 0 VDD Vin VIL 0 VIH Vin VIL VIH VSS = 0 VOLTS DC (a) Inverting Function (b) Non-Inverting Function Figure 11. DC Noise Immunity http://onsemi.com 7 MC14001B Series PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L N C -TSEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 0.38 1.01 M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A14 8 -B1 P 7 PL 0.25 (0.010) 7 G B M M F R X 45 C -TSEATING PLANE 0.25 (0.010) M K D 14 PL M T B S A S http://onsemi.com 8 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC14001B Series PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A -V- CCC EE CCC EE K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 9 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC14001B Series PACKAGE DIMENSIONS F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O 14 NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5 THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE L 7 1 M DETAIL P Z D VIEW P A e c A1 b 0.13 (0.005) M 0.10 (0.004) http://onsemi.com 10 DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --- 0.056 MC14001B Series ORDERING & SHIPPING INFORMATION: Device ORDERING & SHIPPING INFORMATION: Package Shipping Package Shipping MC14001BCP PDIP-14 2000 Units per Box MC14071BCP Device PDIP-14 2000 Units per Box MC14001BD SOIC-14 2750 Units per Box MC14071BD SOIC-14 55 Units per Rail MC14001BDR2 SOIC-14 2500 Units / Tape & Reel MC14071BDR2 SOIC-14 2500 Units / Tape & Reel MC14001BDT TSSOP-14 96 Units per Rail MC14071BDT TSSOP-14 96 Units per Rail MC14001BDTR2 TSSOP-14 2500 Units / Tape & Reel MC14071BDTR2 TSSOP-14 2500 Units / Tape & Reel MC14011BCP PDIP-14 2000 Units per Box MC14073BCP PDIP-14 2000 Units per Box MC14011BD SOIC-14 2750 Units per Box MC14073BD SOIC-14 55 Units per Rail MC14011BDR2 SOIC-14 2500 Units / Tape & Reel MC14073BDR2 SOIC-14 2500 Units / Tape & Reel MC14011BDT TSSOP-14 96 Units per Rail MC14011BDTEL TSSOP-14 2000 Units / Tape & Reel MC14081BCP PDIP-14 2000 Units per Box MC14011BDTR2 TSSOP-14 2500 Units / Tape & Reel MC14081BD SOIC-14 55 Units per Rail MC14081BDR2 SOIC-14 2500 Units / Tape & Reel MC14023BCP PDIP-14 2000 Units per Box MC14081BDT TSSOP-14 96 Units per Rail MC14023BD SOIC-14 2750 Units per Box MC14081BDTR2 TSSOP-14 2500 Units / Tape & Reel MC14023BDR2 SOIC-14 2500 Units / Tape & Reel MC14082BCP PDIP-14 2000 Units per Box MC14025BCP PDIP-14 2000 Units per Box MC14082BD SOIC-14 55 Units per Rail MC14025BD SOIC-14 2750 Units per Box MC14082BDR2 SOIC-14 2500 Units / Tape & Reel MC14025BDR2 SOIC-14 2500 Units / Tape & Reel For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. http://onsemi.com 11 MC14001B Series ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800-282-9855 Toll Free USA/Canada http://onsemi.com 12 MC14001B/D