SPL30A 144KB LCD CONTROLLER/DRIVER GENERAL DESCRIPTION FEATURES The SPL30A is a CMOS 8-bit single chip microprocessor which Built-in 8-bit CPU contains RAM, ROM, I/Os, interrupt controller, 8-bit PWM audio 160 bytes SRAM output and automatic display controller/driver for LCD. 144K bytes ROM For power saving, a software controllable standby switch is also built-in. Max. CPU frequency: 2.0MHz @ 3.0V This chip is implemented with advanced design and process Wide operating voltage: 2.4V - 3.4V technology. It is very suitable for LCD type handheld products. 3.6V - 5.5V The ROM space of this chip can be used to store program or audio Built-in 32.768KHz oscillator circuit for real clock function data. Built-in RC oscillator (only one resistor is needed) (The speech data is about 38 seconds at 7KHz sampling Internal time base generator rate by using 4bit-ADPCM). Key wake-up mode Provide 7 INT sources BLOCK DIAGRAM Operating current: 400A/600KHz @ 3.0V Very low standby current In standby mode: ISTBY < 1A LCD matrix: 44 segments x 5 commons LCD 1/2, 1/3 bias; 1/2, 1/3, 1/4,1/5 duty Two 16-bit timers 12 general I/O pins, 8 input pins Provide standby function (stop osc) Built-in 8-bit PWM output (directly drive a speaker) Note: IOAB7 - 0 can be mask option for segment 43 - 36. The mask option can be used as one I/O for one segment. Note: Patent Circuit Included. Taiwan Patent No. 68824. SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. is believed to be accurate and reliable. Information provided by SUNPLUS TECHNOLOGY CO. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. PAGE 1 SPL30A FUNCTION DESCRIPTION 1. ROM AREA 4. TIME-SETTING REGISTER RELATED SPL30A is a large ROM based micro-controller with 220 dots LCD The basic time base of CPU wake-up and interrupt can be changed driver. by writing to TIME-SETTING register. The large ROM can be defined as a program ROM, LCD For example, the font and audio data continuously without any limitation. To access programmer can change 2Hz wake-up and interrupt into 1Hz the ROM area, user should program the BANK SELECT register wake-up and interrupt by writing 80H into $0A. Therefore, this ($07) first, then access the bank #1 or bank #2 by addressing the system will wake-up to service every second. Also, T16Hz (one of higher bank address ($8000 - $FFFF) to fetch the data. counter`s clock source and wake-up & interrupt) can be one of 4Hz, 8Hz, 16Hz or 32Hz by setting bit0 and bit1 of TIME-SETTING 2. STOP CLOCK MODE register ($0A). SPL30A supports power saving mode for those applications selects 2Hz. At power on state, T16Hz selects 4Hz and T2Hz needing very low standby current. The user simply enables the wake-up sources to stop the CPU clock by writing the STOP 5. PWM OUTPUT CLOCK register($09). Thus CPU will go to standby mode and the Internally, SPL30A has two-set PWMs (one for each channel). RAM and I/O remain in their previous state until awakened. There SPL30A uses Pulse Width Modulation that could directly drive are four sources of wake-up in this chip, PORT IOEF wake-up, speaker or buzzer without any buffer or AMP circuit. TIMER 0 wake-up, 4Hz/8Hz/16Hz/32Hz wake-up and 2Hz/1Hz wake-up. After the chip is awakened, the internal CPU will go to the RESET state. The RAM and I/O are not affected by this wake-up reset. PORT IOAB $0002 IOCD $0003 IOEF $0004 I/O CONFIG $0000 I/O CONFIG $001E *NMI SOURCE: INT1 (from TIMER 1) synthesis. INT1 (from TIMER 1) 2KHz LCDL (1/3, 1/4 duty 256Hz; 1/2 duty 128Hz) 128Hz EXT INT 2Hz ROM BANK #1 $0FFFF $10000 $17FFF $18000 $1FFFF $20000 $23FFF $24000 $27FFF For speech synthesis, this chip can provide INT for precise sampling frequency. * MEMORY MAP $00000 H/W registers , I/Os , LCD RAM $00060 USER RAM and STACK $00100 UNUSED $00200 SUNPLUS TEST PROGRAM $00600 USER's PROGRAM DATA AREA ROM BANK $08000 *INT SOURCE INT0 (from TIMER 0) Since SPL30A can provide a large ROM size and wide CPU operation speed, it is most suitable for speech and melody 3. MAP OF MEMORY AND I/Os *I/O PORT: 6. SPEECH AND MELODY Users can record or synthesize the sound and digitize it into the ROM. The sound can be played back in the sequence of the control functions as designed by the internal user's program. Several algorithms are suggested to be used for high fidelity and good compression of sound: PCM, LOG PCM, DM and ADPCM. dual tone mode. For melody synthesis, SPL30A provides Once entered into the dual tone mode, users only need to program the TM0 and TM1 to tone frequency for each channel, count the envelope of each channel, and the hardware can toggle the tone wave automatically without using INT to handle it. ROM BANK #2 ROM BANK #3 UNUSED ROM BANK #4 7. LCD CONTROLLER SPL30A contains a total of 220 segments LCD controller and drivers. In the power-on state, LCD display is all on state. The programmer can set the LCD status (bias, duty, normal scan) by writing to LCD option ($1F), update the LCD content by writing to LCD registers. After the power-on state, LCD option is defined only one time and then fill the LCD registers to display the desired pattern. The LCD driver are designed to fit most LCD's specifications in SPL30A. It can either be programmed as 1/2 or 1/3 bias. The duty is also programmable from 1/2, 1/3, 1/4 or 1/5 duty. (c) Sunplus Technology Co., Ltd. PAGE 2 MAR. 26, 2001 Version: 1.5 SPL30A 8. TIMER/COUNTER SPL30A contains two 16-bit timer/counters, TM0 and TM1 specified as a counter, the user can reset the counter by loading 0 respectively. In the timer mode, TM0 and TM1 are reloaded up- into register $15 and $16 and loading 0 into the counter by writing When timer overflows from $FFFF to $0000, the carry to $17. After the counter is activated, the count value can also be signal will generate the INT signal if the corresponding bit is read from above registers ($15 and $16) on-the-fly and the read enabled in INT ENABLE register ($0d), and the timer will auto instruction will not affect the counter's value or reset it. counters. reload to the user setup value and up count again. If TM0 is The clock source of the timer/counter are selected as the following: TIMER/COUNTER ADDR. CLOCK SOURCE $0015 16-BIT TIMER CPU CLOCK X 2, the CARRY of timer 1 $0016 $0017 Clock source 1: IOCD1, VDD, T16Hz, 128Hz TM0 $0015 16-BIT COUNTER Clock source 2: IOCD0, Crystal oscillator, CPU CLOCK x 2, $0016 32768Hz. $0017 Note: T16Hz can be one of 4Hz, 8Hz, 16Hz or 32Hz by setting $0A (timesetting register) $0025 TM1 16-BIT TIMER $0026 CPU CLOCK X 2, 32768 Hz $0027 MODE SELECT REGISTER $000B Select TM0 & TM1 configuration PIN DESCRIPTION Mnemonic PIN No. Type Description SEG33 - 0 1 - 34 O SEG35 - 34 74 - 75 COM4 - 0 35 - 39 O LCD driver common output IOAB7 - 0 66 - 73 I/O I/O port or LCD driver segment 43 - 36 IOEF7 - 0 48 - 41 I LCD driver segment output INPUT port (also for key wake input). IOEF7 - 6 can be mask option for crystal oscillator for counter 0 IOCD3 - 0 ROSC 65 - 62 I/O 53 I I/O port ROSC input, connect to VDD through resistor RESET 57 I System reset input AUDP 59 O PWM Audio output AUDN 61 O PWM Audio output X32I 56 I 32.768KHz crystal input (provide LCD frequency) X32O 55 O 32.768KHz crystal output TEST 40 I Test input VDD 54, 60 I Positive supply voltage input VSS 58 I Ground input VDD1, VDD2 49, 52 I Inputs for setting LCD bias CUP1, CUP2 50, 51 I Inputs for setting LCD bias (c) Sunplus Technology Co., Ltd. PAGE 3 MAR. 26, 2001 Version: 1.5 SPL30A ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Ratings DC Supply Voltage V+ < 7V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0 to +60 TSTO -50 to +150 Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. DC CHARACTERISTICS Characteristics Limit Symbol Min. Typ. Max. 2.4 - 3.4 Unit Test Condition V For 2-battery 5.5 V For 3-battery - A FCPU = 600KHz @ 3.0V, no load - 1.0 A VDD = 3.0V, 32768 Hz OFF - - 4.0 MHz VDD = 3.0V - -16 - mA VDD = 3.0V IOL - 24 - mA VDD = 3.0V Input High level VIH 2.0 - - V VDD = 3.0V Input Low level VIL - - 0.8 V VDD = 3.0V Output High I (I/O) IOH -200 - - A VDD = 3.0V, VOH = 2.4V Output Sink I (I/O) IOL 500 - - A VDD = 3.0V, VOL = 0.8V Input Resistor RIN - 50K - For input only OSC Resistor ROSC - 150K - FOSC2 = 1.2MHz @ 3.0V CPU Clock FCPU - - 2.0 MHz Operating Voltage VDD 3.6 - Operating Current IOP - 400 Standby Current ISTBY - OSC Frequency FOSC2 IOH Audio Output Current FCPU = FOSC2/2 @ 3.0V THE RELATIONSHIPS BETWEEN THE ROSC AND THE FOSC 1. VDD = 3.0V, TA = 25 2. VDD = 4.5V, TA = 25 4.0 Fosc ( MHz ) Fosc ( MHz ) 4.0 3.0 2.0 1.0 3.0 2.0 1.0 0.0 0.0 0 200 400 600 0 800 400 600 800 Rosc ( Kohms ) Rosc ( Kohms ) (c) Sunplus Technology Co., Ltd. 200 PAGE 4 MAR. 26, 2001 Version: 1.5 SPL30A APPLICATION NOTES 1. SPL30A APPLICATION CIRCUIT 0.01 F VDD 0.01 F 0.01 F 0.01 F 0.01 F Bias option 1/2 Bias VDD1 VDD2 CUP1 CUP2 1/3 Bias VDD1 VDD2 CUP1 CUP2 SEGs [ 35:0 ] LCD Module COMs [ 4:0 ] SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SPL30A IOAB6 IOAB7 IOCD3 IOCD2 IOCD1 IOCD0 AUDN VDD AUDP VSS RESET X32I X32O VDD ROSC VDD2 CUP2 CUP1 VDD1 IOEF7 IOEF6 IOEF5 IOEF4 IOEF3 IOEF2 IOEF1 IOEF0 100 F VDD 20P I/O I/O DEVICE 32 ~ 64 RESET C5 VDD 0.1 F 0.1 F Rosc 32768Hz 20P Bias option SPL30A Application circuit Inputs MAR. 26, 2001 Version: 1.5 PAGE 5 (c) Sunplus Technology Co., Ltd. SEG34 SEG35 IOAB0 IOAB1 IOAB2 IOAB3 IOAB4 IOAB5 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM4 COM3 COM2 COM1 COM0 TEST SPL30A 2. AUDIO DRIVER/AMPLIFIER FOR PWM MODE AUDN AUDP Power 2.7K AUDP 47K 8050 0.1 F 0.001 F 20K (c) Sunplus Technology Co., Ltd. 3 PAGE 6 6 5 LM386 7 2 + - 4.7K + - AUDN 220 F 4 MAR. 26, 2001 Version: 1.5 SPL30A PAD ASSIGNMENT AND LOCATIONS 1. PAD ASSIGNMENT Chip Size: 2290m x 3540m This IC substrate should be connected to VSS Note1: To ensure IC function properly, please bond all of the VDD and VSS pins. Note2: The 0.1F capacitor between VDD and VSS should be placed to IC as close as passible. 2. ORDERING INFORMATION Product Number Package Type SPL30A-nnnnV-C Chip form Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z). (c) Sunplus Technology Co., Ltd. PAGE 7 MAR. 26, 2001 Version: 1.5 SPL30A 3. PAD LOCATIONS Pad No Pad Name X Y Pad No Pad Name X Y 1 SEG33 -992 1580 39 COM0 850 -1592 2 SEG32 -991 1442 40 TEST 988 -1593 3 SEG31 -991 1303 41 IOEF0 986 -1454 4 SEG30 -992 1159 42 IOEF1 986 -1312 5 SEG29 -991 1042 43 IOEF2 986 -1175 6 SEG28 -992 911 44 IOEF3 980 -1043 7 SEG27 -991 778 45 IOEF4 986 -910 8 SEG26 -991 652 46 IOEF5 982 -780 9 SEG25 -991 520 47 IOEF6 984 -654 10 SEG24 -992 388 48 IOEF7 984 -525 11 SEG23 -991 258 49 VDD1 981 -389 12 SEG22 -991 131 50 CUP1 979 -260 13 SEG21 -991 -1 51 CUP2 981 -129 14 SEG20 -993 -130 52 VDD2 983 0 15 SEG19 -991 -261 53 ROSC 979 132 16 SEG18 -991 -391 54 VDD 987 259 17 SEG17 -988 -524 55 X32O 987 392 18 SEG16 -989 -650 56 X32I 977 522 19 SEG15 -991 -780 57 RESET 984 653 20 SEG14 -992 -915 58 VSS 982 779 21 SEG13 -991 -1040 59 AUDP 986 913 22 SEG12 -991 -1172 60 VDD 984 1046 23 SEG11 -990 -1309 61 AUDN 986 1379 24 SEG10 -991 -1450 62 IOCD0 846 1582 25 SEG9 -992 -1592 63 IOCD1 709 1580 26 SEG8 -854 -1591 64 IOCD2 574 1582 27 SEG7 -716 -1592 65 IOCD3 442 1582 28 SEG6 -579 -1592 66 IOAB7 315 1581 29 SEG5 -447 -1591 67 IOAB6 184 1581 30 SEG4 -321 -1591 68 IOAB5 61 1581 31 SEG3 -199 -1592 69 IOAB4 -66 1581 32 SEG2 -64 -1592 71 IOAB2 -317 1582 33 SEG1 60 -1592 72 IOAB1 -447 1581 34 SEG0 187 -1591 73 IOAB0 -577 1581 35 COM4 315 -1591 74 SEG35 -717 1580 36 COM3 439 -1592 75 SEG34 -854 1582 37 COM2 573 -1592 70 IOAB3 -192 1584 38 COM1 706 -1592 (c) Sunplus Technology Co., Ltd. PAGE 8 MAR. 26, 2001 Version: 1.5 SPL30A DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. (c) Sunplus Technology Co., Ltd. PAGE 9 MAR. 26, 2001 Version: 1.5 SPL30A REVISION HISTORY Date Revision # Description Page MAY. 30, 1997 0.1 Original JUN. 06, 1997 0.2 1. Modify: 32 Segments -> 36 Segments, 4 Commons -> 5 Commons 2. Modify: ROM BANK #4 address "$20000-$27FFF" -> "$24000-$27FFF" 3. Modify: clock source1: IOCD0 -> clock source1: IOCD1, clock source2: IOCD1 -> clock source2: IOCD0 JUL. 30, 1997 0.3 1. Modify: IOA0 - 7 -> IOAB0 - 7 2. Add "MASK OPTION" 3. Add IOEF6, IOEF7 description in "MASK OPTION" 4. Modify: 455Hz-> Crystall oscillatorCPUCLKx2 -> CPU CLOCKx2 5. Modify "LCD CONTROLLER" description 6. Add "APPLICATION CIRCUIT" and "BONDING DIAGRAM" OCT. 27, 1997 0.4 According to the new SPEC. format, modify the index and font. DEC. 09, 1997 0.5 1. Add "THE RELATIONSHIPS BETWEEN THE ROSC AND THE FOSC " 2. Modify: when FOSC = 1.2MHzROSC = 150K (VDD = 3.0V) MAR. 02, 1998 1.0 Delete "Preliminary" MAY. 14, 1998 1.1 Add "Note: To ensure IC function properly, please bond all of the VDD, AVDD and VSS pins." SEP. 16, 1998 1.2 Modify: 1/2 bias in "APPLIACTION CIRCUIT" JAN. 22, 1999 1.3 Add "32768Hz OFF" in the field of standby current of "ELECTRICAL CHARACTERISTICS" DEC. 05, 1999 1.4 1. Modfy Format 2. Add "Pin No" in "PIN DESCRIPTION" 3. Add "DISCLAIMER". MAR. 26, 2001 1.5 1. Add "Note: Patent Circuitry Included. Taiwan Patent No. 68824" 1 2. Add "Note2: The 0.1F capacitor between VDD and VSS..." 7 3. Add "REVISION HISTORY" 10 4. Renew to a new document format (c) Sunplus Technology Co., Ltd. PAGE 10 MAR. 26, 2001 Version: 1.5